CN110110362B - Method for designing chip by using embedded command - Google Patents
Method for designing chip by using embedded command Download PDFInfo
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- CN110110362B CN110110362B CN201910246855.5A CN201910246855A CN110110362B CN 110110362 B CN110110362 B CN 110110362B CN 201910246855 A CN201910246855 A CN 201910246855A CN 110110362 B CN110110362 B CN 110110362B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a method for designing a chip by using an embedded command, which comprises the following operation steps: s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result; s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved; s3: reading codes containing embedded commands and design codes into CAD/EDA software; s4: when compiling the embedded control statement, if the embedded control statement is seen at the top layer module, the CAD/EDA software automatically maps the embedded control statement at the top layer into the module to be controlled inside the module, so that the control comprehensive tool completes the logic comprehensive tool inside the module according to the embedded control statement. Through the mode, the method for designing the chip by using the embedded command provided by the invention controls CAD/EDA software in the top layer file of chip design, comprehensively generates a required circuit according to the requirements of a designer, saves communication time, designs iteration and has good practical performance.
Description
Technical Field
The present invention relates to a control chip design method, and more particularly, to a method for designing a chip using embedded commands.
Background
An unequal number of modules need to be integrated in the Soc (system on chip) chip design, one being that the company's internal design and some being provided by a third party IP provider.
Such as ARM Cortex series processor cores, synopsys corporation USB, PCIE bus modules, and the like. The chip design company can rapidly complete SOC design by adopting the modules mentioned by the third party, avoids risks, and is a chip product which is rapidly marketed. In the SoC design process, chip synthesis is generally required to be controlled, where one scenario is that the control chip uses multiplexers instead of combinational logic to avoid generating burrs, which causes unnecessary post-stage circuits. In the design process, chip synthesis is usually required to be controlled, wherein one scene is that the control chip uses multiplexers instead of combinational logic to avoid generating burrs, and unnecessary flip of a later-stage circuit is caused. A common approach is to require the assistance of a module designer to modify the design. Many third party IPs do not allow modification or require a relatively long period to complete.
Disclosure of Invention
The invention mainly solves the technical problem of how to provide a method for designing a chip by using embedded commands, which controls CAD/EDA software in a top layer file of the chip design, comprehensively generates a required circuit according to the requirements of a designer, saves communication time, designs iteration and has good practical performance.
In order to solve the technical problems, the invention adopts a technical scheme that: there is provided a method of designing a chip using an embedded command, the method of designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the embedded control statement, if the embedded control statement is seen at the top layer module, the CAD/EDA software automatically maps the embedded control statement at the top layer into the module to be controlled inside the module, so that the control comprehensive tool completes the logic comprehensive tool inside the module according to the embedded control statement.
In a specific embodiment, in step S3, an add support for adding embedded control statements at the top layer of the chip code is added in the CAD/EDA software.
In a specific embodiment, in step S3, the embedded control statement is:
//edamame map_to_mux top.modulel.reset wrapper 114 to 115。
in one embodiment, in step S4, the specific operational steps of the logic synthesis tool within the completion module are,
a, reading RTL codes in a comprehensive tool;
b: checking whether an embedded control statement exists in the top module in the comprehensive tool;
c: if so, the comprehensive tool interprets the embedded control statement in the top-level module and maps the embedded control statement inside the top-level module;
d: and finally, the comprehensive tool completes code synthesis according to the embedded control statement mapped in the top-level module.
In one embodiment, the method for designing a chip using embedded commands includes the following steps:
s1: running a Top module1.Rest_wrapper module in a module needing control logic comprehensive results;
s2, changing codes in a module of the logic synthesis result so as to achieve the purpose of controlling the logic synthesis tool;
s3: running and controlling CAD/EDA software in a control chip;
s4: when compiling the control statement, the CAD/EDA maps the control statement into a module needing to be controlled in the module, so that the control comprehensive tool completes the logic comprehensive tool in the module according to the control statement.
In a specific embodiment, in step S2, the embedded control statements are merged in the CAD/EDA and the merged files are stored separately, after which the separately stored files are used as input files for the CAD/EDA.
In one embodiment, in step S4, the specific operation steps are,
reading in RTL codes and separately stored combined files in a comprehensive tool;
c: the comprehensive tool converts the RTL codes and the separately stored combined files into control sentences, and maps the control sentences inside the module;
d: and finally, the comprehensive tool completes code synthesis according to the control statement in the mapping module. .
The beneficial effects of the invention are as follows: CAD/EDA software is controlled on a top-level file of chip design, required circuits are comprehensively generated according to the requirements of a designer, communication time is saved, design iteration is performed, and good practical performance is achieved.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a circuit diagram of a Cadence and Synopsys integrated tool in the method of designing a chip using embedded commands of the present invention that is likely to generate glitches in the output;
FIG. 2 is a circuit diagram of a method of designing a chip using embedded commands to control the integrated tool integrated RTL mapping into a symmetric mux such that a and b arrive at an output time consistent;
FIG. 3 is a diagram showing an embodiment of adding an embedded control statement by a top module in a method for designing a chip using an embedded command according to the present invention;
FIG. 4 is a diagram of an embodiment of a method of designing a chip using embedded commands of the present invention for reading RTL code and separately stored consolidated files in a synthesis tool.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the prior art chip embedded command designs,
problem description 1:
for example, RTL code as follows
If the module containing the above-mentioned R pi L code is integrated into a chip, logic synthesis tools such as Cadence and Synopsys synthesis tools are likely to produce glitches in output. For example, when a=b=1, c changes from 0 to 1, and a, b reaches the output with different paths and different delays, a burr is generated at the output, and the circuit is as shown in fig. 1.
Problem description 2:
the existing solution is to embed control codes in RTL codes, and the control logic synthesis tool selects proper standard logic to realize the same function. Such as
//cadence map_to_mux
To control the synthesis tool synthesis RTL to map to a symmetric mux, to make the a and b arrival times consistent, the circuit is as in fig. 2, and the circuit does not produce glitches at the output. However, the existing method must modify the internal code of the module, which generates additional communication cost and iteration E.
Referring to the drawings, in one embodiment of the present invention, a method of designing a chip using embedded commands is provided,
example 1:
a method for designing a chip using an embedded command, the method for designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the embedded control statement, if the embedded control statement is seen at the top layer module, the CAD/EDA software automatically maps the embedded control statement at the top layer into the module to be controlled inside the module, so that the control comprehensive tool completes the logic comprehensive tool inside the module according to the embedded control statement.
Example 2:
a method for designing a chip using an embedded command, the method for designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the embedded control statement, if the embedded control statement is seen at the top layer module, the CAD/EDA software automatically maps the embedded control statement at the top layer into the module to be controlled inside the module, so that the control comprehensive tool completes the logic comprehensive tool inside the module according to the embedded control statement. In step S3, add support to add embedded control statements at the top layer of the chip code in CAD/EDA software.
Example 3:
a method for designing a chip using an embedded command, the method for designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the embedded control statement, if the embedded control statement is seen at the top layer module, the CAD/EDA software automatically maps the embedded control statement at the top layer into the module to be controlled inside the module, so that the control comprehensive tool completes the logic comprehensive tool inside the module according to the embedded control statement. In step S3, add support to add embedded control statements at the top layer of the chip code in CAD/EDA software.
The embedded control statement is as follows:
//edamame map_to_mux top.modulel.reset wrapper 114 to 115。
example 4:
a method for designing a chip using an embedded command, the method for designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the embedded control statement, if the embedded control statement is seen at the top layer module, the CAD/EDA software automatically maps the embedded control statement at the top layer into the module to be controlled inside the module, so that the control comprehensive tool completes the logic comprehensive tool inside the module according to the embedded control statement.
In step S3, add support to add embedded control statements at the top layer of the chip code in CAD/EDA software. The embedded control statement is as follows:
//edamame map_to_mux top.modulel.reset wrapper 114 to 115。
in step S4, the specific operation steps of the logic synthesis tool in the completion module are,
a, reading RTL codes in a comprehensive tool;
b: checking whether an embedded control statement exists in the top module in the comprehensive tool;
c: if so, the comprehensive tool interprets the embedded control statement in the top-level module and maps the embedded control statement inside the top-level module;
d: and finally, the comprehensive tool completes code synthesis according to the embedded control statement mapped in the top-level module.
Example 5:
a method for designing a chip using an embedded command, the method for designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the control statement, the CAD/EDA maps the control statement into a module needing to be controlled in the module, so that the control comprehensive tool completes the logic comprehensive tool in the module according to the control statement.
Example 6:
a method for designing a chip using an embedded command, the method for designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the control statement, the CAD/EDA maps the control statement into a module needing to be controlled in the module, so that the control comprehensive tool completes the logic comprehensive tool in the module according to the control statement.
In the step S2, the embedded control sentences are combined in the CAD/EDA, the combined files are stored separately, and the separately stored files are used as input files of the CAD/EDA after being stored separately.
Example 7:
a method for designing a chip using an embedded command, the method for designing a chip using an embedded command comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2, adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the control statement, the CAD/EDA maps the control statement into a module needing to be controlled in the module, so that the control comprehensive tool completes the logic comprehensive tool in the module according to the control statement.
In the step S2, the embedded control sentences are combined in the CAD/EDA, the combined files are stored separately, and the separately stored files are used as input files of the CAD/EDA after being stored separately.
In step S4, the specific operation steps are,
reading in RTL codes and separately stored combined files in a comprehensive tool;
c: the comprehensive tool converts the RTL codes and the separately stored combined files into control sentences, and maps the control sentences inside the module;
d: and finally, the comprehensive tool completes code synthesis according to the control statement in the mapping module.
In a specific implementation, the innovation generates gate level circuits that meet design requirements without modifying module level code by improving the method of the control logic synthesis tool of the CAD/EDA tool.
The implementation method comprises the following steps: for example, code requiring control logic to synthesize results is found in the following modules:
top.module1.reset_wrapper
the code that needs to be controlled is at lines 114 and 115.
115: a : b;
The realization method is that functional support is added in a CAD/EDA tool, the following embedded control statement is added at the top layer of a chip code, and the purpose of controlling a logic comprehensive tool is achieved.
// edaname_map_to_mux top.module1.reset_wrapper 114_to_115.
Another implementation is to merge all the required embedded control statements into one specific file (referred to as a specific file) as an input file for the CAD/EDA tool. The purpose of controlling the logic synthesis result can be achieved as well.
The innovation point can be used in the scenes of CAD/EDA tools to infer different types of adders, parallel/limited conditional branches, and the like.
Therefore, the invention has the following advantages: CAD/EDA software is controlled on a top-level file of chip design, required circuits are comprehensively generated according to the requirements of a designer, communication time is saved, design iteration is performed, and good practical performance is achieved.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related arts are included in the scope of the present invention.
Claims (6)
1. A method for designing a chip using an embedded command, the method comprising the steps of:
s1: determining codes in a module top module1.Rest_wrapper which needs to control the logic comprehensive result;
s2: adding an embedded command into the top module, wherein the embedded command comprises the code label determined in the S1, so that the purpose of controlling a logic comprehensive tool is achieved;
s3: reading codes containing embedded commands and design codes into CAD/EDA software;
s4: when compiling the embedded control statement, if the embedded control statement is seen at the top layer module, the CAD/EDA software automatically maps the embedded control statement at the top layer into the module to be controlled inside the module, so that the control comprehensive tool completes the logic comprehensive tool inside the module according to the embedded control statement.
2. The method of designing a chip using embedded commands according to claim 1, wherein in step S3, adding support for adding embedded control statements at the top layer of the chip code is added in CAD/EDA software.
3. The method for designing a chip using an embedded command as claimed in claim 1, wherein in the step S3, the embedded control statement is: the/(edge map_to_mux top. Model. Reset wrapper 114 to 115).
4. The method for designing a chip using embedded commands according to claim 1, wherein in step S4, the specific operation steps of the logic synthesis tool inside the completed module are,
a, reading RTL codes in a comprehensive tool;
b: checking whether an embedded control statement exists in the top module in the comprehensive tool;
c: if so, the comprehensive tool interprets the embedded control statement in the top-level module and maps the embedded control statement inside the top-level module;
d: and finally, the comprehensive tool completes code synthesis according to the embedded control statement mapped in the top-level module.
5. A method for designing a chip using an embedded command, the method comprising the steps of:
s1: running a top module1.Rest_wrapper module in a module needing control logic comprehensive results;
s2, changing codes in a module of the logic synthesis result so as to achieve the purpose of controlling the logic synthesis tool;
s3: running and controlling CAD/EDA software in a control chip;
s4: when compiling a control statement, the CAD/EDA maps the control statement into a module needing to be controlled in the module, so that the control comprehensive tool completes the logic comprehensive tool in the module according to the control statement;
in the step S2, the embedded control sentences are combined in the CAD/EDA, the combined files are stored separately, and the separately stored files are used as input files of the CAD/EDA after being stored separately.
6. The method of designing a chip using embedded commands as recited in claim 5, wherein, in the step S4, the specific operation steps are,
reading in RTL codes and separately stored combined files in a comprehensive tool;
c: the comprehensive tool converts the RTL codes and the separately stored combined files into control sentences, and maps the control sentences inside the module;
d: and finally, the comprehensive tool completes code synthesis according to the control statement in the mapping module.
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| US20060123378A1 (en) * | 2004-12-03 | 2006-06-08 | Ipextreme Inc. | Method, System, and Software Product For Using Synthesizable Semiconductor Intellectual Property In Self-Documenting Electronic Extended Package |
| CN101436225B (en) * | 2008-12-11 | 2010-09-15 | 国网电力科学研究院 | Implementing method of dynamic local reconstructing embedded type data controller chip |
| CN102542191B (en) * | 2010-12-31 | 2014-12-17 | 深圳市证通电子股份有限公司 | RTL (register transfer level) IP (intellectual property) core protecting method |
| CN107688704A (en) * | 2017-08-25 | 2018-02-13 | 金陵科技学院 | ASIP Action logic integrated approach based on Petri net model |
| CN109145517B (en) * | 2018-10-08 | 2022-10-28 | 华大恒芯科技有限公司 | ECO (engineering change order) method for chip design engineering |
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| US7991606B1 (en) * | 2003-04-01 | 2011-08-02 | Altera Corporation | Embedded logic analyzer functionality for system level environments |
| CN102789512A (en) * | 2011-05-20 | 2012-11-21 | 中国科学院微电子研究所 | Method and device for design of electronic design automation (EDA) tool of multi-field programmable gate array (FPGA) system |
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