CN110110362A - A method of using embedded command design chips - Google Patents
A method of using embedded command design chips Download PDFInfo
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- CN110110362A CN110110362A CN201910246855.5A CN201910246855A CN110110362A CN 110110362 A CN110110362 A CN 110110362A CN 201910246855 A CN201910246855 A CN 201910246855A CN 110110362 A CN110110362 A CN 110110362A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The invention discloses a kind of methods using embedded command design chips, including following operating procedure: S1: determining the code in the module top module1.rest_wrapper for needing control logic synthesis result；S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to achieve the purpose that control logic synthesis tool；S3: the code comprising embedded command and design code are read in into CAD/EDA software again；S4: the CAD/EDA software is when compiling embedded Control sentence, if seeing embedded Control sentence in top-level module, automatically in the module needs that the embedded Control sentence in top layer is mapped to inside modules controlled, inside modules logic synthesis tool is completed according to embedded Control sentence to control synthesis tool.By the above-mentioned means, the method provided by the invention using embedded command design chips, designs top document control CAD/eda software in chip, the circuit needed is generated according to designer's demand is comprehensive, time for communication is saved, design iteration has good practical performance.
Description
Technical field
The present invention relates to a kind of control chip design methods, more particularly to the side for using embedded command design chips
Method.
Background technique
Need to integrate module in varying numbers in the design of Soc (system on chip) chip, in You Yigeshi company
It is to have third party IP supplier offer that portion's design, which has some,.
Alert such as ARM Cortex series processors core, the USB of Synopsys company, PCIE bus module etc..Chip is set
Meter company can quickly finish SOC design using the module that these third parties mention, and avoid risk, be the quick face of chip product
City.During SoC design, it usually needs control chip integration, one of scene is that control chip integration uses
Multiple selector rather than combinational logic avoid generating burr, cause unnecessary late-class circuit.In design process, usually need
Chip integration is controlled, one of scene is control chip integration using multiple selector rather than combinational logic comes
It avoids generating burr, unnecessary late-class circuit is caused to overturn.Usual way is that demand module designer helps, and modification is set
Meter.But many third party IP are not allow to modify or need a long period that could complete to modify.
Summary of the invention
It is a kind of soft in chip design top document control CAD/EDA the present invention solves the technical problem of how to provide
Part generates the circuit needed according to designer's demand is comprehensive, saves time for communication, design iteration has good practical performance
Embedded command design chips method.
In order to solve the above technical problems, one technical scheme adopted by the invention is that: it provides a kind of using embedded command
The method of design chips, the method using embedded command design chips include following operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA software is when compiling embedded Control sentence, if seeing embedded Control language in top-level module
, in the module that the needs that the embedded Control sentence in top layer is mapped to inside modules are controlled automatically, to control synthesis
Tool completes inside modules logic synthesis tool according to embedded Control sentence.
In a specific embodiment, in the S3 step, addition is supported to add in chip code top layer in CAD/EDA software
Add embedded control statement.
In a specific embodiment, in the S3 step, the embedded Control sentence are as follows:
//edamame map_to_mux top.modulel.reset wrapper 114 to 115。
In a specific embodiment, in S4 step, the specific operating procedure of inside modules logic synthesis tool is completed
For,
A: RTL code is read in synthesis tool；
B: check in top-level module whether there is embedded Control sentence in synthesis tool；
C: if so, synthesis tool explains the embedded Control sentence in top-level module, and embedded Control sentence is mapped
Inside top-level module；
D: last synthesis tool is comprehensive according to the embedded Control sentence completion code being mapped in inside top-level module.
In a specific embodiment, the method using embedded command design chips is walked comprising following operation
It is rapid:
S1: Top module1.rest_wrapper module is run in the module for needing control logic synthesis result；
S2: the code in the module of logic synthesis result is modified, to achieve the purpose that control logic synthesis tool；
S3: operation and control CAD/eda software in control chip；
S4: the CAD/EDA in way of compiling control sentence, the module that the needs that control statement is mapped to inside modules are controlled
In, inside modules logic synthesis tool is completed according to control statement to control synthesis tool.
In a specific embodiment, in S2 step, embedded Control sentence is merged in CAD/EDA, and
And individually stored combined file, individually using the file individually stored as the input file of CAD/EDA after storage.
In a specific embodiment, in S4 step, specific operating procedure is,
A: the combined file for reading in RTL code in synthesis tool and individually storing；
C: the combined file that synthesis tool is stored by RTL code and individually is converted into control statement, and control statement is reflected
It penetrates in inside modules；
D: last synthesis tool is comprehensive according to the control statement completion code inside mapping block.
The beneficial effects of the present invention are: top document control CAD/eda software is designed in chip, it is comprehensive according to designer's demand
The circuit for generating and needing is closed, time for communication is saved, design iteration has good practical performance.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, in which:
Fig. 1 is that the present invention is had very much using the synthesis tool of Cadence and Synopsys in the method for embedded command design chips
It may be in the circuit diagram of outpu generation burr；
Fig. 2 is that the present invention is mapped to symmetrically using in the method for embedded command design chips with controlling the comprehensive RTL of synthesis tool
Mux makes a and b reach the circuit diagram of outpu time consistency；
Fig. 3 is that the present invention uses top-level module in the method for embedded command design chips to add the specific of embedded Control sentence
Implementation example figure；
Fig. 4 is that the present invention is read in RTL code and individually deposited using in the method for embedded command design chips in synthesis tool
The specific implementation example diagram of the combined file of storage.
Specific embodiment
The technical scheme in the embodiments of the invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's all other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
In previous coremaking piece embedded command design,
Problem describes 1:
Such as following RTL code
If the module comprising above-mentioned R ∏ L code is integrated into chip, logic synthesis tool such as: Cadence and
The synthesis tool of Synopsys is likely to generate burr in output.For example as a=b=1, c becomes 1 from 0, due to a, b
The path for reaching output is different, and delay is different, can generate burr, circuit such as Fig. 1 in output.
Problem describes 2:
Present solution is that control routine is embedded in RTL code, and control logic synthesis tool selects suitable standard to patrol
It collects to realize same function.Such as
//cadence map_to_mux
It is mapped to symmetrical mux to control the comprehensive RTL of synthesis tool, so that a and b is reached outpu time consistency, circuit such as Fig. 2 should
Circuit does not generate burr in output.But the necessary modified module internal code of existing this method, can generate additional communication
Cost and iteration E.
Attached drawing is please referred to, is provided in one particular embodiment of the present invention a kind of using embedded command design chips
Method,
Embodiment 1:
A method of using embedded command design chips, the method using embedded command design chips include with
Lower operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA software is when compiling embedded Control sentence, if seeing embedded Control language in top-level module
, in the module that the needs that the embedded Control sentence in top layer is mapped to inside modules are controlled automatically, to control synthesis
Tool completes inside modules logic synthesis tool according to embedded Control sentence.
Embodiment 2:
A method of using embedded command design chips, the method using embedded command design chips include with
Lower operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA software is when compiling embedded Control sentence, if seeing embedded Control language in top-level module
, in the module that the needs that the embedded Control sentence in top layer is mapped to inside modules are controlled automatically, to control synthesis
Tool completes inside modules logic synthesis tool according to embedded Control sentence.In the S3 step, it is added in CAD/EDA software
It supports to add embedded Control sentence in chip code top layer.
Embodiment 3:
A method of using embedded command design chips, the method using embedded command design chips include with
Lower operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA software is when compiling embedded Control sentence, if seeing embedded Control language in top-level module
, in the module that the needs that the embedded Control sentence in top layer is mapped to inside modules are controlled automatically, to control synthesis
Tool completes inside modules logic synthesis tool according to embedded Control sentence.In the S3 step, it is added in CAD/EDA software
It supports to add embedded Control sentence in chip code top layer.
The embedded Control sentence are as follows:
//edamame map_to_mux top.modulel.reset wrapper 114 to 115。
Embodiment 4:
A method of using embedded command design chips, the method using embedded command design chips include with
Lower operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA software is when compiling embedded Control sentence, if seeing embedded Control language in top-level module
, in the module that the needs that the embedded Control sentence in top layer is mapped to inside modules are controlled automatically, to control synthesis
Tool completes inside modules logic synthesis tool according to embedded Control sentence.
In the S3 step, addition is supported to add embedded Control sentence in chip code top layer in CAD/EDA software.Institute
The embedded Control sentence stated are as follows:
//edamame map_to_mux top.modulel.reset wrapper 114 to 115。
In S4 step, completing the specific operating procedure of inside modules logic synthesis tool is,
A: RTL code is read in synthesis tool；
B: check in top-level module whether there is embedded Control sentence in synthesis tool；
C: if so, synthesis tool explains the embedded Control sentence in top-level module, and embedded Control sentence is mapped
Inside top-level module；
D: last synthesis tool is comprehensive according to the embedded Control sentence completion code being mapped in inside top-level module.
Embodiment 5:
A method of using embedded command design chips, the method using embedded command design chips include with
Lower operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA in way of compiling control sentence, the module that the needs that control statement is mapped to inside modules are controlled
In, inside modules logic synthesis tool is completed according to control statement to control synthesis tool.
Embodiment 6:
A method of using embedded command design chips, the method using embedded command design chips include with
Lower operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA in way of compiling control sentence, the module that the needs that control statement is mapped to inside modules are controlled
In, inside modules logic synthesis tool is completed according to control statement to control synthesis tool.
In S2 step, embedded Control sentence is merged in CAD/EDA, and combined file is subjected to list
Solely storage, individually using the file individually stored as the input file of CAD/EDA after storage.
Embodiment 7:
A method of using embedded command design chips, the method using embedded command design chips include with
Lower operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA in way of compiling control sentence, the module that the needs that control statement is mapped to inside modules are controlled
In, inside modules logic synthesis tool is completed according to control statement to control synthesis tool.
In S2 step, embedded Control sentence is merged in CAD/EDA, and combined file is subjected to list
Solely storage, individually using the file individually stored as the input file of CAD/EDA after storage.
In S4 step, specific operating procedure is,
A: the combined file for reading in RTL code in synthesis tool and individually storing；
C: the combined file that synthesis tool is stored by RTL code and individually is converted into control statement, and control statement is reflected
It penetrates in inside modules；
D: last synthesis tool is comprehensive according to the control statement completion code inside mapping block.
In the specific implementation process, method of the innovation by improving the control logic synthesis tool of CAD/EDA tool,
In the case where not modified module grade code, the gate level circuit for meeting design requirement is generated.
A kind of implementation method are as follows: for example need the code of control logic synthesis result in following module:
top.module1.reset_wrapper
The code for needing to control is in 114 and 115 row
115: a : b;
Implementation method is to add function in CAD/EDA tool to support to add following embedded Control language in chip code top layer
Sentence, achievees the purpose that control logic synthesis tool.
// edaname_map_to_mux top.module1.reset_wrapper 114_to_115.
Another implementation method is that institute's embedded Control sentence in need is merged into a special file (referred to as special text
Part) input file as CAD/EDA tool.The purpose of control logic synthesis result can equally be played.
The innovation point can equally be used in CAD/EDA tool and infer different type adder, parallel/limited conditions branch
Etc. scenes.
Therefore, the invention has the following advantages that top document control CAD/eda software is designed in chip, according to designer
Demand is comprehensive to generate the circuit needed, saves time for communication, and design iteration has good practical performance.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright description is applied directly or indirectly in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (7)
1. a kind of method using embedded command design chips, which is characterized in that described designs core using embedded command
The method of piece includes following operating procedure:
S1: the code in the module top module1.rest_wrapper for needing control logic synthesis result is determined；
S2: top-level module is added in embedded command, embedded command includes the code label determined in S1, to reach control
The purpose of logic synthesis tool；
S3: the code comprising embedded command and design code are read in into CAD/EDA software again；
S4: the CAD/EDA software is when compiling embedded Control sentence, if seeing embedded Control language in top-level module
, in the module that the needs that the embedded Control sentence in top layer is mapped to inside modules are controlled automatically, to control synthesis
Tool completes inside modules logic synthesis tool according to embedded Control sentence.
2. the method according to claim 1 using embedded command design chips, which is characterized in that in the S3 step,
Addition is supported to add embedded Control sentence in chip code top layer in CAD/EDA software.
3. the method according to claim 1 using embedded command design chips, which is characterized in that in the S3 step,
The embedded Control sentence are as follows:
//edamame map_to_mux top.modulel.reset wrapper 114 to 115。
4. the method according to claim 1 using embedded command design chips, which is characterized in that in S4 step,
Completing the specific operating procedure of inside modules logic synthesis tool is,
A: RTL code is read in synthesis tool；
B: check in top-level module whether there is embedded Control sentence in synthesis tool；
C: if so, synthesis tool explains the embedded Control sentence in top-level module, and embedded Control sentence is mapped
Inside top-level module；
D: last synthesis tool is comprehensive according to the embedded Control sentence completion code being mapped in inside top-level module.
5. a kind of method using embedded command design chips, which is characterized in that described designs core using embedded command
The method of piece includes following operating procedure:
S1: top module1.rest_wrapper module is run in the module for needing control logic synthesis result；
S2: the code in the module of logic synthesis result is modified, to achieve the purpose that control logic synthesis tool；
S3: operation and control CAD/eda software in control chip；
S4: the CAD/EDA in way of compiling control sentence, the module that the needs that control statement is mapped to inside modules are controlled
In, inside modules logic synthesis tool is completed according to control statement to control synthesis tool.
6. the method according to claim 5 using embedded command design chips, which is characterized in that in S2 step,
Embedded Control sentence is merged in CAD/EDA, and combined file is individually stored, it individually will after storage
Input file of the file individually stored as CAD/EDA.
7. the method according to claim 5 using embedded command design chips, which is characterized in that in S4 step,
Specific operating procedure is,
A: the combined file for reading in RTL code in synthesis tool and individually storing；
C: the combined file that synthesis tool is stored by RTL code and individually is converted into control statement, and control statement is reflected
It penetrates in inside modules；
D: last synthesis tool is comprehensive according to the control statement completion code inside mapping block.
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