CN109145517B

CN109145517B - ECO (engineering change order) method for chip design engineering

Info

Publication number: CN109145517B
Application number: CN201811168045.4A
Authority: CN
Inventors: 龚永鑫; 廖峰; 沈红伟; 李险峰
Original assignee: Huada Hengxin Technology Co ltd
Current assignee: Sichuan Huada Hengxin Technology Co ltd
Priority date: 2018-10-08
Filing date: 2018-10-08
Publication date: 2022-10-28
Anticipated expiration: 2038-10-08
Also published as: CN109145517A

Abstract

The invention discloses an ECO (electronic engineering change) method for a chip design engineering change command, which comprises the following steps of: carrying out logic analysis on defects of the chip; modifying the function code based on the logical analysis; performing netlist logic cone analysis, searching a logic cone where a corresponding function code is located in a netlist, realizing the function of the code to be modified by using a standard unit, and performing comprehensive logic expression; according to the netlist logic cone analysis, manually modifying the netlist, modifying the connection relation of the standard units, and realizing the function corresponding to the modification of the function codes; and verifying whether the modification is correct.

Description

ECO (electronic engineering) method for chip design engineering change command

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to an ECO (electronic engineering) method for a chip design engineering change command.

Background

In the whole design process of a chip, a designer usually needs to continuously verify the design, and for the problem in the early stage of the design, the designer can modify Register Transfer Level (RTL) codes to solve the problem. At later stages of the design, for example, near final sign-off, this may be accomplished by Engineering Change Order (ECO) techniques. Because the ECO technology focuses on specific problems of specific links rather than starting from the whole design process, the design period is greatly shortened, the design cost is saved, and the ECO technology has great advantages.

Due to the need of adding a design from a customer or an ECO performed when a chip is found to have a defect (bug) after checking a tape-out chip, a great amount of logic gates are added or rewiring work is required to be performed for a function change, which involves the re-modification of all layers of the chip, and the re-manufacturing cost is high.

Disclosure of Invention

The invention aims to modify functional defects and only modify the metal layer and the VIA layer of the chip, thereby reducing the manufacturing cost.

According to an embodiment of the present invention, there is provided an ECO method for a chip design engineering change command, including:

carrying out logic analysis on the defects of the chip;

modifying the function code based on the logical analysis;

performing netlist logic cone analysis, searching a logic cone where a corresponding function code is located in a netlist, realizing the function of the code to be modified by using a standard unit, and performing comprehensive logic expression;

according to the analysis of the logic cone of the netlist, manually modifying the netlist, modifying the connection relation of the standard units and realizing the function corresponding to the modification of the function codes; and

verifying whether the modification is correct.

In one embodiment of the invention, the logic analysis of the defects existing in the chip determines that the combination logic needs to be modified to solve the defects, and the sequential logic does not need to be modified.

In one embodiment of the invention, the netlist logic cone analysis includes disassembling a first combinational logic into a second combinational logic, wherein the second combinational logic is smaller than the first combinational logic.

In one embodiment of the present invention, the netlist logic cone analysis further comprises:

presume that the particular netlist links correspond to particular function codes; and

it is verified by simulating the same stimulus or software call whether a particular netlist connection corresponds to a particular function code.

In one embodiment of the present invention, verifying whether a particular netlist connection corresponds to a particular function code by simulating the same stimulus comprises:

and if the change of the specific netlist connecting line is the same as the change of the specific function code, and when the specific netlist connecting line is connected to an opposite value, the condition of circuit error is the same as the condition of the specific function code negation error, and the specific netlist connecting line is confirmed to correspond to the specific function code.

In one embodiment of the invention, said verifying that the modification is correct comprises:

formal verification, namely verifying that the code modification is equivalent to the manual modification netlist;

after the function, performing simulation verification to verify that the defect is avoided and no new defect appears; and/or

And designing time sequence convergence for ensuring that the repair path meets the requirement and has no influence on the time sequences of other paths.

According to another embodiment of the present invention, there is provided a computer system for a chip design engineering change command ECO, including a memory and a processor for executing a chip design engineering change command ECO method.

According to still another embodiment of the present invention, there is provided a system for commanding an ECO for chip design engineering, including:

a device for logically analyzing the defects of the chip;

means for modifying functional code based on the logical analysis;

a device for analyzing the logic cone of the net list, searching the logic cone of the corresponding function code in the net list, realizing the code function to be modified by a standard unit, and performing comprehensive logic expression;

the device is used for manually modifying the netlist and modifying the connection relation of the standard units according to the netlist logic cone analysis to realize the function corresponding to the modification of the function codes; and

means for verifying that the modification is correct.

In a further embodiment of the invention, the means for logically analyzing the defects present on the chip determine that solving the defects requires modifying the combinational logic, without modifying the sequential logic.

In another embodiment of the present invention, an apparatus for performing netlist logic cone analysis, finding a logic cone where a corresponding function code is located in a netlist, implementing a code function to be modified with a standard cell, and performing synthetic logic expression includes:

means for inferring that the particular netlist connection corresponds to the particular function code; and

means for verifying whether a particular netlist connection corresponds to a particular function code by simulating the same stimulus or software call.

The ECO method for changing the command in the chip design engineering provided by the invention can solve part of defects of the chip after the mass production process and save the manufacturing cost of the chip at the same time, because the ECO method for designing the chip provided by the invention only modifies the metal layer and the VIA (through hole) layer of the original chip, avoids the re-modification of all layers of the chip and reduces the manufacturing cost of the chip.

Drawings

To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.

Fig. 1 shows a schematic perspective view of a chip structure 100 according to an embodiment of the invention.

FIG. 2 shows a flow diagram of a chip design engineering change command ECO method according to one embodiment of the present invention.

FIG. 3 shows a schematic diagram of a logic cone in accordance with one embodiment of the present invention.

FIG. 4 illustrates a logical unwrap analysis graph according to one embodiment of the invention.

FIG. 5 shows a netlist standard cell connection diagram.

FIG. 6 shows a modified netlist standard cell connection diagram.

Detailed Description

In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

In an integrated circuit Design process, a hardware description language of Register Transfer Level (RTL), such as a common Verilog HDL, is mostly used to describe an integrated circuit, and the hardware description language completes a hardware description language code generated after function verification through an Electronic Design Automation (EDA) tool program (such as a Verilog simulator), and then performs an "optimized synthesis action" under a condition of specified constraint parameters, thereby generating a circuit description conforming to the constraint parameters. After the simulation before layout meets the specification, the circuit description will start to perform physical design, which may include element layout, clock circuit synthesis, and timing optimization, and finally generate the circuit after layout.

However, when a design error is found or a specification made changes, the designer usually chooses to modify the logic function directly on the laid out circuit, and this action is usually attributed to the program of the engineering change command ECO. However, the main reason for the logic modification directly after layout is that it is a time-consuming task to modify the hardware description language code of the register transfer level and then perform a physical design process.

The invention provides an ECO method for chip design engineering change commands. The ECO method for chip design provided by the invention can overcome the defects of the chip after the mass production process and save the manufacturing cost of the chip. The main principle of the ECO method for designing the chip provided by the invention is to only modify the metal layer and the VIA (through hole) layer of the original chip, thereby avoiding the re-modification of all layers of the chip and reducing the manufacturing cost of the chip.

The method for changing the command ECO of the chip design engineering provided by the invention comprises the main steps of analyzing a logic function, modifying a function code, analyzing a netlist logic cone, manually modifying a netlist, and verifying and modifying correctness (reformulation verification, function simulation verification and design time sequence convergence). The analysis of the netlist logic cone can further disassemble larger combinational logic into small logic, and the corresponding relation between the netlist connecting line and the function code is quickly confirmed.

The method disclosed by the invention can be used for modifying the functional defects and only modifying the metal layer and the VIA layer of the chip, thereby reducing the manufacturing cost.

In the embodiment of the present invention, the modification of the error defect needs to have the following characteristics: defect resolution can be achieved without modifying sequential logic (e.g., registers), but only by modifying combinatorial logic.

Fig. 1 shows a schematic perspective view of a chip structure 100 according to an embodiment of the invention. As shown in fig. 1, the chip structure 100 includes a substrate layer 101, an active region 102 formed in the substrate layer 101, a contact layer 103 formed above the active region 102, a multi-layer metal layer 104, a via hole 105, and a dielectric layer 106 between the contact layer 103, the multi-layer metal layer 104, and the via hole 105.

In the process of designing an integrated circuit, when a design error is found or a specification established is changed, the design error can be realized by using the ECO technology. The disclosed chip design engineering change order ECO method of the present invention requires only the modification of the layers above the contact layer 103.

FIG. 2 shows a flow diagram of a chip design engineering change command ECO method according to one embodiment of the invention.

At step 210, a logical analysis is performed. The modification of the error bug needs to have the following characteristics: the bug solution can be realized only by modifying the combinational logic without modifying the sequential logic (such as a register). Therefore, in one embodiment of the invention, the corresponding relation can be established according to the bug and the corresponding modification method, so that the bug library capable of being applied to engineering change by the method can be formed. When the logic analysis is carried out, whether the bug belongs to the bug library which can be subjected to engineering change by applying the method can be determined through the analysis of the bug.

At step 220, the function code is modified. For example, the function corresponding to the authority outputs an error, which causes an exception to the chip processing, and thus, the condition for generating the authority needs to be modified.

Then, at step 230, a netlist logic cone analysis is performed. And searching a logic cone where the corresponding function code is located in the netlist, analyzing how the function of the code needing to be modified is realized by using a standard unit, and performing comprehensive logic expression.

Formal verification generally partitions a design into logic cones. FIG. 3 shows a schematic diagram of a logic cone in accordance with one embodiment of the present invention. A logic cone is a logical network with all boundaries consisting of registers, ports, or black boxes. The concept of a pyramid stems from the fact that the logic network has multiple inputs and one output, in the shape of a pyramid.

In some embodiments of the present invention, the possible combinatorial logic is also larger, which is further broken down into smaller logics, and fig. 4 shows a logic breaking analysis diagram according to an embodiment of the present invention.

Suppose there is a function code wire w1= ab? c.

Since the synthetic optimization combinatorial logic will cause link renaming, the netlist link n1 is presumed to correspond to the function code w1. There are two methods to quickly confirm:

the same excitation is simulated and the same,

a) n1 changes are the same as w1 (netlist and function code);

b) When n1 is connected to an opposite value, the circuit error occurs in the same manner as when w1 is inverted and has an error (netlist and function code).

Then, the netlist connecting line n1 is the w1 of the function code.

Confirming the correspondence between the netlist connecting line and the function code through software, wherein the software principle is as follows:

the software invokes the existing emulation stimulus, emulates the same stimulus,

a) n1 changes are the same as w1 (netlist and function code);

And confirming that the netlist connecting line n1 is the w1 of the function code.

The specific software operation is as follows:

clicking to the wire corresponding to the RTL, and then corresponding to a certain connecting line of the netlist.

For example: clicking n1 of the function code RTL can highlight the corresponding netlist connecting line w1 on the interface.

At step 240, the netlist is modified manually based on the netlist logic cone analysis.

And modifying the connection relation of the standard units according to the logic cone analysis of the corresponding function codes in the netlist to realize the functions corresponding to the code modification.

In step 250, it is verified whether the modification is correct. If the modification is correct, the method is complete. If the modification is not correct, return to step 230.

In embodiments of the present invention, the verification may include three kinds of verification:

1) Formal verification:

the code modification is equivalent to the manual modification of the netlist, so that the function of the final ECO design is ensured to be the same as that of the code design.

For example, the report correctness can be checked by the tool formality of synopsys.

2) Performing simulation verification after functions:

and (4) exciting by a software tool to verify that the defects are avoided and no new defects appear.

3) Design timing convergence:

because the ECO causes path modification, the excitation can be carried out through a software tool, and the repair path can be ensured to meet the requirements under all modes and all conditions, and has no influence on the timing sequence of other paths.

The chip design engineering change order ECO method according to the present invention is described in further detail below with reference to specific examples.

Firstly, logic analysis is carried out to determine that the designed authority register has defects and needs to be modified correspondingly. The analysis was as follows:

the function output of the corresponding authority is wrong, so that the chip is abnormal in processing.

Therefore, the conditions for generating the rights need to be modified.

Then, the function code is modified. The original function codes are as follows:

else if((cmd_write|cmd_erase)&&sec_membank&&

(rx_poionter[15:1]＝＝15'b0))//kill

permisson_none＝～(kill_right|kill_w_right|pwd_is_zero)；

the function code is modified as follows:

else if((cmd_write|cmd_erase)&&sec_membank&&

(rx_poionter[15:1]＝＝15'b0))//kill

permisson_none＝no_auth_right|permisson_nolock；

//permisson_none＝～(kill_right|kill_w_right|pwd_is_zero)；

next, a logic cone analysis is performed to find the logic cone corresponding to the permisson _ none in the netlist. And looking at how the original code is expressed in the logic cone through the combinational logic, and the original code is expressed in the netlist as the connection of a plurality of standard units. Because of the synthetically optimized combinational logic, it may be difficult to have a one-to-one correspondence between the connection name and the wire declaration to the code.

Function code: permisson _ none =: (kill _ right | kill _ w _ right | pwd _ is _ zero)

Under the smic 0.13um technology, the combinational logic implementation on the logic cone uses standard cells such as U345, U346 and U348, and a netlist standard cell connection diagram (corresponding to function codes) is shown in FIG. 5.

And quickly confirming the corresponding relation between the netlist connecting line and the function code, confirming the connecting line n102 and the like.

The fourth step:

manual modification of the netlist:

the goal is to modify the function to correspond to the code modification.

Function code modification: permisson _ none = no _ auth _ right | permisson _ nolock;

and disconnecting the standard unit on the standard combination logic, and reconnecting to realize the function corresponding to the code modification.

Netlist manual modification standard cell re-connection diagram (corresponding to function code modification) as shown in fig. 6, the chain line indicates the connection line of the modified connection relationship, wherein the connection line TIEHI _ NET, TIELO _ NET is connected to the adjacent standard cell TIEHI, TIELO.

The fifth step:

and (5) verifying that the modification is correct:

a) Formal verification:

and the code modification is equivalent to the manual modification of the netlist, so that the function realized by the final ECO design is ensured to be the same as that of the code design.

Check report correctness with tool format of synopsys.

b) And (4) performing simulation verification after functions:

and verifying that the bug is avoided, and meanwhile, no new bug appears.

c) Design timing closure

Because the ECO causes path modification, the repair path is guaranteed to meet the requirements under all modes and all conditions, and the timing of other paths is not affected.

In some embodiments of the present invention, the chip design engineering change order ECO method disclosed in the present invention may be implemented by hardware means, software, or any combination thereof. Examples of hardware devices may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application Specific Integrated Circuits (ASIC), programmable Logic Devices (PLD), digital Signal Processors (DSP), field Programmable Gate Array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth.

Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application Program Interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

Some embodiments may be implemented, for example, using a machine-readable storage medium or article. The storage medium may store an instruction or a set of instructions that, when executed by a machine, may cause the machine to perform a method and/or operations in accordance with the embodiments. Such a machine may include, for example, any suitable processing platform, computing device, processing device, computing system, processing system, computer, processor, or the like, and may be implemented using any suitable combination of hardware and/or software.

Embodiments may include a storage medium or a machine-readable article. For example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit may be included, such as, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, compact disk read Only memory (CD-ROM), compact disk recordable (CD-R), compact Disk Rewriteable (CDRW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of Digital Versatile Disk (DVD), a tape, a cassette, or the like. The instructions may include any suitable type of code, such as source code, assembly code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A chip design Engineering Change Order (ECO) method comprises the following steps:

carrying out logic analysis on defects of the chip;

modifying the function code based on the logical analysis;

according to the netlist logic cone analysis, manually modifying the netlist, modifying the connection relation of the standard units, and realizing the function corresponding to the modification of the function codes; and

verifying whether the modification is correct;

the logic analysis of the defects existing in the chip determines that the combined logic needs to be modified to solve the defects, and the sequential logic does not need to be modified.

2. The chip design engineering change command ECO method of claim 1, wherein the netlist logic cone analysis comprises a decomposition of a first combinational logic into a second combinational logic, wherein the second combinational logic is smaller than the first combinational logic.

3. The chip design engineering change command ECO method as claimed in claim 1, wherein the netlist logic cone analysis further comprises:

4. The chip design engineering change command ECO method of claim 1, wherein confirming whether a particular netlist link corresponds to a particular function code by simulating a same stimulus comprises:

5. The chip design engineering change command ECO method of claim 1, wherein the verifying whether the modification is correct comprises:

formal verification, namely verifying that the code modification is equivalent to the manual modification of the netlist;

6. A computer system for a chip design engineering change order ECO comprising a memory and a processor for performing the method of any one of claims 1 to 5.

7. A system for a chip design engineering change command ECO, comprising:

a device for logically analyzing the defects of the chip;

means for modifying functional code based on the logical analysis;

a device for analyzing the netlist logic cone, searching the logic cone where the corresponding function code is located in the netlist, realizing the code function needing to be modified by a standard unit, and performing comprehensive logic expression;

the device is used for manually modifying the netlist and modifying the connection relation of the standard units according to the netlist logic cone analysis, and realizing the function corresponding to the modification of the function codes; and

means for verifying that the modification is correct;

the device for logic analysis of the defects existing in the chip determines that the combined logic needs to be modified to solve the defects, and does not need to modify the sequential logic.

8. The ECO system according to claim 7, wherein the means for performing netlist cone analysis to find a cone corresponding to a function code in the netlist, implementing the function of the code to be modified with a standard cell, and performing synthetic logic expression comprises:

means for inferring a particular netlist connection to correspond to a particular function code; and