CN113657057B - Method for realizing digital circuit load separation by automatic cloning - Google Patents
Method for realizing digital circuit load separation by automatic cloning Download PDFInfo
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- CN113657057B CN113657057B CN202110937522.4A CN202110937522A CN113657057B CN 113657057 B CN113657057 B CN 113657057B CN 202110937522 A CN202110937522 A CN 202110937522A CN 113657057 B CN113657057 B CN 113657057B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for realizing digital circuit load separation by automatic cloning, which comprises the following steps: step 1, designating a source unit and a load which need to be duplicated; step 2, deriving a circuit topology structure of the source unit; step 3, the filtering unit uses a recursion algorithm to remove units which are not on the paths of the source unit and the load unit, and a circuit structure needing to be duplicated is obtained; step 4, the copying unit copies the filtered unit; step 5, disconnecting the original circuit, and then reconnecting the load unit and the copy circuit in the previous step; step 6, circularly copying units of the circuit; and 7, the output unit describes the process from the step 4 to the step 6, and simultaneously outputs a form verification constraint file and an environment setting file required by the copying circuit. The method for realizing the load separation of the digital circuit by automatic cloning can automatically finish the load separation in the circuit realization process, has high reliability, simple realization process and no need of iteration.
Description
Technical Field
The invention discloses a chip related technical field.
Background
In the physical implementation link of the chip, the problems of high fan-out or timing non-convergence caused by too far physical distance of different loads are often encountered in the comprehensive and layout wiring. In order to solve the problem, in the early stage of logic design, the design personnel modify the RTL design to complete the separation of loads, the strategy is to copy the original circuit to obtain several circuits with the same functions, and the circuits are connected to the original load in a scattered way so as to release the strong coupling caused by different loads, and the disadvantage is that dynamic function verification needs to be performed again, and if the original code needs to be modified due to the design problem, the copy code also needs to be modified synchronously; the design needs and the actual physical realization are highly correlated, the reusability of the design is also affected, and the difficulty of rapid adjustment of the complex circuit design is high; when the layout and wiring are completed and enter a Timing ECO stage, if logic replication is needed to decouple the strong coupling between different loads to optimize the time sequence, the time sequence can be realized only by returning to a modified RTL stage according to the traditional flow, and the time sequence is also unacceptable from the project execution time. In the chip implementation stage, how to quickly change the original circuit structure by changing the ECO, i.e. the engineering command, on the chip so as to achieve the aim of quickly converging the time sequence in the digital circuit implementation process on the premise of ensuring the functional correctness of the circuit is a frequent challenge.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a method for realizing the load separation of a digital circuit by automatic cloning, so as to solve the problems of high difficulty in realizing the load separation, low reliability, high verification difficulty and difficult realization of a complex circuit in the traditional ECO method.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a method for realizing digital circuit load separation by automatic cloning comprises the following steps:
step 1, designating a source unit and a load unit which need to be duplicated;
step 2, deriving a circuit topology structure of the source unit by using an EDA tool, wherein the circuit topology structure comprises the source unit, the load unit and all units on a path of the source unit;
step 3, the filtering unit uses a recursion algorithm to remove units which are not on the paths of the source unit and the load unit, and a circuit structure needing to be duplicated is obtained;
step 4, copying the filtered unit by the copying unit, wherein the copied unit is completely consistent with the filtered unit, and the environmental constraint of the original circuit is obtained;
step 5, disconnecting the original circuit, including the load unit and the driving unit thereof, and then reconnecting the load unit and the duplication circuit in the previous step;
step 6, circularly copying the units of the circuit, traversing the input ports which are not connected with the single units for the single units obtained in each cycle, and connecting the single units to the corresponding ports of the original circuit units;
and 7, the output unit describes the process from the step 4 to the step 6, writes the process into an executable command of the EDA tool, namely, an ECO script form, and simultaneously outputs a form verification constraint file and an environment constraint file required by a replication circuit for the realization of a follow-up EDA tool.
Further, in step 3, the load specified in step 1 is used in a filtering process, the filtering process is a reverse tracking process, the load is used as a starting point of a tracking circuit structure, all circuit structures from the load to a source unit are reversely acquired through a recursive algorithm, and units not in the structure are deleted, so that a complete filtered circuit is finally obtained.
Further, the recursive algorithm is specifically: the load unit is acquired first and then its drive unit, and if its drive unit is not the source unit, it is necessary to acquire the drive unit of its drive unit until the drive unit is the source unit.
Further, in step 4, the environmental constraints include: the method comprises timing constraint information, timing exception information and dont_touch information.
Further, the environmental constraints before and after replication remain consistent.
The beneficial effects of the invention are as follows: the method for realizing the load separation of the digital circuit by automatic cloning has the advantages of simple implementation process and strong operability; the reliability is high, the ECO logic positioning is accurate based on the complete replication of the topological structure of the original circuit; RTL codes do not need to be modified, and the reusability is high; the flexibility is high, and the implementation can be completed at any implementation stage of synthesis and layout and wiring.
Drawings
FIG. 1 is a general flow chart for implementing the present invention;
FIG. 2 (a) is a circuit diagram of one implementation of a recursive algorithm, and FIG. 2 (b) is a flow chart of an embodiment of a recursive algorithm;
FIG. 3 is a schematic diagram of an original circuit configuration in the step of obtaining a circuit topology according to the present invention;
FIG. 4 is a circuit configuration of the invention after filtration;
FIG. 5 is a schematic diagram of a replicated unit of the present invention;
FIG. 6 is a schematic diagram showing a copy unit connection of the present invention;
fig. 7 is a circuit diagram of the present invention after implementation.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings.
As shown in figure 1, the method for realizing the load separation of the digital circuit by automatic cloning comprises the following steps that a starting point register, namely a source unit, and a destination register, namely a load unit, of a circuit to be cloned are set, the separation of the load of a specified circuit is automatically completed by using an EDA tool, the topological structure and the connection relation of the circuit are automatically analyzed, and an ECO script and environmental constraint are automatically written. The method comprises the following steps: according to configuration requirements, acquiring a source unit and a load unit thereof which need to be separated, and then acquiring a circuit structure of the source unit and a fan-out unit thereof, namely a logic circuit on a path from the source unit to the load unit and the load unit thereof through EDA (electronic design automation), referring to FIG. 3; the filtering unit simplifies the original circuit structure, namely the fan-out circuit structure, and the simplifying method is to delete the circuit structure irrelevant to the separation load unit and obtain all units on the path from the source unit to the load unit; copying the filtered circuit, wherein the copying unit creates the filtered circuit, namely copying a same circuit unit, and acquiring the environment constraint of the original circuit, wherein the environment constraint of the circuit after the subsequent copying is consistent with the environment constraint before the copying: the environment constraint comprises time sequence constraint information, time sequence exception information, dont_touch information and the like; separating the load, namely disconnecting the load unit from the original circuit and connecting the load unit with the replication circuit; inquiring an input port which is not connected with the replication circuit, wherein the port which is not connected with the replication circuit is connected to a port corresponding to the original circuit; writing the copying, separating and connecting processes into ECO scripts, outputting form verification constraints, namely the matching constraints of gram Long Shanyuan and the source unit and the environment constraints of the copying circuit, and outputting form verification constraint files for subsequent equivalence verification; and outputting the copy circuit environment constraint file, and executing the ECO script to finish cloning.
The method for realizing the load separation of the digital circuit by automatic cloning comprises the following specific processes:
step 1: first, a source unit to be duplicated and a load thereof need to be specified, typically, each source unit corresponds to a plurality of load units, the specified load units will be connected to the duplicated circuit, and other load units maintain the original circuit structure. The designated source unit is used both to acquire the topology of the circuit and to create a replicated circuit, itself also to be replicated, the designated load unit being the end point of replication. srcRegA, srcRegB in fig. 3 is designated as the source unit of the replica circuit, dstRegA, dstRegB as the load unit that needs to be separated.
Step 2: deriving a circuit topology of a source unit using an EDA tool, including the source unit, a load unit, and all units on its path, as shown in FIG. 3, srcRegA, srcRegB, regE, regF is the source unit, dstRegA, dstRegB, regC, regD, regH, regK is the load unit, blockA, blckB, blockC, blckD, blockE, blockF is the fan-out unit; the fan-out structure is a complete fan-out structure of the source unit srcRegA, srcReg and RegE, regF fan-out structures are shown because the portions of the circuit ports that need to be duplicated are driven by them. Because srcRegA, srcRegB is far away from the load dstRegA, dstRegB, the path has a time sequence problem, and an EDA tool can be inserted into a unit with strong driving capability and large area for repairing the time sequence problem, even part of the circuit structure is changed, and the problems of local region density and wire winding consistency are easily caused; other source units and load units meet timing constraints and do not need to be separated, so srcRegA, srcRegB needs to be designated as the source unit of the cloning circuit, and dstRegA, dstRegB is the load unit needing to be separated.
Step 3: the execution process of the filtering unit is shown in fig. 2 (a) and fig. 2 (b), the load designated in step 1 is used in the filtering process, the filtering process is a reverse tracking process, the load is used as the starting point of the tracking circuit structure, all circuit structures from the load to the source unit can be reversely acquired through a recursive algorithm, the units which are not in the structure are deleted, a complete filtered circuit is finally obtained, meanwhile, the environmental constraint of the filtered circuit needs to be acquired for the copied circuit, and the copied circuit needs to be completely connected according to the original connection relation, so that the copied circuit has the same function as the original circuit. In the recursion process, the D port of the load desRegB is used as a Sink port, the X port of the U4 is known to be driven by the Sink port from the circuit structure, so that the D port of the desRegB of the replica circuit needs to be connected to the X port of the U4, the driving port of the X port of the U4 is A, B, C port of the U4, the B port is known to be not on the source/load path from the circuit structure, so that the B port needs to be connected to the B port of the original circuit, the A, C port is on the source/load path, and the a port of the U4 and the C port of the U4 are circularly used as Sink ports, and a recursion algorithm is used until the source unit srcrrega is traced back. In the recursive algorithm, firstly, the load unit dstRegB is acquired, the driving unit U4 is acquired, and if the driving unit is not the source unit, the driving units U2 and U3 of the driving unit U4 need to be acquired until the driving unit is the source unit srcrrega, and the recursive algorithm needs to be continuously invoked in the algorithm. Firstly, acquiring that the drive of a load unit dstR (digital total internal reflection) is an output port X of a U4 unit, and acquiring input ports A and C of the U4 unit, wherein a B port of the U4 does not belong to fan-out of a source unit srcRegA; the method comprises the steps of obtaining an X port of U2 from the drive of an A port of U4, obtaining an A port of an input port U2 of U2, obtaining an X port of U1 from the drive of an A port of U2, obtaining an A port of an input port U1 of U1, obtaining a source unit srcRegA from the drive of an A port of U1, and then processing a C port of U4 according to the same algorithm to finally obtain a circuit structure from a load unit to a source unit: the algorithm is based on the circuit structure to carry out complete copying, so that the copying success rate reaches 100%, and the complexity of the circuit only affects the time of the recursive algorithm.
As shown in fig. 4, the execution result of step 3 is that, after filtering, the BlockE and BlockF are not on the path from the source unit to the separated load, and need to be deleted, and the filtered circuit structure is in the dashed box, and needs to be copied later.
Step 4: the copy unit execution results are shown in fig. 5, where the copy unit creates a filtered unit, and the newly created circuit must be identical to the filtered circuit.
And 5, disconnecting the original circuit, including the load unit and the driving unit thereof, and then reconnecting the load unit and the copy circuit in the last step. Step 5, disconnecting the load unit from the original circuit, instead connecting to the duplicated circuit, dstRegA, dstRegB in fig. 6 being disconnected from the original connection BlockB, blockD, instead connecting to duplicated BlockB ', blockD'; the connections inside the replica circuit are made as original circuit connections, as in the following connection scheme in fig. 6: the srcRegA 'is connected with the BlockA', the BlockA 'is connected with the BlockB', the srcRegB 'is connected with the BlockC', and the BlockC 'is connected with the BlockD'.
Step 6, circularly inquiring the newly created unit, traversing the input port which is not connected, and because the source driving logic is not in a copy list, the port is not logically driven, in order to ensure the consistency of functions before and after ECO, the port needs to be connected to the corresponding port of the original circuit unit, step 6 adopts circularly judging the port of the clone circuit unit to find out the port which is not connected, as shown by a broken line connected in the figure 6, the broken line indicates that the driving of the port is not in the fan-out circuit of the source unit, the port needs to be connected to the corresponding port of the original circuit, and the broken line is connected to the corresponding port of the blockA ', blockB', blockC 'blockD'.
Creating a circuit with a unit for copying filtered, wherein the circuit needs to be completely and uniquely copied, the incomplete circuit leads to inconsistent functions, and the repeated copying leads to the problem of multiple driving, which leads to ECO failure; the copy unit copies the filtered circuit, and srcrrega ', srcrregb', blockA ', blockB', blockC ', blockD' in fig. 6 are copy circuits of srcRegA, srcRegB, blockA, blockB, blockC, blockD in fig. 3.
Step 7: the output unit writes the ECO script described in the above process, the formal verification constraint file, and the environment setting file required for the replica circuit for use by the subsequent EDA tool implementation. Executing the ECO script written in step 7 completes the ECO process, the executed circuit is as shown in fig. 7,
the copied circuits are connected, in fig. 7, all input ports of BlockA ', blockB', blockC ', blockD' are connected in the same manner as the original circuits, and the input ports of srcrrega ', srcrregb' are connected with the input port of the source unit srcRegA, srcRegB, so that the functions of the copied circuits and the original circuits are ensured to be consistent, and dstRegA, dstRegB is successfully separated from the original circuits.
It should be noted that the terms like "upper", "lower", "left", "right", "front", "rear", and the like are also used for descriptive purposes only and are not intended to limit the scope of the invention in which the invention may be practiced, but rather the relative relationship of the terms may be altered or modified without materially altering the teachings of the invention.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (2)
1. A method for realizing digital circuit load separation by automatic cloning is characterized in that: the method comprises the following steps:
step 1, designating a source unit and a load unit which need to be duplicated;
step 2, deriving a circuit topology structure of the source unit by using an EDA tool, wherein the circuit topology structure comprises the source unit, the load unit and all units on a path of the source unit;
step 3, the filtering unit uses a recursion algorithm to remove units which are not on the paths of the source unit and the load unit, and a circuit structure needing to be duplicated is obtained; the load designated in the step 1 is used for a filtering process, the filtering process is a reverse tracking process, the load is used as a starting point of a tracking circuit structure, all circuit structures from the load to a source unit are reversely acquired through a recursion algorithm, and units which are not in the structure are deleted, so that a complete filtered circuit is finally obtained; the recursive algorithm is specifically as follows: firstly, acquiring a load unit, and then acquiring a driving unit of the load unit, and if the driving unit is not a source unit, acquiring the driving unit of the driving unit until the driving unit is the source unit;
step 4, copying the filtered unit by the copying unit, wherein the copied unit is completely consistent with the filtered unit, and the environmental constraint of the original circuit is obtained; the environmental constraints include: timing constraint information, timing exception information, and dot_touch information;
step 5, disconnecting the original circuit, including the load unit and the driving unit thereof, and then reconnecting the load unit and the duplication circuit in the previous step;
step 6, circularly copying the units of the circuit, traversing the input ports which are not connected with the single units for the single units obtained in each cycle, and connecting the single units to the corresponding ports of the original circuit units;
and 7, the output unit describes the process from the step 4 to the step 6, writes the process into an executable command of the EDA tool, namely, an ECO script form, and simultaneously outputs a form verification constraint file and an environment constraint file required by a replication circuit for the realization of a follow-up EDA tool.
2. The method for automatically cloning to achieve digital circuit load splitting according to claim 1, wherein the environmental constraints before and after replication remain consistent.
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