CN102129493B - Method for realizing automated ECO (Engineering Change Order) netlist in digital IC (Integrated Circuit) design process - Google Patents

Abstract

The invention relates to a method for realizing an automated ECO (Engineering Change Order) netlist in a digital IC (Integrated Circuit) design process, comprising the following steps of: extracting an ECO digit circuit in an original circuit, and describing the ECO digit circuit by using RTL (Resistor Transistor Logic); generating a report of an ECO modified script by using the output of an EDA (Electronic Design Automation) tool; and generating the ECO modified script by using an output report of a synthesis tool. In the invention, only the RTL description in the whole process is needed to be modified and few or no ECO modified script is needed to be written, therefore, efficient process, automation realization and difficult error are achieved and temporal constraint can be applied to the ECO process.

Description

Realize the method for robotization ECO net table in the numeral IC design cycle

[technical field]

The invention belongs to digital IC design field, specifically refer to realize in a kind of digital IC design cycle the method for robotization ECO net table.

[background technology]

Numeral IC design cycle is as follows: (whole process, the outstanding part relevant with ECO)

Numeral IC design cycle be from high abstraction level progressively to the process of concrete level, from system describe, arthmetic statement is progressively described specific to functional description, circuit and the process of production technology level.

Describe and the arthmetic statement level in system, usually use higher level lanquage such as C language, carry out the checking of system architecture and algorithm function; After the system algorithm checking is finished, need to be by instrument or manual RTL description (the Method at Register Transfer Level description that algorithm is converted into equivalence by hardware description language, it is the level that hardware circuit is described, be applicable to the digital display circuit of representation function component-level), and verify its functional equivalence.

After using hardware description language to finish the description of specific IC circuit, next step is exactly to convert hardware description language to be comprised of unit in the standard digital cell process storehouse gate level netlist, and in fact this gate level netlist is exactly specific function is mapped to being connected and set of concrete logic gate in the circuit (with door or door, trigger etc. all being referred to as logic gate in the standard block technology library).This process is referred to as logic synthesis, is usually automatically finished by instrument.

After obtaining gate level netlist, just need to finish by instrument the work of placement-and-routing, namely comprise the layout of various logic gates, and the wiring of line between logic gate and the logic gate.These work had both needed to satisfy the consistance of circuit and gate level description function, also needed to satisfy the sequential requirement.Finally, generating last domain produces to chip production factory choosing row.

ECO refers to that on stream certain stage finds mistake, repeats in the full-range situation not needing, by the design in current flow process stage is directly changed, to reduce the prolongation of the PROJECT TIME that whole process repeats to bring.

Because gate level netlist outputs between last domain period of output and still may find design mistake, therefore usually need to be by gate level netlist be directly carried out design alteration.As shown in Figure 1, this flow process is as follows in the prior art:

1, analyzes design code to be changed and logic netlist;

2, analysis logic net table is determined modification;

3, manual Application standard digital units logical combination practical function is also manually write ECO and is revised script;

4, confirm the consistance of RTL and gate level netlist by formal verification (the conforming static authentication methods of function between a kind of assurance RTL and gate level netlist or the gate level netlist);

If 5 formal verifications failure will analyze and produce RTL and the inconsistent reason of gate level netlist, and the rebound first step re-starts net table ECO.

The method of existing net table ECO is the existing gate level netlist of Direct Analysis normally, by directly changing at the net table, logic gate in the Application standard cell library is drawn the logic of revising, and the ECO modification script that net table modifiers can be identified is manually write in all modifications action.

Owing to need the manual digital circuit that RTL is described to convert gate level netlist to, and need manual all modifications is moved to convert ECO modification script to, therefore traditional net table ECO method can only be for the less ECO of logic Modification, otherwise pure craft is described RTL and is converted gate level circuit to, not only make mistakes easily, and workload is larger.And converting the action that the net table is revised to ECO modification script also is easy to make mistakes.

In addition, because traditional ECO flow process is by pure craft standard block to be made up, therefore, this process has larger temporal constraint for the ECO partial circuit, usually can't carry out.

[summary of the invention]

Technical matters to be solved by this invention is to provide a kind of method that improves flow path efficiency and reduce the realization robotization ECO net table of artificial error rate.

The present invention solves the problems of the technologies described above by the following technical solutions:

Realize the method for robotization ECO net table in the numeral IC design cycle, comprise the steps:

Step 100: in original circuit, extract and treat the ECO digital circuit, use RTL to describe the ECO digital circuit;

Step 200: be used for generating the report that ECO revises script by eda tool output;

Step 300: use the synthesis tool output report to generate ECO and revise script.

Further, described step 100 comprises:

Step 101: at first in ifq circuit is described, find out all input registers for the treatment of the ECO logic;

Step 102: and then in ifq circuit is described, find out all output registers for the treatment of the ECO logic;

Step 103: use the RTL describing module, and with the input of all input registers as module, with the output of all output registers as module, and its name stipulated, make its name and register name identical;

Step 104: in the module that RTL describes, code revision is become logical description behind the ECO.

Further, described step 200 comprises:

Step 201: at first use the RTL code after eda tool reads in ECO;

Step 202: in eda tool, specify the standard cell lib that uses;

Step 203: specifying needs satisfied temporal constraint;

Step 204: the naming rule of specifying NET/CELL when comprehensive;

Step 205: use eda tool to carry out comprehensively, the RTL logical description is converted to the gate level netlist that the door in the Application standard cell library is described;

Step 206: use the report output order in the eda tool, export following report: all NET information, all CELL information, all CONNECTION information.

Further, described step 300 comprises:

Step 301: net and the connection order that at first will delete in the original netlist write ECO modification script;

Step 302: by the NET/CELL/CONNECTION of the comprehensive output report of Program extraction, and related command is write ECO revise script;

Step 303: its front and back level register in the net table of input and output name identification by the ECO module, its NET name in comprehensive ECO module is set up being connected of NET and front and back level register, and its action is written to ECO modification script by order line.

The invention has the advantages that: describe owing to only need to revise RTL in the whole process, seldom or not need manually to write ECO and revise script, so it has following advantage: 1, flow path efficiency is high; 2, realize robotization: robotization generates ECO and revises script, does not increase workload fully for the logic Modification of complexity; 3, be difficult for makeing mistakes: only revise RTL in the flow process and describe, avoided the mistake of introducing hand-manipulated; 4, the ECO process can apply temporal constraint: owing to introduced EDA (electron assistant design tool) and carry out comprehensively, so can apply temporal constraint in comprehensive process, make the circuit behind the ECO can satisfy the sequential requirement.

[description of drawings]

The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings.

Fig. 1 is the ECO process synoptic diagram of prior art.

Fig. 2 is robotization net table ECO schematic flow sheet of the present invention.

Fig. 3 is NRT/CELL/CONNECTION/PIN principle schematic among the present invention.

Fig. 4 is robotization net table ECO process synoptic diagram of the present invention.

[embodiment]

Shown in Figure 2 is the method flow synoptic diagram of realizing robotization ECO net table in a kind of digital IC design cycle of the present invention, and Fig. 4 is robotization net table ECO process synoptic diagram of the present invention.Comprise the steps:

Step 100: in original circuit, extract and treat the ECO digital circuit, use RTL to describe the ECO digital circuit; Referring to the part of " manually finishing the RTL code revision " among Fig. 4.

Step 200: be used for generating the report that ECO revises script by eda tool output; Referring to " automatically generating ECO and revise script " part among Fig. 4.

Step 300: use the synthesis tool output report to generate ECO and revise script.Referring to " automatically finishing comprehensively and report output " part among Fig. 4.

Each step of following detailed description:

Step 100 comprises:

Step 101: at first in ifq circuit is described, find out all input registers for the treatment of the ECO logic.

Step 102: and then in ifq circuit is described, find out all output registers for the treatment of the ECO logic.

Step 103: use the RTL describing module, and with the input of all input registers as module, with the output of all output registers as module, and its name stipulated, make its name and register name identical, main like this is to be connected with input-output register by the naming rule coupling for the new logic behind the ECO.

Step 104: in the module that RTL describes, code revision is become logical description behind the ECO.

Step 200 comprises:

Step 201: at first use the RTL code after eda tool reads in ECO;

Step 202: in eda tool, specify the standard cell lib that uses;

Because the logic behind the ECO still will be used the standard logical unit identical with former design, the standard cell lib that uses when therefore needing appointment comprehensive.

Step 203: specifying needs satisfied temporal constraint;

Because some ECO logic has certain temporal constraint in circuit, such as maximum path delay, minimal path delay etc., the form that therefore can use eda tool to accept is herein specified the temporal constraint for the treatment of synthetic circuit.

Step 204: the naming rule of specifying NET/CELL when comprehensive;

For fear of the comprehensive rear NET that produces or CELL and the existing NET of module, CELL duplication of name, therefore NET, CELL naming rule with regard to needing appointment to allow before comprehensive.As: CELL name form is the ECO_CELL_{ date } _ { CELL numbering }, NET name form is the ECO_CELL_{ date } _ { NET numbering }.Like this, not only newly-generated NET, CELL and existing NET, CELL are distinguished, even same module is carried out repeatedly ECO, the situation that CELL or NET name repeat also can not occur.

Step 205: use eda tool to carry out comprehensively, the RTL logical description is converted to the gate level netlist that the door in the Application standard cell library is described;

Step 206: use the report output order in the eda tool, export following report: all NET information, all CELL information, all CONNECTION information.

NET/CELL/CONNECTION mentioned above refers to:

In the connection of as shown in Figure 3 two logic gates, among the figure with door (AND2) and or the door (OR2) be referred to as a CELL, and door and or the door between line NET, with the output pin of door and or the input pin of door be a PIN, be connected to by NET with the output PIN of door or the annexation of the input PIN of door is referred to as CONNECTION.

Step 300 comprises:

For convenience, the order of supposing the Change In Design instrument is new_cell (a newly-built cell), new_net (a newly-built net) new_connection (a newly-built connection), del_connection (deleting existing connection).

Following flow process is all finished automatically by routine processes synthesis tool output report.

Step 301: net and the connection order that at first will delete in the original netlist write ECO modification script.

Need following deletion:

Del_connction n1 register_0/Q (connection between expression deletion register 0Q end and the NET n1)

Del_connction n2 register_1/Q (connection between expression deletion register 1Q end and the NET n2)

Del_connction n3 register_2/Q (connection between expression deletion register 2Q end and the NET n3)

Del_connction n4 register_3/D (connection between expression deletion register 3D end and the NET n4)

del_net?n1；del_net?n2；del_net?n3；del_net?n4。

Step 302: by the NET/CELL/CONNECTION of the comprehensive output report of Program extraction, and related command is write ECO revise script.

The NET that extracts in the consolidated return is:

ECO_NET_n1、ECO_NET_n2、ECO_NET_n3、ECO_NET_n4。

The CELL that extracts is:

ECO_CELL_U1。

The CONNECTION that extracts is:

The A1Pin of ECO_NET_n1 and ECO_CELL_U1 is connected,

The A2Pin of ECO_NET_n2 and ECO_CELL_U1 is connected,

The A3Pin of ECO_NET_n3 and ECO_CELL_U1 is connected,

The Z Pin of ECO_NET_n4 and ECO_CELL_U1 is connected.

By the above behavior of new_net/new_cell/new_connection command description and write several ECO and revise scripts.

Step 303: its front and back level register in the net table of input and output name identification by the ECO module, its NET name in comprehensive ECO module is set up being connected of NET and front and back level register, and its action is written to ECO modification script by order line.

For example:

The input of ECO module is called register_0, the ECO_NET_n1 by name of the NET in its module, being connected of Q Pin of then setting up ECO_NET_n1 and register_0 by the modifiers order;

The output of ECO module is called register_3, the ECO_NET_n4 by name of the NET in its module, being connected of D Pin of then setting up ECO_NET_n4 and register_0 by the modifiers order;

By that analogy.

The present invention will manually search CELL originally, hand drawn ECO circuit, and the flow process of manually writing the ECO script, what become that the present invention proposes writes ECO RTL, automatically generates the new technological process of ECO script; Write the RTL module that ECO uses by treating the method that ECO RTL is extracted into module; By using needed all the NET information of synthesis tool output ECO, all CELL information and all CONNECTION information; The information exchange that comprehensively obtains is crossed the mode of describing in the literary composition to be become ECO and automatically revises script.The present invention has following beneficial effect: 1, robotization, and the time is fast, does not need the manual drawing logical circuit; 2, efficient is high, automatically revises; 3, make mistakes less, as long as the RTL code does not have mistake, revise and once pass through; 4, applied widely, for temporal constraint being arranged or not increasing any difficulty than the net table ECO of complicated circuit.

Claims (1)

1. realize the method for robotization ECO net table in the digital IC design cycle, it is characterized in that: comprise the steps:

Step 100: in original circuit, extract and treat the ECO digital circuit, use RTL to describe the ECO digital circuit; Specifically comprise the steps:

Step 101: at first in ifq circuit is described, find out all input registers for the treatment of the ECO logic;

Step 102: and then in ifq circuit is described, find out all output registers for the treatment of the ECO logic;

Step 103: use the RTL describing module, and with the input of all input registers as module, with the output of all output registers as module, and its name stipulated, make its name and register name identical;

Step 104: in the module that RTL describes, code revision is become logical description behind the ECO;

Step 200: be used for generating the report that ECO revises script by eda tool output; Specifically comprise the steps:

Step 201: at first use the RTL code after eda tool reads in ECO;

Step 202: in eda tool, specify the standard cell lib that uses;

Step 203: specifying needs satisfied temporal constraint;

Step 204: the naming rule of specifying NET/CELL when comprehensive;

Step 205: use eda tool to carry out comprehensively, the RTL logical description is converted to the gate level netlist that the door in the Application standard cell library is described;

Step 206: use the report output order in the eda tool, export following report: all NET information, all CELL information, all CONNECTION information;

Step 300: use the synthesis tool output report to generate ECO and revise script, specifically comprise the steps:

Step 301: net and the connection order that at first will delete in the original netlist write ECO modification script;

Step 302: by the NET/CELL/CONNECTION of the comprehensive output report of Program extraction, and related command is write ECO revise script;

Step 303: its front and back level register in the net table of input and output name identification by the ECO module, its NET name in comprehensive ECO module is set up being connected of NET and front and back level register, and its action is written to ECO modification script by order line.

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