CN108920825A - A kind of SoC visual data manager based on IP kernel - Google Patents
A kind of SoC visual data manager based on IP kernel Download PDFInfo
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- CN108920825A CN108920825A CN201810710817.6A CN201810710817A CN108920825A CN 108920825 A CN108920825 A CN 108920825A CN 201810710817 A CN201810710817 A CN 201810710817A CN 108920825 A CN108920825 A CN 108920825A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The present invention provides a kind of SoC visual data manager based on IP kernel, and the visual data manager includes：Product specification and design tool create system, and the IP-XACT encapsulation of IP kernel visualizes circuit design and self routing, generates rtl code, emulate before simulating, verifying, plate planning, post-simulation and physical verification etc., flow.The present invention completes the design of imitative circuit before RTL level using visual edit mode, and then export as the rtl code of hardware description language, it avoids writing rtl code manually, it is greatly improved the speed and efficiency of circuit design, while being decreased due to directly writing RTL code bring grammer or capability error.
Description
Technical field
The invention belongs to Design of Digital Circuit technical field, in particular to a kind of the visual design side SoC based on IP kernel
Method.
Background technique
So far from the 1990s, a qualitative leap is occurring for IC designed capacity, i.e., from ASIC design method to
The transformation of SoC design method, SoC design method make IC design start further division of labor refinement, the design of IP kernel and SoC system occur
System design, wherein the IP kernel in IP core design may be the IP of enterprises research and development, it is also possible to which third-party IP simply recognizes
For, IP can be interpreted as an ASIC, be to be used on PCB after ASIC is carried out for other in the past, be now IP carry out with
Other is allowed to be integrated in bigger chip afterwards, after integrated circuit develops to the ultra-large stage, the knowledge agglomerated in chip is
Highly concentrated, the transistor integrated on one single chip is more than one hundred million, remain unchanged based single transistor such as fruit chip design rather than
The design of IP-based physical level, is nearly impossible, and IP kernel module abundant library is rapidly design specialized integrated circuit
It dominates the market with monolithic system and as early as possible and provides basic guarantee, reusable IP kernel can be divided into three classes substantially, and soft core is consolidated
Core and stone, soft core generally realized with rtl description, its advantages be there is preferable flexibility and reusability, the disadvantage is that
The optimization of silicon wafer grade and verifying were not carried out；Stone is provided only to user function model and physical routing model for functional verification
And back-end realization, the realization of true domain are generally supplied to chip foundries by IP supplier, Gu core between soft core and stone it
Between
Currently, some eda tools can help us to complete using the high-level languages such as C and C++ or Hardware Description Language VHDL
Deng the advanced algorithm model and simulation model of creation whole system, there are these advanced algorithm models, software and hardware can be obtained
Executable needed for collaborative simulation to illustrate document, for the module that needs redesign, designer needs to redesign, for
Reusable IP kernel, is typically due to that bus interface standards are inconsistent to need to make certain modification, since SoC design includes system knot
Structure design（Also referred to as architecture design）, software structure design and ASIC design（Hardware design）Deng SoC design has become very
Complexity, in order to quickly and effectively carry out SoC design, the multiplexing of IP is that SoC design is essential, in traditional SoC design, IP
Core is not due to having a kind of unified bus interface standards, so in most cases, the multiplexing of IP kernel is in fact frequently necessary to repair
Change, certain workload is brought to circuit designers, even for reusable IP kernel, due to the complexity of SoC design, using big
Measure reusable IP kernel carry out circuit function build and a very cumbersome thing, highly dependent upon circuit designers
Design experiences and understanding level etc. to hardware description language, the code of a large amount of RTL level is for later exploitation and dimension
Shield is also a very cumbersome event, for this purpose, the present invention proposes a kind of SoC visual data manager based on IP kernel.
Summary of the invention
It is of the existing technology in order to solve the problems, such as, the present invention provides a kind of the visual design side SoC based on IP kernel
Method, the present invention imitates the design of circuit before completing RTL level using visual edit mode, and then exports as hardware description language
Rtl code, avoid writing rtl code manually, be greatly improved the speed and efficiency of circuit design.
To achieve the goals above, the present invention is to realize by the following technical solutions：A kind of SoC based on IP kernel can
Depending on changing design method, the visual data manager includes the following steps：
Step 1：Product specification and modeling；Function needed for determining system, including the basic input and output of system, rudimentary algorithm need
It asks and the function of system requirements, performance, power consumption, cost and development time etc., the demand of user is converted to and is used to design
Technical documentation, and primarily determine the design cycle of system, definition explanation and specification of product etc. are formulated, then designer's use is built
Mould language models SoC product；
Step 2：Creation system；After the definition explanation or norm-setting of product finish, using high-level languages such as C and C++ or
The advanced algorithm model and simulation model of the creation whole system such as Hardware Description Language VHDL；
Step 3：The IP-XACT of IP kernel is encapsulated；The encapsulation of IP-XACT format, IP-XACT conduct are carried out to existing IP kernel bank
IP kernel encapsulation unified standard, have it is very strong compatibility and flexibility, IP-XACT by the way of XML to IP kernel into
Row encapsulation, the relevant source file of IP kernel occurs in xml in the form of a link, and relevant numerous source files of IP kernel itself are not
There is any association with XML, since this completely self-contained IP kernel source file system does not need to do any change, so that it may convenient
It is quoted and is used by XML, so that the encapsulation of IP-XACT has stronger independence and flexibility, the circuit designers also made exist
On the basis of original file system add IP-XACT encapsulation without to original file system make it is any modification become can
Can, after being encapsulated to the IP kernel of original file system using IP-XACT, because IP-XACT by the way of VLNV, passes through
IP kernel after encapsulation all has uniqueness, and can further classify to all IP kernels, i.e. the IP of Component type
Core, the IP kernel of Bus type and the IP kernel of Design type, classify different types of IP kernel, it is therefore an objective to visual doing
When changing circuit design, it can more easily remove to search certain type of IP kernel and carry out circuit to further facilitating us and set
Meter, conveniently manages and maintains IP kernel bank；
Step 4：Visualize circuit design and self routing；All IP kernels are managed in the way of VLNV and with tree
The mode of figure is shown, and then, desired IP kernel is dragged in master editor's frame in a manner of pulling, then carries out automatic cloth
Line, to quickly finish circuit design；
Step 5：Generate rtl code；After circuit design finishes, patterned circuit design is exported as into Hardware description language
The form of speech；
Step 6：Simulating, verifying；Then the circuit for generating RTL level is subjected to simulating, verifying, thus rtl circuit imitative before completing
Quick design, the rtl circuit write in the rtl circuit and conventional circuit design of generation can also be emulated respectively and be tested
Card, and then the consistency of contrast verification function complete the linking with conventional circuit design process；
Step 7：Flow；After ensuring that simulating, verifying meets Product Definition explanation, gives wafer foundries and carry out foundry flow.
As a kind of preferred embodiment of the invention, also need to carry out laying out pattern rule before simulating, verifying in the step 6
It draws, power consumption analysis, Time-Series analysis.
As a kind of preferred embodiment of the invention, the IP-XACT encapsulation of IP kernel includes mainly to bus in the step 3
The IP-XACT of interface is encapsulated, component（Component）Encapsulation, and to IC design（Design）Encapsulation.
As a kind of preferred embodiment of the invention, description language is Verilog or VHDL in the step 5.
As a kind of preferred embodiment of the invention, the modeling language in the step 1 is UML, SysML and SystemC
Deng.
As a kind of preferred embodiment of the invention, VLNV is in the step 3（Vender, Library, Name,
Version）.
As a kind of preferred embodiment of the invention, the simulating, verifying includes preceding emulation and post-simulation.
Beneficial effects of the present invention are：
1, the present invention imitates the design of circuit before completing RTL level using visual edit mode, and then exports as hardware description
The rtl code of language avoids writing rtl code manually, is greatly improved the speed and efficiency of circuit design, while
Reduce due to directly writing RTL code bring grammer or capability error；
2, it using the design cycle after the visual data manager of the IP kernel based on IP-XACT, is equivalent in traditional design
Increase several steps among process, on the one hand, in view of most of circuit designers have making for traditional circuit design flow
With habit problem, the step of increase, does not need designer and modifies its original design cycle, allow designer be easy to receive it is new
Design cycle, on the other hand, new design cycle increases several steps in original design cycle, original not changing
While design cycle, verifying can be compared with original design cycle, this inherently can to one kind of new process
By the inspection of property；
3, the present invention can provide the platform of high efficient and reliable for a large amount of IP kernel banks of management service, based on the management to IP kernel bank,
The present invention provides visual IC design platform, what designer can be convenient carries out visualization IC with the IP kernel in IP kernel bank
Design, visualization IC, which has been designed significantly, reduces the IC design cycle, in addition, the present invention also provides the browsing function of RTL netlist,
Designer can be convenient quick reading and understanding RTL netlist.
Detailed description of the invention
Fig. 1 is a kind of SoC visual data manager flow chart based on IP kernel.
Fig. 2 is a kind of visual data manager flow chart of IP kernel based on IP-XACT.
Specific embodiment
To be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below with reference to
Specific embodiment, the present invention is further explained.
Fig. 1 to Fig. 2 is please referred to, the present invention provides a kind of technical solution：A kind of the visual design side SoC based on IP kernel
Method, the visual data manager include the following steps：
Step 1：Product specification and modeling；Function needed for determining system, including the basic input and output of system, rudimentary algorithm need
It asks and the function of system requirements, performance, power consumption, cost and development time etc., the demand of user is converted to and is used to design
Technical documentation, and primarily determine the design cycle of system, definition explanation and specification of product etc. are formulated, then designer's use is built
Mould language models SoC product；
Step 2：Creation system；After the definition explanation or norm-setting of product finish, using high-level languages such as C and C++ or
The advanced algorithm model and simulation model of the creation whole system such as Hardware Description Language VHDL；
Step 3：The IP-XACT of IP kernel is encapsulated；The encapsulation of IP-XACT format, IP-XACT conduct are carried out to existing IP kernel bank
IP kernel encapsulation unified standard, have it is very strong compatibility and flexibility, IP-XACT by the way of XML to IP kernel into
Row encapsulation, the relevant source file of IP kernel occurs in xml in the form of a link, and relevant numerous source files of IP kernel itself are not
There is any association with XML, since this completely self-contained IP kernel source file system does not need to do any change, so that it may convenient
It is quoted and is used by XML, so that the encapsulation of IP-XACT has stronger independence and flexibility, the circuit designers also made exist
On the basis of original file system add IP-XACT encapsulation without to original file system make it is any modification become can
Can, after being encapsulated to the IP kernel of original file system using IP-XACT, because IP-XACT by the way of VLNV, passes through
IP kernel after encapsulation all has uniqueness, and can further classify to all IP kernels, i.e. the IP of Component type
Core, the IP kernel of Bus type and the IP kernel of Design type, classify different types of IP kernel, it is therefore an objective to visual doing
When changing circuit design, it can more easily remove to search certain type of IP kernel and carry out circuit to further facilitating us and set
Meter, conveniently manages and maintains IP kernel bank；
Step 4：Visualize circuit design and self routing；All IP kernels are managed in the way of VLNV and with tree
The mode of figure is shown, and then, desired IP kernel is dragged in master editor's frame in a manner of pulling, then carries out automatic cloth
Line, to quickly finish circuit design；
Step 5：Generate rtl code；After circuit design finishes, patterned circuit design is exported as into Hardware description language
The form of speech；
Step 6：Simulating, verifying；Then the circuit for generating RTL level is subjected to simulating, verifying, thus rtl circuit imitative before completing
Quick design, the rtl circuit write in the rtl circuit and conventional circuit design of generation can also be emulated respectively and be tested
Card, and then the consistency of contrast verification function complete the linking with conventional circuit design process；
Step 7：Flow；After ensuring that simulating, verifying meets Product Definition explanation, gives wafer foundries and carry out foundry flow.
As a kind of preferred embodiment of the invention, also need to carry out laying out pattern rule before simulating, verifying in the step 6
It draws, power consumption analysis, Time-Series analysis.
As a kind of preferred embodiment of the invention, the IP-XACT encapsulation of IP kernel includes mainly to bus in the step 3
The IP-XACT of interface is encapsulated, component（Component）Encapsulation, and to IC design（Design）Encapsulation.
As a kind of preferred embodiment of the invention, description language is Verilog or VHDL in the step 5.
As a kind of preferred embodiment of the invention, the modeling language in the step 1 is UML, SysML and SystemC
Deng.
As a kind of preferred embodiment of the invention, VLNV is in the step 3（Vender, Library, Name,
Version）.
As a kind of preferred embodiment of the invention, the simulating, verifying includes preceding emulation and post-simulation.
The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention, for this field skill
For art personnel, it is clear that invention is not limited to the details of the above exemplary embodiments, and without departing substantially from spirit of the invention or
In the case where essential characteristic, the present invention can be realized in other specific forms.Therefore, in all respects, should all incite somebody to action
Embodiment regards exemplary as, and is non-limiting, the scope of the present invention by appended claims rather than on state
Bright restriction, it is intended that including all changes that fall within the meaning and scope of the equivalent elements of the claims in the present invention
It is interior.Any reference signs in the claims should not be construed as limiting the involved claims.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped
Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should
It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
The other embodiments being understood that.
Claims (7)
1. a kind of SoC visual data manager based on IP kernel, which is characterized in that the visual data manager includes following step
Suddenly：
Step 1：Product specification and modeling；Function needed for determining system, including the basic input and output of system, rudimentary algorithm need
It asks and the function of system requirements, performance, power consumption, cost and development time etc., the demand of user is converted to and is used to design
Technical documentation, and primarily determine the design cycle of system, definition explanation and specification of product etc. are formulated, then designer's use is built
Mould language models SoC product；
Step 2：Creation system；After the definition explanation or norm-setting of product finish, using high-level languages such as C and C++ or
The advanced algorithm model and simulation model of the creation whole system such as Hardware Description Language VHDL；
Step 3：The IP-XACT of IP kernel is encapsulated；The encapsulation of IP-XACT format, IP-XACT conduct are carried out to existing IP kernel bank
IP kernel encapsulation unified standard, have it is very strong compatibility and flexibility, IP-XACT by the way of XML to IP kernel into
Row encapsulation, the relevant source file of IP kernel occurs in xml in the form of a link, and relevant numerous source files of IP kernel itself are not
There is any association with XML, since this completely self-contained IP kernel source file system does not need to do any change, so that it may convenient
It is quoted and is used by XML, so that the encapsulation of IP-XACT has stronger independence and flexibility, the circuit designers also made exist
On the basis of original file system add IP-XACT encapsulation without to original file system make it is any modification become can
Can, after being encapsulated to the IP kernel of original file system using IP-XACT, because IP-XACT by the way of VLNV, passes through
IP kernel after encapsulation all has uniqueness, and can further classify to all IP kernels, i.e. the IP of Component type
Core, the IP kernel of Bus type and the IP kernel of Design type, classify different types of IP kernel, it is therefore an objective to visual doing
When changing circuit design, it can more easily remove to search certain type of IP kernel and carry out circuit to further facilitating us and set
Meter, conveniently manages and maintains IP kernel bank；
Step 4：Visualize circuit design and self routing；All IP kernels are managed in the way of VLNV and with tree
The mode of figure is shown, and then, desired IP kernel is dragged in master editor's frame in a manner of pulling, then carries out automatic cloth
Line, to quickly finish circuit design；
Step 5：Generate rtl code；After circuit design finishes, patterned circuit design is exported as into Hardware description language
The form of speech；
Step 6：Simulating, verifying；Then the circuit for generating RTL level is subjected to simulating, verifying, thus rtl circuit imitative before completing
Quick design, the rtl circuit write in the rtl circuit and conventional circuit design of generation can also be emulated respectively and be tested
Card, and then the consistency of contrast verification function complete the linking with conventional circuit design process；
Step 7：Flow；After ensuring that simulating, verifying meets Product Definition explanation, gives wafer foundries and carry out foundry flow.
2. a kind of SoC visual data manager based on IP kernel according to claim 1, which is characterized in that the step
Also need to carry out laying out pattern planning, power consumption analysis, Time-Series analysis in six before simulating, verifying.
3. a kind of SoC visual data manager based on IP kernel according to claim 1, which is characterized in that the step
The IP-XACT encapsulation of IP kernel mainly includes the IP-XACT encapsulation to bus interface, component in three（Component）Encapsulation, with
And IC is designed（Design）Encapsulation.
4. a kind of SoC visual data manager based on IP kernel according to claim 1, which is characterized in that the step
Description language is Verilog or VHDL in five.
5. a kind of SoC visual data manager based on IP kernel according to claim 1, which is characterized in that the step
Modeling language in one is UML, SysML and SystemC etc..
6. a kind of SoC visual data manager based on IP kernel according to claim 1, which is characterized in that the step
VLNV is in three（Vender, Library, Name, Version）.
7. a kind of SoC visual data manager based on IP kernel according to claim 1, which is characterized in that the emulation
Verifying includes preceding emulation and post-simulation.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112560370A (en) * | 2020-12-21 | 2021-03-26 | 上海逸集晟网络科技有限公司 | Chip design code generation method, terminal and storage medium |
| CN117391002A (en) * | 2023-10-23 | 2024-01-12 | 苏州异格技术有限公司 | IP core extension description method and IP core generation method |
| CN117521587A (en) * | 2024-01-03 | 2024-02-06 | 北京开源芯片研究院 | Design method and device of system-on-chip, electronic equipment and storage medium |
| CN117709259A (en) * | 2024-02-01 | 2024-03-15 | 北京开源芯片研究院 | Chip design method and device, electronic equipment and readable storage medium |
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Application publication date: 20181130 |