CN113657057A - Method for realizing digital circuit load separation by automatic cloning - Google Patents
Method for realizing digital circuit load separation by automatic cloning Download PDFInfo
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- CN113657057A CN113657057A CN202110937522.4A CN202110937522A CN113657057A CN 113657057 A CN113657057 A CN 113657057A CN 202110937522 A CN202110937522 A CN 202110937522A CN 113657057 A CN113657057 A CN 113657057A
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- G06F30/32—Circuit design at the digital level
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Abstract
The invention discloses a method for realizing digital circuit load separation by automatic cloning, which comprises the following steps: step 1, appointing a source unit and a load which need to be copied; step 2, deriving a circuit topological structure of the source unit; 3, the filtering unit removes units which are not on the paths of the source unit and the load unit by using a recursive algorithm to obtain a circuit structure to be copied; step 4, the copying unit copies the filtered unit; step 5, disconnecting the original circuit, and then reconnecting the load unit and the replica circuit in the previous step; step 6, circularly copying a unit of the circuit; and 7, describing the processes from the step 4 to the step 6 by an output unit, and simultaneously outputting a form verification constraint file and an environment setting file required by the copy circuit. The method for realizing the digital circuit load separation by automatic cloning can automatically finish the separation of the load in the circuit realization process, and has the advantages of high reliability, simple realization process and no need of iteration.
Description
Technical Field
The invention discloses a chip and relates to the technical field of chips.
Background
In the physical implementation link of a chip, the integration and layout wiring often suffer from high fan-out or timing non-convergence caused by too far physical distance of different loads. In order to solve the problem, the common method is that in the early stage of logic design, load separation is completed by modifying RTL design by designers, the strategy is to copy the original circuit to obtain a plurality of circuits with the same function, and the circuits are dispersedly connected to the original load so as to remove strong coupling caused by different loads, the disadvantage is that dynamic function verification needs to be carried out again, if the original code needs to be modified due to the design problem, the copied code also needs to be synchronously modified; the design needs to be highly associated with actual physical implementation, the reusability of the design is also influenced, and the quick adjustment difficulty of the complex circuit design is high; when the layout and wiring are finished and enter the Timing ECO stage, if the logic needs to be copied to release the strong coupling among different loads to optimize the time sequence, the conventional process has to be returned to the RTL stage for realization, and the project execution time is also unacceptable. In the chip implementation phase, how to quickly change the original circuit structure by means of performing ECO, i.e., engineering command change on the chip, so as to achieve the purpose of quick timing sequence convergence in the digital circuit implementation process on the premise of ensuring the circuit function correctness is a challenge often faced.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a method for realizing digital circuit load separation by automatic cloning, which solves the problems of high load separation difficulty, low reliability, high verification difficulty and difficulty in realizing complex circuits in the traditional ECO method.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method for realizing digital circuit load separation by automatic cloning comprises the following steps:
step 1, appointing a source unit and a load unit which need to be copied;
3, the filtering unit removes units which are not on the paths of the source unit and the load unit by using a recursive algorithm to obtain a circuit structure to be copied;
step 4, the copying unit copies the filtered unit, the copied unit is completely consistent with the filtered unit, and the environmental constraint of the original circuit is obtained;
step 5, disconnecting the original circuit, including the load unit and the drive unit thereof, and then reconnecting the load unit and the replica circuit in the previous step;
step 6, circularly copying a circuit unit, for a single unit obtained in each circulation, traversing an input port which is not connected with the single unit, and connecting the input port to a corresponding port of an original circuit unit;
and 7, describing the processes from the step 4 to the step 6 by an output unit, writing the processes into commands executable by the EDA tool, namely an ECO script form, and simultaneously outputting a form verification constraint file and an environment constraint file required by a copy circuit by the output unit for realizing use of a subsequent EDA tool.
Further, step 3 specifically includes using the load specified in step 1 in the filtering process, where the filtering process is a backward tracing process, the load is used as a starting point of tracing the circuit structure, and through a recursive algorithm, all circuit structures from the load to the source unit are obtained backward, and units not in the structure are deleted, so as to finally obtain a complete filtered circuit.
Further, the recursive algorithm is specifically: the load unit is acquired first and then the drive unit is acquired, and if the drive unit is not the source unit, the drive unit of the drive unit is acquired until the drive unit is the source unit.
Further, in step 4, the environmental constraints include: the method comprises time sequence constraint information, time sequence exception information and dot _ touch information.
Further, the environmental constraints before and after replication remain consistent.
The invention has the beneficial effects that: the method for realizing digital circuit load separation by automatic cloning has the advantages of simple implementation process and strong operability; the reliability is high, complete replication is carried out based on the topological structure of the original circuit, and ECO logic positioning is accurate; RTL codes do not need to be modified, and reusability is strong; the flexibility is high, and the method can be implemented and finished at any implementation stage of synthesis and layout wiring.
Drawings
FIG. 1 is a general flow chart for practicing the present invention;
FIG. 2(a) is a circuit diagram of an embodiment of a recursive algorithm, and FIG. 2(b) is a flow chart of an embodiment of a recursive algorithm;
FIG. 3 is a schematic diagram of the original circuit structure in the step of obtaining the circuit topology according to the present invention;
FIG. 4 is a filtered circuit configuration of the present invention;
FIG. 5 is a schematic diagram of a replicated unit according to the present invention;
FIG. 6 is a schematic diagram of a copy cell connection display of the present invention;
fig. 7 is a circuit diagram after the present invention is implemented.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings.
As shown in FIG. 1, a method for realizing digital circuit load separation by automatic cloning comprises the following steps of setting a starting point register, namely a source unit, and a destination point register, namely a load unit, of a circuit to be cloned, automatically completing the separation of specified circuit loads by using an EDA tool, automatically analyzing the topological structure and the connection relation of the circuit, and automatically writing an ECO script and environmental constraints. The method comprises the following steps: according to the configuration requirement, a source unit and a load unit thereof which need to be loaded separately are obtained, and then the circuit structures of the source unit and a fan-out unit thereof, namely, the logic circuits from the source unit to the load unit and the paths thereof are obtained through EDA, referring to fig. 3; then, the filtering unit simplifies the original circuit structure, namely a fan-out circuit structure, wherein the simplification method is to delete the circuit structure irrelevant to the separation of the load unit and obtain all units on the path from the source unit to the load unit; copying the filtered circuit, wherein the copying unit creates the filtered circuit, namely copying the same circuit unit, and acquiring the environmental constraint of the original circuit, and the subsequent copied circuit environmental constraint is consistent with the environmental constraint before copying: the environment constraint comprises time sequence constraint information, time sequence exception information, dot _ touch information and the like; separating the load, namely disconnecting the load unit from the original circuit and connecting the load unit with the replica circuit; inquiring an input port which is not connected with the replica circuit, wherein the port which is not connected with the replica circuit is connected to a port corresponding to the original circuit; writing the copying, separating and connecting processes into an ECO script, outputting formal verification constraints, namely matching constraints of a clone unit and a source unit and environment constraints of a copying circuit, and outputting formal verification constraint files for subsequent equivalence verification; and outputting the copy circuit environment constraint file, and executing the ECO script to finish cloning.
A method for realizing digital circuit load separation by automatic cloning comprises the following specific processes:
step 1: the method comprises the steps of firstly, specifying a source unit to be copied and loads thereof, wherein each source unit corresponds to a plurality of load units, the specified load units are connected to a copied circuit, and other load units keep the original circuit structure. The designated source unit is used both to obtain the topology of the circuit and to create a replica circuit, which itself also needs to be replicated, the designated load unit being the end point of the replication. The srcRegA and srcRegB in fig. 3 are designated as source units of the replica circuit, and the dstRegA and dstRegB are designated as load units which need to be separated.
Step 2: deriving a circuit topology of the source unit using an EDA tool, including the source unit, the load unit and all units on its path, as shown in fig. 3, srrega, srcRegB, RegE, RegF are source units, dstRegA, dstRegB, RegC, RegD, RegH, RegK are load units, BlockA, BlckB, blockac, BlckD, blockae, blockaf are fan-out units; the fan-out structures are the complete fan-out structure of the source cells srcRegA, srcReg and the fan-out structure of RegE, RegF, which are shown because the part of the circuit ports that need to be duplicated are driven by them. Because the SRRegA and the SRRegB are far away from the loads dstRegA and dstRegB, the time sequence problem exists in the path, the EDA tool inserts units with strong driving capability and large area in order to repair the time sequence problem, and even changes part of circuit structures, the problems of local density and winding consistency are easily caused; the other source units and load units meet the timing constraint and do not need to be separated, so that the srcRegA and the srcRegB need to be designated as the source units of the clone circuit, and the dstRegA and the dstRegB need to be separated.
And step 3: the filtering unit executing process is as shown in fig. 2(a) and fig. 2(b), the load specified in step 1 is used in the filtering process, the filtering process is a reverse tracing process, the load is used as a starting point of a tracing circuit structure, all circuit structures from the load to a source unit can be reversely obtained through a recursive algorithm, units which are not in the structures are deleted, a complete filtered circuit is finally obtained, meanwhile, the environmental constraint of the filtered circuit is required to be obtained for the copied circuit, and the copied circuit is required to be completely connected according to the original connection relation, so that the copied circuit is ensured to have the same function as the original circuit. In the recursive process, a D port of a load desRegB is initialized as a Sink port, the circuit structure knows that an X port of U4 is a drive of the D port, so that the D port of the desRegB of the copy circuit needs to be connected to the X port of U4, a drive port of the X port of U4 is a A, B, C port of U4, and the circuit structure knows that the B port is not on a source/load path, so that the B port needs to be connected to a B port of an original circuit, a A, C port is on the source/load path, so that an A port of U4 and a C port of U4 are circularly used as Sink ports, and a recursive algorithm is used until the source unit srcRegA is cut. In the recursive algorithm, the load unit dstRegB and the drive unit U4 are acquired first, and if the drive unit is not the source unit, the drive units U2 and U3 of the drive unit U4 are acquired until the drive unit is the source unit srcRegA, and the recursive algorithm is called continuously. Firstly, acquiring that the drive of a load unit dstRegB is an output port X of a U4 unit, acquiring input ports A and C of a U4 unit, and acquiring that a port B of U4 does not belong to the fan-out of a source unit srcRegA; acquiring the drive of the a port of U4 as the X port of U2, acquiring the a port of the input port U2 of U2, acquiring the drive of the a port of U2 as the X port of U1, acquiring the a port of the input port U1 of U1, acquiring the drive of the a port of U1 as the source unit srcRegA, then processing the C port of U4 according to the same algorithm, and finally obtaining the circuit structure from the load unit to the source unit: the algorithm is based on the circuit structure to carry out complete replication, so the replication success rate reaches 100%, and the complexity of the circuit only influences the time of the recursive algorithm.
As shown in fig. 4, the execution result of step 3 is filtered, so that BlockE and BlockF are not in the path from the source unit to the separation load and need to be deleted, and the circuit structure after filtering is in the dashed line box and needs to be copied later.
And 4, step 4: copy cell execution results as shown in fig. 5, the copy cell creates a filtered cell, and the newly created circuit must be identical to the filtered circuit.
And 5, disconnecting the original circuit, including the load unit and the drive unit thereof, and then reconnecting the load unit and the replica circuit in the previous step. Step 5, disconnecting the load unit from the original circuit, and changing the load unit to be connected to the copied circuit, wherein in the figure 6, the dstRegA and the dstRegB are disconnected from the original connection Block B and Block D, and are changed to be connected to the copied Block B 'and Block D'; the connections within the replica circuit are made according to the original circuit connections, as in the following connection scheme in fig. 6: srcRegA 'is linked to BlockA', BlockA 'is linked to BlockB', srcRegB 'is linked to BlockC', and BlockC 'is linked to BlockD'.
Step 6, circularly inquiring the newly created unit, traversing the input port which is not connected with the newly created unit, and having no logic to drive the port because the source driving logic is not in the copy list, and in order to ensure consistency of functions before and after the ECO, connecting the newly created unit to the corresponding port of the original circuit unit, step 6 adopting a circular judgment to clone the port of the circuit unit, finding out the port which is not connected with the newly created unit, such as the port which is connected with a dotted line in fig. 6, wherein the dotted line indicates that the driving of the newly created unit is not in the fan-out circuit of the source unit, and the port which is connected with the corresponding port of the original circuit unit is required to be connected, and the dotted line is connected to BlockA ', BlockB', and BlockC 'BlockD'.
Creating a unit to copy a filtered circuit, wherein the step needs complete and unique copying, incomplete copying results in inconsistent functions, and repeated copying results in multiple driving problems, which all result in ECO failure; the copying unit copies the filtered circuit, and srcRegA ', srcRegB', Block A ', Block B', Block C 'and Block D' in FIG. 6 are the copying circuits of srcRegA, srcRegB, Block A, Block B, Block C and Block D in FIG. 3.
And 7: and the output unit writes an ECO script, a formal verification constraint file and an environment setting file required by the copy circuit, which are described in the process, for the realization of a subsequent EDA tool. The ECO script written in the step 7 is executed to complete the ECO process, and the executed circuit is shown in FIG. 7,
the copied circuits are connected, all input ports of Block A ', Block B', Block C 'and Block D' in the graph 7 are connected in the same mode as the original circuit, and the input ports of srcRegA 'and srcRegB' are connected with the input ports of the source units srcRegA and srcRegB, so that the copied circuits and the original circuit are guaranteed to be in the same function, and the dstRegA and the dstRegB are successfully separated from the original circuit.
It should be noted that the terms "upper", "lower", "left", "right", "front", "back", etc. used in the present invention are for clarity of description only, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not limited by the technical contents of the essential changes.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (5)
1. A method for realizing digital circuit load separation by automatic cloning is characterized in that: the method comprises the following steps:
step 1, appointing a source unit and a load unit which need to be copied;
step 2, using EDA tool to derive the circuit topological structure of the source unit, including the source unit, the load unit and all units on the path;
3, the filtering unit removes units which are not on the paths of the source unit and the load unit by using a recursive algorithm to obtain a circuit structure to be copied;
step 4, the copying unit copies the filtered unit, the copied unit is completely consistent with the filtered unit, and the environmental constraint of the original circuit is obtained;
step 5, disconnecting the original circuit, including the load unit and the drive unit thereof, and then reconnecting the load unit and the replica circuit in the previous step;
step 6, circularly copying a circuit unit, for a single unit obtained in each circulation, traversing an input port which is not connected with the single unit, and connecting the input port to a corresponding port of an original circuit unit;
and 7, describing the processes from the step 4 to the step 6 by an output unit, writing the processes into commands executable by the EDA tool, namely an ECO script form, and simultaneously outputting a form verification constraint file and an environment constraint file required by a copy circuit by the output unit for realizing use of a subsequent EDA tool.
2. The method according to claim 1, wherein in step 3, the load specified in step 1 is used in a filtering process, the filtering process is an inverse tracing process, the load is used as a starting point of tracing a circuit structure, all circuit structures from the load to a source unit are reversely obtained through a recursive algorithm, units not in the structures are deleted, and finally a complete filtered circuit is obtained.
3. The method according to claim 2, wherein the recursive algorithm is specifically: the load unit is acquired first and then the drive unit is acquired, and if the drive unit is not the source unit, the drive unit of the drive unit is acquired until the drive unit is the source unit.
4. The method of claim 2, wherein in step 4, the environmental constraints include: the method comprises time sequence constraint information, time sequence exception information and dot _ touch information.
5. The method of claim 1, wherein the environmental constraints before and after copying are consistent.
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| CN115048887A (en) * | 2022-06-21 | 2022-09-13 | 深圳国微芯科技有限公司 | Processing method, verification method and storage medium of implementation circuit with gating clock |
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