JPS61151782A - Formation of logic operation circuit - Google Patents

Abstract

PURPOSE:To hold a logic equivalent characteristic by changing partially these when higher rank hierarchical data and lower rank hierarchical data are changed by a design change, in the system having multi hierarchical circuit data. CONSTITUTION:When higher rank hierarchical data 100 are changed to lower rank hierarchical data 300 by the design change, logic comparison is executed. Namely, first, an identifying code ID2 is checked concerning overs and shorts of an identifying code, and second, identifying codes ID1 and ID3 are checked concerning overs and shorts of the input output signal of a logical set. Third, a pool system comparison of an output signal of a logic set is executed, the logic set of the code ID1 is logically equivalent, and the logical set of ID3 is verified to be dissident logically. Thus, the logic set of the lower rank hierarchical logic having the code ID1 is preserved, the logic set of the lower rank hierarchical logic having the code ID2 is deleted and the logical set having the code ID3 is redeveloped and replaced from the higher rank hierarchical logic. Thus, by changing partially, the logic equivalent characteristic can be kept.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logic design system for a digital logic device, and in particular to a logic circuit suitable for comparing upper and lower hierarchical logic and automating updating when changing the design in hierarchical logic design. Regarding data creation methods.

[Background of the invention]

In the manufacturing of semiconductor integrated circuits and printed circuits, in order to give the semiconductor integrated circuit the desired functionality, a process is necessary to decide what kind of circuit elements to combine, how to combine them, and how to arrange them. be done. After this step, various types of masks are created based on the data created in this step.

In creating this data, two-layer data is created. One is the upper layer, which is data representing the logical functions of the semiconductor integrated circuit as a collection of functional blocks expressed in a pool format.

The other one is the lower hierarchy, which is created based on the upper hierarchy data, and is data indicating combinations of circuit elements.

By the way, in order to check whether the upper layer data has been expanded correctly to the lower layer data, and when the upper layer data is changed due to design changes or logic changes due to the result of checking the signal delay amount based on the lower layer data, In order to change the lower layer data, it is necessary to know the correspondence between the upper layer data and the lower layer data.

Regarding the above change, it is not necessary to know the correspondence if all the upper layer data is converted back to lower layer data. However, generally, the lower layer data includes layout information such as component names, mounting position information, pin numbers, etc. added to the data converted from the upper layer data. If all the upper layer data is converted again, not only this conversion operation but also an operation of re-applying layout information is required. Therefore, it is desirable to partially convert only the parts where changes have occurred.

Conventionally, because the notation methods for upper layer data and lower layer data are different, signal names were also assigned using different systems. Therefore, in order to establish a correspondence between the upper layer data and the lower layer data, a correspondence table between the signal names in the upper □ layer data and the signal number 2 names in the lower layer data has been manually created.

However, it takes a lot of effort to create this correspondence table, and the process of finding correspondences between functional blocks from the correspondence table is difficult, and furthermore, when the signal names change, the correspondence table must be re-created. There are issues such as necessity.

Regarding automatic design, Japanese Patent Publication No. 56-42005 is known.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned problem, and when upper layer data and lower layer data are changed due to design changes in a system having multi-layer circuit data, these logics can be corrected by partially changing them. The objective is to provide a method for maintaining homodominance.

[Summary of the invention]

In the present invention, the correspondence between each functional block of the upper layer data and the corresponding logical M data of the lower layer data is checked, and the portion where the lower layer data should be recreated is determined for each function block. It is now possible to partially modify lower layer data.

[Embodiments of the invention]

FIG. 1 shows an example of a portion of upper layer data, and FIG. 2 shows a portion of lower layer data corresponding to FIG. 1.

In Fig. 1, 100 represents the upper layer logic, and 101 to
Box 103 represents a pool-type logical set. A-F
, U-Y represent the input and output signal names of the logical sets 101 to 103, respectively. Here, logical sets 101, 102
, 103 include identification codes ID1., 103 for identifying logical sets according to the present invention. ID2 and ID5 are given.

Reference numeral 200 in FIG. 2 represents lower hierarchy logic expanded from the upper hierarchy logic 100 in FIG. Here, 201~
Reference numeral 207 indicates a gate, and A-F and U-Y indicate input/output signal names corresponding to FIG. The same identification name is given to equivalent signals in upper layer data and lower layer data. ID1 to ID5 given below the gates 201 to 207 are identification codes indicating correspondence with the upper layer logic in FIG. 1. Although not shown here, the signals generated inside the logic set after it is expanded to the lower layer logic (lines connecting 203 and 204 and 205 and 206 in FIG. 2)
must be named using a naming convention that allows them to be easily distinguished from input/output signals of logical sets. In FIG. 2, mounting position information indicated within 0 is also provided. Here, a method of logical comparison between upper and lower hierarchies will be explained. Logical comparison is performed in the following three steps.

1st step: Check for excess or deficiency of identification code (the logic element with the identification code that exists in 100 is present in 200.1
200 has a logic element with an identification code that does not exist in 00. ) 2nd step: Check for excess or deficiency of input/output signals of the logic set (whether there is excess or deficiency of the input/output signals between the matched function blocks and logic elements) 3rd step: Output of the logic set Pool comparison of signals (1
(The logic element in 200 with the identification code present in 00 has the same pool type function as the pool type represented by 100.) Next, due to design changes etc., logic correspondence between upper and lower hierarchies is no longer possible. Let's discuss an example. 300 in FIG. 3 is the upper layer logic, and 301 to 303 are the boo'' formula (7)! [set wo, A, B, E-H, U, V.

Y and Z represent the output/power signalers of the logical sets 301 to 303. 400 in FIG. 4 is the upper layer logic 3 in FIG.
Represents the lower hierarchy logic expanded from 00, 401 to 40
7 is the gate, A, B, E-H, U.

V, Y, and Z indicate signal names corresponding to FIG. From the identification code given in Figures 3 and 4, 1, ID3
, ID4 are according to the present invention. Now, let's consider a case where logic equivalence was guaranteed by the relationship between Figures 1 and 2 mentioned above, but the upper layer logic was changed from Figure 1 to Figure 3 due to a design change. . If we attempt the above-mentioned 5-step logical comparison using FIG. 3 as the upper layer and the second Fg5 as the lower layer, we will find that in the first step: there is an excess or deficiency in the identification code. Identification code ID2 (gates 203 to 20
6) is excessive and ID4 (no applicable gate) is insufficient.

Second step: Identification code ID1. We have taken action regarding ID5. (Both 100 and 200 exist). Here, there is no excess or deficiency of input/output signals. That is, ID1
The logical set of is A, B.

The signals U and V are E and F in the logical set of ID3.

The Y signals correspond to each other, including the input/output classification.

Third step: The logical set of identification code ID1 is logically equivalent, but the logical set of identification code ID3 is logically inconsistent. That is, the output signal U=A−B of the logical set of ID1
and V=A+B correspond in FIG. 3 and FIG. 2, but the output signal Y of the logical set of ID3 is E■F in FIG. 3, but it is E■F in FIG.

In this way, the first to third steps can be used to verify the logical equivalence of each logical set. Based on this, in order to guarantee the upper layer logic as true, the identification code I
The logical set of the lower hierarchical logic with ID D1 is saved, the logical set of the lower hierarchical logic with the identification code ID2 is deleted, and the logical set with the identification code ID3 is redeployed from the upper hierarchical logic (gate 403 in FIG. 4, 404) and replace it, and expand the logical set with identification code ID4 from the upper layer logic (
Gates 405 to 407 in FIG. 4 are generated) and added.

In this case, after expanding to the lower level logic before updating, if no manual logic optimization or addition of layout information has been performed, the entire logic set may be expanded again. but,
If information that you do not want to lose, such as the mounting information shown in parentheses in Figures 2 and 4, such as layout information, is added, the above procedure should be taken. (Gates 201 and 202 in Figure 4, Gates 401 and 40 in Figure 4)
2) can be saved with additional information. The mounting information in this example is a number assigned to an area obtained by dividing a semiconductor integrated circuit board into squares.

The above-mentioned means for comparing logic between upper and lower hierarchies and means for updating lower-layer logic using upper-layer logic as a mask will be explained as computer data processing with reference to FIGS. 5 to 8.

5, 6, and 7 show tables created on the main memory, and FIG. 8 shows a processing flow executed under the control of a program in a computer.

FIG. 5 is a table created regarding upper layer logic data, which is stored on the storage medium of the upper layer logic. In FIG. 5, reference numeral 501 is an identification code table, in which all identification codes of upper layers are arranged in a fixed order. A signal name table 502 is registered including the input/output classification of the signal, and is pointed from the identification code of the corresponding logical block in the identification code table 501.

503 is a pool type table, and identification code table 5
Pointing is performed from the output signal of 02, and a pool expression representing the output is registered for each output signal.

! 61ffl is a table created regarding lower layer logic data, and is stored on the storage medium of the lower layer logic. In FIG. 6, 601 is an identification code table, in which all identification codes of lower hierarchy logic are arranged in a fixed order. 6
02 is a component name table in which as many components as the components used in the lower hierarchy logic are registered, and are pointed from the identification code table 601. In the lower hierarchy, there may be multiple parts with the same identification code, so one identification code is pointed to multiple part names. 603 is a bin table in which all pins (signals IIjI) used in lower layer logic are registered including input/output classifications indicating whether they are inputs or outputs for the component; Pointing is performed from the component name that has the pin in the component name table. 604 is a signal name table in which all input/output signals and internal signals are registered. In addition, information on classification of whether the signal is an input signal or an output signal for the functional block to which the original jlJ code is given in the upper layer data is stored. Reference numeral 605 is a link table in which link information between the signal name table 604 and pin table 605 is registered in order to establish a correspondence between signal names and component pins across all lower layer logic, and pointing is performed using the link pointer of the signal name table 604. has been done. This is to search for the pin number from the signal name. Except for the input and output ends of the functional block, one signal passes through at least two pins. The addresses of the bin table 603 for all pins related to the signal are stored in the position addressed by the link pointer of the link information 605. On the other hand, the address of the component name table 602 of the component name related to the signal is also stored. 606 is a pool formula table in which pool formulas viewed from output signals are registered, and are pointed from the output signals of the signal name table 604.

FIG. 7 is a table of parts, which is created from the storage medium of the parts library. In FIG. 7, reference numeral 701 is a component name table, in which component names are registered as many as the types of components used in the lower hierarchy logic. Reference numeral 706 is a pool formula table, in which the logical functions seen from the output pins of the components in table 701 are registered as input pin pool formulas.

5, 6, and 7, excluding the function block input/output classification column of the signal name table 604 and the table 606, it is created by sequentially reading the upper layer data and writing it in the corresponding column. be done. The function block input/output classification column of the signal name table 604 is created as follows. The signal names in the signal name table 604 are read out in order, and the following processing is performed for each signal name. The link information 605 is read from the link pointer corresponding to the signal name, and the table 603 is searched according to the address of the total pin number table registered therein to check its input/output classification. As a result, if there is only an output pin, the signal name is an output signal of a certain functional block, so information indicating the output is stored in the input/output classification column of the table 604. If there is only an input pin, the signal name is an input signal of a certain functional block, so information indicating the input is stored in the input/output category column of the table 604. If input pins and output pins coexist, nothing is written to the table 604 because the names are signals within a certain functional block.

Next, creation of table 606 will be explained.

The following processing is performed for the signal name whose input/output classification is output in the table 604. Read the link information 605 using the link pointer, read the table 602 for all the part name addresses registered here, index the table 701 according to this part name, read the table 703 with the address obtained as a result, and express the function of the part. Get the pool formula. This is stored in a work area not shown. Next, the pin number is indexed from the same link information 605, and the signal name is thereby indexed. If the signal name is different from the previous one, the component name is again determined from the table 602 based on the link information 605, and from this a pool expression indicating the function of the component is determined and combined with the pool expression stored in the previous work area. This process is shown in table 60.
Step 4 is repeated until the signal name that has classification information with the input is reached. As described above, it is possible to obtain a pool expression in which a certain output signal of a certain functional block is represented by an input signal of that functional block, and this is stored in the table 606.

The above processing is performed for all signal names to which information indicating output is given in table 604. Next, execution of logical comparison will be explained. The above-mentioned check for excess or deficiency of identification codes in the first step is performed by comparing the identification code table 501 of FIG. 5 with the identification code table 601 of FIG. 6.

In the second step, the input/output signal excess/deficiency check is performed using Table 5 for the identification codes found to exist in both the upper layer logic and the lower layer logic by the check in the first step.
This is done by comparing signal names in table 604 with signal names in table 604.

The pool expression comparison of the output signals in the fifth step is performed by comparing the pool expression of table 503 pointed from the signal name of the output category of table 502 and the signal of the output category of table 604 for the identification codes whose all signal names matched in the second step. This is done by comparing the pool expressions in table 606 pointed to by the name.

For comparison between pool type and pool type, please refer to “Bina
ry f)gcizziorLDiagrawz J
by 5hadonB.

Akarz, 1978 IEEE.

Next, the procedure for updating the lower layer logic using the upper layer logic as a mask will be explained using FIG.

FIG. 8 is a flowchart showing the update procedure, 801
and 811 are terminals, 802, 805 to 807 and 810
803, 804, 808, and 809 indicate processing, and 803, 804, and 809 indicate determination.

When the upper layer data is changed due to a design change or the like, the following processing is performed using the tables shown in FIGS. 5 and 6 described above.

Processing is started (801).

A new identification code is extracted from the upper layer (802).

Determine whether or not there is the identification code in the lower layer, and if there is, 80
If not, the process branches to 807 (803). ``When it is determined that the input and output signal names of the logical set are the same,
Then, it is determined whether the pool expressions of the output signals are equivalent, and if they are equivalent, the process branches to 805, and if they are not equivalent, the process branches to 806 (8
04). If they are equivalent, the logical set in the upper layer is unchanged, so the logical set in the lower layer is saved (a
OS). When it is determined that they are not equivalent, the logical set in the upper layer has been changed, so the logical set is redeployed from the upper layer to replace the logical set in the lower layer (806
). When it is determined in step 803 that there is no identification code in the lower layer, the logical set in the upper layer has been added, so the logical set is redeployed from the upper layer and added to the lower layer (807).

Next, check whether all the upper layer identification codes have been processed. a
Oa), if all have been processed, the process branches to 809; if there are any remaining, the process branches to 802.

If all have been processed, it is determined whether there is an identification code in the lower layer that does not correspond to the upper layer (809), and if there is, the process branches to 810, and if not, the process branches to 811.

If there is, the functional block with that identification code in the upper layer has been deleted, so all the corresponding data in the lower layer is deleted (ela). Although the determination in step 809 is NO, when the process in step 81o is finished, the process for modifying the lower layer data is finished (step 811).

In this way, when the upper layer logic is changed, the update of the lower layer logic can be limited to only the logical sets that are involved in the change, and the logical sets that are not related to the change can be saved as they are. Such partial updating of lower hierarchy logic is very effective in preventing re-addition work when logic optimization and layout information have been manually added after development from the upper hierarchy.

Finally, we will explain the expansion from the upper hierarchy logic to the lower hierarchy logic and the operation of design changes using the upper hierarchy logic as the master after the existence of the upper and lower hierarchy logics.

FIG. 9 is an operational flow diagram when creating the lower layer logic for the first time after the upper layer logic is created.

゛In the figure, 9oO is a design file 901 that stores upper layer logic (corresponding to the logic shown in Figure 1 above).
902 is a design file storing lower level logic (corresponding to the logic shown in FIG. 2), and 902 is an expansion process.

Logic set 10 of upper layer logic 100 as shown in FIG.
1, 102, and 105 have identification names ID1. ID2゜ID
The data of the upper layer logic created by adding 3 is stored in the design file 900. The upper layer logic data is read and evaluated through logic simulation, and the data is changed according to the evaluation as the case may be. Next, using the upper layer logic data stored in the design file 900, configuration data of the lower layer logic 200 as shown in FIG. 2 is created through a development process 902. During this expansion, the identification codes (ID1, ID2, ID3) are also
It is propagated and expanded to 0 data. The created lower hierarchy logical data is stored in the design file 901. The lower layer logic data of the design file 901 is read out, the delay time of signal propagation is calculated, and the data is changed as necessary.

FIG. 10 is an operational flowchart of a design change in which the upper layer logic becomes the master after the upper and lower layer logic data is created. In the figure, 95o is a design file that stores upper layer logical data updated due to design changes, 951 is a design file that stores lower layer logical data before design changes, and 95
4 is a design file 95 in which upper layer logical data is stored.
A work file that stores lower layer logical data created by partially expanding only the logical set with the identification code whose design has been changed (added, changed) from 0, 956 is a design that stores the updated lower layer logical data. It is a file. Also,
952 is a comparison process for comparing the upper level logical data after the update of the design file 950 and the lower hierarchy logical data before the update of the design file 951; 953 is a comparison process of the design file 950
This is an expansion process that partially expands only the logic set with the design-changed identification code in the upper layer logic after the update.

Reference numeral 955 is a comparison/merging process in which the identification codes that do not match are received from the comparison process 952, the logical set of matching identification codes is also received from the design file 951, and the logical set of identification codes that are not matching are sequentially received from the work file 954. This is a merging process in which the two files are merged. First, in a comparison process 952, by comparing the updated upper layer data and the lower layer logical data before the update, the logic set whose design has been changed is recognized by an identification code (upper layer logic shown in FIG. 1). 1
If 00 is changed to the upper layer in FIG. 3, logic 300, ID1 is the identification code to be saved.
D2 is recognized as an identification code to be deleted, ID3 is recognized as an identification code to be changed, and ID4 is recognized as an identification code to be added. ) In the expansion process 953, the identification code that is inconsistent is received from the comparison process 952, and only the logical set having the design-changed identification code is partially expanded from the design file 950 to create lower layer logical data. , stored in the work file 954 (
In the above example, the logical set 501 of the identification code ID5 and the logical set 303 of the identification code ID4 are partially developed to create the lower hierarchical logics 405 to 407 in FIG. 4). Next, in the merging process 955, the identification codes that do not match are received from the comparison process 952, and the data of the logical set of the matching identification codes (in the above example, 201 in FIG. and 202) create lower hierarchy logical data after the design change by sequentially selecting and merging the logical set data added and changed among the logical sets that are inconsistent from the design file 954 from the work file 954. It is stored in the design file 956.

The initial expansion shown in FIG. 9 above is also effective for redeployment from upper hierarchy logic to lower hierarchy logic. In addition, the deployment of design changes shown in Figure 10 is particularly effective when non-logical information such as implementation information is added to the design file of the lower level logic after initial deployment, and the non-logical information disappears and is re-initialized by reinitial deployment. Additional work can be avoided.

The development of the design change in FIG. 10 shows an example in which the upper layer logic is changed and the lower layer logic is changed, but the identification code ID
1, ID2, ID3, and ID4 can also be applied to the case where the lower layer logic is changed and then the upper layer logic is changed.

As described above, according to this embodiment, the identification code (I
D1, ID2. ID3. By adding ID4), logical comparison between upper and lower hierarchical logics can be made faster, and update processing for ensuring equivalence can be easily performed.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to quickly verify the equidominance of the logic in the upper and lower layers without significantly increasing the number of manual design steps in the hierarchical logic design of a digital logic device. Since it can be limited to the logical set indicated by the identification code, it is possible to easily update to ensure equivalence, and it is possible to save the information added to the lower layer logic to the maximum extent possible.

[Brief explanation of drawings]

FIG. 1 shows an example of upper layer logic in an embodiment of the present invention, and FIG. 2 shows an example of lower layer logic corresponding to FIG. FIG. 3 shows another example of the upper layer logic in the embodiment of the present invention, and FIG. 4 shows an example of the lower layer logic corresponding to FIG. FIG. 5 shows an example of a table for managing upper layer data. FIG. 6 shows an example of a table for managing lower layer data. FIG. 7 shows a table for creating the table of FIG. FIG. 8 is a flowchart showing a process for modifying lower layer data in accordance with changes in upper layer data in the embodiment of the present invention. FIG. 9 is a chart showing a process for creating lower layer data in an embodiment of the present invention, and FIG. 10 is a chart showing an overall outline of a process for creating lower layer data in an embodiment of the present invention. 100, 300...Top FMFI data, 200
, 400...lower hierarchy data. Ω Agent Patent Attorney Akira Takahashi Fuman 1st ward, 2nd floor 50th, 30th 90th floor, 70 units

Claims (1)

[Scope of Claim] A method for checking correspondence between upper layer data having a plurality of functional blocks each having input/output signals and lower layer data created based on the upper layer data, the method comprising the steps of: a first step of attaching the same first identification code to the corresponding lower layer data, and corresponding to the input/output signals of each of the functional blocks and the corresponding signals of the lower layer data, respectively; a second step of attaching a second identification code indicating the upper layer data; a third step of determining whether the first identification code included in the upper layer data is included in the lower layer data; and a third step of determining whether the first identification code included in the upper layer data is included in the lower layer data; A second identification code corresponding to the input/output signal of the functional block whose code is included in both the upper layer data and the lower layer data is included in all the lower layer data. 4 step, and in the fourth step, the functional block for which it is determined that the second identification code is entirely included in the lower layer and the functional block having the same first identification code as the functional block. A method for creating logic circuit data, comprising: a fifth step of determining whether the lower layer data has the same function.