CN107729692B

CN107729692B - Automatic physical verification method for semi-custom back-end design of integrated circuit

Info

Publication number: CN107729692B
Application number: CN201711111878.2A
Authority: CN
Inventors: 徐靖
Original assignee: Jiaxing Yiwei Electronic Technology Co ltd
Current assignee: Jiaxing Yiwei Electronic Technology Co ltd
Priority date: 2017-11-13
Filing date: 2017-11-13
Publication date: 2021-07-20
Anticipated expiration: 2037-11-13
Also published as: CN107729692A

Abstract

The invention discloses an automatic physical verification method for semi-custom back-end design of an integrated circuit. Step S1: the back-end design tool configures and outputs physical verification parameters. Step S2: and the back-end design tool acquires the physical verification parameters. Step S3: the back-end design tool acquires the physical verification parameters, and generates and outputs an execution command according to the physical verification parameters. Step S4: and the back end design tool acquires the initial data and the execution command, automatically performs physical verification according to the initial data and the execution command, and outputs a physical verification result to a specified position. The invention discloses an automatic physical verification method for semi-custom back-end design of an integrated circuit, which clearly defines a physical verification execution task related to design and improves the working efficiency and robustness of a physical verification stage.

Description

Automatic physical verification method for semi-custom back-end design of integrated circuit

Technical Field

The invention belongs to the technical field of design automation (EDA) in the integrated circuit design industry, and particularly relates to an automatic physical verification method for semi-custom back-end design of an integrated circuit.

Background

As integrated circuit fabrication technology continues to advance, the size of integrated circuit chips continues to shrink. While the chip size is reduced, the chip scale is increasing and the design complexity is also increasing.

In the field of design automation (EDA) technology in the integrated circuit design industry, physical verification of a chip is an important ring in the whole back-end design process. Semi-custom back-end designers of modern VLSI development face tremendous product time-to-market pressures, with very tight progress in the physical verification phase.

At present, in the technical field of design automation (EDA) in the conventional integrated circuit design industry, an effective general method for improving the working efficiency and the robustness in the physical verification stage does not exist, and the method is a technical problem to be solved urgently.

Disclosure of Invention

The present invention provides an automatic physical verification method for semi-custom back-end design of an integrated circuit, which aims at the state of the prior art and the technical problems.

The invention adopts the following technical scheme that the automatic physical verification method for the semi-customized back-end design of the integrated circuit comprises the following steps:

step S1: the back-end design tool configures and outputs physical verification parameters;

step S2: a back-end design tool acquires the physical verification parameters;

step S3: the back end design tool acquires the physical verification parameters, and generates and outputs an execution command according to the physical verification parameters;

step S4: and the back end design tool acquires the initial data and the execution command, automatically performs physical verification according to the initial data and the execution command, and outputs a physical verification result to a specified position.

According to the above technical solution, after the step S4, the method further includes the step S5:

step S5: and the back-end design tool indexes the physical verification result and outputs the index result to a specified position.

According to the above technical solution, in step S1, the back-end design tool includes a physical verification parameter collection module, a physical verification parameter definition module, and a physical setting result output module.

According to the above technical solution, in step S1, the physical verification parameter collection module is configured to collect task setting information, operating environment design information, data setting information, and tool setting information.

According to the above technical solution, in step S2, the back-end design tool includes an initial data collection module, an initial data sorting module, and an initial data output module.

According to the above technical solution, in step S2, the initial data collection module is configured to collect a physical information file, a netlist file, a physical verification rule file, and a GDS & SPICE library file.

According to the above technical solution, in step S4, the back-end design tool includes a GDS generation module, a SPICE generation module, a symbol generation module, and a physical verification execution module.

According to the above technical solution, in step S4, the physical verification performing module includes a DRC check unit, a LVS check unit, an antenna effect check unit, an XOR check unit, and a DFM check unit.

The automatic physical verification method for the semi-customized back-end design of the integrated circuit disclosed by the invention has the beneficial effects that the physical verification execution task related to the design is clearly defined, and the working efficiency and the robustness in the physical verification stage are improved.

Drawings

Fig. 1 is a block flow diagram of a preferred embodiment of the present invention.

Fig. 2 is a partial flow diagram of a preferred embodiment of the present invention.

Fig. 3 is a partial flow diagram of a preferred embodiment of the present invention.

Fig. 4 is a screenshot of a header file of a preferred embodiment of the present invention.

Fig. 5A to 5C are schematic diagrams illustrating connection relationship definitions according to preferred embodiments of the present invention.

Fig. 6 is a partial flow diagram of a preferred embodiment of the present invention.

Detailed Description

The invention discloses an automatic physical verification method for semi-custom back-end design of an integrated circuit, and the specific implementation mode of the invention is further described by combining the preferred embodiment.

Referring to fig. 1, fig. 2, fig. 3 and fig. 6 of the drawings, the related flows of the integrated circuit semi-custom back-end design automatic physical verification method are respectively shown. Fig. 4 shows a screenshot of a header file, and fig. 5A to 5C show connection relationship definitions of an actual connection, a soft connection, and a virtual connection, respectively.

Preferably, the integrated circuit semi-custom back-end design automatic physical verification method comprises the following steps:

step S1: the back-end design tool configures and outputs physical verification parameters, all physical verification execution tasks related to the design are clearly defined through the steps, after the parameters are defined, manual intervention is not needed until all physical verification processes are completed, all the work is automatically executed, and the purpose of improving the work efficiency is achieved;

step S2: the back end design tool acquires the physical verification parameters, collects and outputs initial data according to the physical verification parameters, collects all required initial data of the physical verification design through the step, arranges the data according to a certain format and stores the data in a local directory for a design task to use;

step S3: the back end design tool obtains the physical verification parameters, generates and outputs an execution command according to the physical verification parameters, automatically generates the execution command corresponding to each link of the physical verification design through the steps, does not need manual generation, and comprises modifying the top module name and path according to the actual design, and header files and connection relation definitions of physical verification rule files provided by a tape carrier manufacturer;

step S4: the back end design tool obtains the initial data and the execution command, automatically carries out physical verification according to the initial data and the execution command, and simultaneously outputs a physical verification result to a specified position.

In step S1, the back-end design tool includes a physical verification parameter collection module, a physical verification parameter definition module, and a physical setting result output module; the physical verification parameter collection module is used for collecting task setting information, running environment design information, data setting information, tool setting information and other setting information; the physical verification parameter definition module is used for sorting, classifying and converting the information results of the physical verification parameter collection module into a data format which can be identified by the whole physical verification design process and is called by a subsequent design link; and the physical setting result output module is used for respectively outputting the data which can be identified by the design process to the corresponding subsequent design modules according to the attributes of the design links.

In step S1, the task setting information defines tasks that need to be completed in the entire design process for physical verification, and configures a design flow meeting the requirements according to the requirements of specific projects; the operation environment setting information defines operation environment variables of each design link in the physical verification process, such as CPU resources, memory resources, hard disk size resources and the like; the data setting information is used for defining initial data source information and data output information of each design link in the physical verification process; the tool setting defines EDA tool information correspondingly used in different design links in the physical verification process; the other setting information includes user-defined design information and special requirement information.

In step S2, the back-end design tool includes an initial data collection module, an initial data sorting module, and an initial data output module; wherein the initial data collection module is used for collecting a physical information file (DEF), a netlist file, a physical verification rule file, a GDS & SPICE library file and other files; the initial data sorting module sorts and stores the physical information file (DEF), the netlist file, the physical verification rule file, the GDS & SPICE library file and other files according to a design link, and updates the sorted and stored information so as to automatically obtain corresponding design initial data according to the sorted and stored information data in a subsequent design link without manual intervention; the initial data output module is used for converting the physical information file (DEF), the netlist file, the physical verification rule file, the GDS & SPICE library file and other files, storing the files into a format which can be identified by a design tool, and outputting the files to a corresponding design link.

In step S4, the back-end design tool includes a GDS generation module, a SPICE generation module, a symbol generation module, and a physical verification execution module; the physical verification execution module comprises a DRC check unit, a LVS check unit, an antenna effect check unit, an XOR check unit, a DFM check unit and other check units; the GDS generation module, the SPICE generation module and the symbol generation module are used as special realization modules of the application, and similar processes do not exist in the conventional design method at present; the GDS generation module and the SPICE generation module automatically generate corresponding GDS files and SPICE files according to the initial data and the execution command respectively; wherein the symbol generation module automatically generates a corresponding symbol file according to the physical information file (DEF).

After the step S4, the method further includes a step S5:

It will be apparent to those skilled in the art that modifications and equivalents may be made in the embodiments and/or portions thereof without departing from the spirit and scope of the present invention.

Claims

1. An automatic physical verification method for semi-custom back-end design of an integrated circuit is characterized by comprising the following steps:

step S1: the back-end design tool is used for configuring and outputting physical verification parameters, and comprises a physical verification parameter collecting module, a physical verification parameter defining module and a physical setting result output module, wherein the physical verification parameter collecting module is used for collecting task setting information, running environment design information, data setting information and tool setting information; the physical verification parameter definition module is used for sorting and classifying the information results of the physical verification parameter collection module and converting the information results into a data format which can be recognized by the whole physical verification design process and is called by a subsequent design link; the physical setting result output module is used for respectively outputting data which can be identified by a design process to the corresponding subsequent design modules according to the attributes of the design links;

step S2: the back end design tool acquires the physical verification parameters, and collects and outputs initial data according to the physical verification parameters;

2. The method of automatic physical verification of semi-custom back-end design of integrated circuit of claim 1, further comprising step S5 after step S4:

3. The method for automated physical verification of semi-custom back-end designs of integrated circuits according to claim 1, wherein in step S2, the back-end design tool comprises an initial data collection module, an initial data arrangement module and an initial data output module.

4. The automated physical verification method for integrated circuit semi-custom back-end designs according to claim 3, wherein in step S2, the initial data collection module is used to collect physical information files, netlist files, physical verification rule files, GDS & SPICE library files.

5. The method of claim 1, wherein in step S4, the back-end design tool comprises a GDS generation module, a SPICE generation module, a symbol generation module, and a physical verification execution module.

6. The method according to claim 5, wherein in step S4, the physical verification execution module comprises a DRC check unit, a LVS check unit, an antenna effect check unit, an XOR check unit, and a DFM check unit.