CN102890729A - Method for carrying out layout wiring on high fan-out programmable gate array - Google Patents
Method for carrying out layout wiring on high fan-out programmable gate array Download PDFInfo
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Abstract
The invention discloses a method for carrying out layout wiring on a high fan-out programmable gate array. The method comprises the following steps: reading chip structure information of the programmable gate array (FPGA) and net list information generated after packing; carrying out layout on the FPGA according to read chip structure information of the programmable gate array (FPGA) and the net list information; wiring the FPGA according to the layout result of the FPGA, and generating a layout wiring result to finish layout wiring of the FPGA. By utilizing the method, delay of a circuit can be effectively shortened, and the utilization rate of a wiring resource is improved.
Description
Technical field
The present invention relates to integrated circuit and EDA Technique field, particularly a kind of programmable gate array to high fan-out (FPGA) carries out the method for placement-and-routing.
Background technology
FPGA is widely used programming device in the market, has short and low cost and other advantages of construction cycle.FPGA can realize various application, and in the CAD software flow of FPGA design, placement-and-routing is a vital step.Layout method has determined to realize each logical block piece position in FPGA that circuit function needs, its optimization aim be the logical block piece that links to each other near placing to reduce to greatest extent needed interconnection resource, but sometimes also want among the balance FPGA needed wiring density or improve to greatest extent circuit speed.In case determined the position of all logical block pieces in the circuit, wiring unit just can be got through suitable programmable switch with the input and output pin of all logical block pieces of connecting circuit needs.The wiring unit of most FPGA has strategy that a cover avoids crowding to solve the interconnection resource race problem.
In the application of FPGA, high fan-out refer to the packing after net table information in, a source connects the situation of a plurality of drain terminals (usually above 10, as shown in Figure 2), high fan-out generally can cause very large puzzlement to placement-and-routing, because it will take a large amount of interconnection resources, and in critical path, also basically all comprising the source with high fan-out.Do not do special processing for high fan-out in common placement-and-routing's process, this can cause a large amount of interconnection resource wastes, and the time-delay of meeting increasing circuit, even can cause circuit to be cabled successfully.
Most circuit all can have the existence of high fan-out, therefore is necessary to improve for placement-and-routing's method of the FPGA of high fan-out.
Summary of the invention
The technical matters that (one) will solve
In view of this, fundamental purpose of the present invention is to provide a kind of the programmable gate array of high fan-out is carried out the method for placement-and-routing, the placement-and-routing of the programmable gate array of high fan-out is improved realizing.
(2) technical scheme
For achieving the above object, the invention provides and a kind of the programmable gate array of high fan-out is carried out the method for placement-and-routing, the method comprises:
Read the net table information that generates after programmable gate array fpga chip structural information and the packing;
According to the programmable gate array fpga chip structural information that reads and net table information FPGA is carried out layout;
According to the layout result to FPGA FPGA is connected up; And
Generate the result of placement-and-routing, finish the placement-and-routing to FPGA.
In the such scheme, the programmable gate array fpga chip structural information that described basis reads and net table information are carried out in the process of layout FPGA, if the source of corresponding certain the high fan-out of the drain terminal of certain logic module that moves, then this layout comprises:
Whether judgement is in alignment direction in the mobile logic module logic module corresponding with source that up till now drain terminal was corresponding; If mobile up till now the two was in alignment direction, then reduce the probability that this logic module moves;
Whether judgement is in alignment direction in the mobile rear logic module logic module corresponding with source corresponding to this drain terminal; If after mobile this two be in alignment direction, then improve this logic module and add mobile probability.
In the such scheme, in the process that described basis connects up to FPGA to the layout result of FPGA, for the corresponding drain terminal of the source of high fan-out, this wiring comprises:
Judge whether this drain terminal is in and the source aligned position;
Judge whether this drain terminal is in critical path;
Whether judgement has other corresponding drain terminals on the alignment direction of source; And
If there is the drain terminal more than to be in alignment direction, then increase the chance that connects source and drain terminal with long line.
In the such scheme, in the described step that reads the net table information that generates after fpga chip structural information and the packing, described fpga chip structural information comprises that the pin name, Pin locations, logical block piece input pin of position, the logical block piece of various types of logical block pieces in the chip are to the time-delay of output pin, the width of wiring channel, the distribution of interconnect line segment and position, type, the time-delay of time-delay and Routing Switch; The pin of the logical block piece that the net table information that generates after the described packing comprises the title of the logical block piece that generates after the packing and type, use and source and the drain terminal of institute's wired network.
In the such scheme, the programmable gate array fpga chip structural information that described basis reads and net table information are carried out layout to FPGA, employing simulated annealing is carried out, this simulated annealing is to imitate to cool off gradually the deposite metal to make the annealing process of metal material, have a cost function Cost (S), this cost function Cost (S) is as follows:
Cost(S)＝(1-timing_tradeoff-Afac)*bb_cost+timing_tradeoff*timing_cost+Afac*alignment；
Wherein, timing_tradeoff is the sequential factor, is used for regulating time-delay for the impact of layout; Bb_cost is the value of gauze bounding box; Timing_cost is the sequential value, the alignment factor of Afac for adding, and alignment is the alignment value, and the alignment initial value is 0.Described alignment factors A fac is a dynamic factor, and the high fanout purpose square relation of being inversely proportional to of its value and circuit is proportional with the gauze number of circuit.
In the such scheme, in the step that described basis connects up to FPGA to the layout result of FPGA, path search algorithm is adopted in described wiring, this path search algorithm is the derived method of labyrinth type wiring unit, suppose that at the wiring initial stage every gauze all is crucial, do not remember the problem of reusing of interconnection resource, each the bar gauze in the rerouting circuit of taking out stitches repeatedly is until all crowding problems all are resolved.Described path search algorithm adopts the wavefront spread method.
In the such scheme, in the step that described basis connects up to FPGA to the layout result of FPGA, described FPGA is carried out after layout finishes, the method also creates two-dimensional array AlignmentInfo, the first dimension of this two-dimensional array AlignmentInfo is the gauze value, the second dimension of this two-dimensional array AlignmentInfo is the value of current gauze source or drain terminal, two-dimensional array AlignmentInfo canned data is whether current drain terminal aligns with source, how many alignment of level or vertical direction is apart from the distance of source.
In the such scheme, in the described process that FPGA is connected up, if the source of certain gauze N is high fan-out, then when source and drain terminal wiring, judge first whether this source is in critical path to drain terminal, if so, then connect up routinely; If not, then read two-dimensional array AlignmentInfo; Judge whether this drain terminal aligns with source, if so, then read again the drain terminal whether other are arranged on this drain terminal alignment direction and exist; If there are other drain terminals to exist, then estimate respectively the cost of the various connected modes that connect this drain terminal, and the cost of these various connected modes is compared, select lower-cost connected mode.
(3) beneficial effect
Can find out that from technique scheme the present invention has following beneficial effect:
1, method of the programmable gate array of high fan-out being carried out placement-and-routing provided by the invention, in layout process for the drain terminal place logic module of high fan-out, improve the probability that this logic module moves the aligned position of paramount fan-out source place logic module, realized the placement-and-routing of the programmable gate array of high fan-out is improved.
2, method of the programmable gate array of high fan-out being carried out placement-and-routing provided by the invention, drain terminal for high fan-out in wiring process connects up, improve the probability that uses long line connection according to the actual conditions of drain terminal, realized the placement-and-routing of the programmable gate array of high fan-out is improved.
3, provided by the invention the programmable gate array of high fan-out is carried out the method for placement-and-routing, be applied to placement-and-routing's method of FPGA, effectively reduced circuit delay and reduced the use of interconnection resource.
Description of drawings
Fig. 1 is the method flow diagram according to the FPGA placement-and-routing of the embodiment of the invention;
Fig. 2 is the synoptic diagram according to a simple high fan-out in the FPGA layout of the embodiment of the invention;
Fig. 3 is the synoptic diagram according to logic module alignment in the FPGA layout of the embodiment of the invention;
Fig. 4 is the synoptic diagram of exchange logic module during according to the FPGA layout of the embodiment of the invention;
Fig. 5 is the synoptic diagram that improves front wiring rule according to the FPGA wiring method of the embodiment of the invention;
Fig. 6 is the synoptic diagram according to the wiring rule after the FPGA wiring method improvement of the embodiment of the invention;
Fig. 7 is the synoptic diagram according to the two-dimensional array AlignmentInfo memory contents of the embodiment of the invention.
Fig. 8 contrasts synoptic diagram according to result before and after placement-and-routing's method improvement of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Method of the programmable gate array of high fan-out being carried out placement-and-routing provided by the invention, if be the leakage that the logic module that is moved in layout process comprises some high fan-outs, then there is higher probability this module to be positioned over the alignment direction of leaking corresponding place, source module with this; If the source of wiring is high fan-out in wiring process, then can check the drain terminal number in this source alignment direction, in order to use long line wiring.The method can effectively reduce the time-delay of circuit, improves the utilization factor of interconnection resource.
As shown in Figure 1, Fig. 1 is that the method comprises according to the method flow diagram of the FPGA placement-and-routing of the embodiment of the invention: read the net table information that generates after programmable gate array fpga chip structural information and the packing; According to the programmable gate array fpga chip structural information that reads and net table information FPGA is carried out layout; According to the layout result to FPGA FPGA is connected up; And generate the result of placement-and-routing, finish the placement-and-routing to FPGA.
Wherein, the programmable gate array fpga chip structural information that described basis reads and net table information are carried out in the process of layout to FPGA, if the source of corresponding certain the high fan-out of the drain terminal of the logic module that certain moves, then this layout comprises: judge in the mobile logic module logic module corresponding with source that up till now drain terminal was corresponding whether be in alignment direction; If mobile up till now the two was in alignment direction, then reduce the probability that this logic module moves; Whether judgement is in alignment direction in the mobile rear logic module logic module corresponding with source corresponding to this drain terminal; If after mobile this two be in alignment direction, then improve this logic module and add mobile probability.
In the process that described basis connects up to FPGA to the layout result of FPGA, for the corresponding drain terminal of the source of high fan-out, this wiring comprises: judge whether this drain terminal is in and the source aligned position; Judge whether this drain terminal is in critical path; Whether judgement has other corresponding drain terminals on the alignment direction of source; And if have the drain terminal more than to be in alignment direction, then increase the chance with long line connection source and drain terminal.
Below in conjunction with Fig. 1 to Fig. 8 the present invention is described in further detail.
Referring again to Fig. 1, Fig. 1 is that the method may further comprise the steps according to the method flow diagram of the FPGA placement-and-routing of the embodiment of the invention:
Step S1, the net table information that reads the fpga chip structural information and pack and generate afterwards.The fpga chip structural information generally include the pin name, Pin locations, logical block piece input pin of position, the logical block piece of various types of logical block pieces in the chip to the position of the distribution of the width of the time-delay of output pin, wiring channel, interconnect line segment and time-delay and Routing Switch, type, time-delay etc.The pin of the logical block piece that the net table information that generates after the packing comprises the title of the logical block piece that generates after the packing and type, use and source and the drain terminal of institute's wired network.
Step S2, FPGA is carried out layout.That adopt in layout process is simulated annealing (simulated annealing) SA.Simulated annealing is to imitate to cool off gradually the deposite metal to make the annealing process of metal material.The false code of simulated annealing is as follows:
Wherein cost function Cost (S) is very big to the quality influence of simulated annealing, and the formula of Cost (S) is as follows:
Cost(S)＝(1-timing_tradeoff)*bb_cost+timing_tradeoff*timing_cost；
Timing_tradeoff is the sequential factor in the following formula, is used for regulating time-delay for the impact of layout; Bb_cost is the value of gauze bounding box; Timing_cost is the sequential value.In this cost function, the end points with high fan-out adopts identical processing means with common end points, and this can cause in the wiring stage, and high fan-out will take a large amount of interconnection resources.Therefore, just consider the characteristic of high fan-out end points at layout stage, introduced logic module alignment concept.
As shown in Figure 3, Fig. 3 is the synoptic diagram according to logic module alignment in the FPGA layout of the embodiment of the invention.The module that is in same level or vertical direction with logic module A is called the alignment module of modules A, such as logic module 1,2,3,4.
Module alignment two advantages are arranged:
(1), in when wiring, can reduce the turning of wiring, reduce time-delay.
(2), in when wiring, can utilize long line to connect up, and reduce the use of interconnection resource.
Therefore, need in the time of layout, add an alignment factor.The formula of cost function is amended as follows:
Cost(S)＝(1-timing_tradeoff-Afac)*bb_cost+timing_tradeoff*timing_cost+Afac*alignment；
Wherein, the alignment factor of Afac (Alignment factor) for adding, alignment is alignment value (the alignment initial value is 0).
The synoptic diagram of exchange logic module when as shown in Figure 4, Fig. 4 is FPGA layout according to the embodiment of the invention.The source A of logic module 0 is the end points of a high fan-out, and the drain terminal B of logic module 1 and the drain terminal C of logic module 3 are two drain terminals corresponding to source A.If module 1 is exchanged with module 2 in layout process, then module 1 becomes alignment module by the non-alignment module, and the alignment value subtracts 1, so just can reduce the value of cost, so that the current probability that exchanges increases.On the contrary, if module 3 is exchanged with module 4, then module 3 has become the non-alignment module by alignment module, and the value of alignment adds 1, has so just increased the value of cost, so that the current probability that exchanges reduces.
Afac is a dynamic factor, shows through a large amount of example of operation, and the value of best Afac and the high fanout purpose square relation of being inversely proportional to of circuit, proportional with the gauze number of circuit.
Step S3, FPGA is connected up.In wiring process, adopt path search algorithm (PathFinder).Path search algorithm is the derived method of labyrinth type wiring unit.Its essential following formula operation dijkstra's algorithm.Path search algorithm all is crucial at every gauze of wiring initial stage supposition, does not remember the problem of reusing of interconnection resource, and each the bar gauze in the rerouting circuit of taking out stitches repeatedly is until all crowding problems all are resolved.
Path search algorithm has adopted the wavefront spread method in order to accelerate the cloth linear velocity, and as shown in Figure 5, Fig. 5 is the synoptic diagram that improves front wiring rule according to the FPGA wiring method of the embodiment of the invention.The drain terminal B of module 1 and the drain terminal C of module 2 are corresponding two drain terminals of the source A of module 0.
Before wiring, drain terminal B and drain terminal C and source A are without being connected.When wiring began to carry out, drain terminal B was connected to source A by interconnection resource gauze 1 first.In carrying out the process that connects up with drain terminal C, path search algorithm is not again to begin search from source A, but in all interconnection resources that source A connects, seek the interconnection resource nearest apart from drain terminal C, be connected to drain terminal C so begin wiring from gauze 1 by gauze 2.But the wavefront spread method has a drawback can not find global optimum's line exactly.
As shown in Figure 6, Fig. 6 is the synoptic diagram according to the wiring rule after the FPGA wiring method improvement of the embodiment of the invention.If source A adopts gauze 3 when connecting drain terminal B, can be connected to simultaneously drain terminal C.Adopt the connected mode of gauze 3 more efficient compared with the connected mode that adopts gauze 1 and gauze 2.
Therefore, wiring process is done following improvement:
(1), after layout finishes, create two-dimensional array AlighmentInfo, as shown in Figure 7, Fig. 7 is the synoptic diagram according to the two-dimensional array AlignmentInfo memory contents of the embodiment of the invention.The first dimension is the gauze value, and the second dimension is the value of current gauze source or drain terminal, and the two-dimensional array canned data is whether current drain terminal aligns with source, and how many alignment of level or vertical direction is apart from the distance of source.
(2), in wiring process, if the source of certain gauze N is high fan-out, then in the time of the wiring of source and drain terminal, judge first whether this source is in critical path to drain terminal, if so, then connect up routinely; If not, read the AlignmentInfo array; Judge whether this drain terminal aligns with source, if so, read again the drain terminal whether other are arranged on this drain terminal alignment direction and exist.If there are other drain terminals to exist, refer again to Fig. 6, the cost of net1+net2 and the cost of use net3 are used in estimation respectively, and compare, if use the cost of net3 lower, then select net3 to connect.
Through this two step, can effectively utilize long line to connect drain terminal on alignment direction corresponding to high fan-out, namely can save interconnection resource, can reduce time-delay again.
Step S4, the generation result of placement-and-routing.The FPGA placement-and-routing for high fan-out that the embodiment of the invention provides improves one's methods and has following beneficial effect: (1), reduced circuit delay; (2), improved the interconnection resource utilization factor.
As shown in Figure 8, Fig. 8 contrasts synoptic diagram according to result before and after placement-and-routing's method improvement of the embodiment of the invention.Wiring result before control methods improves, time-delay has reduced by 6.97%, and interconnection resource has saved 1.01%, and working time is substantially constant.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. one kind is carried out the method for placement-and-routing to the programmable gate array of high fan-out, it is characterized in that the method comprises:
Read the net table information that generates after programmable gate array fpga chip structural information and the packing;
According to the programmable gate array fpga chip structural information that reads and net table information FPGA is carried out layout;
According to the layout result to FPGA FPGA is connected up; And
Generate the result of placement-and-routing, finish the placement-and-routing to FPGA.
2. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 1, it is characterized in that, the programmable gate array fpga chip structural information that described basis reads and net table information are carried out in the process of layout to FPGA, if the source of corresponding certain the high fan-out of the drain terminal of the logic module that certain moves, then this layout comprises:
Whether judgement is in alignment direction in the mobile logic module logic module corresponding with source that up till now drain terminal was corresponding; If mobile up till now the two was in alignment direction, then reduce the probability that this logic module moves;
Whether judgement is in alignment direction in the mobile rear logic module logic module corresponding with source corresponding to this drain terminal; If after mobile this two be in alignment direction, then improve this logic module and add mobile probability.
3. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 1, it is characterized in that, in the process that described basis connects up to FPGA to the layout result of FPGA, for the corresponding drain terminal of the source of high fan-out, this wiring comprises:
Judge whether this drain terminal is in and the source aligned position;
Judge whether this drain terminal is in critical path;
Whether judgement has other corresponding drain terminals on the alignment direction of source; And
If there is the drain terminal more than to be in alignment direction, then increase the chance that connects source and drain terminal with long line.
4. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 1, it is characterized in that, in the described step that reads the net table information that generates after fpga chip structural information and the packing, described fpga chip structural information comprises that the pin name, Pin locations, logical block piece input pin of position, the logical block piece of various types of logical block pieces in the chip are to the time-delay of output pin, the width of wiring channel, the distribution of interconnect line segment and position, type, the time-delay of time-delay and Routing Switch; The pin of the logical block piece that the net table information that generates after the described packing comprises the title of the logical block piece that generates after the packing and type, use and source and the drain terminal of institute's wired network.
5. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 1, it is characterized in that, the programmable gate array fpga chip structural information that described basis reads and net table information are carried out layout to FPGA, employing simulated annealing is carried out, this simulated annealing is to imitate to cool off gradually the deposite metal to make the annealing process of metal material, have a cost function Cost (S), this cost function Cost (S) is as follows:
Cost(S)＝(1-timing_tradeoff-Afac)*bb_cost+timing_tradeoff*timing_cost+Afac*alignment；
Wherein, timing_tradeoff is the sequential factor, is used for regulating time-delay for the impact of layout; Bb_cost is the value of gauze bounding box; Timing_cost is the sequential value, the alignment factor of Afac for adding, and alignment is the alignment value, and the alignment initial value is 0.
6. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 5, it is characterized in that, described alignment factors A fac is a dynamic factor, and the high fanout purpose square relation of being inversely proportional to of its value and circuit is proportional with the gauze number of circuit.
7. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 1, it is characterized in that, in the step that described basis connects up to FPGA to the layout result of FPGA, path search algorithm is adopted in described wiring, this path search algorithm is the derived method of labyrinth type wiring unit, suppose that at the wiring initial stage every gauze all is crucial, do not remember the problem of reusing of interconnection resource, each bar gauze in the rerouting circuit of taking out stitches repeatedly is until all crowding problems all are resolved.
8. according to claim 7 the programmable gate array of high fan-out is carried out the method for placement-and-routing, it is characterized in that described path search algorithm adopts the wavefront spread method.
9. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 7, it is characterized in that, in the step that described basis connects up to FPGA to the layout result of FPGA, described FPGA is carried out after layout finishes, the method also creates two-dimensional array AlignmentInfo, the first dimension of this two-dimensional array AlignmentInfo is the gauze value, the second dimension of this two-dimensional array AlignmentInfo is the value of current gauze source or drain terminal, two-dimensional array AlignmentInfo canned data is whether current drain terminal aligns with source, how many alignment of level or vertical direction is apart from the distance of source.
10. method of the programmable gate array of high fan-out being carried out placement-and-routing according to claim 9, it is characterized in that, in the described process that FPGA is connected up, if the source of certain gauze N is high fan-out, then when source and drain terminal wiring, judge first whether this source is in critical path to drain terminal, if so, then routinely wiring; If not, then read two-dimensional array AlignmentInfo; Judge whether this drain terminal aligns with source, if so, then read again the drain terminal whether other are arranged on this drain terminal alignment direction and exist; If there are other drain terminals to exist, then estimate respectively the cost of the various connected modes that connect this drain terminal, and the cost of these various connected modes is compared, select lower-cost connected mode.
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| CN106649898A (en) * | 2015-10-29 | 2017-05-10 | 京微雅格（北京）科技有限公司 | Method for packing and deploying adders |
| CN106709119A (en) * | 2015-11-18 | 2017-05-24 | 京微雅格（北京）科技有限公司 | FPGA chip wiring method |
| CN109710981A (en) * | 2018-02-27 | 2019-05-03 | 上海安路信息科技有限公司 | The wiring method and system of FPGA |
| CN109710981B (en) * | 2018-02-27 | 2021-02-02 | 上海安路信息科技有限公司 | FPGA wiring method and system |
| CN111159967A (en) * | 2019-12-27 | 2020-05-15 | 天津芯海创科技有限公司 | FPGA circuit layout and resource allocation method based on webpage ranking algorithm |
| CN111241778A (en) * | 2020-01-06 | 2020-06-05 | 武汉理工大学 | FPGA automatic parameter adjustment optimization method and system based on machine learning |
| CN111241778B (en) * | 2020-01-06 | 2022-04-19 | 武汉理工大学 | FPGA automatic parameter adjustment optimization method and system based on machine learning |
| CN112149376A (en) * | 2020-09-25 | 2020-12-29 | 无锡中微亿芯有限公司 | FPGA layout legalization method based on maximum flow algorithm |
| CN113095033A (en) * | 2021-04-23 | 2021-07-09 | 中国科学院计算技术研究所 | Superconducting RSFQ circuit layout method for double-clock framework |
| CN113095033B (en) * | 2021-04-23 | 2023-07-21 | 中国科学院计算技术研究所 | Superconducting RSFQ circuit layout method for dual-clock architecture |
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