CN103366029B - A kind of field programmable gate array chip layout method - Google Patents
A kind of field programmable gate array chip layout method Download PDFInfo
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Abstract
The invention provides a kind of field programmable gate array chip layout method, the net table information of the logic module generated after the structural information of the logical block of field programmable gate array chip and packing are provided; Interconnection resource figure is set up according to the structural information of the logical block of described chip; Carry out the layout of field programmable gate array chip according to described net table information and interconnection resource figure, carry out fast wiring simultaneously.The present invention carries out fast wiring according to interconnection resource figure in layout process, place and route process is combined closely, improves and be routed to power, reduces the time delay of circuit simultaneously, improves interconnection resource utilization factor.
Description
Technical field
The present invention relates to integrated circuit (IC) design and field of electron design automation, particularly relate to a kind of field programmable gate array chip layout method.
Background technology
FPGA (Field-ProgrammableGateArray, field programmable gate array) chip is widely used programming device in the market, has construction cycle short and low cost and other advantages.By the wiring of interconnection line between the layout of logic module and logic module, fpga chip can realize various application, and therefore, in the software flow carrying out FPGA design, place and route is vital step.Layout determines the position of each logic module in fpga chip that realizing circuit function needs, wiring by interconnection line between logic module is connected, the optimization aim of layout is near placing to reduce required interconnection resource to greatest extent the logic module be connected, meanwhile, also need to balance the wiring density in fpga chip and circuit delay.After completing the layout of fpga chip, wiring unit just can get through the input and output pin of all logic modules that suitable programmable switch needs with connecting circuit, completes the place and route of fpga chip.
In fpga chip, the area of wiring accounts for more than 50% of the chip total area, after wiring in critical path the time delay of wiring channel than the logical time delay several times to tens times greatly of logic module, this sufficient proof importance connected up in fpga chip.In most placement-and-routings tool software, the relation between place and route is too loose, the interconnection line that during usual layout, unpredictable wiring stage uses, and the therefore time delay that brings of unpredictable interconnection line, finally causes the time delay of fpga chip to increase.
At present, simultaneously the best solution reducing fpga chip time delay is carried out by place and route, but when place and route carries out simultaneously, placement-and-routing's tool software can increase more than decades of times working time, has a strong impact on placement-and-routing's time of fpga chip.
Summary of the invention
The object of this invention is to provide a kind of layout method of field programmable gate array chip, realize the fast layout of field programmable gate array chip and reduce circuit delay.
The invention provides a kind of field programmable gate array chip layout method, comprise step:
The net table information of the logic module generated after the structural information of the logical block of field programmable gate array chip and packing are provided;
Interconnection resource figure is set up according to the structural information of the logical block of described chip;
Carry out the layout of field programmable gate array chip according to described net table information and interconnection resource figure, carry out fast wiring simultaneously.
Preferably, described layout of carrying out field programmable gate array chip according to described net table information and interconnection resource figure, carry out fast wiring simultaneously, comprise step:
Logic module described in arbitrary placement and quick prewiring, and set layout temperature, occupied for described interconnection line total degree is stored in data structure;
Move or exchange described logic module according to described net table information and carry out layout;
Move according to described layout temperature computation or the value at cost of exchange logic module;
According to described interconnection resource figure, quick local wiring is carried out to described movement or exchange logic module, upgrade the occupied number of times of interconnection line in described data structure;
Calculate the value at cost after described quick local wiring, judge described movement or exchange whether accept according to described value at cost change;
Judge that whether layout temperature meets to impose a condition, if not, upgrade layout temperature, perform and describedly move or exchange described logic module according to described net table information and carry out layout step; If so, layout is terminated.
Preferably, path search algorithm is adopted to carry out quick prewiring.
Preferably, describedly move or exchange described logic module according to described net table information and carry out layout step and be:
The first module and the first module coordinate is selected in described net table information, wherein said first module is not constrained to fixed position, the position of the first module is not at described first module coordinate, and the type of the first module is identical with the module type at described first module coordinate place;
If described first module coordinate is unoccupied, then move described first module to the first module coordinate place; If described first module coordinate is taken by the second module, described second module is not constrained on the first module coordinate, then exchange described first module and the second module.
Preferably, the value at cost step of the described movement of described calculating or exchange logic module is:
Simulated annealing is adopted to calculate the value at cost of described movement or exchange logic module.
Preferably, describedly according to described interconnection resource figure, quick local wiring is carried out to described movement or exchange logic module, is specially:
Travel through the gauze that mobile or after exchanging logic module uses, every bar gauze all uses Routing Algorithm to carry out fast wiring, and described Routing Algorithm is path search algorithm.
Preferably, described in the structural information of the logical block of field programmable gate array chip is provided, comprising:
There is provided the position of various types of logical block block, the pin name of logical block block, Pin locations, logical block block input pin to the position of the time delay of output pin, the width of wiring channel, the distribution of interconnect line segment and time delay and Routing Switch, type, time delay.
Preferably, described in the logical block packing of field programmable gate array chip is provided after the net table information of logic module that generates, comprising:
There is provided described logical block pack after the title of logic module that generates and type, the pin of logical block block used and the source of institute's wired network and drain terminal.
Preferably, the structural information of the described logical block according to described chip sets up interconnection resource figure, comprising:
The annexation of logical block source and logic module output pin is set up according to the structural information of the logical block of described chip, the annexation of logical block drain terminal and logic module input pin, the annexation of logic module input and output pin and interconnection line, annexation between interconnection line, the annexation of same logic module internal logic unit, and the annexation of other modules and interconnection line.
Compared with prior art, method of the present invention has following advantages:
Fpga chip layout method of the present invention, the net table information of the logic module generated after the structural information of the logical block of field programmable gate array chip and packing are provided; Interconnection resource figure is set up according to the structural information of the logical block of described chip; Carry out the layout of field programmable gate array chip according to described net table information and interconnection resource figure, carry out fast wiring simultaneously.The present invention carries out fast wiring according to interconnection resource figure in layout process, place and route process is combined closely, improves and be routed to power, reduces the time delay of circuit simultaneously, improves interconnection resource utilization factor.
Accompanying drawing explanation
Shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawing indicates identical part.Deliberately do not draw accompanying drawing by physical size equal proportion convergent-divergent, focus on purport of the present invention is shown.
Fig. 1 is fpga chip layout method process flow diagram of the present invention;
Fig. 2 is the schematic diagram of the interconnection resource figure according to the foundation of fpga chip structural information;
Fig. 3 is the layout process flow diagram carrying out fpga chip according to net table information and interconnection resource figure;
Fig. 4 and Fig. 5 is mobile in layout and Switching Module position view.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Secondly, the present invention is described in detail in conjunction with schematic diagram, and when describing the embodiment of the present invention in detail, for ease of illustrating, described schematic diagram is example, and it should not limit the scope of protection of the invention at this.
As described in background, in current most placement-and-routings tool software, the relation between place and route is too loose, the interconnection line that during usual layout, unpredictable wiring stage uses, therefore the time delay that brings of unpredictable interconnection line, finally causes the time delay of fpga chip to increase.Simultaneously the best solution reducing fpga chip time delay is carried out by place and route, but when place and route carries out simultaneously, placement-and-routing's tool software can increase more than decades of times working time, has a strong impact on placement-and-routing's time of fpga chip.
In order to quick solution fpga chip placement-and-routing latency issue, the invention provides a kind of fpga chip layout method, the method is when fpga chip layout, first the initial layout of logic module is carried out, carry out local fast prewiring, the value at cost that when utilizing simulated annealing to calculate layout, logic module moves or exchanges simultaneously, move according to described value at cost decision logic module or exchange and whether accept, then according to layout temperature, judge whether to terminate layout.Layout process and wiring process combine closely by fpga chip layout method of the present invention, effectively reduce the time delay of interconnection line, improve interconnection resource utilization factor.
Field programmable gate array chip layout method process flow diagram of the present invention, see Fig. 1, comprises step:
Step S1, the net table information of the logic module generated after the structural information of the logical block of field programmable gate array chip and packing are provided.
Fpga chip structural information generally includes the position of various types of logical block block in chip, the pin name of logical block block, Pin locations, logical block block input pin to the position, type, time delay etc. of the time delay of output pin, the width of wiring channel, the distribution of interconnect line segment and time delay and Routing Switch.
The logical block of fpga chip is packed formation logic module after Technology Mapping, described logic module is made up of several logical block and local interconnection line, the source of logical block is connected by the output pin of local interlinkage wired-AND logic circuits module, and the drain terminal of logical block is connected by the input pin of local interlinkage wired-AND logic circuits module.
The title of the logic module that the net table information of the logic module generated after packing generates after comprising packing and type, the pin of logical block block used and the source of institute's wired network and drain terminal.
Step S2, sets up interconnection resource figure according to the structural information of the logical block of described chip.
Interconnection line interconnection resource is communicated with all logical blocks of FPGA inside, and the length of interconnection line and technique decide the driving force of signal on line and transmission speed.
As shown in Figure 2, interconnection resource figure comprises: the annexation of logical block source and logic module output pin, the annexation of logical block drain terminal and logic module input pin; The annexation of logic module input and output pin and interconnection line; Annexation between interconnection line, such as interconnection line 1, annexation between interconnection line 2 and interconnection line 3; The annexation of same logic module internal logic unit, and the annexation of other modules and interconnection line.
Step S3, carries out the layout of fpga chip, carries out fast wiring simultaneously according to described net table information and interconnection resource figure.
In fpga chip layout method of the present invention, see Fig. 3, concrete layout process can comprise:
Step S31, logic module described in arbitrary placement and quick prewiring, and set layout temperature, occupied for described interconnection line total degree is stored in data structure.
The logic module that circuit needs is placed on each position of fpga chip at random, completes initial layout, and set layout temperature, interconnection line fast wiring is carried out to initial layout.
Interconnection line fast wiring can adopt path search algorithm (PathFinder), suppose that every bar interconnection line is all crucial when connecting up, do not remember the repetition occupation problem of interconnection resource, add up the occupied number of times of every bar interconnection line, by occupied for interconnection lines all in interconnecting channel number of times superposition, be stored in data structure congestion.
Step S32, moves or exchanges described logic module according to described net table information and carry out layout.
See Fig. 4 and Fig. 5, in layout logic module move or exchange process as follows:
Random selecting first modules A in described net table information, and random selecting first module coordinate B, wherein, the first modules A is not constrained to fixed position, the position of the first modules A is not at the first module coordinate B, and the type of the first modules A is identical with the module type at the first module coordinate B place; If the first module coordinate B place is occupied by module, this module is not constrained on fixed position.
When above condition meets, if position B does not have occupied, as Fig. 4, modules A moves to module coordinate B place; If position B is taken by module C, as Fig. 5, then modules A and module C transposition.
Wherein, the type of described module can be logic module, input output module etc.
Step S33, moves or the value at cost of exchange logic module according to described layout temperature computation.
In layout process, calculate value at cost that is mobile or exchange logic module, adopt simulated annealing (SA, SimulatedAnnealing).Simulated annealing imitates to cool deposite metal gradually to manufacture the annealing process of metal material.The false code of annealing algorithm is as follows:
Wherein, bb_cost is gauze border box value, representative be distance between logic module, timing_cost is the delay value between logic module.
Step S34, carries out quick local wiring according to described interconnection resource figure to described movement or exchange logic module, upgrades the occupied number of times of interconnection line in described data structure.
After module is moved or exchanges, interconnection line release is taken by former for gauze, statistics moves or exchange logic module gauze used, the gauze that mobile or after exchanging logic module uses is traveled through, every bar gauze all uses Routing Algorithm to carry out fast wiring, Routing Algorithm is path search algorithm, do not consider during wiring that whether interconnection line is occupied, but the occupied number of times of interconnection line is added up, occupied for interconnection line in whole interconnecting channel number of times superposition calculation is stored in data structure congestion.
Step S35, calculates the value at cost after described quick local wiring, judges described movement or exchange whether accept according to described value at cost change.
Assess the cost value, and value at cost Cost (S) formula in step S33 is increased by an item constraint Afac*congestion to describe the crowding of interconnecting channel, and formula is as follows:
Cost (S)=(1-timing_tradeoff-Afac) * bb_cost+timing_tradeoff*timing_cost+Afac*congestion; In the bound term wherein newly added, whether the congestion item interconnection line use number represented in interconnecting channel exceedes the interconnection line number in interconnecting channel, if be 1 more than congestion value, otherwise is 0;
Calculate IC=Cost (S
new)-Cost (S); And r=random (0,1);
If r < sets up, then this secondary module moves or exchanges acceptance, otherwise refusal.
Step S36, judges whether the layout temperature of fpga chip meets and imposes a condition, if not, upgrade layout temperature, perform step S32; If so, layout is terminated.
What layout temperature met imposes a condition as temperature conditions, and imposing a condition, it is several relevant to take with gauze, is usually set as a smaller value.Impose a condition if layout temperature does not meet, namely when layout temperature is higher, after upgrading layout temperature, perform step S32, move or exchange described logic module according to described net table information and carry out layout, circulate, impose a condition until the layout temperature of fpga chip meets, then layout terminates, and obtains layout result.
Adopt fpga chip layout method of the present invention to carry out layout, in layout process, carried out quick prewiring, effectively combine place and route process, can improve and be routed to power, improve interconnection resource utilization factor, reduce the time delay of circuit.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs to the scope of technical solution of the present invention protection.
Claims (8)
1. a field programmable gate array chip layout method, is characterized in that, comprises step:
The net table information of the logic module generated after the structural information of the logical block of field programmable gate array chip and packing are provided;
Interconnection resource figure is set up according to the structural information of the logical block of described chip;
Carry out the layout of field programmable gate array chip according to described net table information and interconnection resource figure, carry out fast wiring simultaneously, comprise step:
Logic module described in arbitrary placement and quick prewiring, and set layout temperature, occupied for interconnection line total degree is stored in data structure;
Move or exchange described logic module according to described net table information and carry out layout;
Move according to described layout temperature computation or the value at cost of exchange logic module;
According to described interconnection resource figure, quick local wiring is carried out to described movement or exchange logic module, upgrade the occupied number of times of interconnection line in described data structure;
Calculate the value at cost after described quick local wiring, judge described movement or exchange whether accept according to described value at cost change;
Judge that whether layout temperature meets to impose a condition, if not, upgrade layout temperature, perform and describedly move or exchange described logic module according to described net table information and carry out layout step; If so, layout is terminated.
2. method according to claim 1, is characterized in that, adopts path search algorithm to carry out quick prewiring.
3. method according to claim 1, is characterized in that, describedly moves or exchanges described logic module according to described net table information and carry out layout step and be:
The first module and the first module coordinate is selected in described net table information, wherein said first module is not constrained to fixed position, the position of the first module is not at described first module coordinate, and the type of the first module is identical with the module type at described first module coordinate place;
If described first module coordinate is unoccupied, then move described first module to the first module coordinate place; If described first module coordinate is taken by the second module, described second module is not constrained on the first module coordinate, then exchange described first module and the second module.
4. method according to claim 1, is characterized in that, the value at cost step of the described movement of described calculating or exchange logic module is:
Simulated annealing is adopted to calculate the value at cost of described movement or exchange logic module.
5. method according to claim 1, is characterized in that, describedly carries out quick local wiring according to described interconnection resource figure to described movement or exchange logic module, is specially:
Travel through the gauze that mobile or after exchanging logic module uses, every bar gauze all uses Routing Algorithm to carry out fast wiring, and described Routing Algorithm is path search algorithm.
6. the method according to any one of claim 1-5, is characterized in that, described in the structural information of the logical block of field programmable gate array chip is provided, comprising:
There is provided the position of various types of logical block block, the pin name of logical block block, Pin locations, logical block block input pin to the position of the time delay of output pin, the width of wiring channel, the distribution of interconnect line segment and time delay and Routing Switch, type, time delay.
7. the method according to any one of claim 1-5, is characterized in that, described in the logical block packing of field programmable gate array chip is provided after the net table information of logic module that generates, comprising:
There is provided described logical block pack after the title of logic module that generates and type, the pin of logical block block used and the source of institute's wired network and drain terminal.
8. the method according to any one of claim 1-5, is characterized in that, the structural information of the described logical block according to described chip sets up interconnection resource figure, comprising:
The annexation of logical block source and logic module output pin is set up according to the structural information of the logical block of described chip, the annexation of logical block drain terminal and logic module input pin, the annexation of logic module input and output pin and interconnection line, annexation between interconnection line, the annexation of same logic module internal logic unit, and the annexation of other modules and interconnection line.
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| CN109635328A (en) * | 2017-11-08 | 2019-04-16 | 成都华微电子科技有限公司 | Integrated circuit layout method and distributed design approach |
| CN108133094B (en) * | 2017-12-14 | 2021-08-24 | 中国电子科技集团公司第四十七研究所 | Layout and wiring display method for field programmable gate array of anti-fuse |
| CN109284578B (en) * | 2018-02-27 | 2021-06-01 | 上海安路信息科技股份有限公司 | Logic circuit layout and wiring method, graphical display method and system thereof |
| CN109829230B (en) * | 2019-01-29 | 2023-06-20 | 中科亿海微电子科技（苏州）有限公司 | Design method of FPGA IP core |
| CN110364506B (en) * | 2019-07-04 | 2022-01-28 | 武汉理工大学 | Bionic integrated circuit with high stability |
| CN111027274B (en) * | 2019-12-18 | 2023-08-22 | 京微齐力(北京)科技有限公司 | Three-dimensional chip layout method |
| CN113407258A (en) * | 2021-07-05 | 2021-09-17 | 武汉理工大学 | Self-adaptive resource allocation layout and wiring method and system of storage and computation integrated architecture |
| CN114169283B (en) * | 2021-10-27 | 2024-04-05 | 深圳市紫光同创电子有限公司 | Delay estimation method, delay estimation device, delay estimation equipment and delay estimation storage medium of programmable logic device |
| CN114282474B (en) * | 2021-11-16 | 2022-08-09 | 山东芯慧微电子科技有限公司 | FPGA wiring resource data compression method |
| CN117151003B (en) * | 2023-10-27 | 2024-01-30 | 中科亿海微电子科技（苏州）有限公司 | FPGA layout method and device based on clock domain division |
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Effective date of registration: 20220424 Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |