CN109284578B - Logic circuit layout and wiring method, graphical display method and system thereof - Google Patents
Logic circuit layout and wiring method, graphical display method and system thereof Download PDFInfo
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Abstract
The application relates to a programmable logic array, and discloses a logic circuit layout and wiring method, a graphical display method and a system thereof. Aiming at the graphical display of a logic circuit, the invention adopts a directed acyclic graph generation algorithm and a preset column distribution rule to carry out logic column distribution, and simultaneously adopts a heuristic algorithm and carries out logic row distribution based on median sorting, thereby optimizing the number of connecting line intersection points, and simultaneously distributing the physical coordinates of elements according to the physical sizes of the elements in the automatic layout process, so that the elements are concentrated and compactly arranged; and a cache and windowing mapping method is also adopted to realize quick response when the large-layout logic circuit drags and checks. Finally, the generated logic circuit diagram is uniformly distributed, the input and the output accord with the circuit habit, the number of the intersection points of the connecting lines is small, and the diagram is formed quickly.
Description
Technical Field
The present invention relates to programmable logic arrays, and more particularly, to a layout and routing method, a graphic display method, and a system thereof for a logic circuit.
Background
Programmable Logic Array (PLA) is a kind of Programmable Logic device, which is a large scale integrated circuit with Programmable and/or Array and containing memory elements, and can implement combinational circuit of arbitrary Logic function and implement sequential circuit.
As the complexity of programmable logic arrays, such as FPGA circuit designs, increases, designers are increasingly concerned with high-level design methodologies. The use of a graph of logic circuits (schema) is crucial in order to improve interactivity during the design process. Traditionally, designers manually draw logic circuit diagrams based on the feedback results of EDA tools, which results in a lot of wasted time and effort, especially in the case of larger circuit scale, which is prone to errors. Although the existing EDA software also realizes the drawing of the logic circuit diagram, as the circuit designed by a user is more and more complex, the used FPGA resources are more and more, the logic circuit is naturally more and more complex, the existing logic circuit diagram drawing tool occupies a lot of memories to cause the used system to be stuck, and the drawn logic circuit is complex in connection and inconvenient to look up.
Disclosure of Invention
The application aims to provide a logic circuit layout and wiring method, a graphical display method and a system thereof. When a complex logic circuit is drawn, the circuit is reasonably arranged and wired, so that the logic circuit diagram is uniformly distributed, the number of connection intersection points is reduced, and the problem that the existing drawing tool occupies a system memory due to unreasonable arrangement and wiring and finally causes system blockage is solved.
In order to solve the above problem, the present application discloses a method for laying out and routing a logic circuit, comprising the steps of:
the method comprises the steps of modeling an example, adding a connection relation of points by adopting a directed acyclic graph generation algorithm, performing logic column distribution of a logic circuit according to a preset column distribution rule, performing logic row distribution of the circuit by adopting a heuristic algorithm and based on a median sorting rule, and finally placing the example in a grid formed by row-column layout according to the connection relation to finish automatic layout;
automatically wiring in a channel mode according to a preset wiring rule;
after the size relation of the logic circuit is set, the coordinates of each instance in the logic circuit are determined by combining the automatic layout and wiring results, and secondary wiring is carried out according to the physical size of each instance.
In a preferred embodiment, the preset routing rule includes: under the condition that the routing is not overlapped, the same track is occupied; the routing lines starting from the same pin occupy the same track; the track should be adjacent to the edge of the channel that is close to the pin; wherein the track refers to a routing path between the instances.
In a preferred embodiment, the adding the connection relationship of the point by using the directed acyclic graph generation algorithm includes: regarding the circuit as a directed graph, the connection relationship between the points is M to N, the inside allows the appearance of a ring connection, and the point is placed on a certain point in the row-column layout through comprehensive adjustment, wherein M and N are natural numbers.
In a preferred embodiment, the preset column distribution rule includes: the input of the instance is 0 and is placed in the first column, the output of the instance is 0 and is placed in the last column, starting from the second column, if the rest instances have direct connection relation with the previous column, the rest instances are placed in the current column, and the column allocation is finished by the analogy;
the median ordering rule includes: calculating the connection relation between the examples in the previous column and the examples, and selecting one example in the middle of the vertical coordinates as the vertical coordinate of the example;
and finally, the row-column layout places the instances in the grids formed by the row-column layout according to the connection relations of the instances, and determines the row-column positions so that the instance positions are concentrated, are uniform and symmetrical, are closely connected, or are close to the instance positions with function dependence.
The application also discloses a logic circuit graphical display method, which comprises the following steps:
generating or creating netlist data through an EDA tool, and then analyzing the netlist data;
carrying out layout and wiring by adopting the layout and wiring method described above;
and calling a component graphic library according to the example type, and drawing the logic circuit on the equipment screen by a reasonably designed graphical method.
In one preferred embodiment, the netlist database includes: netlist data of any one of user behavior level description, register transfer level optimization, gate level optimization and layout and routing, wherein the netlist data comprises input/output ports, port bit widths and net connection relations of the circuit;
the network data parsing comprises the following substeps:
converting the circuit into a mathematical model which can be identified by a program, and establishing a data structure to store the circuit connection relation and the circuit information;
traversing all the instances in the instance information base, acquiring the instance information, and storing the instance information in the memory; wherein the instance information includes the instance name, the instance input-output interface, the instance type, and the instance underlying logic.
The application also discloses a logic circuit graphical display system, which comprises a netlist database module, a netlist analysis module, a layout and wiring module, a graphical display module and a component library module;
the netlist database module generates or creates netlist data through an EDA tool; the netlist analyzing module is used for analyzing the netlist data; the placement and routing module is used for processing the placement and routing method described in the foregoing; the component library module is used for calling a manufactured component graphic library according to the type of an instance; the graphic display module is used for drawing the logic circuit on a screen of the equipment.
In a preferred embodiment, the netlist data includes: netlist data of any one of user behavior level description, register transfer level optimization, gate level optimization and layout and routing, wherein the netlist data comprises input/output ports, port bit widths and net connection relations of the circuit;
the netlist analyzing module comprises a netlist analyzing submodule and an instance information obtaining submodule, wherein the netlist analyzing submodule is used for converting the circuit into a mathematical model which can be identified by a program, establishing a proper data structure and storing the circuit connection relation and the circuit information; the instance information acquisition submodule is used for traversing all instances in an instance information base, acquiring the names of the instances, the input and output interfaces, the types of the instances and whether the instances have underlying logic circuits or not, and storing the instance information in a memory. The application also discloses a logic circuit graphical display device, including:
a memory for storing computer executable instructions; and the number of the first and second groups,
a processor for implementing the steps in the method as described hereinbefore when executing the computer executable instructions.
The present application also discloses a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the steps in the method as described hereinbefore.
In the embodiment of the application, a row and column layout and wiring algorithm of a circuit example is developed aiming at the graphical display of a logic circuit.
For a more complex logic circuit, the conventional logic circuit diagram drawing tool occupies a lot of system memory due to disordered graphic layout, unclear wire nets formed during wiring and more connection intersection points, so that the used system is blocked.
The row and column layout and wiring algorithm of the circuit example effectively optimizes the circuit layout and wiring method, logic column distribution is carried out according to a directed acyclic graph generation algorithm and a preset column distribution rule, logic row distribution is carried out by adopting a heuristic algorithm and based on a median sorting rule, and automatic row and column layout of logic circuits is realized by the logic column distribution and the logic row distribution; then, automatically wiring in a channel mode according to a preset wiring rule; finally, reasonably distributing the physical coordinates of the elements according to the actual sizes of the elements, and performing secondary wiring; the finally obtained layout wiring pattern elements are centralized and compact in arrangement, the input and the output conform to the circuit habit, unnecessary wiring intersection points are avoided, and the number of the intersection points is reduced.
Moreover, the more complex the logic circuit, the more obvious the advantages of the present application are expressed and the more prominent the effect.
The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.
Drawings
FIG. 1 is a flow chart of a logic circuit graphical display method according to a second embodiment of the present application
FIG. 2 is a flow chart illustrating an example of a column distribution preset in the first embodiment of the present application
FIG. 3 is a schematic diagram of the relationship between modules, instances, nets, independent ports and dependent ports according to the present application
FIG. 4 is a schematic view showing an example of a passage and a rail according to the first embodiment of the present application
FIG. 5 is a schematic diagram of an embodiment of track allocation rules preset in the first embodiment of the present application
FIG. 6 is a schematic diagram of an embodiment of the processing procedure of steps a, b and c in the second embodiment of the present application
FIG. 7 is a schematic diagram of an embodiment of the processing procedure of steps a, b and c in the second embodiment of the present application
FIG. 8 is a schematic diagram of a logic circuit graphic display system according to a third embodiment of the present application
FIG. 9 is a partial schematic diagram of an intermediate pattern formed after row and column layout routing of logic circuits according to the first embodiment of the present application
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
Description of partial concepts:
1. programmable logic array (programmable logic array, PLA for short): is a programmable device for implementing combinational logic circuit.
2. Logic circuit (schema): the circuit is a circuit which is used for transmitting and processing discrete signals and realizes the logical operation and operation of digital signals by using a binary system as a principle.
FPGA (Field-Programmable Gate Array): the FPGA is a product developed on the basis of programmable devices such as PAL, GAL, CPLD and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
EDA is an abbreviation for electronic Design Automation (Electronics Design Automation): the EDA technology is implemented by using a computer as a tool, a designer completes a design file on an EDA software platform by using a hardware description language Verilog/VHDL, and then the computer automatically completes logic compiling, simplification, segmentation, synthesis, optimization, layout, wiring and simulation until the work of adaptive compiling, logic mapping, programming downloading and the like for a specific target chip. The advent of EDA technology has greatly improved the efficiency and operability of circuit design, reducing the labor intensity of designers.
5. Logical rows/columns: it is meant that the theoretical rows/columns defined in the automatic layout of the present invention are rows/columns without regard to instance size, relative to physical rows/columns.
6. Physical row/column: the actual rows/columns defined in the automatic layout in the present invention are the rows/columns in consideration of the actual size of the example, and are consistent with the rows on the final logic circuit diagram.
Module: modules (modules) are the most basic concept of verilog, and are basic units in v-design, and each v-design system is composed of a plurality of modules. The module is a program in language form that starts with the keyword module and ends with the keyword endmodule. The actual meaning of a module is to represent a logical entity on a hardware circuit. Each module implements a specific function. The module is described in a way of behavior modeling and structural modeling. The modules are operated in parallel. The modules are layered, and the high-level modules realize complex functions by calling and connecting the instances of the low-level modules. The connection of modules to complete the whole system requires a top-level module.
Down module: is the bottom module.
9. The relationship between modules (modules), instances (instances), networks (nets), independent ports (ports) and dependent ports (pins) is shown in fig. 3.
10. Directed Acyclic Graph (Direct Acyclic Graph, DAG for short): refers to a directed graph without loops, and mathematically defined, a DAG is a finite directed graph without directed loops. In particular, it consists of a finite number of vertices (also referred to herein as "points") and directed edges, each directed edge pointing from one vertex to another; starting from any vertex, the original vertex cannot be returned through the directed edges.
11. And (3) heuristic algorithm: is proposed with respect to an optimization algorithm, which is an algorithm based on an intuitive or empirical construction, giving a feasible solution to the problem to be solved at an acceptable cost (in terms of computation time and space), the degree of deviation of which from the optimal solution is generally not predictable.
12. Method of caching and windowing mapping: the invention can store data in the memory of the computer when calculating the position, layout, wiring and other data of the instance, and can draw the graph timely and efficiently. The windowing drawing refers to drawing only the graphics in the range of the visible window according to the graphic proportion, and not drawing the graphics in the range of the invisible window, so as to achieve timely and efficient customer experience.
13. Secondary wiring: the method is characterized in that on the basis of first logic wiring, a program removes space gaps caused by inconsistent example heights according to the physical dimensions of each example on rows and columns, so that elements are more concentrated and more compactly arranged, and meanwhile, crossed wiring, wiring bending and circuitous connection are avoided.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
A first embodiment of the present application relates to a method for laying out and routing a logic circuit, the flow of which is shown in fig. 1, the method comprising the steps of:
a, taking an example as a mathematical point after modeling, adding a connection relation of the point by adopting a directed acyclic graph generation algorithm, performing logic column distribution of a logic circuit according to a preset column distribution rule, performing logic row distribution of the circuit by adopting a heuristic algorithm and based on a median sorting rule, and finally placing the example in a grid formed by row-column layout according to the connection relation to complete automatic layout;
b, automatically wiring in a channel mode according to a preset wiring rule;
and C, after the size relation of the logic circuit is set, determining the coordinates of each instance in the logic circuit by combining the automatic layout and wiring results, and carrying out secondary wiring according to the physical size of each instance.
Optionally, the connection relationship of the points added by using the directed acyclic graph generation algorithm in the application is specifically: regarding the whole circuit as a directed graph (note: because the example is modeled as mathematical points, the pin information is not considered at this time), the connection relationship between the points may be M to N (M, N is a natural number), the inside may be a ring connection, and finally the points are placed on each point in the row-column layout by comprehensive adjustment, completing the distribution of the points, and at the same time, preliminarily forming a grid of the row-column layout of the logic circuit.
Alternatively, the column distribution rule preset in the present application is to determine the positions of the front and rear columns according to the input (referred to as in degree) and output (referred to as out degree) of the example.
A preferred embodiment of the preset column distribution rule in the present application is shown in fig. 2, where the column distribution rule corresponds to a logic column, and the specific steps are as follows:
1) firstly, determining that the input is 0 and is placed in a first column, and the output is 0 and is placed in a last column;
2) all instances pointed to by the instances in the starting column are specified in the next column, the second column;
3) the instances pointed to by the instances in the new column are all specified in the next column of the new column, i.e. the third column;
4) by analogy, all instances complete the logical column positioning.
Optionally, the median ordering rule of the present application is: and calculating the connection relation between the example in the previous column and the example, and selecting the ordinate of one example in the middle of the ordinates as the ordinate of the example.
Specifically, the logic row allocation is carried out based on the median sorting rule, so that the number of the intersection points of the connecting lines is optimized. Compared with the full arrangement with overlarge operation amount, the median sorting operation amount is smaller and the speed is higher.
Optionally, on the basis of the median ranking, the following optimization may be performed: 1) a small-range swap instance location; 2) the number of intersections before and after switching is calculated to determine whether to switch, for example, if the number of intersections of the circuit before switching is greater than the number of intersections of the circuit after switching, switching is performed.
Optionally, the logic row-column layout finally places the instance in the grid formed by the row-column layout according to the connection relationship of the instance, and determines the row-column position, so that the instance positions are centralized, uniform and symmetrical, the connection relationship is tight, or the instance positions with functional dependence are close.
Optionally, the present application designs a routing strategy according to the scale of the circuit, and distributes the connection lines between the instances in a channel formed by the row-column layout, wherein the channel is divided into a vertical channel and a horizontal channel.
It should be understood that the channels formed by the row-column layout in the present application correspond to the grids formed by the row-column layout.
FIG. 4 is a schematic view of one embodiment of the channel and track of the present application.
Optionally, the routing rule preset in the present application may be changed by setting.
Fig. 5 is a schematic view of an embodiment of a routing rule preset in the present application, where the rule specifically includes (note: this includes at the same time) but is not limited to: 1. in the case of non-overlapping traces, occupying the same track, as in fig. 5 (a); 2. the same pin starts the routing, and occupies the same track, as shown in fig. 5 (b); 3. the track should be adjacent to the edge of the channel that is close to the pin, as in fig. 5 (c); wherein the track refers to a routing path between the instances.
Optionally, the processing object generated by the logic circuit graph is a module class, and simultaneous drawing of the top layer circuit and the bottom layer circuit is supported, so that layered display can be achieved, and the whole logic circuit and the local logic circuit can be viewed.
It should be understood that the form and the examples of the independent port in the example information library or the component graphic library are the same, so the examples and the independent port are collectively referred to as the examples in the present application.
FIG. 9 is a partial schematic diagram of an intermediate pattern formed after row and column layout routing of logic circuits according to the first embodiment of the present application.
A second embodiment of the present application relates to a logic circuit graphical display method, a flow of which is shown in fig. 1, the method comprising the following steps:
generating or creating netlist data through an EDA tool, and then analyzing the netlist database;
carrying out automatic layout and wiring by adopting the layout and wiring method according to the first embodiment of the application;
and F, calling a component graphic library according to the example type, and drawing the logic circuit on the equipment screen by a reasonably designed graphical method.
Optionally, the netlist data comprises: netlist data of any one of user behavior level description, register transfer level optimization, gate level optimization and layout and routing, wherein the netlist data comprises input/output ports, port bit widths and net connection relations of the circuit;
optionally, the step D consists of three substeps, a. generating or creating a netlist database by an EDA tool; b. converting the circuit into a mathematical model which can be identified by a program, and establishing a data structure to store the circuit connection relation and the circuit information; c. traversing all the instances in the instance information base, acquiring the instance information, and storing the instance information in the memory; wherein the instance information includes the instance name, the instance input-output interface, the instance type, and the instance underlying logic.
The system processing procedure of the three substeps a, b, c is various, optionally, as shown in fig. 6, it is an embodiment of the system processing procedure, the system performs step c, step a, step b in turn, wherein step b and step c can also be performed synchronously and in parallel; optionally, as shown in fig. 7, which is an embodiment of a system processing procedure, the system performs step a, step b, and step c in sequence, wherein step b and step c may also be performed synchronously and in parallel.
It should be understood that the form and instances of the individual ports in the instance library or component graphics library are the same, and thus the instances and individual ports are collectively referred to herein as instances.
The third implementation method of the present application relates to a logic circuit graphical display system, as shown in fig. 8, including a netlist database module, a netlist parsing module, a layout and routing module, a component library module and a graphical display module;
the netlist database module generates or creates netlist data through an EDA tool; the netlist analyzing module is used for analyzing the netlist data; the placement and routing module is used for implementing the placement and routing method related to the first embodiment of the application; the component library module is used for calling the manufactured component graph according to the instance type; the graphic display module is used for drawing the logic circuit on the screen of the equipment.
Optionally, the netlist data of the netlist database module includes: netlist data for any one of user behavior level description, register transfer level optimization, gate level optimization, and the place and route, the netlist data including input/output ports, port bit widths, and net connections for the circuit.
Optionally, as shown in fig. 8, the netlist parsing module includes a netlist parsing submodule and a real-time information obtaining submodule; the netlist analyzing submodule is used for converting the circuit into a mathematical model which can be identified by a program, establishing a proper data structure and storing the circuit connection relation and the circuit information; the instance information obtaining submodule is used for traversing all instances in the instance information base, obtaining the name, the input and output interface, the instance type and whether the instance has a bottom layer logic circuit or not, and storing the instance information in the memory.
Optionally, as shown in fig. 8, the layout and wiring module includes an automatic layout sub-module, an automatic wiring sub-module, and a secondary wiring sub-module, where the automatic layout sub-module is configured to treat the modeled instances as mathematical points, add connection relationships of the points by using a directed acyclic graph generation algorithm, perform logic column distribution of logic circuits according to a preset column distribution rule, perform logic row distribution of the circuits by using a heuristic algorithm and based on a median sorting rule, and finally place the instances in a grid formed by row-column layout according to the connection relationships, thereby completing automatic layout; the automatic wiring submodule is used for automatically wiring in a channel mode according to a preset wiring rule; the secondary wiring submodule is used for determining the coordinates of each example in the logic circuit by combining the automatic layout and wiring results after the size relation of the logic circuit is set, carrying out secondary wiring according to the physical size of each example, and simultaneously realizing quick response when the large layout logic circuit is dragged and checked by adopting a cache and windowing construction method.
Optionally, the connection relationship of the points added by using the directed acyclic graph generation algorithm in the application is specifically: regarding the whole circuit as a directed graph (note: because the example is modeled as mathematical points, the pin information is not considered at this time), the connection relationship between the points may be M to N (M, N is a natural number), the inside may be a ring connection, and finally the points are placed on each point in the row-column layout by comprehensive adjustment, completing the distribution of the points, and at the same time, preliminarily forming a grid of the row-column layout of the logic circuit.
Alternatively, the column distribution rule preset in the present application is to determine the positions of the front and rear columns according to the input (referred to as in degree) and output (referred to as out degree) of the example.
A preferred embodiment of the column distribution rule preset in the present application is shown in fig. 2, and the specific steps are as follows:
1) firstly, determining that the input is 0 and is placed in a first column, and the output is 0 and is placed in a last column;
2) all instances pointed to by the instances in the starting column are specified in the next column, the second column;
3) the instances pointed to by the instances in the new column are all specified in the next column of the new column, i.e. the third column;
4) by analogy, all instances complete the column positioning.
Optionally, the median ordering rule of the present application is: and calculating the connection relation between the example in the previous column and the example, and selecting the ordinate of one example in the middle of the ordinates as the ordinate of the example.
Specifically, the logic row allocation is carried out based on the median sorting rule, so that the number of the intersection points of the connecting lines is optimized; compared with the full arrangement with overlarge operation amount, the median sorting operation amount is smaller and the speed is higher.
Optionally, on the basis of the median ranking, the following optimization may be performed: 1) a small-range swap instance location; 2) the number of intersections before and after switching is calculated to determine whether to switch, for example, if the number of intersections of the circuit before switching is greater than the number of intersections of the circuit after switching, switching is performed.
Optionally, the row-column layout finally places the instance in the grid formed by the row-column layout according to the connection relationship of the instance, and determines the row-column position, so that the instance positions are concentrated, uniform and symmetrical, the connection relationship is tight, or the instance positions with function dependence are close.
Optionally, the present application designs a routing strategy according to the scale of the circuit, and distributes the connection lines between the instances in a channel formed by the row-column layout, wherein the channel is divided into a vertical channel and a horizontal channel.
It should be understood that the channels formed by the row-column layout and the grids formed by the row-column layout correspond to each other in the present application.
FIG. 4 is a schematic view of one embodiment of the channel and track of the present application.
Optionally, the routing rule preset in the present application may be changed by setting.
Fig. 5 is a schematic view of an embodiment of a routing rule preset in the present application, where the rule specifically includes (note: this includes at the same time) but is not limited to: 1. in the case of non-overlapping traces, occupying the same track, as in fig. 5 (a); 2. the same pin is routed to occupy the same track, as shown in fig. 5 (b); 3. the rail should be adjacent to the edge of the channel that is close to the pin, as shown in fig. 5 (c); wherein the track refers to a routing path between the instances.
It should be understood that the form and the examples of the independent port in the example library or the component graphics library are the same, so the examples and the independent port are collectively referred to as the examples in the present application.
Optionally, the processing object generated by the logic circuit graph is a module class, and simultaneous drawing of the top layer circuit and the bottom layer circuit is supported, so that layered display can be achieved, and the whole logic circuit and the local logic circuit can be viewed.
It should be noted that, as will be understood by those skilled in the art, the implementation functions of the modules shown in the embodiment of the logic circuit graphic display system can be understood by referring to the description related to the logic circuit graphic display system. The functions of the respective blocks shown in the above-described embodiments of the logic circuit graphic display device may be implemented by a program (executable instructions) running on a processor, or may be implemented by a specific logic circuit. The logic circuit graphical display system according to the embodiment of the present invention may also be stored in a computer readable storage medium if it is implemented in the form of a software functional module and sold or used as an independent product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.
Accordingly, embodiments of the present invention also provide a computer storage medium, in which computer-executable instructions are stored, and when executed by a processor, implement the method embodiments of the present invention.
In addition, the embodiment of the invention also provides a logic circuit graphical display device, which comprises a memory for storing computer executable instructions and a processor; the processor is configured to implement the steps of the method embodiments described above when executing the computer-executable instructions in the memory.
It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.
All documents mentioned in this application are to be considered as being incorporated in their entirety into the disclosure of this application so as to be subject to modification as necessary. Further, it is understood that various changes or modifications may be made to the present application by those skilled in the art after reading the above disclosure of the present application, and such equivalents are also within the scope of the present application as claimed.
Claims (9)
1. A layout wiring method of a logic circuit, characterized by comprising the steps of:
taking the instance as a point in mathematics after modeling, and adding the connection relation of the point by adopting a directed acyclic graph generation algorithm;
and distributing the logic columns of each instance in the logic circuit according to the connection relation of the points and a preset column distribution rule, wherein the preset column distribution rule comprises the following steps: the input of the example is 0 and is placed in the first column, the output of the example is 0 and is placed in the last column, starting from the second column, if the rest examples have direct connection relation with the last column, the rest examples are placed in the current column, and the logic column distribution is finished by analogy;
and performing logic row distribution of each instance in the circuit by adopting a heuristic algorithm according to the connection relation of the points and based on a median sorting rule, wherein the median sorting rule comprises the following steps: calculating the connection relation between the example in the previous column and the example, and selecting the ordinate of the example with the ordinate in the middle as the ordinate of the example;
according to the connection relation of the points, the examples are placed in a grid formed by row-column layout, and automatic layout is completed;
automatically wiring in a channel mode according to a preset wiring rule, wherein the preset wiring rule simultaneously comprises the following steps: under the condition that the routing is not overlapped, the same track is occupied; the routing lines starting from the same pin occupy the same track; the track should be adjacent to the edge of the channel that is close to the pin; wherein the track refers to a routing path between the instances;
after the size relation of the logic circuit is set, the coordinates of each instance in the logic circuit are determined by combining the automatic layout and wiring results, and secondary wiring is carried out according to the physical size of each instance.
2. The method of claim 1, wherein adding the connection relationship of the points using a directed acyclic graph generation algorithm comprises: regarding the circuit as a directed graph, the connection relationship of the points is M to N, the inside allows the appearance of ring-shaped connection, and the points are placed on a certain point in the row-column layout through comprehensive adjustment, wherein M and N are natural numbers.
3. The method according to claim 1, wherein the row and column layout finally places the instances in the grid formed by the row and column layout according to the connection relationship of the instances, and determines the row and column positions so that the instance positions are concentrated and the instance positions with function dependence are close.
4. A logic circuit graphical display method is characterized by comprising the following steps:
generating or creating netlist data through an EDA tool, and then analyzing the netlist data;
performing placement and routing by using the placement and routing method according to any one of claims 1 to 3;
and calling a component graphic library according to the example type, and designing a graphic method to draw the logic circuit on the screen of the equipment.
5. The logic circuit graphical display method of claim 4, wherein the netlist data comprises: netlist data of any one of user behavior level description, register transfer level optimization, gate level optimization and layout and routing, wherein the netlist data comprises input/output ports, port bit widths and net connection relations of the circuit;
the step of parsing the netlist data includes the substeps of:
converting the circuit into a mathematical model which can be identified by a program, and establishing a data structure to store the circuit connection relation and the circuit information;
traversing all instances in an instance information base, acquiring instance information, and storing the instance information in a memory; wherein the instance information includes the instance name, the instance input-output interface, the instance type, and the instance underlying logic.
6. A logic circuit graphical display system is characterized by comprising a netlist database module, a netlist analysis module, a layout and wiring module, a graphical display module and a component library module;
the netlist database module generates or creates netlist data through an EDA tool; the netlist analyzing module is used for analyzing the netlist data; the placement and routing module places and routes the instance by adopting the method of any one of claims 1 to 3; the component library module is used for calling a manufactured component graphic library; the graphic display module is used for drawing the logic circuit on the screen of the equipment.
7. The system of claim 6, wherein the netlist data comprises: netlist data of any one step of user behavior level description, register transmission level optimization, gate level optimization and layout and wiring, wherein the netlist data comprises input/output ports of a circuit, port bit width and net connection relation;
the netlist analyzing module comprises a netlist analyzing submodule and an example information obtaining submodule, the netlist analyzing submodule is used for converting the circuit into a mathematical model which can be identified by a program, a proper data structure is established, the circuit connection relation and the circuit information are stored, the example information obtaining submodule is used for traversing all examples in an example information base, obtaining the name, the input and output interface and the type of the example and whether the example has a bottom layer logic circuit, and storing the example information in a memory.
8. A logic circuit graphical display system, comprising:
a memory for storing computer executable instructions; and the number of the first and second groups,
a processor for implementing the steps in the method of any one of claims 1 to 5 when executing the computer-executable instructions.
9. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the steps in the method of any one of claims 1 to 5.
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