CN112016259B - Circuit and configuration method thereof - Google Patents

Abstract

A circuit and a method of configuring the same. The circuit including multiple modules and the configuration method thereof include: taking one of the multiple modules as a first-level module, taking modules other than the first-level module as the first remaining modules, and obtaining the first-level module and the first-level module. The number of connections of the boundary timing units in the remaining modules, compare the number of connections between the first-level module and the first-remaining module, and select the first-remaining module with the largest number of connections with the first-level module as the second-level module , and configure the second-level module adjacent to the first-level module.

Description

Circuit and configuration method thereof

technical field

The present invention relates to a circuit and a configuration method thereof, in particular to a circuit and a configuration method thereof configured based on the connected quantity of boundary sequential units between modules.

Background technique

According to the existing technology, front-end engineers can provide a rough data flow, but the data flow provided by front-end engineers is limited by the front-end engineers' understanding of the design and their own experience. The physical implementation tool can also provide data flow, but the data flow provided by the physical implementation tool includes the data cloud in the analysis and the interconnection of all other modules, and there is a lot of interference information. Therefore, if the time sequence path analysis between modules is performed based on these prior art data flows, the analysis results will have situations where the accuracy, real-time performance, and coverage cannot meet the engineering design requirements.

For example, the data flow provided by the data cloud generated by the physical implementation tool using the netlist includes data flow between logical units, data flow between logical units and boundary sequential units, and data flow between boundary sequential units. Because the steady-state output of the logic unit is only related to the input data signal, that is, in the timing path, the logic unit is only equivalent to the node that transmits the data signal, so in some cases, the data flow between the logic units and the logic unit The data flow with the boundary timing unit cannot be used as the data flow between modules. Therefore, directly using the timing paths between modules provided by the data flow analysis provided by the data cloud to guide the settings between modules will lead to deviations in module layout.

SUMMARY OF THE INVENTION

In view of this, the present invention proposes a circuit and a configuration method thereof, which can quickly and accurately organize the data cloud in the netlist structure into a clear data flow to guide the configuration of a circuit in the early stage of design. Through the circuit configuration method proposed by the present invention, the effective data flow between modules is sorted out first. By obtaining the number of connecting lines corresponding to the effective data flow, it can guide the early configuration of the circuit, speed up the design convergence, and reduce the cost. In the design of the present invention, the circuit data configured in the early stage is in line with the actual needs, the probability of data flow cross winding between the modules of the configured circuit is reduced, and it is avoided to increase the design convergence due to iteration caused by the unreasonable physical positions of the circuit modules. time, which is of great help in speeding up timing closure.

An embodiment of the present invention provides a method for configuring a circuit, which is applicable to a circuit including multiple modules, including using one of the multiple modules as a first-level module, and using modules other than the first-level module as the first remaining modules module; obtain the number of connections between the first-level module and the boundary sequence unit in the first remaining module; compare the size of the number of connections between the first-level module and the first remaining module; select the largest number of connections with the first-level module The first remaining modules are second-level modules; and the second-level modules are configured adjacent to the first-level modules.

An embodiment of the present invention provides a circuit, the circuit includes: a first-level module, a first residual module, and a microprocessor, the microprocessor is coupled to the first-level module and the first residual module, and obtains the first-level module and the first-level module and the first residual module. The number of connections of boundary timing units in a remaining module, compare the number of connections between the first-level module and the first remaining module, and select the first remaining module with the largest number of connections with the first-level module as the second-level module module, the second-level module is configured to be adjacent to the first-level module.

Regarding other additional features and advantages of the present invention, those skilled in the art can make some changes and modifications according to the circuit and device configuration method disclosed in the implementation method of the present application without departing from the spirit and scope of the present invention. get.

Description of drawings

FIG. 1 is a schematic diagram of a data cloud 100 generated based on a netlist according to an embodiment of the present invention.

FIG. 2 is a flowchart of a method 200 for directing circuit configuration according to a valid data flow according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a circuit 300 according to an embodiment of the present invention.

FIG. 4 is a flowchart of a method 400 for directing circuit configuration according to a valid data flow according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a circuit 500 according to another embodiment of the present invention.

Detailed ways

In order to make the above-mentioned and other objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings. It should be noted that what is described in this chapter is the best mode for implementing the present invention, and the purpose is to illustrate the spirit of the present invention rather than limit the protection scope of the present invention. It should be understood that the following embodiments can be implemented through software, hardware, firmware or the above any combination to achieve.

FIG. 1 is a schematic diagram of a data cloud 100 generated by a physical implementation tool using a netlist according to an embodiment of the present invention. As shown in FIG. 1 , the data cloud 100 includes modules m1 to m3 and data flows between the modules m1 to m3. The modules m1-m3 include logic modules d1-d3, boundary sequential units r1-r6, and logic units c1-c7. The boundary sequential units r1 to r6 and the logic units c1 to c7 perform data transmission between modules through the connection lines n1 to n4. The data flow between the logic units is, for example, the data flow between the logic unit c5 and the logic unit c7, and the data flow between the logic unit and the boundary sequential unit is, for example, the data flow between the logic unit c5 and the boundary sequential unit r5.

As shown in Figure 1, the signal in the module m3 goes from the boundary sequence unit r5 to the logic unit c5, then passes through the logic unit c7 in the module m1, then goes to the logic unit c6 in the module m2, and finally reaches the boundary sequence unit in the module m2. r6. The signal first passes through the module m3 to the module m1, and then from the module m1 to the module m2. There is no direct data flow between the modules m3 and m2. However, the timing path starts from the timing unit and ends at the timing unit, so in the timing path from the boundary timing unit r5 to the boundary timing unit r6, the logic unit c7 is only equivalent to the node that transmits the signal, and the signal is only from the module m1 (isolated node c7) Passing by, in essence, flows directly from module m3 (boundary sequential unit r5) to module m2 (boundary sequential unit r6). Therefore, if "signals flow from module m3 to module m1, and then from module m1 to module m2" as the data flow between modules m1, m2, and m3, the analysis of the timing paths between modules and the subsequent layout production between modules will be made. wrong guidance. Therefore, in order to obtain the correct data flow between modules, so as to guide the establishment of timing paths between modules and the layout between modules, it is necessary to first extract the data flow between the corresponding boundary timing units from the data flow generated based on the netlist (below). Called valid data flow), for example, from the "signal from the boundary timing unit r5 in the module m3 to the logic unit c5, then through the logic unit c7 in the module m1, to the logic unit c6 in the module m2, and finally to the logic unit c6 in the module m2. The valid data flow between the boundary timing units of "the signal arrives from the boundary timing unit r5 in the module m3 to the boundary timing unit r6 in the module m2" is extracted from the boundary timing unit r6", and the "signal arrives from the module m3" is extracted. Data flow between modules of module m2". According to an embodiment of the present invention, the boundary sequential unit may be a boundary register or an instantiated unit. The following describes the case where the boundary sequential unit is a boundary register and how to extract a valid data stream from the data cloud and subsequent steps to be performed in conjunction with FIG. 2 and FIG. 3 . operation is explained.

FIG. 2 is a flowchart of a method 200 for directing circuit configuration according to an effective data flow according to an embodiment of the present invention, and FIG. 3 is a schematic diagram of a circuit 300 according to an embodiment of the present invention. The method 200 disclosed in FIG. 2 for directing circuit configuration according to a valid data flow is applicable to the circuit 300 shown in FIG. 3 . For ease of understanding, FIG. 3 illustrates that under the module configuration of FIG. 1 , the circuit layout is guided according to the effective data flow guide circuit configuration 200 proposed by the present invention.

2 and 3 at the same time. As shown in FIG. 3 , the circuit 300 includes a microprocessor 310 and a module group 320 . The microprocessor 310 is coupled to the module group 320, the module group 320 includes modules m1-m3, the modules m1-m3 include logic modules d1, d2 and d3, sequence units r1-r6, and logic units c1-c7, and are connected by connecting wires n1- n5 realizes the interconnection between modules, and the arrows on the connecting lines n1 to n5 represent the flow of data between modules. For example, the processor 310 may be a central processing unit (Central Processing Unit, CPU) configured in a computer host, and in this application, the method of instructing the circuit configuration according to the valid data flow is performed.

The main spirit of the present invention is that, because a module may have data flow and connection relationship with multiple modules, first obtain the module and its boundary sequence units according to the level and connection relationship defined in the netlist; then according to the logic of the data cloud The data flow between the units, the data flow between the logic unit and the boundary sequence unit, extract the valid data flow between the boundary sequence units; obtain the number of connection lines between the modules corresponding to the valid data flow, and sort the number of connections between the modules , the module with the largest number of connections with the defined reference module is the lower-level module that can be laid out next to the reference module, wherein the lower-level module and the reference module are configured to be adjacent. According to an embodiment of the present invention, defining the reference module refers to first determining the layout position of the reference module. According to an embodiment of the present invention, obtaining the number of connection lines between modules refers to taking the number of connection lines between at least one boundary sequential cell in one module and at least one boundary sequential cell in another module as the number of connection lines between the two modules. The number of connecting lines.

The method for directing circuit configuration according to the effective data flow of the present invention includes: step S210, the microprocessor 310 obtains the number of connection lines between at least one boundary timing unit in the reference module and at least one boundary timing unit in other multiple modules respectively. ; Step S220, the microprocessor 310 compares the number of connecting lines between the reference module and each module. In step S230, the microprocessor 310 selects the next-level module adjacent to the reference module that can be laid out among other modules with the largest number of connection lines between the reference module and the reference module.

In the first embodiment of the present invention, as in steps S210 to S230 above, referring to FIG. 3 , the module m3 is defined as a reference module. Between module m3 and module m1, the interconnection number of boundary sequential units is 0. Between the boundary sequential unit r5 of module m3 and module m1, there is no boundary sequential unit connected, only combinational logic units c5 and c7 are connected. The connection of the combinational logic unit is not counted, so the number of interconnections is 0. There are boundary sequential units r5 and r6 interconnected between modules m3 and m2, so the interconnection number is 1. That is to say, in the example of Fig. 3, when m3 is the reference module, the lower-level module of module m3 is the module m2 with the maximum number of interconnected boundary timing units, that is to say, the module m2 is the first module after the reference module m3. A lower-level module that can be arranged around the reference module m3 is hereinafter referred to as the first adjacent module.

In the method for guiding circuit configuration according to the effective data flow of the present invention, it further includes step S240: after selecting the first adjacent module, taking the first adjacent module as a reference module, and selecting the remaining modules adjacent to the first adjacent module Among them, the second adjacent module with the highest number of interconnections with the first adjacent module is selected as the lower-level module of the first adjacent module.

Referring to FIG. 3 , after selecting m2 as the first adjacent module, among the adjacent modules m1 and m3 of the module m2, the second adjacent module with the highest number of interconnections with the module m2 is selected. The boundary sequence unit r2 of the module m2 is connected to the boundary sequence unit r1 of the module m1, and the boundary sequence unit r4 of the module m2 is connected to the boundary sequence unit r3 of the module m1, so the number of interconnections between the module m2 and the module m1 is 2. The boundary sequence unit r6 of the module m2 is connected with the boundary sequence unit r5 of the module m3, so the interconnection number between the module m2 and the module m3 is 1. Because the number of interconnections between the modules m2 and m1 is the highest, the module m1 is a subordinate module of the module m2.

Continuing from the above, taking the example of FIG. 3 as an example, according to the method of directing the circuit configuration according to the effective data flow of the present invention, it can be sorted out that the relative data flow of the modules m1, m2 and m3 exists between the module m3 and the module m2. , and between module m2 and module m1.

FIG. 4 is a flowchart of a method for directing circuit configuration according to a valid data flow according to another embodiment of the present invention, and FIG. 5 is a schematic diagram of a circuit 500 according to another embodiment of the present invention. The biggest difference between the circuit 500 and other embodiments is that the circuit 500 includes instantiated modules and ports. The instantiated module refers to a module that the designer formalizes the commonly used functions according to the design requirements. Generally speaking, the circuit function executed by the instantiated module can be adjusted directly by adjusting the input parameters. The instantiated module is a kind of boundary sequential unit, and the port 550 is the data output and input interface of the circuit 500 . In the embodiment of the present invention, the instantiated module is arranged in the region closest to the reference module (port 550 ) among the selected first adjacent modules, so as to facilitate the input and output of data.

The circuit 500 shown in FIG. 5 includes the microprocessor 310 and a module group 520 . The module group 520 includes a module m4 , a module m5 , a module m6 and a module m7 . Module m4 includes instantiated module group 530 , and module m7 includes instantiated module group 540 . The instantiated module group 530 includes 8 instantiated modules, and the instantiated module group 540 includes 4 instantiated modules. Module m4 includes internal logic d4, module m5 includes internal logic d5, module m6 includes internal logic d6, and module m7 includes internal logic d7. The boundary sequential cells r1 to r19 and the logic cells c1 to c15 included in the module group 520 are arranged in different modules. As shown in FIG. 5 , the boundary registers between the modules are interconnected by the boundary sequential units r1 - r19 , the logic units c1 - c15 and the connection lines n1 - n7 .

4 and 5, in this embodiment, when the module group 520 includes or is coupled to the port 550, the port 550 can also be regarded as one of the modules in the module group 520. At this time, the microprocessor 310 first uses the port 550 is used as the reference module to first determine the position, among the modules of the circuit 500, the one with the highest number of interconnections with the port 550 of the circuit 500 is the first adjacent module, and the port 550 is bounded by at least one of the other multiple modules. The number of connection lines of the sequential unit is used as the number of connection lines between the reference module and each other module (step S405 shown in FIG. 4 ). As shown in FIG. 5, the instantiated module group 530 included in the module m4 is interconnected with the port 550. The instantiated module group 530 includes 8 instantiated modules that can be regarded as boundary sequential units, and each instantiated module is connected to the port, Therefore, the number of interconnections between module m4 and port 550 is 8, so the number of interconnections between module m4 and port 550 is the highest. The module m4 is the first adjacent module selected in this embodiment.

In FIG. 5 , the microprocessor 310 continues to use the first adjacent module m4 as a new reference module, and obtains the interconnection numbers of the boundary sequential cells in the first adjacent module m4 and the boundary sequential cells in the remaining modules m5, m6, and m7, respectively. 410, wherein the number of connecting lines between at least one boundary sequential cell in the reference module and at least one boundary sequential cell in other multiple modules is the number of connecting lines between the reference module and each other module. The microprocessor 310 compares the interconnection numbers of boundary sequential cells in the first adjacent module m4 and the remaining modules m5, m6, and m7 (step S420 in FIG. 4). The microprocessor 310 selects, among the remaining modules m5, m6, and m7, the one with the highest interconnection quantity with the first adjacent module m4 as the lower-level module of the first adjacent module m4, that is, the second adjacent module ( Step S430 in FIG. 4 ). Four instantiated modules in the instantiated module group 530 of the first adjacent module m4 are connected to 4 instantiated modules in the instantiated module group 540 of the module m7, and the boundary sequence unit r1 of the first adjacent module m4 is connected to the module The boundary sequential units r15 of m7 are interconnected, so the number of interconnections between the first adjacent module m4 and the module m7 is 5, which is greater than the number of interconnections between the first adjacent module m4 and the other remaining modules m5 and m6. Therefore, the module m7 having the highest number of interconnections with the first adjacent module m4 is the second adjacent module in this embodiment.

Next, after the second adjacent module m7 is selected, among the remaining modules m5 and m6, the lower-level module of the second adjacent module m7 with the highest interconnection quantity with the second adjacent module m7 is selected as the third phase module neighbor module (step S440 in FIG. 4 ). The boundary sequential units r17, r18 and r19 of the module m7 are respectively interconnected with the boundary sequential units r14, r13 and r12 of the module m6, so the number of interconnections between the second adjacent module m7 and the module m6 is three. In the second adjacent module m7, only the boundary sequential unit r16 is connected to the boundary sequential unit r8 of the module m5, so the number of interconnections between the second adjacent module m7 and the module m5 is only one. The next-level module m6 of the second adjacent module m7 is the third adjacent module. At this time, since there is only one module m5 in the remaining modules, the module m5 is directly defined as the subordinate module of the third adjacent module m6, that is, the fourth adjacent module.

As a whole, through the process of guiding the circuit configuration according to the effective data flow proposed by the present invention, it can be sorted out that in the embodiment shown in FIG. , and finally to module m5. After the data flow is sorted through the process of the embodiment of the present invention, the physical layout between the modules can be carried out according to this order, that is, the first adjacent module m4 with the highest number of interconnections with the port 550 is laid out. At the position adjacent to the reference module (port 550 ), the second adjacent module m7 is placed next to the position adjacent to the first adjacent module m4, and the third adjacent module m6 is placed in the second adjacent position. position adjacent to the adjacent module m7, and the fourth adjacent module m5 is arranged at a position adjacent to the third adjacent module m6. In this way, valid data streams extracted from the data cloud can be used to guide the order and location of circuit layouts.

The present invention proposes a method for guiding circuit configuration according to effective data flow, which can generate a data cloud according to the netlist in the initial stage of design, and quickly and accurately extract the circuit configuration in the circuit design instructed by the effective data flow from the data cloud. Through the effective data flow extraction method proposed by the present invention, the position and configuration sequence of the modules in the circuit are guided, which has a great guiding effect on the early layout of the circuit. According to the present invention, the circuit layout based on the effective data flow guidance is consistent with the data flow between the actual required circuit modules, and the probability of data flow cross-entanglement in the physical position of the circuit modules configured by the guidance is effectively reduced. The unreasonable location causes iteration and increases the data transfer time, which is of great help to speed up timing closure.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system and method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention should be determined by the scope defined by the appended claims.

Claims (10)

1. A method of configuring a circuit, the circuit comprising a plurality of modules, the method of configuring the circuit comprising:

one of the plurality of modules is taken as a first-level module;

acquiring at least one first connection quantity of the first-level module and at least one other module;

comparing the at least one first number of connections;

taking the other modules corresponding to the maximum value of the at least one first connecting line number as second-level modules; and

the second level module is disposed adjacent to the first level module,

wherein the first number of connections is a number of connections between at least one boundary timing unit of the other of the plurality of modules and the boundary timing unit of the first-level module.

2. The method of configuring a circuit of claim 1, further comprising:

obtaining at least one second connection quantity of the second-level module and at least one remaining plurality of modules;

taking the rest modules corresponding to the maximum value of the number of the at least one second connecting line as third-stage modules; and

the third level module is disposed adjacent to the second level module,

the second connection number refers to a connection number of at least one boundary timing unit of the remaining modules and the boundary timing unit of the second-level module.

3. The method according to claim 1, further comprising taking the port of the circuit as the first stage module when the plurality of modules include the port of the circuit.

4. The circuit configuration method of claim 1, wherein the boundary timing unit is a boundary register or an instantiation module.

5. A method of configuring a circuit as claimed in claim 4, comprising configuring the instantiation module in the region closest to the first level module when the second level module comprises the instantiation module.

6. A circuit, coupled to a microprocessor, comprising:

a first level module; and

at least one of the other modules is provided with,

wherein, the microprocessor obtains at least one first connecting line quantity of the first-stage module and at least one other module, compares the at least one first connecting line quantity, takes the other module corresponding to the maximum value of the at least one first connecting line quantity as a second-stage module, and configures the second-stage module to be adjacent to the first-stage module,

the first connection quantity refers to the connection quantity of at least one boundary timing unit of one other module and the boundary timing unit of the first-stage module.

7. The circuit of claim 6, wherein the microprocessor obtains at least one second number of connections of the second level module to at least one remaining said other module;

the microprocessor takes the rest other modules corresponding to the maximum value of the number of the at least one second connecting line as third-stage modules; and

the third level module is disposed adjacent to the second level module,

the second connection number refers to a connection number between at least one boundary timing unit of the remaining other modules and the boundary timing unit of the second-level module.

8. The circuit of claim 6, wherein the port of the circuit can be the first stage module.

9. The circuit of claim 6, wherein the boundary timing unit is a boundary register or an instantiating module.

10. The circuit of claim 9, wherein when the second stage module comprises the instantiation module, the instantiation module is configured in an area of the second stage module closest to the first stage module.

Images