CN112016259B

CN112016259B - Circuit and configuration method thereof

Info

Publication number: CN112016259B
Application number: CN202010893469.8A
Authority: CN
Inventors: 李翊; 李小静; 肖婷
Original assignee: VIA Alliance Semiconductor Co Ltd
Current assignee: Shanghai Zhaoxin Semiconductor Co Ltd
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2022-08-30
Anticipated expiration: 2040-08-31
Also published as: CN112016259A

Abstract

A circuit and a configuration method thereof. The circuit comprising a plurality of modules and the configuration method thereof comprise the steps of taking one of the modules as a first-stage module, taking the module except the first-stage module as a first residual module, obtaining the number of connecting lines of the first-stage module and a boundary time sequence unit in the first residual module, comparing the number of the connecting lines of the first-stage module and the first residual module, selecting the first residual module with the largest number of the connecting lines with the first-stage module as a second-stage module, and configuring the second-stage module to be adjacent to the first-stage module.

Description

Circuit and configuration method thereof

Technical Field

The present invention relates to a circuit and a configuration method thereof, and more particularly, to a circuit configured based on the number of connected boundary timing units between modules and a configuration method thereof.

Background

In the prior art, the front-end engineer can provide a rough data stream, but the data stream provided by the front-end engineer is subject to the degree of understanding of the design by the front-end engineer and its own experience. The physical implementation tool can also provide data streams, but the data streams provided by the physical implementation tool include data clouds in the interconnection relationship between the analysis module and all other modules, and the interference information is much. Therefore, if the timing path analysis between modules is performed based on these data streams in the prior art, the accuracy, real-time performance, and coverage of the analysis result may not meet the engineering design requirements.

For example, the data stream provided by the data cloud generated by the physical implementation tool using the Netlist (Netlist) includes data streams between logic cells, data streams between logic cells and boundary timing cells, and data streams between boundary timing cells. Since the steady-state output of the logic unit is only related to the input data signal, that is, the logic unit only corresponds to a node for transmitting the data signal in the timing path, the data flow between the logic units and the data flow between the logic unit and the boundary timing unit cannot be regarded as the data flow between the modules in some cases, and therefore, the deviation of the module layout will be caused if the setting between the modules is guided by the timing path between the modules which is analyzed by directly using the data flow provided by the data cloud.

Disclosure of Invention

In view of the above, the present invention provides a circuit and a configuration method thereof, which quickly and accurately arrange data clouds in a netlist structure into a clear data stream to guide configuration of a circuit in an initial stage of design. By the circuit configuration method provided by the invention, the effective data stream between the modules is firstly cleared up. By acquiring the number of the connecting lines corresponding to the effective data stream, the early configuration of the circuit is guided, the design convergence is accelerated, and the cost is reduced. In the design of the invention, the data of the circuit configured in the early stage is consistent with the actual requirement, the probability of the data stream cross winding among the modules of the configured circuit is reduced, the increase of the design convergence time caused by the iteration due to the unreasonable physical positions configured by the circuit modules is avoided, and the invention is greatly helpful for accelerating the timing sequence convergence.

The embodiment of the invention provides a configuration method of a circuit, which is suitable for a circuit comprising a plurality of modules, and comprises the steps of taking one of the modules as a first-stage module, and taking the modules except the first-stage module as first residual modules; acquiring the number of connecting lines of the boundary time sequence units in the first-stage module and the first residual module; comparing the number of the connecting lines of the first-stage module and the first residual module; selecting a first residual module with the largest number of connecting lines with the first-stage module as a second-stage module; and configuring the second level module adjacent to the first level module.

An embodiment of the present invention provides a circuit, including: the microprocessor is coupled to the first stage module and the first residual module, acquires the number of connecting lines of boundary timing sequence units in the first stage module and the first residual module, compares the number of the connecting lines of the first stage module and the first residual module, selects the first residual module with the largest number of the connecting lines with the first stage module as a second stage module, and configures the second stage module to be adjacent to the first stage module.

Other additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention.

Drawings

Fig. 1 is a schematic diagram of a data cloud 100 generated based on a netlist according to an embodiment of the present invention.

Fig. 2 is a flow chart of a method 200 for directing circuit configuration according to an active data stream according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a circuit 300 according to an embodiment of the invention.

FIG. 4 is a flowchart of a method 400 for directing a circuit configuration according to an active data stream according to another embodiment of the present invention.

Fig. 5 is a schematic diagram of a circuit 500 according to another embodiment of the invention.

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. It is noted that while the best mode for carrying out the invention has been described in this section for the purpose of illustrating the spirit of the invention and not for the purpose of limiting the scope of the invention, it should be understood that the following embodiments may be implemented in software, hardware, firmware or any combination thereof.

Fig. 1 is a schematic diagram of a data cloud 100 generated by a physical implementation tool using a netlist according to an embodiment of the present invention. As shown in FIG. 1, the data cloud 100 includes data flows between modules m 1-m 3 and modules m 1-m 3. The modules m 1-m 3 include logic modules d 1-d 3, boundary timing units r 1-r 6 and logic units c 1-c 7. The boundary timing units r1 to r6 and the logic units c1 to c7 perform data transmission between modules through the connection lines n1 to n 4. The data flow between logic units is, for example, the data flow between logic unit c5 and logic unit c7, and the data flow between logic unit and boundary timing unit is, for example, the data flow between logic unit c5 and boundary timing unit r 5.

As shown in FIG. 1, signals in block m3 go from boundary timing cell r5 to logic cell c5, then through logic cell c7 in block m1, then to logic cell c6 in block m2, and finally to boundary timing cell r6 in block m 2. The signal goes from block m3 to block m1, then from block m1 to block m2, and there is no direct data flow between blocks m3 and m 2. However, since the timing path starts from the timing cell and ends at the timing cell, in the timing path from the boundary timing cell r5 to the boundary timing cell r6, the logic cell c7 only corresponds to the node for transmitting signals, and the signals only pass through the module m1 (isolated node c7), and essentially flow directly from the module m3 (boundary timing cell r5) to the module m2 (boundary timing cell r 6). Therefore, if the "signal flows from the module m3 to the module m1 and then from the module m1 to the module m 2" is used as the data flow among the modules m1, m2 and m3, the analysis of the timing path among the modules and the subsequent layout of the modules will be guided erroneously. Therefore, in order to obtain a correct data flow between modules and thus guide the establishment of inter-module timing paths and the layout between modules, it is necessary to extract a data flow (hereinafter referred to as an effective data flow) between corresponding boundary timing units from a data flow generated based on a netlist, for example, to extract an effective data flow between boundary timing units from a signal from the boundary timing unit r5 to the logic unit c5 in the module m3, then to pass through the logic unit c7 in the module m1, then to the logic unit c6 in the module m2, and finally to the boundary timing unit r6 "in the module m2, and to extract a data flow between boundary timing units from the boundary timing unit r5 in the module m3 to the boundary timing unit r 6" in the module m2, and thus to extract a data flow between boundary timing units from the module m3 to the module m 2. According to an embodiment of the present invention, the boundary timing unit may be a boundary register or an instantiation unit, and the following description will be given with reference to fig. 2 and fig. 3 with respect to a case where the boundary timing unit is a boundary register and how to extract an effective data stream from a data cloud and a subsequent operation to be performed.

Fig. 2 is a flowchart of a circuit configuration method 200 according to an embodiment of the invention, and fig. 3 is a schematic diagram of a circuit 300 according to an embodiment of the invention. The method 200 disclosed in fig. 2 for directing circuit configuration according to an active data stream is applicable to the circuit 300 shown in fig. 3. For ease of understanding, fig. 3 illustrates a circuit arrangement directed according to the efficient data flow directed circuit configuration 200 proposed by the present invention under the module configuration of fig. 1.

Reference is also made to fig. 2 and 3. As shown in FIG. 3, the circuit 300 includes a microprocessor 310 and a module group 320. The microprocessor 310 is coupled to a module group 320, the module group 320 includes modules m 1-m 3, the modules m 1-m 3 include logic modules d1, d2 and d3, timing units r 1-r 6 and logic units c 1-c 7, and the modules are interconnected through connecting lines n 1-n 5, and arrows on the connecting lines n 1-n 5 represent the flow direction of data between the modules. For example, the processor 310 may be a Central Processing Unit (CPU) configured in a computer host, and the method for directing circuit configuration according to the valid data stream is executed in the present application.

The main spirit of the invention is that, because a module may have data flow and connection relation with a plurality of modules, the module and the boundary time sequence unit therein are obtained according to the level and connection relation defined in the netlist; extracting effective data streams between the boundary time sequence units according to data streams between the logic units of the data cloud and data streams between the logic units and the boundary time sequence units; and acquiring the number of connecting lines among the modules corresponding to the effective data stream, sequencing the number of the connecting lines among the modules, and determining the module with the largest number of the connecting lines among the defined reference modules, namely a subordinate module which can be arranged next to the reference module, wherein the subordinate module and the reference module are configured to be adjacent. According to an embodiment of the present invention, defining the reference module means first determining a layout position of the reference module. According to an embodiment of the present invention, obtaining the number of the connection lines between the modules means that the number of the connection lines between at least one boundary timing unit in one module and at least one boundary timing unit in another module is equal to the number of the connection lines between the two modules.

The method for guiding circuit configuration according to the effective data flow comprises the following steps: step S210, the microprocessor 310 obtains the number of connection lines between at least one boundary timing unit in the reference module and at least one boundary timing unit in other modules; in step S220, the microprocessor 310 compares the number of connection lines between the reference module and each module. In step S230, the microprocessor 310 selects the next module having the largest number of connecting lines with the reference module from the other modules as the next module that can be arranged adjacent to the reference module.

In the first embodiment of the present invention, as in the above steps S210 to S230, referring to fig. 3, the module m3 is defined as a reference module. The number of interconnections between the module m3 and the module m1 is 0, and between the boundary timing unit r5 of the module m3 and the module m1, there is no boundary timing unit, only the combinational logic units c5 and c7 are connected, and the connections of the combinational logic units are not counted, so the number of interconnections is 0. And the boundary timing units r5 and r6 are interconnected between the modules m3 and m2, so the number of interconnections is 1. That is, in the example of fig. 3, when m3 is the reference module, the lower module of the module m3 is the module m2 having the largest number of boundary timing unit interconnections, that is, the module m2 is the lower module which can be first laid out around the reference module m3 after the reference module m3, and is referred to as the first adjacent module.

In the method for directing circuit configuration according to the valid data stream of the present invention, further comprises step S240: and after the first adjacent module is selected, selecting a second adjacent module with the highest interconnection quantity with the first adjacent module from the rest of modules adjacent to the first adjacent module by taking the first adjacent module as a reference module, and taking the second adjacent module as a lower module of the first adjacent module.

Referring to fig. 3, after m2 is selected as the first neighbor module, the second neighbor module having the highest number of interconnections with module m2 is selected from among the neighbor modules m1 and m3 of module m 2. The boundary timing cell r2 of module m2 is connected to the boundary timing cell r1 of module m1, and the boundary timing cell r4 of module m2 is connected to the boundary timing cell r3 of module m1, so the number of interconnections between module m2 and module m1 is 2. And the boundary timing unit r6 of the module m2 is connected with the boundary timing unit r5 of the module m3, so the number of interconnections between the module m2 and the module m3 is 1. Since the module m2 has the highest number of interconnections with the module m1, the module m1 is a lower module of the module m 2.

As described above, in the example of fig. 3, if the method for directing the circuit configuration according to the valid data stream according to the present invention is used, it can be concluded that data streams corresponding to modules m1, m2, and m3 exist between module m3 and module m2, and between module m2 and module m 1.

Fig. 4 is a flowchart illustrating a method for directing circuit configuration according to an efficient data flow according to another embodiment of the present invention, and fig. 5 is a schematic diagram illustrating a circuit 500 according to another embodiment of the present invention. The circuit 500 differs from the other embodiments most significantly in that the circuit 500 includes an instantiating block and a port. The instantiation module refers to a module in which a designer normalizes a common function according to a design requirement, and generally speaking, the circuit function executed by the instantiation module can be directly adjusted by adjusting an input parameter. The instantiation module is one of the boundary timing units, and the port 550 is the data input and output interface of the circuit 500. In the embodiment of the present invention, the instantiated module is disposed in the area closest to the reference module (port 550) in the selected first neighboring module for facilitating the data input and output.

The circuit 500 shown in FIG. 5 includes a microprocessor 310 and a module group 520, wherein the module group 520 includes a module m4, a module m5, a module m6 and a module m 7. Module m4 includes an instantiating module set 530 and module m7 includes an instantiating module set 540. The instantiation module group 530 includes 8 instantiation modules, and the instantiation module group 540 includes 4 instantiation modules. Module m4 includes internal logic d4, module m5 includes internal logic d5, module m6 includes internal logic d6, and module m7 includes internal logic d 7. The boundary timing cells r 1-r 19 and the logic cells c 1-c 15 of the module group 520 are arranged in different modules. As shown in FIG. 5, the boundary registers between the modules are interconnected by the boundary timing units r 1-r 19, the logic units c 1-c 15 and the connection lines n 1-n 7.

Referring to fig. 4 and 5, in the present embodiment, when the module group 520 includes or is coupled to the port 550, the port 550 may also be regarded as one of the modules in the module group 520, and at this time, the microprocessor 310 first uses the port 550 as a reference module for determining a position first, selects a module having the highest interconnection number with the port 550 of the circuit 500 as a first adjacent module in each module of the circuit 500, and uses the number of connection lines of the port 550 and at least one boundary timing unit in other modules as the number of connection lines of the reference module and each other module (step S405 shown in fig. 4). As shown in fig. 5, the module m4 includes an instantiated module group 530 interconnected with the port 550, the instantiated module group 530 includes 8 instantiated modules which can be regarded as boundary timing units, and each instantiated module is connected with the port, so the number of interconnections between the module m4 and the port 550 is 8, so the highest number of interconnections with the port 550 is the module m4, the connections between other modules m5, m6 and m7 with the port are less than the number of interconnections between the module m4 and the port 550, and the module m4 is the first adjacent module selected in this embodiment.

The microprocessor 310 in fig. 5 continues to use the first neighboring module m4 as a new reference module to respectively obtain the interconnection numbers of the boundary timing unit in the first neighboring module m4 and the boundary timing units in the remaining modules m5, m6 and m7, i.e., step S410 in fig. 4, wherein the connection number of the at least one boundary timing unit in the reference module and the at least one boundary timing unit in the other modules is used as the connection number of the reference module and each other module. The microprocessor 310 compares the number of interconnections of the boundary timing cells between the remaining modules m5, m6 and m7 in the first adjacent module m4 (step S420 of fig. 4). The microprocessor 310 selects a lower module, i.e., a second neighboring module, as the first neighboring module m4, having the highest number of interconnections with the first neighboring module m4 among the remaining modules m5, m6 and m7 (step S430 of fig. 4). The 4 instantiation modules in the instantiation module group 530 of the first adjacent module m4 are connected to the 4 instantiation modules in the instantiation module group 540 of the module m7, and the boundary timing unit r1 of the first adjacent module m4 is interconnected to the boundary timing unit r15 of the module m7, so the number of interconnections between the first adjacent module m4 and the module m7 is 5, which is greater than the number of interconnections between the first adjacent module m4 and the other remaining modules m5 and m 6. Therefore, the module m7 having the highest number of interconnections with the first adjacent module m4 is the second adjacent module of the present embodiment.

Next, after the second adjacent module m7 is selected, the lower module of the second adjacent module m7 having the highest interconnection number with the second adjacent module m7 is selected as the third adjacent module among the remaining modules m5 and m6 (step S440 of fig. 4). The boundary timing cells r17, r18 and r19 of the module m7 are interconnected with the boundary timing cells r14, r13 and r12 of the module m6, respectively, so the number of interconnections of the second adjacent module m7 and the module m6 is 3. And the second adjacent module m7 has only boundary timing unit r16 connected to boundary timing unit r8 of module m5, so the number of interconnections between the second adjacent module m7 and module m5 is only 1. The next stage module m6 of the second adjacent module m7 is a third adjacent module. At this time, since the remaining module has only one module m5, the module m5 is directly defined as a lower module of the third neighboring module m6, i.e., a fourth neighboring module.

Overall, the flow of the circuit configuration according to the efficient data flow proposed by the present invention can be collated into the embodiment shown in fig. 5, in which the layout sequence starts from block m4, goes to block m7, goes to block m6, and finally goes to block m 5. After the data stream arrangement is performed through the flow of the embodiment of the present invention, the physical layout between the modules may be performed according to the order, that is, the first adjacent module m4 having the highest number of interconnections with the port 550 is laid out at a position adjacent to the reference module (port 550), and then the second adjacent module m7 is laid out at a position adjacent to the first adjacent module m4, the third adjacent module m6 is laid out at a position adjacent to the second adjacent module m7, and the fourth adjacent module m5 is laid out at a position adjacent to the third adjacent module m6 in this order. As such, the valid data stream extracted from the data cloud can be used to guide the order and location of the circuit layout.

The invention provides a method for guiding circuit configuration according to effective data flow, which can generate data cloud according to a net list at the initial stage of design and quickly and accurately extract the effective data flow from the data cloud to guide the circuit configuration in circuit design. The effective data stream extraction method provided by the invention guides the position and configuration sequence of modules in the circuit, and has great guidance effect on the early layout of the circuit. The circuit layout guided by effective data flow conforms to the data flow between the actually needed circuit modules, the probability of data flow cross winding of the configured circuit modules in the physical position is guided to be effectively reduced, the increase of data transmission time caused by iteration due to unreasonable physical positions configured by the modules is avoided, and great help is brought to the acceleration of time sequence convergence.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. For example, the systems and methods described in the embodiments of the present invention may be implemented in physical embodiments in hardware, software, or a combination of hardware and software. Therefore, the scope of the present invention is defined by the appended claims.

Claims

1. A method of configuring a circuit, the circuit comprising a plurality of modules, the method of configuring the circuit comprising:

one of the plurality of modules is taken as a first-level module;

acquiring at least one first connection quantity of the first-level module and at least one other module;

comparing the at least one first number of connections;

taking the other modules corresponding to the maximum value of the at least one first connecting line number as second-level modules; and

the second level module is disposed adjacent to the first level module,

wherein the first number of connections is a number of connections between at least one boundary timing unit of the other of the plurality of modules and the boundary timing unit of the first-level module.

2. The method of configuring a circuit of claim 1, further comprising:

obtaining at least one second connection quantity of the second-level module and at least one remaining plurality of modules;

taking the rest modules corresponding to the maximum value of the number of the at least one second connecting line as third-stage modules; and

the third level module is disposed adjacent to the second level module,

the second connection number refers to a connection number of at least one boundary timing unit of the remaining modules and the boundary timing unit of the second-level module.

3. The method according to claim 1, further comprising taking the port of the circuit as the first stage module when the plurality of modules include the port of the circuit.

4. The circuit configuration method of claim 1, wherein the boundary timing unit is a boundary register or an instantiation module.

5. A method of configuring a circuit as claimed in claim 4, comprising configuring the instantiation module in the region closest to the first level module when the second level module comprises the instantiation module.

6. A circuit, coupled to a microprocessor, comprising:

a first level module; and

at least one of the other modules is provided with,

wherein, the microprocessor obtains at least one first connecting line quantity of the first-stage module and at least one other module, compares the at least one first connecting line quantity, takes the other module corresponding to the maximum value of the at least one first connecting line quantity as a second-stage module, and configures the second-stage module to be adjacent to the first-stage module,

the first connection quantity refers to the connection quantity of at least one boundary timing unit of one other module and the boundary timing unit of the first-stage module.

7. The circuit of claim 6, wherein the microprocessor obtains at least one second number of connections of the second level module to at least one remaining said other module;

the microprocessor takes the rest other modules corresponding to the maximum value of the number of the at least one second connecting line as third-stage modules; and

the third level module is disposed adjacent to the second level module,

the second connection number refers to a connection number between at least one boundary timing unit of the remaining other modules and the boundary timing unit of the second-level module.

8. The circuit of claim 6, wherein the port of the circuit can be the first stage module.

9. The circuit of claim 6, wherein the boundary timing unit is a boundary register or an instantiating module.

10. The circuit of claim 9, wherein when the second stage module comprises the instantiation module, the instantiation module is configured in an area of the second stage module closest to the first stage module.