CN113177380B - Time sequence optimization method based on dummy - Google Patents
Time sequence optimization method based on dummy Download PDFInfo
- Publication number
- CN113177380B CN113177380B CN202110477027.XA CN202110477027A CN113177380B CN 113177380 B CN113177380 B CN 113177380B CN 202110477027 A CN202110477027 A CN 202110477027A CN 113177380 B CN113177380 B CN 113177380B
- Authority
- CN
- China
- Prior art keywords
- dummy
- path
- timing
- repair
- slack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/10—Internal combustion engine [ICE] based vehicles
- Y02T10/40—Engine management systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A timing optimization method based on dummy includes the steps: step S1: constructing a dummy library; step S2: analyzing the physical design time sequence to prepare data for formulating a proper repair strategy; step S3: processing the data in the step S2, classifying the timing violations, and dividing the timing violations into a data path and a clock path according to different repair paths; wherein the data path may be used to repair hold time hold violations and the clock path may be used to repair setup time setup and hold time hold violations; step S4: repairing the data path by inserting dummy; step S5: repairing the clock path by inserting dummy; step S6: and (5) re-performing static time sequence STA analysis to finish time sequence violation repair. The method has the advantages of simple principle, low implementation cost, capability of rapidly and accurately repairing the time sequence violations and the like.
Description
Technical Field
The invention mainly relates to the technical field of high-performance chip design, in particular to a dummy-based time sequence optimization method.
Background
For high performance chip designs, high frequencies are often accompanied by increased performance, which means higher demands on the timing. However, as the frequency increases, the timing is more and more difficult to converge, and the timing violations are more and more difficult to repair, especially the critical paths become very "sensitive", which looks like small changes, perhaps large changes, to the critical paths, which intangibly increase the difficulty of physical design, and increase the design iteration period.
For example, chinese patent application CN202010791428.8 discloses a method for timing repair of a chip circuit, the method for timing repair comprising: determining a virtual area corresponding to a driving unit in a chip circuit, and dividing the virtual area into a plurality of virtual subareas with equal areas by utilizing N virtual lines; setting a virtual subarea with the largest fan-out units as a target area, and executing buffer adding operation in the target area; and after the buffer adding operation is finished, if the target area does not meet the time sequence design rule constraint, taking the buffer as a new driving unit, and executing the operation of determining the virtual area corresponding to the driving unit in the chip circuit.
For another example, chinese patent application CN201811475551.8 discloses a timing repair method based on a time margin, comprising: step 1, extracting netlist information of all paths in a chip layout, and then entering step 2; step 2, determining a time sequence violation path and a corresponding time allowance thereof in the generated static time sequence analysis based on the configured time sequence constraint condition, and then entering step 3; step 3, judging whether the time allowance is larger than a preset threshold value, if so, determining a starting point or an ending point of a preset analysis path in the time sequence violation path, and adjusting the clock delay of the time sequence violation path; otherwise, based on the static time sequence analysis, extracting logic units on a data path and a clock path, further extracting logic modules connected with a time sequence violation path and network information thereof, adjusting the line length between the logic modules connected with the time sequence violation path, performing optimized layout according to the optimized line length, and returning to the step 1. The design area of the chip can be reduced, and the working frequency of the chip can be improved.
For another example, chinese patent application CN201010234176.5 discloses a timing repair method that solves the problem of increased chip design area caused by repair of timing circuits in integrated circuit applications by employing an intervention on the clock path to partially shift the design problem of the data path to the clock path. The method comprises the following steps: analyzing characteristics of the timing violation counter; analyzing paths with violations; when the paths with all starting points as starting points have enough setup time allowance and the paths with all starting points as finishing points have enough hold time allowance, repairing a hold time sequence mode by adopting a mode of increasing clock delay of the starting points of the paths; when there is enough setup time margin for all paths whose end points are end points and enough hold time margin for all paths whose end points are start points, a method of repairing hold time sequence by shortening clock delay of the end points of the paths is entered. According to the scheme, different clock delay design modes are selected, so that the circuit complexity of the integrated circuit chip design can be effectively reduced, and the design area of the chip is reduced.
However, the conventional technical schemes including the above schemes are very complex to implement, and either the original hardware topology structure needs to be changed, or the accuracy and the repair efficiency are low, and the consistency and observability before and after repair cannot be ensured.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides the dummy-based time sequence optimization method which is simple in principle, low in implementation cost and capable of rapidly and accurately repairing time sequence violations.
In order to solve the technical problems, the invention adopts the following technical scheme:
a timing optimization method based on dummy includes the steps:
step S1: constructing a dummy library;
step S2: analyzing the physical design time sequence to prepare data for formulating a proper repair strategy;
step S3: processing the data in the step S2, classifying the timing violations, and dividing the timing violations into a data path and a clock path according to different repair paths; the data path can be used for repairing the hold time hold violations, and the clock path can be used for repairing the setup time setup and hold time hold violations;
step S4: repairing the data path by inserting dummy;
step S5: repairing a clock path by inserting dummy;
step S6: and (5) re-performing static time sequence STA analysis to finish time sequence violation repair.
As a further improvement of the process of the invention: in step S1, a dummy library is constructed by using an existing cell construction.
As a further improvement of the process of the invention: in step S2, the physical design timing sequence is analyzed to obtain information of the size, position, number and distribution of violations, so as to form a reference basis for preparing data for formulating a proper repair strategy.
As a further improvement of the process of the invention: in step S3, the data path and the clock path are divided into weights given during repair, and the processing clock path is weighted higher than the data path.
As a further improvement of the process of the invention: the higher weight of the clock path than the data path means that the clock path is embodied in the number or type of dummy.
As a further improvement of the process of the invention: in the steps S4 and S5, dummy is inserted in parallel, and the repair of the illegal path is realized through dummy in equivalent Delay.
As a further improvement of the process of the invention: the step S4 includes:
step S401: selecting an X node of an insertion point, and calculating the size and the number of dummy to be inserted according to the violation value slack;
step S402: taking the X node as a branch, connecting one or more dummy into the X node in a parallel mode, wherein the operation does not change the logic structure and the hierarchy of the original path;
step S403: and the repair of the illegal path is realized by adjusting the equivalent Delay of the X node.
As a further improvement of the process of the invention: the step S5 includes:
step S501: selecting a proper insertion point Y node, and calculating the size and the number of dummy to be inserted according to the violation value slack;
step S502: the Y node is taken as a branch, one or more dummy are connected into the Y node in parallel, and the operation does not change the logic structure and the hierarchy of the original path;
step S503: and the repair of the illegal path is realized by adjusting the equivalent Delay of the Y node.
As a further improvement of the process of the invention: the violation value slack is a time sequence result obtained through a physical design tool and comprises an establishment time slack and a maintenance time slack, wherein the positive time slack indicates that the time sequence meets the requirement, and the negative time slack indicates that the time sequence does not meet the requirement, namely the time sequence violations need to be corrected.
Compared with the prior art, the invention has the advantages that:
1. the dummy-based time sequence optimizing method has the advantages of simple principle, low realization cost, rapid and accurate repair of time sequence violations, no need of introducing a new network (net), direct connection into the existing network in a parallel connection mode, and great reduction of design complexity compared with the traditional repair method.
2. The dummy-based time sequence optimization method does not need to change the original logic, changes the original topological structure of the design less, ensures the consistency of the logic before and after the design, and can conveniently and clearly see the change before and after the time sequence repair.
3. The dummy-based time sequence optimization method provided by the invention can completely restore one or more previous steps when design errors or repair errors are encountered and rollback is needed, and the design consistency is not affected.
4. According to the dummy-based time sequence optimization method, the equivalent Delay of the inserted dummy is high in precision and large in configurable range, and the excessive repair of the illegal path can be effectively prevented, so that the purposes of accuracy and effectiveness are achieved, and resources are saved.
Drawings
FIG. 1 is a schematic flow chart of the method of the invention in a specific example.
FIG. 2 is a schematic diagram of the present invention in a specific application example for repairing on a data path.
Fig. 3 is a schematic diagram of the present invention in a specific application example for repairing on a clock path.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific examples.
As shown in FIG. 1, the method for optimizing time sequence based on dummy comprises the following steps:
step S1: constructing a dummy library;
step S2: analyzing the physical design time sequence to prepare data for formulating a proper repair strategy;
step S3: processing the data in the step S2, classifying the timing violations, and dividing the timing violations into a data path (data path) and a clock path (clock path) according to different repair paths; the data path may be used to repair hold time (hold) violations, and the clock path may be used to repair setup time (setup) and hold time (hold) violations.
Step S4: repairing a data path (data path), namely inserting dummy in a parallel manner, and realizing the repair of the illegal path by equivalent Delay through the dummy;
step S5: repairing a clock path, namely inserting dummy in a parallel manner, and realizing the repair of the illegal path by equivalent Delay through the dummy;
step S6: and (5) carrying out static time Sequence (STA) analysis again to finish time sequence violation repair.
In step S1, a dummy library designed by the user may be selected according to actual needs, or existing cells (cells) may be utilized, and in a specific application example of the present invention, a plurality of common cells are selected from the design library, and data shown in table 1 is obtained through experiments or simulations, where the weight is only a label;
TABLE 1dummy correspondence library
| Unit name | Input load | Equivalent delay time | Weight of the belonged |
| cell_1 | Cload_1 | Delay_1 | Class A |
| cell_2 | Cload_2 | Delay_2 | Class B |
| …… | …… | …… | |
| cell_n-1 | Cload_n-1 | Delay_n-1 | Class B |
| cell_n | Cload_n | Delay_n | Class A |
In a specific application example, in step S2, information of the size, the position, the number, the distribution, etc. of the violations can be obtained by analyzing the physical design timing sequence, so as to form a reference basis for preparing data for formulating a proper repair strategy.
In a specific application example, in step S3, the data path (data path) and the clock path (clock path) are differentiated, the clock path is processed more finely than the data path, and the weights can be determined by the designer.
In a specific application example, in step S4, for the repair on the data path, as shown in fig. 2, the detailed flow in this example includes:
step S401: selecting a proper insertion point (taking an X node as an example), and calculating the size and the number of the dummy to be inserted according to the violation value (slot); the size and the number of the dummy are confirmed according to the size of the slack;
step S402: taking the X node as a branch, connecting one or more dummy into the X node in a parallel mode, wherein the operation does not change the logic structure and the hierarchy of the original path;
step S403: and the repair of the illegal path is realized by adjusting the equivalent Delay of the X node.
In a specific application example, in step S5, for repair on the clock path, as shown in fig. 3, the detailed flow in this example includes:
step S501: selecting a proper insertion point (taking a Y node as an example), and calculating the size and the number of dummy needed to be inserted according to a violation value (slot);
step S502: the Y node is taken as a branch, one or more dummy are connected into the Y node in parallel, and the operation does not change the logic structure and the hierarchy of the original path;
step S503: and the repair of the illegal path is realized by adjusting the equivalent Delay of the Y node.
In a specific application example, the equivalent Delay, namely the cell corresponding unit Delay, can be obtained through Hsepice simulation, can also be obtained through RC parameter extraction calculation from practical application, and can also be obtained through searching the corresponding simulation value in the time sequence library provided by a process manufacturer.
In a specific application example, the violation value slot is a timing result obtained through a physical design tool, and includes a setup time slot and a hold time slot, where the slot is positive and indicates that the timing meets the requirement, and the slot is negative and indicates that the timing does not meet the requirement, that is, the timing violation needs to be corrected.
As a specific example, assume a path of regtrerg, startpoint is A, endpoint is B, and the hold time of A to B violates-0.120 ns; then a delay of at least 0.120ns on the datapath a to B is required to make the hold time meet the timing requirement;
if the equivalent delay corresponding to the cell_n is 0.030ns, 4 cells_n need to be inserted;
then if the equivalent delay for cell n-1 is 0.060ns, then 2 cells n-1 need to be inserted.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (8)
1. The time sequence optimizing method based on dummy is characterized by comprising the following steps:
step S1: constructing a dummy library;
step S2: analyzing the physical design time sequence to prepare data for formulating a proper repair strategy;
step S3: processing the data in the step S2, classifying the timing violations, and dividing the timing violations into a data path and a clock path according to different repair paths; the data path is used for repairing the hold time hold violations, and the clock path is used for repairing the setup time setup and hold time hold violations;
step S4: repairing the data path by inserting dummy;
step S5: repairing a clock path by inserting dummy;
step S6: performing static time sequence STA analysis again to finish time sequence violation repair;
the step S4 includes:
step S401: selecting an X node of an insertion point, and calculating the size and the number of dummy to be inserted according to the violation value slack;
step S402: taking the X node as a branch, connecting one or more dummy into the X node in a parallel mode, wherein the operation does not change the logic structure and the hierarchy of the original path;
step S403: the repair of the illegal path is realized by adjusting the equivalent Delay of the X node;
the step S5 includes:
step S501: selecting a proper insertion point Y node, and calculating the size and the number of dummy to be inserted according to the violation value slack;
step S502: the Y node is taken as a branch, one or more dummy are connected into the Y node in parallel, and the operation does not change the logic structure and the hierarchy of the original path;
step S503: and the repair of the illegal path is realized by adjusting the equivalent Delay of the Y node.
2. The dummy-based timing optimization method according to claim 1, wherein in step S1, a dummy library is constructed using existing cell construction.
3. The dummy-based timing optimization method according to claim 1, wherein in step S2, the physical design timing is analyzed to obtain information of the size, position, number, and distribution of violations, and a reference is formed for preparing data for formulating an appropriate repair strategy.
4. A dummy-based timing optimization method according to claim 1, 2 or 3, wherein in step S3, the weights given in repair are differentiated for the data path and the clock path, and the processing clock path is weighted higher than the data path.
5. The dummy-based timing optimization method as recited in claim 4, wherein the clock path is higher than the data path weight by a finger that is embodied in the number or type of dummy.
6. A dummy-based timing optimization method according to claim 1, 2 or 3, wherein dummy is inserted in parallel in steps S4 and S5, and repair of the offending path is implemented by dummy with equivalent Delay.
7. The dummy-based timing optimization method of claim 1, wherein the violation value slack is a timing result obtained by a physical design tool, and includes a setup time slack, and a hold time slack, where slack is positive to indicate that the timing satisfies the requirement, and slack is negative to indicate that the timing does not satisfy the requirement, that is, the timing violation needs to be corrected.
8. The dummy-based timing optimization method of claim 1, wherein the violation value slack is a timing result obtained by a physical design tool, and includes a setup time slack, and a hold time slack, where slack is positive to indicate that the timing satisfies the requirement, and slack is negative to indicate that the timing does not satisfy the requirement, that is, the timing violation needs to be corrected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110477027.XA CN113177380B (en) | 2021-04-29 | 2021-04-29 | Time sequence optimization method based on dummy |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110477027.XA CN113177380B (en) | 2021-04-29 | 2021-04-29 | Time sequence optimization method based on dummy |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113177380A CN113177380A (en) | 2021-07-27 |
| CN113177380B true CN113177380B (en) | 2023-05-23 |
Family
ID=76925438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110477027.XA Active CN113177380B (en) | 2021-04-29 | 2021-04-29 | Time sequence optimization method based on dummy |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113177380B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114742001B (en) * | 2022-03-16 | 2023-08-29 | 南京邮电大学 | System static time sequence analysis method based on multiple FPGA |
| CN115577675B (en) * | 2022-11-23 | 2023-03-07 | 飞腾信息技术有限公司 | Time sequence violation repairing method and device, server and readable storage medium |
| CN116402011B (en) * | 2023-05-26 | 2023-11-03 | 南京芯驰半导体科技有限公司 | Method and storage medium for inter-path convergence offset for EDA software |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456087A (en) * | 2010-11-03 | 2012-05-16 | 上海华虹集成电路有限责任公司 | Method for repairing establishing timing sequence |
| CN109583103A (en) * | 2018-12-04 | 2019-04-05 | 珠海市微半导体有限公司 | A kind of time sequence repairing method based on time margin |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8519444B2 (en) * | 2010-09-10 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modified design rules to improve device performance |
| US8522186B2 (en) * | 2011-12-16 | 2013-08-27 | Industrial Technology Research Institute | Method and apparatus of an integrated circuit |
| CN104714842B (en) * | 2013-12-17 | 2018-04-13 | 北京华大九天软件有限公司 | It is a kind of to adjust clock path delay to repair the method for sequential violation |
| US10199082B2 (en) * | 2016-01-18 | 2019-02-05 | Avago Technologies International Sales Pte. Limited | Automatic delay-line calibration using a replica array |
| KR102539066B1 (en) * | 2018-11-09 | 2023-06-01 | 삼성전자주식회사 | Integrated circuit including different types of cells, and method and system of designing the same |
| CN111950226A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Chip back end design and layout design method, tool, chip and storage medium |
| CN112232005B (en) * | 2020-09-25 | 2023-03-28 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, equipment and storage medium for repairing hold time violation |
| CN112069763B (en) * | 2020-09-29 | 2022-11-29 | 上海兆芯集成电路有限公司 | Method for correcting circuit |
| CN112214960B (en) * | 2020-10-13 | 2023-07-25 | 飞腾信息技术有限公司 | Redundant metal filling method and system considering integrated circuit time sequence |
-
2021
- 2021-04-29 CN CN202110477027.XA patent/CN113177380B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456087A (en) * | 2010-11-03 | 2012-05-16 | 上海华虹集成电路有限责任公司 | Method for repairing establishing timing sequence |
| CN109583103A (en) * | 2018-12-04 | 2019-04-05 | 珠海市微半导体有限公司 | A kind of time sequence repairing method based on time margin |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113177380A (en) | 2021-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113177380B (en) | Time sequence optimization method based on dummy | |
| US6397170B1 (en) | Simulation based power optimization | |
| US8875082B1 (en) | System and method for detecting and prescribing physical corrections for timing violations in pruned timing data for electronic circuit design defined by physical implementation data | |
| US8458640B2 (en) | Routing using a dynamic grid | |
| EP2460106B1 (en) | Hierarchical order ranked simulation of electronic circuits | |
| US9881123B1 (en) | Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact | |
| US20100153897A1 (en) | System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce leakage power in an electronic circuit and electronic design automation tool incorporating the same | |
| Slpsk et al. | Karna: A gate-sizing based security aware EDA flow for improved power side-channel attack protection | |
| US8713506B2 (en) | System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same | |
| CN115017846B (en) | Interface-based time sequence repairing method, device and medium | |
| US8037443B1 (en) | System, method, and computer program product for optimizing an altered hardware design utilizing power reports | |
| EP2529283A2 (en) | Zone-based leakage power optimization | |
| JP2003502736A (en) | Circuit simulation using dynamic partitioning and on-demand evaluation | |
| US20100050144A1 (en) | System and method for employing signoff-quality timing analysis information to reduce leakage power in an electronic circuit and electronic design automation tool incorporating the same | |
| US7380228B2 (en) | Method of associating timing violations with critical structures in an integrated circuit design | |
| US11593543B2 (en) | Glitch power analysis with register transfer level vectors | |
| CN112597716B (en) | Method for simulating and screening bottleneck units based on STA and SPICE models | |
| CN112560373B (en) | Burr power analysis and optimization engine | |
| US10963610B1 (en) | Analyzing clock jitter using delay calculation engine | |
| US8776003B2 (en) | System and method for employing side transition times from signoff-quality timing analysis information to reduce leakage power in an electronic circuit and an electronic design automation tool incorporating the same | |
| US7191417B1 (en) | Method and apparatus for optimization of digital integrated circuits using detection of bottlenecks | |
| US8762915B1 (en) | System and method for integrated circuit die size reduction | |
| Singh et al. | A geometric programming-based worst case gate sizing method incorporating spatial correlation | |
| US8181143B2 (en) | Method and apparatus for generating a memory-efficient representation of routing data | |
| US20130152034A1 (en) | System and method for reducing integrated circuit timing derating |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |