CN111950226A

CN111950226A - Chip back end design and layout design method, tool, chip and storage medium

Info

Publication number: CN111950226A
Application number: CN202010820385.1A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-08-14
Filing date: 2020-08-14
Publication date: 2020-11-17

Abstract

The embodiment of the application discloses a chip back end design and layout design method, a tool, a chip and a storage medium, wherein the generation method comprises the following steps: importing library files and design data; when the wiring PnR tool carries out wiring processing based on the library file and the design data, after the optimization timing sequence command is executed, a first writing-out command is executed, and a first report, a first netlist and a first file are obtained; based on the first network table and the first file, the static timing sequence analysis STA tool executes a first analysis command to generate a second report; correcting the information of the PnR tool based on the first report and the second report to obtain corrected information; based on the library file and the design data, the STA tool executes a second analysis command to obtain a time sequence report; if the time sequence report has time sequence violation, executing a change command, and carrying out ECO processing on other information except the corrected information of the PnR tool; and the STA tool continues to execute the next analysis command until the obtained timing report has no timing violation, and the layout is output.

Description

Chip back end design and layout design method, tool, chip and storage medium

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a chip back end design and layout design method, a tool, a chip and a storage medium.

Background

Since the chip back-end design time takes a large proportion of the whole chip design cycle, how to shorten the chip back-end design time is very important in order to improve the chip design efficiency.

In the process of designing the layout of the integrated circuit, the design flow is very complex because the back end design of the integrated circuit has long flow and more links. With the increasing chip scale and the increasing competition, the requirements for the chip back end design are also higher and higher. At present, when the back end of a chip is designed, problems existing in the design need to be repaired through continuous iteration of an Engineering Change Order (ECO) flow. However, inconsistencies between the routing tool and the static timing tool can result in an increased number of iterations in the back-end design process, which severely impacts the on-time-slice of the chip.

Disclosure of Invention

The embodiment of the application provides a chip back end design and layout design method, a tool, a chip and a storage medium, which can greatly reduce the iteration times of an ECO flow, further shorten the chip back end design time and effectively improve the chip design efficiency.

The technical scheme of the embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a chip back end design method, where the method includes:

importing library files and design data; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed;

when the wiring PnR tool carries out wiring processing based on the library file and the design data, after the optimization time sequence command is executed, executing a first writing-out command to obtain a first report, a first netlist and a first file;

based on the first netlist and the first file, the static timing analysis STA tool executes a first analysis command to generate a second report;

correcting the information of the PnR tool based on the first report and the second report to obtain corrected information;

based on the library file and the design data, the STA tool executes a second analysis command to obtain a timing report;

if the time sequence report has time sequence violation, executing a change command, and carrying out ECO processing on other information of the PnR tool except the corrected information;

and the STA tool continues to execute the next analysis command until the obtained time sequence report has no time sequence violation, and the layout is output.

In a second aspect, an embodiment of the present application provides a layout design method, where the layout design method is applied to an EDA tool, and the method includes:

receiving a fourth starting command, starting a layout design flow, and analyzing library files and design data carried in the fourth starting command; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed;

when a wiring PnR tool is called to perform wiring processing in the layout design flow based on the library file and the design data, if the optimization timing sequence command is executed, a second stop command and a second write-out command are generated;

responding to the second stop command, stopping the wiring processing, and responding to the second write-out command to obtain a third report, a second netlist and a second file;

calling an STA tool to perform static timing analysis processing based on the second netlist and the second file, and generating a fourth report;

receiving a fifth starting command, starting a correction process, and correcting the information of the PnR tool based on the third report and the fourth report to obtain corrected information;

and receiving a sixth starting command, continuing the layout design process based on the corrected information, and outputting the layout.

In a third aspect, an embodiment of the present application provides a back-end design tool, including: an introduction unit, a first acquisition unit, a first generation unit, a first correction unit, a change unit, a first output unit,

the import unit is used for importing library files and design data; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed;

the first obtaining unit is used for executing a first writing-out command after the optimization timing sequence command is executed when the wiring PnR tool carries out wiring processing based on the library file and the design data, and obtaining a first report, a first netlist and a first file;

the first generation unit is used for executing a first analysis command by the static timing sequence analysis STA tool based on the first netlist and the first file to generate a second report;

the first correcting unit is used for correcting the information of the PnR tool based on the first report and the second report to obtain corrected information;

the first obtaining unit is further configured to, based on the library file and the design data, execute a second analysis command by the STA tool to obtain a timing report;

the change unit is used for executing a change command and carrying out ECO processing on other information of the PnR tool except the corrected information if the timing report has a timing violation;

the first obtaining unit is further configured to continue to execute a next analysis command by the STA tool until the obtained timing report does not have a timing violation;

the first output unit is used for outputting the layout.

In a fourth aspect, an embodiment of the present application provides a back-end design tool, where the back-end design tool includes a first processor, and a first memory storing instructions executable by the first processor, and when the instructions are executed by the first processor, the back-end design method of the chip is implemented.

In a fifth aspect, embodiments of the present application provide an EDA tool, including: a receiving unit, an analyzing unit, a calling unit, a second generating unit, a stopping unit, a second obtaining unit, a second correcting unit and a second output unit,

the receiving unit is used for receiving a fourth starting command and starting a layout design process;

the analysis unit is used for analyzing the library file and the design data carried in the fourth starting command; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed;

the calling unit is used for calling a wiring PnR tool to perform wiring processing in the layout design flow based on the library file and the design data;

the second generating unit is used for generating a second stop command and a second write-out command if the optimization timing sequence command is executed;

the suspending unit is configured to suspend the wiring process in response to the second stop command;

the second obtaining unit is used for responding to the second writing-out command and obtaining a third report, a second netlist and a second file;

the calling unit is further configured to call an STA tool to perform static timing analysis processing based on the second netlist and the second file, and generate a fourth report;

the receiving unit is further configured to receive a fifth start command and start a correction process;

the second correcting unit is used for correcting the information of the PnR tool based on the third report and the fourth report to obtain corrected information;

the receiving unit is further configured to receive a sixth start command;

and the second output unit is used for continuing the layout design process based on the corrected information and outputting the layout.

In a sixth aspect, an embodiment of the present application provides an EDA tool, where the EDA tool includes a second processor, and a second memory storing instructions executable by the second processor, and when the instructions are executed by the second processor, the layout design method is implemented as described above.

In a seventh aspect, an embodiment of the present application provides a chip, where the chip includes a programmable logic circuit and/or a program instruction, and when the chip runs, the chip back end design method and the layout design method described above are implemented.

In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a program is stored, and the program is applied to a back-end design tool and an EDA tool, where the program is executed by a first processor to implement the chip back-end design method described above, and the program is executed by the first processor to implement the layout design method described above.

The embodiment of the application provides a chip back-end design and layout design method, a tool, a chip and a storage medium, wherein a back-end design tool imports library files and design data; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed; when the wiring PnR tool carries out wiring processing based on the library file and the design data, after the optimization timing sequence command is executed, a first writing-out command is executed, and a first report, a first netlist and a first file are obtained; based on the first network table and the first file, the static timing sequence analysis STA tool executes a first analysis command to generate a second report; correcting the information of the PnR tool based on the first report and the second report to obtain corrected information; based on the library file and the design data, the STA tool executes a second analysis command to obtain a time sequence report; if the timing report has a timing violation, executing a change command, and carrying out ECO processing on other information except the corrected information of the PnR tool; and the STA tool continues to execute the next analysis command until the obtained timing report has no timing violation, and the layout is output. That is to say, in the present application, in the routing stage, a correction procedure is inserted, and a precise correction process is performed according to a first report obtained by the PnR tool and a second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem that the number of iterations in the ECO procedure is increased due to the inconsistency between the PnR tool and the STA tool, and being capable of greatly reducing the number of iterations in the ECO procedure, further shortening the time of chip back-end design, and effectively improving the chip design efficiency.

Drawings

FIG. 1 is a schematic diagram of a back-end design flow;

FIG. 2 is a schematic illustration of an ECO flow scheme;

FIG. 3 is a first schematic flow chart of a chip back-end design method;

FIG. 4 is a schematic diagram of a second implementation flow of the chip back-end design method;

FIG. 5 is a third schematic flow chart of the implementation of the chip back-end design method;

fig. 6 is a schematic diagram of a back-end design process of a chip proposed in the present application;

FIG. 7 is a schematic diagram of an implementation flow of the layout design method;

FIG. 8 is a first schematic diagram of the back end design tool;

FIG. 9 is a second schematic structural diagram of a back-end design tool;

FIG. 10 is a first schematic diagram of the composition of an EDA tool;

FIG. 11 is a second schematic view of the composition of the EDA tool.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are illustrative of the relevant application and are not limiting of the application. It should be noted that, for the convenience of description, only the parts related to the related applications are shown in the drawings.

Before further detailed description of the embodiments of the present invention, terms and expressions mentioned in the embodiments of the present invention are explained, and the terms and expressions mentioned in the embodiments of the present invention are applied to the following explanations.

Performance, Power consumption, Area (Performence, Power, Area, PPA).

Place and Route (PnR). Wherein, Place is the layout, and Route is the wiring.

Electronic Design Automation (EDA) is a Design method for completing processes of functional Design, Integration, verification, physical Design (including layout, wiring, layout, Design rule check, etc.) of a Very Large Scale Integration (VLSI) chip by using Computer Aided Design (CAD) software.

The Geometric Data Standard (GDS) records layout information before chip fabrication.

Engineering Change Order (ECO) is usually used for engineering change after new product development is completed, after the engineering department confirms necessary change, a document is sent to deal with a related unit countersign to ensure that stock and work in process are properly processed, the change is immediate, the change is done after use, and the like, sales units, manufacturing units and material units need to agree and take necessary actions, generally, ECO has a large involvement range and a long lead-in time, and needs strict system management.

Clock Tree Synthesis (CTS) is to synthesize the Clock tree of design. The main purpose is to have each clock communicate to all the D-type flip-flops (DFFs) they drive in as short a time as possible.

Static Timing Analysis (STA), applying a specific Timing Model (Timing Model), analyzes whether it violates the Timing Constraint given by the designer for a specific circuit. That is, the STA determines whether the Integrated Circuit (IC) can normally operate in the time-series environment of the user through a complete analysis method, and provides a good solution to the problem of ensuring the quality of the IC. The STA can be classified into Path-Based and Block-Based by means of analysis.

The GDSII stream format, commonly abbreviated GDSII, is a database file format. It is used for data conversion of integrated circuit layouts and becomes a de facto industry standard. The GDSII is a binary file that contains the geometry, text or labels of planes in the integrated circuit layout, as well as other pertinent information, and may be composed of a hierarchy. The GDSII data may be used to reconstruct all or part of the layout information. It can be used for making photoetching mask.

EDA tool software (EDA tools).

Flip chip (Flip chip), a leadless structure, generally contains circuit elements. Designed to be electrically and mechanically connected to the circuit by a suitable number of solder balls (covered by a conductive adhesive) on its face.

Gate-Level netlist (Gate-Level netlist), which is used to describe the connection relationship of circuit elements in circuit design, is generally a text file following some relatively simple markup syntax. The gate-level refers to the level of circuit synthesis described by the netlist. As the name implies, in a gate-level netlist, the circuit elements described are essentially gates (gates) or the same level of elements.

Deep sub-micron (deep sub-micron), generally 0.35-0.8 μm and below is referred to as submicron, 0.25um and below is referred to as deep submicron, 0.05um and below is referred to as nanoscale. The key technology of deep submicron manufacturing mainly comprises an ultraviolet lithography technology, a plasma etching technology, an ion implantation technology, a copper interconnection technology (different interconnections) and the like. The mainstream production technology of the integrated circuit is 0.010-0.028 μm internationally.

Design for test (DFT), a chip is often provided with a test circuit inside, and the purpose of DFT is to consider future tests during Design. A common approach to DFT is to insert scan chains into the design, changing non-scan cells (e.g., registers) into scan cells.

Further, the following terms may be referred to in embodiments of the present application: group (group), region (region), timing constraint (timing constraint), power ring (power ring), timing analysis (timing analysis), line, wire (net), Congestion (Congestion), pin (pin), timing engine (timing engine), row channel (row), cell (cell), PAD (PAD), clock tree (clock tree), Buffer (Buffer), Buffer tree (Buffer tree), padding cell (file cell), clock tree delay (clock insertion delay), megacell (megacell), clock skew (clock skew), transfer time (transfer time), delivery (tap out), standard cell (standard cell), setup/maintenance timing conflict (setup/d time conflict), metal (wiring) layer (layer), script (script). Built-in self test (BIST).

Chip design is undoubtedly an important step in the chip manufacturing process, and chip design can be divided into front-end design and back-end design. The front end is mainly responsible for logic implementation, and usually performs behavior level description by using verilog, VHDL and other languages. And the rear end is mainly responsible for changing the design of the front end into a real schematic diagram and layout (schema & layout), a tape and mass production. By analogy, the front end is like a blueprint and can be functional and structural. And the back end changes the blueprint into a real high-rise building.

The chip back end design mainly comprises the following parts:

1. design For Test (Design For Test, DFT)

The interior of a chip is often provided with a test circuit, and the purpose of DFT is to consider future tests at the time of design. A common approach to DFT is to insert scan chains into the design, changing non-scan cells (e.g., registers) into scan cells.

2. Layout planning (Floor Plan)

3、CTS

The simple point is the wiring of the clock. Due to the global command of the clock signal on the digital chip, the clock signal should be distributed symmetrically to each register unit, so that the clock delay difference is minimized when the clocks arrive at each register from the same clock source. This is also the reason why the clock signal needs to be wired separately.

4. Wiring (PnR)

The wiring here is a normal signal wiring including wiring between various standard cells (basic logic gate circuits). Such as the commonly heard 0.13um process, or 90nm process, is actually the minimum width that can be achieved by the metal wiring here, which is microscopically the channel length of the MOS transistor.

5. Parasitic parameter extraction

Due to the resistance of the wires and mutual inductance between adjacent wires, signal noise, crosstalk and reflection can be generated inside the chip by the coupling capacitor. These effects can create signal integrity problems, leading to signal voltage fluctuations and variations, and if severe, signal distortion errors. Extracting parasitic parameters for further analysis and verification, it is very important to analyze the signal integrity problem.

6. Physical verification of layout

Verifying the physical Layout after wiring in function and time sequence, wherein a large number of verification items are provided, such as Layout and Schematic (LVS) verification, and in short, the verification is the comparison verification of the Layout and a gate-level circuit diagram after logic synthesis; design Rule Checking (DRC), Checking whether a wiring pitch, a wiring width, and the like satisfy process requirements, Electrical Rule Checking (ERC), Checking Electrical Rule violations such as short circuits and open circuits, and the like.

Practical back-end flow also includes circuit power consumption analysis, as well as design for manufacturability (DFM) issues that arise as manufacturing processes continue to advance.

And the physical layout verification is completed, namely the whole chip design stage is completed, and then the chip is manufactured. The physical layout is delivered to a chip foundry to make an actual circuit on a wafer silicon chip in a GDSII file format, and then packaging and testing are carried out to obtain an actual chip.

Fig. 1 is a schematic diagram of a back-end design process, and as shown in fig. 1, the process related to the chip back-end design mainly includes the following steps:

step 101, data preparation.

For the Silicon Ensemble of CDN, the data required for the back-end design is mainly library files of standard cells, macro cells and I/O pads provided by the Foundry, which include a physical library, a timing library and a netlist library, given in the form of lef, tlf and v, respectively. The front-end chip design is synthesized to generate a gate-level netlist, a script file with timing constraints and clock definitions and a gcf constraint file generated thereby, and a def (design Exchange format) file defining the power Pad. (for Astro by Synopsys, the gate-level netlist generated after synthesis, the timing constraint file SDC is the same, and the definition file of Pad- -tdf,. tf-file- -technology file, library files of standard CELLs, macro CELLs and I/O Pad provided by Foundation, are given in FRAM, CELL view, LM view form (Milkway reference library and DB, LIB file).

And 102, layout planning.

Mainly the layout of standard cells, I/O pads and macro cells. The I/O Pad gives a position in advance, the macro cells are placed according to the time sequence requirements, and the standard cells give a certain area and are automatically placed by a tool. After layout planning, the chip size, Core area, Row form, Ring and Strip of power and ground lines are determined. After the automatic placement of standard cells and macro cells, if necessary, PNA (power network analysis) -IR drop and EM can be done once.

And step 103, layout.

After layout planning, the positions of macro cells, I/O pads and the areas for placing standard cells are determined, and the information SE (silicon Ensemble) is transmitted to a PC (physical compiler) through a DEF file, and the PC automatically places standard cells according to netlist and timing constraint information obtained by the DB file, and simultaneously performs timing check and cell placement optimization. If PC + Astro is used, then write _ milkway, read _ milkway may be used to transfer the data.

Step 104, Clock tree synthesis (CTS Clock tree synthesis).

The clock network in the chip drives all the time sequence units in the circuit, so that the gate units at the clock source end carry a lot of loads, the load delay is large and unbalanced, and a buffer needs to be inserted to reduce the load and balance the delay. The clock network and the buffers thereon form a clock tree. Usually, the clock tree is repeated several times to form an ideal clock tree. -Clock skew.

Step 105, Routing (Routing). Global Routing-Track alignment-Detail Routing-Routing optimization Routing refers to connecting units and I/O pads by using interconnection lines according to the connection relationship of circuits under the condition that the process rule, the limitation of the number of Routing layers, the limitation of line width and line spacing and the electrical property constraint of reliable insulation of each line network are met, and the interconnection lines are performed under the condition of Timing drive (Timing drive) to ensure that the length of the connection lines on a critical Timing path can be minimum. -Timing report clear.

Step 106, increment of Dummy Metal and insert of Filler (pad flier, cell filer).

Filler refers to the logic independent Filler defined in the standard cell library and I/O Pad library to fill the gaps between standard cells and standard cells, and between I/O pads and I/O pads, which mainly connects the diffusions to meet DRC rules and design requirements.

Foundry has specified the metal density not to be lower than a certain value, so as to prevent the metal layer of the connecting wire from being excessively etched in the etching stage in the chip manufacturing process, thereby reducing the performance of the circuit. The Dummy Metal is added to increase the density of the Metal.

Step 107, STA static timing analysis and post-simulation.

After the clock tree is inserted, the position of each unit is determined, the tool can provide a Global Route type connecting line parasitic parameter, and the extraction of the delay parameter is accurate. SE passes the. V and. SDF files to PrimeTime for static timing analysis. And after confirming that no time sequence violation exists, transmitting the two files to front-end personnel for post-simulation. For Astro, after detail routing, E.V sum was generated using the extraction of the startRC XT parameter, and the SDF file was passed to PrimeTime for static timing analysis, which would be more accurate.

Step 108, ECO (engineering Change order).

Aiming at the problems in static time sequence analysis and post simulation, the circuit and unit layout is changed in a small range.

Step 109, DRC and LVS. DRC is a design rule check (width) of each layer of physical patterns in the chip layout, and it also includes a check of the antenna effect to ensure that the chip is normally taped. The LVS mainly compares the layout with the circuit netlist to ensure that the layout circuit from the tape-out is consistent with the actually required circuit. DRC and LVS checks- -EDA tool Synopsy hercules/mentor calibre/CDN Dracula. Astro also include LVS/DRC check commands.

And step 1010, flow sheet. And (4) transmitting the final layout GDSII file to a Foundation factory for mask manufacturing under the condition that all checks and verifications are correct.

In the back-end design process of the chip, the ECO is a key path which cannot be ignored, and a good ECO flow and strategy can accelerate the time of the tape-out.

Fig. 2 is a schematic diagram of an ECO process, and as shown in fig. 2, a conventional ECO process mainly includes the following steps:

and 108a, judging whether a timing violation exists, if so, executing 108b, otherwise, executing 109.

And step 108b, ECO correction processing is carried out, and then the step 106 is returned to continue the next static timing analysis.

Due to the poor correlation between the PnR tool and the STA tool, especially when the PnR and the STA tools are from different suppliers, for example, PnR uses the innovus tool of cadence, and STA uses the primetime of synopsis, the consistency between the two is poor, and the inconsistency may cause the backend design to need multiple iterations to time the meet during the timing ECO, even the risk of not being able to fix exists, so that the chip cannot time the tapeout.

In order to solve the existing problems, in the application, a correction flow is inserted in a routing stage, and accurate correction processing is performed according to a first report obtained by a PnR tool and a second report obtained by an STA tool so as to correct the correlation between the PnR tool and the STA tool, so that the problem that the number of iterations in an ECO flow is increased due to inconsistency between the PnR tool and the STA tool can be solved, the number of iterations in the ECO flow can be greatly reduced, the time for designing the back end of a chip is shortened, and the chip design efficiency is effectively improved.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

An embodiment of the present application provides a chip back end design method, and fig. 3 is a schematic diagram illustrating an implementation flow of the chip back end design method, as shown in fig. 3, in the embodiment of the present application, the chip back end design method may include the following steps:

step 201, importing library files and design data; the design data includes a gate-level netlist and timing constraints obtained after the chip front end is designed.

In the embodiment of the application, after the front-end design is completed, the back-end design tool can lead the warehousing file and the design data when the back-end design of the chip is performed. The importing library file and the design data may also be understood as the beginning of the back-end design process of the chip.

In the embodiments of the present application, the backend design tool may be configured to enter the required data when performing backend design. Specifically, these data may specifically include library files and design data, wherein the library files may be library files of standard cells, macro cells and I/O pads provided by a Foundry of chips (Foundry), which include a physical library, a timing library and a netlist library, given in the form of lef, tlf and v, respectively. The design data may be a gate-level netlist generated by synthesizing a chip front-end design, a script file with timing constraints and clock definitions, and a gcf constraint file generated therefrom.

Further, in the embodiments of the present application, the back-end design tool is an EDA tool, and may include a plurality of tools provided by different suppliers, and in particular, when different commands are executed and different types of processing are performed, different back-end design tools may be used. For example, common layout PnR tools are IC Compiler, Astro, and SOC-Encon, Inc. of Synopsys, Inc. IC Compiler is another PnR tool, which was introduced by Synopsys, Inc. following Astro, which is commonly used for ultra-deep submicron level layout at 10nm technology.

For example, in the present application, when performing design for testability DFT, the DFT tool selected for use may be DFT Compiler of Synopsys; in layout planning, the tool used may be Astro from Synopsys; when performing the clock tree synthesis CTS, the CTS tool used can be Synopsys Physical Compiler; when wiring is performed, the used PnR tool may be Astro of Synopsys; in performing the extraction of the parasitic parameter extraction, the tool used may be Star-RCXT of Synopsys; when the physical verification of the layout is carried out, the used tool can be Hercules of Synopsys; in performing static timing analysis of the STA, the STA tool used may be Prime Time from Synopsys.

It is understood that, in the present application, after the chip front-end design meets the requirement, a corresponding file, such as a gate-level netlist, a scdc file, etc., may be output for subsequent timing analysis and verification. Whether the comprehensive time sequence is correct or not is verified through static time sequence analysis and form verification, wherein the static time sequence analysis can more accurately analyze the time sequence so as to check whether the comprehensive time sequence is correct or not; and the formal verification is to verify whether the functions of the synthesized circuit are consistent with those of the original circuit by a mathematical method. After the verification is passed, the next placement and wiring can be carried out, otherwise, the new synthesis is carried out.

Then, the physical design stage, i.e. the back-end design of the chip, can be entered. In the chip back-end design, the generated gate-level netlist related to the front end is converted into layout information which is available for a mask by Foundry.

It should be noted that, in the back-end design flow of the chip, the design data output by the front-end design required by the back-end design tool at least includes a gate level netlist (gate level netlist), a timing constraint (timing constraint) and a timing analysis report (timing analysis report).

It is understood that the design data (netlist file) may be checked for quality by the back-end design tool before importing the design data to confirm that the errors and defects existing therein have been eliminated, for example, whether the following conditions exist or not may be checked: grammar error, short circuit connection, net without any connection, net without driving input pin (pin), assign statement, line (wire) type, special character starting from \ ", writing method of data bus, length of name and the like are used, and different manufacturers and software have some limitations, so that it is recommended to define a set of stricter netlist writing rules.

For example, in the present application, the netlist writing rules may include "net without any connection" and "no-drive input pin", no assign statement, only wire type net, all names only capital and small english letters, numbers and underlines, the first letter is english letters, length is less than 1024, and the invocation between modules uniformly uses the explicit format.

Further, in the embodiment of the present application, if the testability DFT and automatic test format generation is required, the back-end design tool also needs to check whether the design requirements of scan chain (scan chain) and Memory built-in self test (Memory BIST) are met.

Next, it is also necessary to check whether the timing settings in the timing constraint (timing constraint) file are complete and reasonable. Finally, a flow timing analysis report is required, if the setup vision exists, the flow timing analysis report is generally not allowed to be more than 10% of a clock period, and the hold vision can be temporarily unresolved and is removed after being left on a wiring.

Step 202, when the PnR tool performs routing processing based on the library file and the design data, after the optimization timing command is executed, the first write-out command is executed, and the first report, the first netlist and the first file are obtained.

In the embodiment of the application, after the library file and the design data are imported, the PnR tool may perform routing processing based on the library file and the design data, and in the process of routing processing, after the optimization timing command is executed, the PnR tool may execute a first write-out command to obtain a first report, a first netlist, and a first file.

Further, in the embodiment of the present application, the routing process performed by the PnR tool is a common signal routing, and may specifically include routing between various standard cells (basic logic gates). The common 0.13um process, or 90nm process, is actually the minimum width that can be reached by metal wiring during wiring process, and microscopically is the channel length of the MOS transistor.

Illustratively, in the present application, the PnR tool may be Astro of Synopsys.

It is understood that in the embodiments of the present application, during the wiring process, a trace and an isolation space for analog signals may be reserved. Then, considering the routing of the clock tree, there is no digital signal routing, so there is a great freedom to choose the metal layer with faster transmission speed for the routing of the clock tree. And finally, digital signal wiring. This function is proposed to be used if the routing software can take into account timing requirements. If there is no such function and there are some critical paths (critical paths), then these nets can be weighted to be routed preferentially. If there is no large area or centralized wiring problem in the wiring result, the STA may be done first without correcting the small problem caused by automatic wiring, since there is a high possibility that a wiring engineering change (routing ECO) needs to be done after the STA.

It should be noted that, in the embodiment of the present application, the route command related to the routing may mainly include: route _ auto, route _ opt, route _ eco, route _ group, route _ global, route _ track, route _ detail.

Specifically, route _ auto is a routing, mainly referring to a signal line. Normally, the net of the clock tree is already wound during CTS, and of course, if the clock tree is not wound, route _ auto can wind the clock tree and signal net together. route _ auto is used only once in the PnR flow.

route _ auto, which consists of three subcommands, is accomplished by Automatically. However, if the auto (auto) executor does not want to execute three sub-commands, the auto _ track + route _ detail may be manually executed, and the effect is the same.

Specifically, route _ global is a quick link, but does not create real metal (only VIA is created); adding real metal to the route _ track according to the result of the route _ global, but not considering DRC; route _ detail is modified DRC.

route _ global, fast wire. After route _ global is executed, all nets are connected. However, no real metal is put, only a thin wire with no width. These thin lines have layer information and also have real holes. For example, for a net, it is exported from Z pin of buffer _ X to I pin of the next buffer _ Y, and from Z pin of buffer _ X there is a VIA12, then a thin line of M2 goes through VIA23 to M3, then M3 is connected to A pin of buffer _ Y through VIA23, M2 and VIA 12. Thus, it is a complete global route. It has four VIAs and three connecting lines.

In addition to thin lines and holes, global route has a lot of useful information, such as NDR. Some nets have twice space requirements, global route can comply with the space requirements, some nets can only be placed on a certain layer, and global route can also comply with the space requirements.

It can be said that the constraint on net is basically done by global route. Meanwhile, the result of global route determines the final winding quality to a great extent.

route _ global is very useful and is said to be ubiquitous in PnR. For example, invoking global route by initial drc can make the buffer tree longer better; the placer calls route _ global to evaluate the conjestion; calling route _ global by the optimizer to perform RC evaluation of pre-route; the CTS calls global route long clock trees, and even route _ eco calls global route to connect broken lines.

route _ track, which creates a metal (shape) from the results of global route, regardless of DRC. After the route _ track is completed, the thin wire disappears and becomes a metal with a width. The route _ track process is very fast because no other cost is considered, but there is also timing _ drive and crosstalk _ drive.

route _ detail (-incr), DRC modified. Shape after route _ track is sure to have a large number of DRCs, and the more complicated the process, the more DRCs. DRC modification is all by route _ detail, this engine. Typically, a default is 40 rounds, but it is not necessary to wait for 40 rounds to finish, e.g., if the DRC number is found to be under-modified, route _ detail will exit early.

route _ group, winding the specified net. Route _ group can be understood as a fast version of route _ auto, which wraps the specified net and also contains three steps, route _ global, route _ track, and route _ detail. The speed is very fast because only the assigned net is wound.

The more common scenario is to wind some timing critical nets in advance and make these nets go straight. Alternatively, the clock tree is wound.

route _ eco, which winds the net (or newly added net) disconnected after eco (timing or function) and repairs DRC. This command is often used during the timing phase, since after an ECO has been performed, the winding must be disconnected, or there is a DRC, or there is a new net added to the winding. Whatever the case, it is handled uniformly with route _ eco.

route _ eco actually performs two actions, respectively: connect new/disconnected net (call route _ global + route _ track), and modify DRC (call route _ detail-incr), wherein, when modifying DRC, only DRC of ECO net may be modified, or DRC of all nets may be modified.

In general, it is proposed to use route _ detail-incr modified DRC, although route _ eco modified DRC can be used, i.e. new/disconnected net of route _ eco does not work, but modified DRC works.

route _ opt, optimize timing (also optimize area, power consumption, transition, hold, etc.), and do eco routing. Specifically, route _ opt can be understood as three steps:

1. post route optimization, optimize setup, area, power consumption, transition, hold, etc. (size _ cell and insert _ buffer are the main ones)

2. The Legallize _ displacement, after the first step of the collapse, has many cells with overlap or not on the site row, and requires Legallizer to place them on Legalli location.

3. route _ eco, after completing post route optimization and Legallize _ placement, the loss of winding is large, and route _ eco needs to be called. The default is 5 rounds, or may be set to 10 or more, and route _ opt may run multiple rounds to get better PPA.

Further, in the embodiment of the present application, when the PnR tool performs the routing processing based on the library file and the design data, after the optimization timing command is executed, that is, after route _ opt is completed, the first write-out command may be executed, and then the current hold report, netlist, and def in the PnR tool are written out, that is, the first report, the first netlist, and the first file are obtained.

It can be understood that, in the embodiment of the present application, before entering the timing ECO, the back-end design tool may add a correction procedure at the Routing stage, where the correction procedure is used to correct the inconsistency between the PnR tool and the STA tool, so as to save the modification time and the number of iterations in the ECO procedure.

Specifically, in the embodiment of the present application, when the back-end design tool joins the correction flow in the Routing stage, after route _ opt is completed, the current hold report, netlist, and def may be written first, and then the subsequent correction processing is performed by using the current hold report, netlist, and def. At this point, the original back-end design flow is temporarily suspended but not exited.

It is to be understood that in the present application, the def file is a description of the design (design), so that the def can be written from the back-end tool according to the design requirement. The information in the def file is used for describing design, and specifically comprises PIN foot information, length, height, coordinate positioning, area size of the digital PR and the like.

It should be noted that, in the embodiment of the present application, the first report written by the PnR tool includes hold slope. Specifically, the slack can be used to indicate whether the design meets the timing requirement, and can be divided into setup slack and hold slack, if the value of the slack is positive, it indicates that the design can meet the setup time or hold time requirement, otherwise, it indicates that the design does not meet the setup time or hold time requirement.

Further, in the embodiment of the present application, if the setup slope is positive, indicating that the Data Required Time is after the Data Arrival Time, the setup Time is necessarily satisfied. Otherwise, the setup time is not satisfied; if the hold slot is positive, indicating that the Data Arrival Time is after the Data required Time, then the hold Time must be satisfied. Otherwise, the hold time is not satisfied.

It should be noted that, in the embodiment of the present application, the hold slope written by the PnR tool when performing the correction procedure only represents the timing information of the PnR tool at the current time, and is not completely accurate and real, so that in the subsequent processing procedures, the hold slope in the first report needs to be corrected.

Step 203, based on the first netlist and the first file, the STA tool executes the first analysis command to generate a second report.

In an embodiment of the application, after the PnR tool executes the first write-out command to obtain the first report, the first netlist, and the first file, the STA tool may execute the first analysis command to generate the second report based on the first netlist and the first file.

Further, in an embodiment of the present application, after the PnR tool executes the write-out instruction and writes out the first report, the first netlist, and the first file, based on the first netlist and the first file, the STA tool may execute the first analysis command and then generate the second report.

It should be noted that, in the embodiment of the present application, based on the first netlist and the first file, the STA tool executes the first analysis command, and in the process of generating the second report, the backend design tool may first execute the first insertion command based on the first netlist and the first file, and perform insertion processing on the gap; then, the back end design tool can execute the first extraction command to extract the first parasitic parameter; finally, the STA tool may execute the first analysis command to perform static analysis processing on the first parasitic parameter, thereby generating a second report.

That is, in the present application, based on the layout result obtained from the first netlist and the first file, the STA tool may extract the delay data according to the estimated line length for static timing analysis.

It can be understood that, in the present application, the backend design tool mainly performs the filer and dummy insertion processing when executing the first insertion command based on the first netlist and the first file.

Specifically, in the present application, the filler refers to std cell filler, which is a filler silicon layer, poly, and the bottom power rail, and is mainly used for connecting the power source and the well region. Further, filer refers to a logic-independent filler defined in the standard cell library and the I/O Pad library, which is used to fill the gaps between the standard cells and the standard cells, between the I/O Pad and the I/O Pad, and the insertion of filer (Pad bridge), which mainly connects the diffusion layers to meet DRC rules and design requirements.

Specifically, in the present application, dummy refers to dummy metal, which is a metal on the fill layer, and is mainly used to ensure the CMP effect. Furthermore, Foundry has specified the metal density not to be lower than a certain value, so as to prevent over etching the metal layer of the interconnect during the etching stage in the chip manufacturing process and reduce the circuit performance, and dummy metal is added to increase the metal density.

It is to be understood that in the present application, the back-end design tool is mainly used to extract the parasitic parameters when executing the first extraction command based on the first netlist and the first file. The tool for extracting parasitic parameters may be Star-RCXT of Synopsys, among others.

In particular, in the present application, due to the resistance of the wires themselves, mutual inductance between adjacent wires, and coupling capacitance may generate signal noise, crosstalk, and reflection inside the chip. These effects can create signal integrity problems, leading to signal voltage fluctuations and variations, and if severe, signal distortion errors. To solve this problem, the back-end design tool may extract the parasitic parameters for further analysis and verification.

Further, in the embodiment of the present application, the STA tool executes the first analysis command, and analyzes the extracted first parasitic parameter to generate the second report, which also includes the hold slope. The hold slack corresponding to the STA tool is accurate and real compared to the hold slack of the PnR tool in the first report, so the hold slack in the second report should be obtained with reference to the STA tool.

And 204, correcting the information of the PnR tool based on the first report and the second report to obtain corrected information.

In an embodiment of the application, after the STA tool executes the first analysis command and generates the second report, the information of the PnR tool may be corrected according to the first report and the second report, and the corrected information may be obtained.

It should be noted that, in the embodiment of the present application, when the back-end design tool corrects the information of the PnR tool based on the first report and the second report, and obtains the corrected information, the back-end design tool may determine the margin difference according to the hold slack in the first report and the hold slack in the second report; then, the information of the PnR tool is corrected according to the residue difference value.

Further, in the embodiment of the present application, the hold slack in the first report written by the PnR tool is not completely accurate and real, and in contrast, the STA tool may obtain the hold slack in the second report as accurate and real, so that the margin difference may be determined by using the hold slack in the first report and the hold slack in the second report, that is, performing a difference operation on the two hold slack to obtain a difference result.

It is understood that, in the embodiment of the present application, after determining the margin difference according to the hold slope in the first report and the hold slope in the second report, the back-end design tool may perform a modification process on the PnR tool information according to the margin difference.

Specifically, in the embodiment of the application, when the back-end design tool corrects the information of the PnR tool according to the margin difference, the margin difference obtained by calculation may be inversely scaled to the PnR tool, so that the correction of the information of the PnR tool may be completed.

It should be noted that, in the embodiment of the present application, during the execution of the correction procedure, the PnR tool writes out the first report, and the STA tool obtains the second report, and although the hold interval in the second report can be considered to be correct and real, since the PnR tool cannot directly obtain the hold interval in the second report, the PnR tool cannot directly correct its own timing information by using the hold interval in the second report.

Further, in the embodiment of the present application, after the information of the PnR tool is modified, the correction process proposed in the above step 202 to step 204 is executed and ended, in the correction process, the back-end design tool directly completes the modification of the information of the PnR tool by using the first report and the second report, so that continuous iteration for modifying the information of the PnR tool is not required in the subsequent ECO process, and the time and the power consumption of the ECO process are saved.

Step 205, based on the library file and the design data, the STA tool executes a second analysis command to obtain a timing report.

In an embodiment of the application, after the information of the PnR tool is corrected according to the first report and the second report to obtain corrected information, the STA tool may continue to execute the second analysis command based on the library file and the design data to obtain the timing report.

It is understood that, in the embodiment of the present application, after the execution of the calibration procedure is completed, the back-end design tool may continue to execute the suspended back-end design procedure, and specifically, the STA tool may continue to execute the second analysis command to further obtain the timing analysis result, i.e., the timing report.

It should be noted that, in the embodiment of the present application, since the wiring is already completed, the extracted delay data is relatively high in reality, and further, the re-optimization performed on the basis of the extracted delay data should be able to effectively remove any setup and hold conflicts (visualization).

Further, in the embodiment of the present application, a complete layout result is obtained based on the library file and the design data, and if there is no congestion (congestion) problem, the STA tool may extract the delay data according to the estimated line length for static timing analysis, so as to complete the analysis processing of the timing path of the circuit designed based on the library file and the design data, and output the timing report.

It is understood that, in the embodiment of the present application, based on the library file and the design data, the specific process of the STA tool executing the second analysis command may include: the back end design tool firstly executes a second insertion command based on the library file and the design data to perform insertion processing on the gap; then, the back end design tool can execute a second extraction command to extract a second parasitic parameter; finally, the STA tool executes a second analysis command to perform static analysis processing on the second parasitic parameter, so that a timing report can be generated.

And step 206, if the timing report has a timing violation, executing a change command, and performing ECO processing on other information except the corrected information of the PnR tool.

In the embodiment of the application, based on the library file and the design data, after the STA tool executes the second analysis command to obtain the timing report, if there is a timing violation in the timing report, the STA tool needs to execute a change command to perform engineering change on other information of the PnR tool than the corrected information.

Further, in the embodiment of the present application, after the STA tool completes timing analysis to obtain a timing report, it may be determined whether a timing violation exists in a current design result according to the timing report, and if the timing violation exists, the back-end design tool needs to perform an ECO process.

Different from a common scheme, the ECO method provided by the application does not need to correct the information of the PnR tool any more, obtains the corrected information, and only needs to correct other information except the corrected information, so that the fix hold can be accurate, the flow is simple and easy to realize, and the method has very important help for reducing project timing convergence and timing tapeout.

It can be understood that, in the present application, just at the chip routing stage, the back-end design tool terminates the wiring process in the back-end design flow without exiting, inserts the correction flow, and completes the information correction process of the PnR tool through the correction flow, so that the information of the PnR tool does not need to be subjected to the ECO process in the subsequent ECO flow, and the number of iterations is greatly reduced.

In general, the back-end design tool can start to repair the Hold after CTS, and the PnR tool ICC of Synopsys can be used to correct the Hold violation that may occur at each stage according to the execution process of the chip back-end design flow.

Illustratively, in this application, for a Hold violation occurring after CTS and before routing, the repair can be done using > psynopt-only _ Hold _ time, where the psynopt command has two functions, one is to perform a logic optimization of the incremental timing drive; the other is Legallizes placement.

Exemplarily, in the present application, for the Hold violation occurring in the routing stage, the CCD can be used to repair:

>set_concurrent_clock_and_data_strategy；

>route_opt-concurrent_clock_and_data；

it can also be repaired by specifying routing optimization options:

>route_opt-incr-only_hold_time。

illustratively, in this application, for a Hold violation occurring at the chipfinish stage, a CCD can be used to repair:

>focal_opt-concurrent_clock_and_data\

-hold_endpoints all

the software can also be enabled to automatically repair all hold endipins:

>focal_opt-hold_endpoints all\

-effort high

REG2REG paths may also be designated for repair, using, if the violations are all concentrated on the REG2REG path:

>focal_opt-hold_endpoints all\

-register_to_register

if the Violation cannot be repaired by the method of automatic repair by command at a specific stage and the Violation value is large, the problem needs to be solved by manually inserting buffer or delaycell, that is, the problem is solved manually by using the method of ECO. Before insertion it is ensured that no Core filer is inserted or that remove if filer is present.

The inserted buffer is placed at random, may be overlapped with other cells, or is not placed on the Row, so that the buffer needs to be placed at a reasonable position. The inserted buffer is not wired and needs to be wired with an ECO.

If a manual ECO method is not used, the netlist and the spef of the whole design can be imported into the PT, the PT is repaired by the PT, then the script of the ECO is exported, and then the script is imported into the ICC for repair.

It should be noted that the restoration of the hold is not performed such that every stage is Clean, for example, for the older 0.18um process, the WNS violation or permission of about 0.1ns after CTS, and after all, the operation of wiring is performed, and the line delay is also beneficial to the hold; there is a very small amount after the wiring, and violations on the order of 0.01 or so are also permissible, and can be resolved by focal _ opt.

Specifically, in the present application, ECO refers to a case where the total number of changed (including addition and deletion) cells (cells) is less than 10%, and a change that is too large is suggested to be made from scratch. If the clock tree is not to be changed, the ECO is required to have no flip-flop scaling and no relocation of the location, but may allow the size of the existing flip-flops to be changed (size up/down) if the clock tree is not already wired. The general logic combination unit (cell) can be modified in any way. Layout change (Placement ECO) and static timing analysis and re-optimization (STA & OPT) can loop many times until there are no large conflicts (resolution).

In contrast, routing ECO is more restricted than placement ECO, and cannot be modified by any flip-flop, and only a logical combination cell (cell) can be modified. Any change to a cell (cell) connected to the clock tree results in a change to the clock tree connections, and in order to minimize the impact on timing, it is proposed to modify the clock tree manually. The routing ECO may cycle multiple times until all setup and hold views are removed.

And step 207, continuing to execute the next analysis command by the STA tool until the obtained time sequence report has no time sequence violation, and outputting the layout.

In the embodiment of the application, after the engineering change is completed on the PnR tool and on the other information except the corrected information, the STA tool may continue to execute the next analysis command until the obtained timing report does not have a timing violation, so that the back-end design process of the chip may be ended, and the layout may be output.

That is, in the embodiment of the present application, after completing an ECO repair, the back-end design tool may iterate to the next round to continue the timing analysis. Specifically, the STA tool continues to execute the next analysis command and obtain the next timing report, and if there is still a timing violation in the next timing report, the ECO process continues until there is no timing violation in the obtained timing report, and at this time, the layout may be output.

It should be noted that, in the embodiment of the present application, the back-end design tool outputs the layout according to the GDSII format. That is, the layout is delivered to Foundry (where the actual circuit is formed on the wafer silicon wafer, and then packaged and tested to obtain the actual chip) in the GDSII file format.

Therefore, for the chip back-end design flow, the input data comprises a gate-level netlist, a library file and a timing constraint, and the final output is a layout in a GDSII format through the design and ECO repair of a back-end design tool.

In summary, with the chip back-end design method proposed in the above steps 201 to 207, the back-end design tool can basically reach the hold operation clean in the PnR stage by correcting the correlation between the PnR tool and the STA tool in the routing stage, thereby greatly reducing the iteration number of the timing fix and reducing the risk of the timing fix. In addition, due to the fact that correlation between the PnR tool and the STA tool is correct, the situation that a large number of delay cells are inserted by a fix hold in a wrong mode is avoided, and dynamic power consumption is effectively reduced. That is to say, in the present application, the back-end design tool stops the routing process in the back-end design flow at the chip routing stage without exiting, and inserts the correction flow to correct the correlation between the PnR tool and the STA tool, which can accurately fix the hold, and the flow is simple and easy to implement, and is very important to reduce the project timing convergence and to help to tapeout at time.

The embodiment of the application provides a chip back end design method, wherein a back end design tool imports library files and design data; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed; when the wiring PnR tool carries out wiring processing based on the library file and the design data, after the optimization timing sequence command is executed, a first writing-out command is executed, and a first report, a first netlist and a first file are obtained; based on the first network table and the first file, the static timing sequence analysis STA tool executes a first analysis command to generate a second report; correcting the information of the PnR tool based on the first report and the second report to obtain corrected information; based on the library file and the design data, the STA tool executes a second analysis command to obtain a time sequence report; if the timing report has a timing violation, executing a change command, and carrying out ECO processing on other information except the corrected information of the PnR tool; and the STA tool continues to execute the next analysis command until the obtained timing report has no timing violation, and the layout is output. That is to say, in the present application, in the routing stage, a correction procedure is inserted, and a precise correction process is performed according to a first report obtained by the PnR tool and a second report obtained by the STA tool, so as to correct the correlation between the PnR tool and the STA tool, thereby solving the problem that the number of iterations in the ECO procedure is increased due to the inconsistency between the PnR tool and the STA tool, and being capable of greatly reducing the number of iterations in the ECO procedure, further shortening the time of chip back-end design, and effectively improving the chip design efficiency.

Based on the foregoing embodiment, in yet another embodiment of the present application, fig. 4 is a schematic diagram of an implementation flow of a chip back-end design method, as shown in fig. 4, in the embodiment of the present application, based on a library file and design data, an STA tool executes a second analysis command, and after obtaining a timing report, that is, after step 205, the chip back-end design method may further include the following steps:

and step 208, outputting the layout if the timing violation does not exist in the timing report.

In the embodiment of the application, based on the library file and the design data, after the STA tool executes the second analysis command and obtains the timing report, if there is no timing violation in the timing report, the STA tool does not need to execute the change command, and can directly output the layout.

Further, in an embodiment of the present application, fig. 5 is a third schematic implementation flow diagram of a chip back-end design method, as shown in fig. 5, in the embodiment of the present application, when a PnR tool performs a routing process based on a library file and design data, after an optimization timing command is executed, a first write-out command is executed, and before a first report, a first netlist, and a first file are obtained, that is, before step 202, the chip back-end design method may further include the following steps:

and step 209, based on the library file and the design data, executing the layout command by the PnR tool to perform layout processing.

And step 2010, based on the library file and the design data, executing a generation command by the PnR tool to generate a clock tree.

In the embodiment of the present application, after the library file and the design data are imported, a layout command may be executed first, and layout processing may be performed based on the library file and the design data, and then a generation command may be executed, and a clock tree may be generated based on the library file and the design data.

It should be noted that in the embodiments of the present application, the layout mainly refers to how to reasonably place standard cells (standard cells), and in general, it is not desirable that the software excessively moves the already placed mega cells (mega cells). The layout can be performed simply according to the connection of the cell, or according to the timing requirement, or mainly based on the congestion degree (congestion).

For example, in the present application, the layout tool may select Astro from Synopsys.

With the increase of chip speed, more and more schemes are first selected to be laid out according to timing requirements, and timing constraints (timing constraints) are needed at this time. Before the layout begins, some groups or partitions (regions) can be made, which has the advantage of telling the layout software a general layout scope, but this contradicts the given timing requirements, especially for the border cells (cells). It is therefore recommended to define groups (groups) or zones (regions) as loosely as possible and to allow a certain percentage of cells (cells) to be placed outside the groups (groups) or zones (regions), which has the same effect as the so-called amoeba layout.

If a layout with timing requirements is used and the timing engine (timing engine) for the layout is not the same as the engine (engine) for the routing or calculation delay, it is important to note the calculation errors between the engines (engines), which sometimes have a 10-fold difference.

Note that, in the embodiment of the present application, the clock tree synthesis CTS is a wiring of a clock. Due to the global command function of the clock signal in the digital chip, the clock signal should be distributed symmetrically to each register unit, so that when the clock reaches each register from the same clock source, the clock delay difference is minimized, and therefore, the clock signal needs to be wired separately.

Illustratively, in the present application, the CTS tool may be selected from the Synopsys Physical Compiler.

Further, in the embodiments of the present application, in a large-scale integrated circuit, the clock frequency of most sequential elements, which is controlled by clock synchronization, determines the data processing and transmission speed, and the clock frequency is the most dominant sign of the circuit performance. In the deep submicron stage of the integrated circuit, two main factors for determining the clock frequency are the longest circuit delay of the combinational logic part and the clock skew (clock skew) in the synchronous element, and the switching speed of the combinational logic circuit is continuously improved along with the reduction of the transistor size, and the clock skew becomes a restriction factor influencing the circuit performance. The main purpose of clock tree synthesis is to reduce clock skew.

Taking a clock domain as an example, a clock source point (source) is finally fanned out to a clock terminal (sink) of many registers, the fanout from a clock source is very large, the load is very large, and the clock source cannot drive so many loads behind the clock source point. Thus, a clock tree structure is needed to drive the final leaf node (register) through one level of buffer.

Specifically, compared with the buffer tree, the clock tree is different from the buffer tree in that the buffer tree generally considers only the driving capability and does not concern the delay and skew (skew) of the tree, and is mainly used for the connection lines without timing requirements, such as reset (reset), scan enable (scan enable), and the like.

In the present application, several items, such as a root node of a tree, a clock cycle, a maximum delay of the tree, a minimum delay of the tree, skew (skew), a transit time (transition time), and a type of a buffer, are necessary indexes that are commonly used in making a clock tree. There are also options: nodes that are particularly leaf nodes (leaf pins), nodes that are particularly not leaf nodes (exceeded pins), and unit (cell) protection units (predicted cells) that are particularly required to remain in the clock tree, etc.

In the embodiment of the present application, further, after the library file and the design data are imported, I/O cell placement (I/O Place), Megacell placement (Megacell Place), Row channel Generation (Row Generation), and Power Routing (Power Routing) may also be performed.

Specifically, in the present application, when performing I/O cell placement, the backend design tool needs to consider the location of each internal module, the number and the type of power PADs. Different types of signal PADs need different types of power supplies, some power supplies with the same voltage cannot be shared, especially, analog signals and the power supplies of the analog signals need to be isolated from other signals, and the minimum requirement of chip packaging and the power consumption in a chip need to be considered in the calculation of the number of the power supply PADs.

Specifically, in the present application, the components such as ADC, DAC, PLL, memory belong to megacell (megacell), and all back-end EDA layout software has a function of automatically placing megacell (megacell). Typically, manual placement of megacells (megacells) is chosen in designs with more than five megacells. Before discharging, the flow direction of the operation data, the relation and the position among the big modules need to be known, and therefore the general position of the megacell (megacell) is determined.

Further, in the present application, when placing each megacell (megacell) one by one, the position, direction, number and correspondence relationship between the pins (pins) are considered, because the megacell (megacell) often prohibits the use of several metal wiring layers, it is noted that enough space is left for the signal lines passing through it, especially the distance between the megacells (megacells).

If the megacell itself does not have a power ring, it leaves more room around it to add a ring. The width of the ring is determined from the rate of change of the data by the manufacturer's formula. Some software can put several megacells (megacells) adjacent together into a ring to save space, where the width of the common ring should be the largest of the individual ring widths. A common layout planning (floor plan) method is to put megacells (megacells) around and standard cells (standard cells) in the middle. The spatial shape of the standard cell (standard cell) is left to be the best in the square.

Specifically, in the present application, the Row channel (Row) is used for placing a standard cell (standard cell), and the overall shape of the Row channel (Row) is already roughly determined by the position of the megacell (megacell), and a certain space is left between the Row channel (Row) and the megacell (megacell) to facilitate signal connection of the megacell (megacell). A few row lanes (rows) can be made between megacells (megacells) for use when too long a line is connected, buffer relays are added, or a clock tree is generated.

Specifically, in the present application, the wiring density differs depending on the power consumption of each module when the power supply is wired. After the power wiring is completed, the overall power supply condition can be checked. In the traditional design that the standard cell (standard cell) is placed in the center and is powered by the pins on the periphery, a circle of power supply ring can be added on the periphery of the row concentrated by the standard cell (standard cell).

Based on the above embodiment, in a further embodiment of the present application, in the embodiment of the present application, before importing the library file and the design data, that is, before step 201, the chip back-end design method may further include the following steps:

step 2011, a first start command is executed to start the back-end design process.

In the embodiment of the application, before the back-end design tool starts chip back-end design, the back-end design tool may execute a first start command to start a back-end design flow. After the chip back end design is started, the back end design tool stores files and design data into a local storage space.

It should be noted that, in the embodiment of the present application, step 202 may include:

in step 202a, when the PnR tool performs the wiring process based on the library file and the design data, the optimization timing command is executed.

And after step 202a, i.e. after the execution of the optimization timing command,

step 202b, the PnR tool executes the first write-out command to obtain a first report, a first netlist and a first file.

Further, in the embodiment of the present application, when the PnR tool performs the wiring processing based on the library file and the design data, after the optimization timing command is executed, that is, after step 202a, the chip back-end design method may further include the following steps:

step 2012, a first stop command is executed to terminate the routing process in the back-end design flow.

And 2013, executing the second starting command, starting a correction process, and correcting the information of the PnR tool through the correction process to obtain corrected information.

In the embodiment of the present application, in the routing stage, i.e., in the routing process in the back-end design flow, the back-end design tool may execute the first stop command to temporarily suspend the routing process in the back-end design flow, i.e., suspend routing, and at this time, the back-end design flow of the chip is not exited.

Further, in the embodiment of the application, the back-end design tool may further execute a second start command to start the correction process, so that the information of the PnR tool may be corrected through the correction process to obtain the corrected information.

It should be noted that, in the present application, the correction procedure may be used to correct the correlation between the PnR tool and the STA tool, so as to improve the consistency between the two tools.

It is understood that, in the embodiment of the present application, the backend design tool may perform the methods of step 2012 and step 2013 in sequence, or may notify the method of step 2012 and step 2013.

Further, in the embodiment of the present application, after the information of the PnR tool is corrected based on the first report and the second report and the corrected information is obtained, that is, after step 204, the chip back-end design method may further include the following steps:

and step 2014, executing a third starting command, and continuing a back-end design process to complete the back-end design of the chip and output the layout.

In the embodiment of the application, after the back-end design tool finishes the correction of the information of the PnR tool according to the first report and the second report, the third start command may be executed, the back-end design process is continued, and after a plurality of iterations, the back-end design of the chip is finished, and the layout is output.

It should be noted that, in the embodiment of the present application, after the execution of the correction flow is completed, the information of the PnR tool has been modified, and therefore, when the back-end design tool continues to perform the back-end design flow, only the other information of the PnR tool except the modified information needs to be repaired, and the information of the PnR tool does not need to be iteratively repaired, so that the number of iterations is greatly reduced, tapeout is accelerated, and power consumption is saved.

Further, in the embodiment of the present application, fig. 6 is a schematic diagram of a back-end design process of a chip proposed in the present application, and as shown in fig. 6, compared with the current ECO process in fig. 2, the back-end design tool of the present application adds a correction process at a Routing stage before a project enters into timing ECO. The specific method comprises the following steps: after route _ opt, a write-out instruction is executed to write out the current hold report, netlist, and def (step 108 c). At this time, the ECO process is stopped but not exited, the background calls an insert dummy file (step 108d), a starRC (step 108e), and an STA process (step 108f), then generates a corresponding STA hold report, compares the STA hold report with the hold report generated by the PnR tool, determines a hold fall difference, then, the back-end design tool may denormalize the hold fall difference to the current PnR to realize a fix hold (step 108g), and continues to execute step 106 after the correction process is completed.

Therefore, in the application, the correlation between the PnR tool and the STA tool is corrected in the routing stage by the back-end design tool, so that the hold visualization clean in the PnR stage can be basically achieved, the iteration times of the timing fix are greatly reduced, and the risk of the timing fix is reduced. In addition, due to the fact that correlation between the PnR tool and the STA tool is correct, the situation that a large number of delay cells are inserted by a fix hold in a wrong mode is avoided, and dynamic power consumption is effectively reduced. That is to say, in the present application, the back-end design tool stops the routing process in the back-end design flow at the chip routing stage without exiting, and inserts the correction flow to correct the correlation between the PnR tool and the STA tool, which can accurately fix the hold, and the flow is simple and easy to implement, and is very important to reduce the project timing convergence and to help to tapeout at time.

An embodiment of the present application provides a layout design method, and fig. 7 is a schematic diagram of an implementation flow of the layout design method, as shown in fig. 7, in the embodiment of the present application, the layout design method may include the following steps:

301, receiving a fourth starting command, starting a layout design process, and analyzing library files and design data carried in the fourth starting command; the design data includes a gate-level netlist and timing constraints obtained after the chip front end is designed.

Step 302, when the routing PnR tool is called to perform routing processing in the layout design flow based on the library file and the design data, if the optimization timing command is executed, a second stop command and a second write-out command are generated.

Step 303, in response to the second stop command, stopping the wiring process, and in response to the second write-out command, acquiring a third report, a second netlist, and a second file.

And step 304, based on the second netlist and the second file, calling an STA tool to perform static timing analysis processing, and generating a fourth report.

And 305, receiving a fifth starting command, starting a correction process, and correcting the information of the PnR tool based on the third report and the fourth report to obtain corrected information.

And step 306, receiving a sixth starting command, continuing the layout design process based on the corrected information, and outputting the layout.

In the embodiment of the present application, after the front-end design is completed, when the EDA tool performs layout design, the EDA tool may receive a fourth start command, start a layout design flow, and analyze library files and design data carried in the fourth start command. Wherein, importing the library file and the design data can also be understood as the beginning of the layout design process.

It should be noted that, in the embodiment of the present application, the EDA tool may be imported with required data when performing layout design. Specifically, these data may specifically include library files and design data, wherein the library files may be library files of standard cells, macro cells and I/O pads provided by a Foundry of chips (Foundry), which include a physical library, a timing library and a netlist library, given in the form of lef, tlf and v, respectively. The design data may be a gate-level netlist generated by synthesizing a chip front-end design, a script file with timing constraints and clock definitions, and a gcf constraint file generated therefrom.

Further, in the embodiments of the present application, the EDA tool is an EDA tool, and may include a plurality of tools provided by different suppliers, and in particular, different EDA tools may be used when different commands are executed and different types of processes are performed. For example, common layout PnR tools are IC Compiler, Astro, and SOC-Encon, Inc. of Synopsys, Inc. IC Compiler is another PnR tool, which was introduced by Synopsys, Inc. following Astro, which is commonly used for ultra-deep submicron level layout at 10nm technology.

In the embodiment of the application, after the library file and the design data are imported, the EDA tool calls the PnR tool to perform routing processing based on the library file and the design data, and in the routing processing, after the optimization timing command is executed, the EDA tool may generate a second stop command and a second write-out command, and may further respond to the second stop command to stop the routing processing, and may respond to the second write-out command to obtain a third report, a second netlist, and a second file.

Further, in the embodiment of the present application, when the PnR tool performs the routing processing based on the library file and the design data, after the optimization timing command is executed, that is, after route _ opt is completed, a second write-out command may be executed, and then the current hold report, netlist, and def in the PnR tool are written out, that is, the third report, the second netlist, and the second file are obtained.

Specifically, in the embodiment of the present application, when the EDA tool joins the correction flow in the Routing stage, after route _ opt is completed, the current hold report, netlist, and def may be written first, and then the subsequent correction processing may be performed using the current hold report, netlist, and def. At this time, the original layout design flow is temporarily suspended but not exited.

Further, in an embodiment of the present application, after the EDA tool writes out the third report, the second netlist, and the second file, the STA tool may be called to perform static timing analysis processing based on the second netlist and the second file, so as to generate a fourth report.

It should be noted that, in the embodiment of the present application, the EDA tool may receive the fifth start command, start the correction procedure, and then modify the information of the PnR tool based on the third report and the fourth report to obtain modified information, specifically, the EDA tool may first determine the margin difference according to the hold slope in the third report and the hold slope in the fourth report; then, the information of the PnR tool is corrected according to the residue difference value.

It is understood that, in the embodiment of the present application, after determining the margin difference according to the hold slope in the third report and the hold slope in the fourth report, the EDA tool may perform the correction process on the PnR tool information according to the margin difference.

Specifically, in the embodiment of the present application, when the EDA tool corrects the information of the PnR tool according to the margin difference, the margin difference obtained by calculation may be inversely scaled to the PnR tool, so that the correction of the information of the PnR tool may be completed.

Further, in the embodiment of the present application, after the information of the PnR tool is modified, the correction process is finished, and in the correction process, the EDA tool modifies the information of the PnR tool, so that continuous iteration for modifying the information of the PnR tool is not required in the subsequent ECO process, thereby saving the time and power consumption of the ECO process.

It is understood that, in the embodiment of the present application, after the correction process is completed, the EDA tool may receive the sixth start command, continue the layout design process based on the corrected information, and output the layout.

It should be noted that, in the embodiment of the present application, the EDA tool outputs the layout according to the GDSII format. That is, the layout is delivered to Foundry (where the actual circuit is formed on the wafer silicon wafer, and then packaged and tested to obtain the actual chip) in the GDSII file format.

Therefore, for the chip layout design flow, the input data comprises a gate-level netlist, a library file and a timing constraint, and the layout in the GDSII format is finally output through design and ECO repair of an EDA tool.

Specifically, in the present application, the layout design process is continued based on the corrected information, and when the layout is output, the EDA tool may call the STA tool to perform the static timing analysis processing based on the library file and the design data to obtain the timing report; if the timing report has a timing violation, executing a change command, and carrying out ECO processing on other information except the corrected information of the PnR tool; then, the EDA tool may continue to call the STA tool to perform static timing analysis processing until the obtained timing report does not have a timing violation, and output the layout.

In summary, by the layout design method provided in steps 301 to 306, the EDA tool can basically reach the hold visualization clean in the PnR stage by correcting the correlation between the PnR tool and the STA tool in the routing stage, thereby greatly reducing the iteration number of the timing fix and reducing the risk of the timing fix. In addition, due to the fact that correlation between the PnR tool and the STA tool is correct, the situation that a large number of delay cells are inserted by a fix hold in a wrong mode is avoided, and dynamic power consumption is effectively reduced. That is to say, in the present application, the EDA tool stops the routing process in the layout design process at the chip routing stage without exiting, and inserts the correction process to correct the correlation between the PnR tool and the STA tool, which can accurately fix the hold, and the process is simple and easy to implement, and is very important to reduce the project timing convergence and to help in order to tapeout.

The embodiment of the application provides a layout design method, wherein an EDA tool receives a fourth starting command, starts a layout design flow, and analyzes a library file and design data carried in the fourth starting command; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed; when a wiring PnR tool is called to perform wiring processing in the layout design flow based on the library file and the design data, if the optimization timing sequence command is executed, a second stop command and a second write-out command are generated; stopping the wiring processing in response to the second stop command, and simultaneously responding to the second write-out command to obtain a third report, a second netlist and a second file; calling an STA tool to perform static time sequence analysis processing based on the second netlist and the second file, and generating a fourth report; receiving a fifth starting command, starting a correction process, and correcting the information of the PnR tool based on the third report and the fourth report to obtain corrected information; and receiving a sixth starting command, continuing the layout design process based on the corrected information, and outputting the layout. That is to say, in the application, in the routing stage, a correction flow is inserted, and the correlation between the PnR tool and the STA tool is corrected by performing accurate correction processing according to the first report obtained by the PnR tool and the second report obtained by the STA tool, so that the problem of increased iteration times in the ECO flow caused by inconsistency between the PnR tool and the STA tool can be solved, the iteration times of the ECO flow can be greatly reduced, the time of layout design can be further shortened, and the layout design efficiency can be effectively improved.

Based on the above embodiments, in another embodiment of the present application, fig. 8 is a schematic structural diagram of a back-end design tool, and as shown in fig. 8, the back-end design tool 10 according to the embodiment of the present application may include: an introduction unit 11, a first acquisition unit 12, a first generation unit 13, a first correction unit 14, a change unit 15, a first output unit 16,

the import unit 11 is configured to import library files and design data; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed;

the first obtaining unit 12 is configured to, when the PnR tool performs routing processing based on the library file and the design data, execute a first write-out command after the optimization timing command is executed, and obtain a first report, a first netlist, and a first file;

the first generating unit 13 is configured to execute a first analysis command by the static timing analysis STA tool based on the first netlist and the first file, and generate a second report;

the first correcting unit 14 is configured to correct the information of the PnR tool based on the first report and the second report, and obtain corrected information;

the first obtaining unit 12 is further configured to, based on the library file and the design data, execute a second analysis command by the STA tool to obtain a timing report;

the change unit 15 is configured to execute a change command to perform ECO processing on information of the PnR tool other than the corrected information if the timing report has a timing violation;

the first obtaining unit 12 is further configured to continue to execute a next analysis command by the STA tool until the obtained timing report does not have a timing violation;

the first output unit 16 is used for outputting the layout.

In an embodiment of the present application, further, fig. 9 is a schematic structural diagram of a back-end design tool, as shown in fig. 9, the back-end design tool 10 provided in the embodiment of the present application may further include a first processor 17 and a first memory 18 storing executable instructions of the first processor 17, and further, the back-end design tool 10 may further include a first communication interface 19, and a first bus 110 for connecting the first processor 17, the first memory 18, and the first communication interface 19.

In an embodiment of the present invention, the first Processor 17 may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a ProgRAMmable Logic Device (PLD), a Field ProgRAMmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic devices for implementing the above processor functions may be other devices, and the embodiments of the present application are not limited in particular. The back-end design tool 10 may further comprise a first memory 18, which first memory 18 may be connected to the first processor 17, wherein the first memory 18 is configured to store executable program code comprising computer operating instructions, and wherein the first memory 18 may comprise a high-speed RAM memory and may further comprise a non-volatile memory, such as at least two disk memories.

In the embodiment of the present application, the first bus 110 is used to connect the first communication interface 19, the first processor 17, and the first memory 18 and the intercommunication among these devices.

In an embodiment of the present application, the first memory 18 is used for storing instructions and data.

Further, in the embodiment of the present application, the first processor 17 is configured to import library files and design data; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed; when the wiring PnR tool carries out wiring processing based on the library file and the design data, after the optimization time sequence command is executed, executing a first writing-out command to obtain a first report, a first netlist and a first file; based on the first netlist and the first file, the static timing analysis STA tool executes a first analysis command to generate a second report; correcting the information of the PnR tool based on the first report and the second report to obtain corrected information; based on the library file and the design data, the STA tool executes a second analysis command to obtain a timing report; if the time sequence report has time sequence violation, executing a change command, and carrying out ECO processing on other information of the PnR tool except the corrected information; and the STA tool continues to execute the next analysis command until the obtained time sequence report has no time sequence violation, and the layout is output.

In practical applications, the first Memory 18 may be a volatile Memory (volatile Memory), such as a Random-Access Memory (RAM); or a non-volatile Memory (non-volatile Memory), such as a Read-Only Memory (ROM), a flash Memory (flash Memory), a Hard Disk (Hard Disk Drive, HDD) or a Solid-State Drive (SSD); or a combination of the above types of memories and provides instructions and data to the first processor 17.

In addition, each functional module in this embodiment may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.

Based on the understanding that the technical solution of the present embodiment essentially or a part contributing to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The embodiment of the application provides a back-end design tool, wherein a correction flow is inserted into the back-end design tool in a routing stage, and accurate correction processing is carried out according to a first report obtained by a PnR tool and a second report obtained by an STA tool so as to correct the correlation between the PnR tool and the STA tool, so that the problem that the number of iterations in an ECO flow is increased due to the inconsistency of the PnR tool and the STA tool can be solved, the number of iterations of the ECO flow can be greatly reduced, the time for designing the back end of a chip is shortened, and the chip design efficiency is effectively improved.

Based on the above embodiments, in another embodiment of the present application, fig. 10 is a schematic structural diagram of an EDA tool, and as shown in fig. 10, an EDA tool 20 provided in this embodiment of the present application may include: a receiving unit 21, an analyzing unit 22, a calling unit 23, a second generating unit 24, a stopping unit 25, a second acquiring unit 26, a second correcting unit 27, a second outputting unit 28,

the receiving unit 21 is configured to receive a fourth start command and start a layout design process;

the analysis unit 22 is configured to analyze the library file and the design data carried in the fourth start command; the design data comprises a gate-level netlist and a time sequence constraint obtained after the front end of the chip is designed;

the calling unit 23 is configured to call a routing PnR tool to perform routing processing in the layout design flow based on the library file and the design data;

the second generating unit 24 is configured to generate a second stop command and a second write-out command if the optimization timing command is executed;

the suspending unit 25 configured to suspend the wiring process in response to the second stop command;

the second obtaining unit 26 is configured to obtain a third report, a second netlist, and a second file in response to the second write-out command;

the calling unit 23 is further configured to call an STA tool to perform static timing analysis processing based on the second netlist and the second file, and generate a fourth report;

the receiving unit 21 is further configured to receive a fifth start command, and start a calibration process;

the second correcting unit 27 is configured to correct the information of the PnR tool based on the third report and the fourth report, and obtain corrected information;

the receiving unit 21 is further configured to receive a sixth start command;

and the second output unit 28 is configured to continue the layout design process based on the corrected information, and output the layout.

Further, in an embodiment of the present application, the second output unit 28 is specifically configured to invoke the STA tool to perform static timing analysis processing based on the library file and the design data, so as to obtain a timing report; if the time sequence report has time sequence violation, executing a change command, and carrying out ECO processing on other information of the PnR tool except the corrected information; and continuously calling the STA tool to perform static time sequence analysis processing until the obtained time sequence report has no time sequence violation, and outputting the layout.

Further, in the embodiment of the present application, the second correcting unit 27 is specifically configured to determine a margin difference according to the hold slack in the third report and the hold slack in the fourth report; and correcting the information of the PnR tool according to the margin difference.

In an embodiment of the present application, further, fig. 11 is a schematic structural diagram of a component of an EDA tool, as shown in fig. 11, the layout design tool 20 provided in the embodiment of the present application may further include a second processor 29, a second memory 210 storing executable instructions of the second processor 29, and further, the EDA tool 20 may further include a second communication interface 211, and a second bus 212 for connecting the second processor 29, the second memory 210, and the second communication interface 211.

The embodiment of the application provides a back-end design tool, wherein a correction flow is inserted into an EDA tool in a routing stage, and accurate correction processing is carried out according to a first report obtained by a PnR tool and a second report obtained by an STA tool so as to correct the correlation between the PnR tool and the STA tool, so that the problem that the number of iterations in an ECO flow is increased due to the inconsistency between the PnR tool and the STA tool can be solved, the number of iterations in the ECO flow can be greatly reduced, the layout design time is shortened, and the layout design efficiency is effectively improved.

An embodiment of the present application provides a computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the program implements the chip back-end design method as described above.

Specifically, the program instructions corresponding to a chip back end design method in this embodiment may be stored in a storage medium such as an optical disc, a hard disc, or a usb disk, and when the program instructions corresponding to a chip back end design method in the storage medium are read or executed by an electronic device, the method includes the following steps:

Specifically, the program instructions corresponding to a layout design method in this embodiment may be stored in a storage medium such as an optical disc, a hard disk, or a usb disk, and when the program instructions corresponding to a layout design method in the storage medium are read or executed by an electronic device, the method includes the following steps:

The embodiment of the present application provides a chip, where the chip includes a programmable logic circuit and/or a program instruction, and when the chip runs, the chip back end design method described above is implemented, and specifically includes the following steps:

The embodiment of the present application provides a chip, where the chip includes a programmable logic circuit and/or a program instruction, and when the chip runs, the layout design method described above is implemented, and the method specifically includes the following steps:

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of implementations of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks in the flowchart and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.

Claims

1. A chip back end design method, applied to a back end design tool, the method comprising:

if the timing report has a timing violation, executing a change command, and performing engineering change ECO processing on other information of the PnR tool except the corrected information;

2. The method of claim 1, wherein the STA tool executes a first analysis command based on the first netlist and the first file to generate a second report comprising:

executing a first insert command based on the first netlist and the first file, and performing insert processing on a gap;

executing a first extraction command, and extracting a first parasitic parameter;

and the STA tool executes the first analysis command, performs static analysis processing on the first parasitic parameter and generates the second report.

3. The method of claim 1, wherein modifying the PnR tool information based on the first report and the second report to obtain modified information comprises:

determining a margin difference according to the hold slack in the first report and the hold slack in the second report;

and correcting the information of the PnR tool according to the margin difference.

4. The method of claim 3, wherein modifying the PnR tool information according to the margin difference comprises:

and reversely marking the margin difference to the PnR tool to finish the correction processing.

5. The method of claim 1, wherein prior to importing the library file and the design data, the method further comprises:

and executing the first starting command and starting the back-end design flow.

6. The method of claim 5, wherein when the PnR tool performs routing processing based on the library file and the design data, after performing an optimization timing command, the method further comprises:

executing a first stop command, and stopping the wiring processing in the back-end design flow;

and executing a second starting command, and starting a correction process to correct the information of the PnR tool through the correction process to obtain corrected information.

7. The method of claim 6, wherein the modifying the PnR tool information based on the first report and the second report, and after obtaining modified information, the method further comprises:

and executing a third starting command, continuing the back-end design process to complete the back-end design of the chip, and outputting the layout.

8. A layout design method, applied to an EDA tool, the method comprising:

9. The method according to claim 8, wherein the continuing the layout design process based on the corrected information and outputting the layout comprises:

calling the STA tool to perform static time sequence analysis processing based on the library file and the design data to obtain a time sequence report;

and continuously calling the STA tool to perform static time sequence analysis processing until the obtained time sequence report has no time sequence violation, and outputting the layout.

10. The method of claim 8, wherein modifying the PnR tool information based on the third report and the fourth report to obtain modified information comprises:

determining a margin difference according to the hold slack in the third report and the hold slack in the fourth report;

11. A back-end design tool, the back-end design tool comprising: an introduction unit, a first acquisition unit, a first generation unit, a first correction unit, a change unit, a first output unit,

the first output unit is used for outputting the layout.

12. A back-end design tool comprising a first processor, a first memory storing instructions executable by the first processor, the instructions when executed by the first processor implementing the method of any of claims 1-7.

13. An EDA tool, comprising: a receiving unit, an analyzing unit, a calling unit, a second generating unit, a stopping unit, a second obtaining unit, a second correcting unit and a second output unit,

the receiving unit is further configured to receive a sixth start command;

14. An EDA tool comprising a second processor, a second memory storing instructions executable by said second processor, said instructions when executed by said second processor implementing the method of any of claims 8 to 10.

15. A chip comprising programmable logic circuits and/or program instructions which, when run, implement the method of any one of claims 1-7 and 8-10.

16. A computer readable storage medium, on which a program is stored, for application in back-end design tools and EDA tools, characterized in that the program, when executed by a first processor, implements the method of any of claims 1-7, and the program, when executed by a second processor, implements the method of any of claims 8-10.