CN117521572B - Chip design verification method and non-transitory computer readable storage medium - Google Patents
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Abstract
A chip design verification method and a non-transitory computer readable storage medium, the chip design verification method includes: providing a netlist of a digital chip, the netlist comprising a plurality of registers each including an output; and the operation circuit performs static time sequence analysis on the netlist to generate an analysis result. In response to the analysis result being compliant, further comprising: the operation circuit analyzes a plurality of fan-out values of a plurality of registers; the operation circuit sets a fan-out threshold value and generates a register list according to the fan-out threshold value and a plurality of fan-out values, wherein the register list records at least one of a plurality of registers, and the fan-out value of the at least one of the plurality of registers is larger than or equal to the fan-out threshold value; the arithmetic circuit sets gating logic at an output end of the at least one of the plurality of registers in the register list; and the operation circuit performs functional mode timing verification on the adjusted netlist to generate a verification result. The chip design verification method can effectively improve the dynamic voltage drop problem of the digital chip.
Description
Technical Field
The present disclosure relates to a chip design verification method, and more particularly, to a chip design verification method capable of reducing dynamic voltage drop in early stage of chip design and a non-transitory computer readable storage medium.
Background
Along with the evolution of the production process of the digital chip, the resistance value of the metal wire inside the chip is continuously increased along with the reduction of the width, so that the voltage drop inside the chip is more and more obvious, and the deviation between the time sequence inside the chip and the ideal time sequence is caused. Therefore, voltage drop has become one of the key acceptance items of the back end of the chip.
The voltage drop of the chip includes a static voltage drop and a dynamic voltage drop. The static voltage drop results from the resistive partial pressure of the internal circuitry of the chip and can be resolved by analyzing the resistive effect. The dynamic voltage drop is a voltage drop generated by current fluctuation when the switching circuit performs switching, and when a large number of switching circuits perform switching simultaneously, a large amount of current is generated in a short time, so that the dynamic voltage drop occurs. Therefore, how to effectively improve the dynamic voltage drop problem of the digital chip is one of the problems in the art.
Disclosure of Invention
The application document relates to a chip design verification method, comprising the following steps: (a) Providing a netlist of the digital chip, wherein the netlist comprises a plurality of registers, and each of the registers comprises an output terminal; and (b) the operation circuit performs a static timing analysis on the netlist to generate an analysis result. In response to the analysis result compliance, the chip design verification method further comprises: (c) The operation circuit analyzes a plurality of fan-out values of a plurality of registers; (d) The operation circuit sets a fan-out threshold value and generates a register list according to the fan-out threshold value and a plurality of fan-out values, wherein the register list records at least one of the plurality of registers, and the fan-out value of the at least one of the plurality of registers is larger than or equal to the fan-out threshold value; (e) The arithmetic circuit sets gating logic at an output end of the at least one of the plurality of registers in the register list; and (f) the operation circuit performs functional mode timing verification on the adjusted netlist to generate a verification result.
In some embodiments of the chip design verification method, in response to the analysis result or the verification result being non-compliant, the chip design verification method further comprises: the operation circuit generates a risk message through the output device to prompt the analysis result or the verification result to be not compliant.
In some embodiments of the chip design verification method, in response to the verification result being compliant, the chip design verification method further comprises: the operation circuit generates a release message through the output device to prompt the analysis result and verify the compliance of the result.
In some embodiments of the chip design verification method, step (f) comprises: the operation circuit generates a design for a testability circuit (DFT) netlist according to the adjusted netlist; and the operation circuit performs functional mode timing verification by using the testability netlist and the functional mode timing constraint file to generate a verification result.
In some embodiments of the chip design verification method, the chip design verification method further comprises: step (b) is performed again in response to the functional mode design of the netlist being adjusted.
In some embodiments of the chip design verification method, step (e) comprises: the arithmetic circuit uses the engineering change instruction to set gating logic at an output of the at least one of the plurality of registers.
In some embodiments of the chip design verification method, functional combinational logic is included between an output of the at least one of the plurality of registers and an input of another one of the plurality of registers, and gating logic is located between the output of the at least one of the plurality of registers and the functional combinational logic.
In some embodiments of the chip design verification method, the gating logic includes an AND (AND) gate AND a NOT (NOT) gate in series.
The present disclosure relates to a non-transitory computer readable storage medium storing a plurality of computer readable instructions that when executed by one or more processors to verify a netlist of a digital chip, the one or more processors perform the following operations: (a) Static timing analysis is performed on the netlist to produce analysis results. In response to the analysis result compliance, the one or more processors are further configured to: (b) analyzing a plurality of fan-out values of a plurality of registers of the netlist; (c) Setting a fan-out threshold value, and generating a register list according to the fan-out threshold value and a plurality of fan-out values, wherein the register list records at least one of a plurality of registers, and the fan-out value of the at least one of the plurality of registers is greater than or equal to the fan-out threshold value; (d) Setting gating logic at an output of the at least one of the plurality of registers in the register list; and (e) performing functional mode timing verification on the adjusted netlist to produce a verification result.
In some embodiments of the non-transitory computer readable storage medium, in response to the analysis result or the verification result being not compliant, the one or more processors are further configured to: the output device is used for generating a risk message to prompt the analysis result or verify that the result is not compliant.
In some embodiments of the non-transitory computer readable storage medium, in response to verifying that the results are compliant, the one or more processors are further configured to: a release message is generated by the output device to prompt the analysis result and verify the compliance of the result.
In some embodiments of the non-transitory computer readable storage medium, step (e) comprises: generating a design for a testability (DFT) netlist from the adjusted netlist; and performing functional mode timing verification using the testability netlist and the functional mode timing constraint file to generate a verification result.
In some embodiments of the non-transitory computer readable storage medium, the one or more processors are further configured to: step (a) is performed again in response to the functional mode design of the netlist being adjusted.
In some embodiments of the non-transitory computer readable storage medium, step (d) comprises: an engineering change instruction is used to set gating logic at an output of the at least one of the plurality of registers.
In some embodiments of the non-transitory computer readable storage medium, the functional combinational logic is included between an output of the at least one of the plurality of registers and an input of another one of the plurality of registers, and the gating logic is located between the output of the at least one of the plurality of registers and the functional combinational logic.
In some embodiments of non-transitory computer readable storage media, the gating logic includes an AND (AND) gate AND a NOT (NOT) gate in series.
By the chip design verification method and the non-transient computer readable storage medium, the dynamic voltage drop problem can be improved under the condition of not greatly increasing the chip area, and the improvement is carried out in the early stage of the digital chip design, so that the digital chip has longer repair time before mass production.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description of the drawings in which:
FIG. 1 is a flow chart of a chip design verification method according to an embodiment of the present application;
FIG. 2 is a simplified schematic diagram of a netlist depicted in accordance with an embodiment of the present application; and
FIG. 3 is a simplified schematic diagram of a netlist depicted in accordance with an embodiment of the present application.
[ symbolic description ]
100 Chip design verification method
S110, S120, S125, S130 step
S135, S140, S150, S160 step
S170, S175, S180 step
200 Netlist of the design
R1-R10 register
D input terminal
Q output terminal
Gate logic
FL: function combination logic
CLK1, CLK2 clock signals
DATA-DATA Signal
Description of the embodiments
Embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or similar elements or method flows.
In this document, when an element is referred to as being "connected," it may be referred to as being "electrically connected" or "optically connected," and when an element is referred to as being "coupled," it may be "electrically coupled" or "optically coupled. "connected" or "coupled" may also mean that two or more elements co-operate or interact with each other. Unless the context specifically defines the article, "a" and "an" may refer to one or more. It will be further understood that the terms "comprises," "comprising," "includes," and/or "having," when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 is a flow chart of a chip design verification method 100 according to an embodiment of the present application. In some embodiments, the chip design verification method 100 includes steps S110, S120, S125, S130, S135, S140, S150, S160, S170, S175, and S180. One or more steps of the chip verification method 100 may be performed by an electronic device (not shown) that incorporates an arithmetic circuit, such as a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA), or other suitable logic circuit.
In step S110, a netlist of the digital chip is provided, wherein the netlist includes a plurality of registers, and each register includes an output terminal. For the configuration of registers in the netlist, please further refer to fig. 2. FIG. 2 is a simplified schematic diagram of netlist 200 depicted in accordance with an embodiment of the present application.
As shown in FIG. 2, netlist 200 includes registers R1-R10. The registers R1-R10 each include an input D, an output Q, and a timing signal (labeled with triangle symbols). The input end D of the register R1 is used for receiving the DATA signal DATA, the output end Q of the register R1 is coupled to the input ends D of the registers R2 and R3, wherein a function combination logic FL is respectively included between the output end Q of the register R1 and the input ends D of the registers R2 and R3, and the timing signal ends of the registers R1 to R3 are used for receiving the same clock signal CLK1. The input end D of the register R4 is used for receiving the DATA signal DATA, the output end Q of the register R4 is coupled to the input end D of the registers R5-R10, wherein a function combination logic FL is respectively included between the output end Q of the register R4 and the input end D of the registers R5-R10, and the timing signal ends of the registers R4-R10 are used for receiving the clock signal CLK2 in the same manner, wherein the clock signal CLK1 is different from the clock signal CLK 2. In some embodiments, functional combination logic FL may be implemented by a half adder, a half subtractor, a full adder, a full subtractor, a decoder, an encoder, other logic circuits, or any combination thereof.
It should be noted that the output terminals Q of the registers R2-R3, R5-R10 may be respectively coupled to at least one other register, and the other registers coupled to the output terminals Q of the registers R2-R3, R5-R10 are omitted in fig. 2 and 3 for brevity.
After the step S110 is performed, the operation circuit will perform step S120. In step S120, the arithmetic circuit performs a static timing analysis (Static Timing Analysis, STA) on the netlist (e.g., netlist 200) to generate an analysis result. Then, the operation circuit will execute step S125.
Taking the embodiment of FIG. 2 as an example, in static timing analysis, the operation circuit analyzes netlist 200 to check whether a hold time violation or a setup time violation has occurred. After the level of the clock signals CLK1, CLK2 changes (e.g., switches from low to high), if the DATA signal DATA is held for a short period of time, the DATA signal DATA cannot be recorded by the register at the next level change of the clock signals CLK1, CLK2, resulting in a "hold time violation". Furthermore, if the DATA signal DATA is kept for a short time before the levels of the clock signals CLK1, CLK2 change, the DATA signal DATA cannot be recorded by the register when the levels of the clock signals CLK1, CLK2 change, resulting in the occurrence of "setup time violation".
In step S125, the arithmetic circuit decides the step to be performed next based on the analysis result. If the analysis result is not compliant (e.g. a hold time violation or a setup time violation occurs), the operation circuit will execute step S130. If the analysis result is compliance, the operation circuit will execute step S140.
In step S130, the operation circuit controls the output device to generate a risk message to indicate that the analysis result is not compliant or that the verification result (described in the following paragraphs) corresponds to the verification failure. Taking the embodiment of fig. 2 as an example, when the computing circuit determines that the netlist 200 has a hold time violation or a build time violation, the computing circuit controls an output device (e.g., a screen or a speaker) to generate a risk message (e.g., a prompt tone, a text message, etc.) to remind a designer (e.g., a Design For Test (DFT) person, a functional designer, etc.) to correct the functional mode Design of the netlist 200. Then, the operation circuit will execute step S135.
In step S135, the arithmetic circuit decides the step to be performed next according to whether the functional mode design of the netlist (for example, netlist 200) is adjusted. In this document, the operation of adjusting the functional mode design of a netlist represents modifying the circuit design of a digital chip having the netlist. If the functional mode design of the netlist is adjusted (e.g. the functional mode design of the netlist 200 is adjusted according to the hold time violation or the build time violation condition), the operation circuit will execute step S120 again. If the functional mode design of the netlist is not adjusted (e.g., the functional mode design of the netlist 200 has not been modified for the hold time violation or the build time violation), the operation circuit will execute step S130 again.
In step S140, the arithmetic circuit analyzes Fan-out (Fan out) values for all registers in the netlist. Taking the embodiment of fig. 2 as an example, since the output terminal Q of the register R1 is coupled to the input terminals D of the registers R2, R3, the fan-out value of the register R1 is 2. On the other hand, since the output terminal Q of the register R4 is coupled to the input terminal D of the registers R5-R10, the fan-out value of the register R4 is 6. Then, the operation circuit will execute step S150.
In step S150, the operation circuit sets a fan-out Threshold (Threshold), and generates a register list according to the fan-out Threshold and the fan-out value analyzed by the operation circuit in step S140, wherein the register list records at least one register, and the fan-out value of the at least one register is greater than or equal to the fan-out Threshold. Next, step S160 is performed.
For example, the arithmetic circuit analyzes the registers R1-R10 in the netlist 200 in step S140 to obtain the following Table 1.
TABLE 1
| Register | Fan-out value |
| R1 | 2 |
| R2 | 2 |
| R3 | 8 |
| R4 | 6 |
| R5 | 3 |
| R6 | 6 |
| R7 | 1 |
| R8 | 4 |
| R9 | 10 |
| R10 | 1 |
Next, in step S150, the arithmetic circuit sets the fan-out threshold to 5, and according to the above table 1 and the fan-out threshold, the arithmetic circuit may generate a register list as shown in the following table 2.
TABLE 2
It should be noted that the number of registers, connection status, and fanout threshold values of fig. 2 and tables 1 and 2 above are only examples, and are not intended to limit the present application, and the number of other registers, connection status, and fanout threshold values are within the scope of the present application.
In step S160, the arithmetic circuit sets gating logic at its output for the registers in the register list obtained in step S150. For the change of the netlist 200 before and after the operation circuit performs the step S160, please refer to fig. 2 and 3 together. FIG. 3 is a simplified schematic diagram of netlist 200 after performing step S160 according to an embodiment of the present application.
First, please refer to the embodiment of fig. 2, before executing step S160, the output Q of the registers R1-R10 is not coupled to any gating logic. Then, since the registers R3, R4, R6 and R9 are recorded in the register list in step S150, in step S160, the operation circuit couples the output Q of the registers R3, R4, R6 and R9 to the gating logic G, which is located between the output Q of the registers R3, R4, R6 and R9 and the function combination logic FL coupled to the registers R3, R4, R6 and R9, as shown in fig. 3. On the other hand, since the registers R1, R2, R5, R7, R8 and R10 are not recorded in the register list in step S150, the gate logic G is not set at the output Q of the registers R1, R2, R5, R7, R8 and R10 in step S160.
In some embodiments, the gating logic G includes an AND (AND) gate AND a NOT (NOT) gate in series to control whether the output of the register outputs data. In some embodiments, the operation of the arithmetic circuit to set the gating logic G at the output Q of the register may be implemented by having the arithmetic circuit use an engineering change instruction (Engineering Change Order, ECO).
After the operation circuit finishes the step S160, the operation circuit will execute the step S170. In step S170, the operational circuitry performs functional mode timing verification on a netlist (e.g., netlist 200) to produce a verification result. In detail, in step S170, the operation circuit first generates a design for a testability (DFT) netlist according to the adjusted netlist. Then, the operation circuit uses the testability circuit design netlist and a functional mode timing constraint file to execute functional mode timing verification, if the testability circuit design netlist meets the functional mode timing constraint file (i.e. the adjusted netlist has no hold time violation and build time violation), the operation circuit generates a verification result corresponding to successful verification. Conversely, if the testability circuit design netlist fails to satisfy the functional mode timing constraint file (i.e., the adjusted netlist has a hold time violation or a build time violation), the operation circuit generates a verification result corresponding to a verification failure. Then, the operation circuit will execute step S175.
In step S175, the arithmetic circuit decides the step to be performed next based on the verification result. If the verification result corresponds to a successful verification, the operation circuit will execute step S180. If the verification result corresponds to a verification failure, the operation circuit will execute step S130.
In step S180, the operation circuit determines the adjusted netlist compliance, and at this time, the operation circuit controls the output device to generate a release message to prompt compliance of the analysis result and to verify that the verification result corresponds to successful verification.
Compared with the traditional method of setting gating logic at the output ends of all registers in a netlist to improve dynamic voltage drop, the chip design verification method 100 of the application document only sets gating logic for registers with larger fanout values in the netlist by analyzing the fanout values of all registers and sorting out a register list according to fanout threshold values by using an operation circuit, not only can the problem of dynamic voltage drop be improved, but also the situation that a large amount of area is increased due to the fact that too many gating logic is introduced and the building time among the registers is not influenced can be avoided.
In addition, in the conventional chip design method, the operation of setting the gating logic for the dynamic voltage drop of the netlist is generally operated in the back-end flow of the chip design, and the phenomenon that the time sequence setup time of the digital chip is affected due to too late repair of the digital chip is easy to occur. In the chip design verification method 100, the fan-out value is analyzed and the gating logic is set through the operation circuit in the Front-End process (Front-End) of the chip design, so that the digital chip has more time to establish time sequence before mass production, the risk of introducing the gating logic is reduced, and the stability of repair is improved.
It should be noted that the number and order of steps in the chip design verification method 100 of the present application are only examples, and are not intended to limit the present application, and the number and order of other steps are all within the scope of the present application. In some embodiments, step S135 may be omitted, so step S120 is directly performed after step S130 is completed.
The present application provides a non-transitory computer readable storage medium storing a plurality of computer readable instructions that, when executed by one or more processors, are configured to perform the chip design verification method 100 described above. In some embodiments, the non-transitory computer readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). For example, non-transitory computer readable storage media include semiconductor or solid state Memory, magnetic tape, magnetic disk, random access Memory (Random Access Memory, RAM), read Only Memory (ROM), hard disk, and/or optical disk. In some embodiments using optical discs, the non-transitory computer readable storage medium includes a Compact disc-Read Only Memory (CD-ROM), a Compact disc-Read/Write (CD-R/W), and/or a digital video optical disc (Digital Video Disc, DVD).
The foregoing is merely a preferred embodiment of the present application, and various modifications and equivalent changes can be made in the structure of the present application without departing from the scope or spirit of the present application. In summary, modifications and equivalent variations made to the present application within the scope of the following claims are intended to be covered by the present application.
Claims (16)
1. A chip design verification method, comprising:
(a) Providing a netlist of a digital chip, wherein the netlist comprises a plurality of registers, and each of the registers comprises an output terminal; and
(b) An operation circuit performs a static timing analysis on the netlist to generate an analysis result,
wherein in response to the netlist not having a retention time violation and not having a build time violation, the analysis results are compliant, the chip design verification method further comprises:
(c) The operation circuit analyzes a plurality of fan-out values of the registers;
(d) The operation circuit sets a fan-out threshold value and generates a register list according to the fan-out threshold value and the fan-out values, wherein the register list records at least one of the registers, and the fan-out value of the at least one of the registers is larger than or equal to the fan-out threshold value;
(e) The operation circuit sets a gate logic at the output end of at least one of the registers in the register list; and
(f) The operation circuit performs a functional mode timing verification on the adjusted netlist, comprising: determining whether the adjusted netlist has the hold time violation and the build time violation to generate a verification result.
2. The chip design verification method according to claim 1, wherein in response to the analysis result or the verification result being not compliant, the chip design verification method further comprises:
the operation circuit generates a risk message through an output device to prompt that the analysis result or the verification result is not compliant.
3. The chip design verification method according to claim 1, wherein in response to the verification result compliance, the chip design verification method further comprises:
the operation circuit generates a release message through an output device to prompt the compliance of the analysis result and the verification result.
4. The chip design verification method according to claim 1, wherein the step (f) comprises:
generating a testability circuit design netlist by the operation circuit according to the adjusted netlist; and
the operation circuit uses the testability netlist and a function mode time sequence constraint file to execute the function mode time sequence verification so as to generate a verification result.
5. The chip design verification method according to claim 1, further comprising: in response to a functional mode design of the netlist being adjusted, step (b) is performed again.
6. The chip design verification method according to claim 1, wherein the step (e) comprises:
the arithmetic circuit uses an engineering change instruction to set the gating logic at the output of the at least one of the plurality of registers.
7. The chip design verification method according to claim 1, wherein a function combination logic is included between the output of the at least one of the plurality of registers and an input of another one of the plurality of registers, and the gating logic is located between the output of the at least one of the plurality of registers and the function combination logic.
8. The chip design verification method according to claim 1, wherein the gating logic comprises an AND gate and an NOT gate connected in series.
9. A non-transitory computer readable storage medium storing a plurality of computer readable instructions that when executed by one or more processors to validate a netlist of a digital chip, the one or more processors are configured to:
(a) Performing a static timing analysis on the netlist to generate an analysis result,
wherein in response to the netlist not experiencing a hold time violation and not experiencing a build time violation, the analysis results are compliant, the one or more processors are further configured to:
(b) Analyzing a plurality of fan-out values of a plurality of registers of the netlist;
(c) Setting a fan-out threshold, and generating a register list according to the fan-out threshold and the fan-out values, wherein the register list records at least one of the registers, and the fan-out value of the at least one of the registers is greater than or equal to the fan-out threshold;
(d) Setting a gate logic at an output of the at least one of the plurality of registers in the register list; and
(e) Performing a functional mode timing verification on the adjusted netlist, comprising: determining whether the adjusted netlist has the hold time violation and the build time violation to generate a verification result.
10. The non-transitory computer-readable storage medium of claim 9, wherein in response to the analysis result or the verification result being non-compliant, the one or more processors are further configured to:
a risk message is generated by an output device to indicate whether the analysis result or the verification result is not compliant.
11. The non-transitory computer-readable storage medium of claim 9, wherein in response to the verification result compliance, the one or more processors are further configured to:
a release message is generated by an output device to prompt compliance of the analysis result and the verification result.
12. The non-transitory computer readable storage medium of claim 9, wherein step (e) comprises:
generating a testability circuit design netlist according to the adjusted netlist; and
performing the functional mode timing verification using the testability netlist and a functional mode timing constraint file to generate the verification result.
13. The non-transitory computer readable storage medium of claim 9, wherein the one or more processors are further configured to: in response to a functional mode design of the netlist being adjusted, step (a) is performed again.
14. The non-transitory computer readable storage medium of claim 9, wherein step (d) comprises:
an engineering change instruction is used to set the gating logic at the output of the at least one of the plurality of registers.
15. The non-transitory computer readable storage medium of claim 9, wherein a function combination logic is included between the output of the at least one of the plurality of registers and an input of another one of the plurality of registers, and the gating logic is located between the output of the at least one of the plurality of registers and the function combination logic.
16. The non-transitory computer readable storage medium of claim 9, wherein the gating logic comprises an and gate and a not gate in series.
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| CN111950226A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Chip back end design and layout design method, tool, chip and storage medium |
| CN116302721A (en) * | 2021-12-20 | 2023-06-23 | 瑞昱半导体股份有限公司 | Chip design verification system and method and computer readable recording medium |
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| CN116302721A (en) * | 2021-12-20 | 2023-06-23 | 瑞昱半导体股份有限公司 | Chip design verification system and method and computer readable recording medium |
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