CN117556755A

CN117556755A - Static time sequence analysis method and static time sequence analysis system

Info

Publication number: CN117556755A
Application number: CN202210930083.9A
Authority: CN
Inventors: 陈英杰; 余美俪; 罗幼岚
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2024-02-13

Abstract

The invention discloses a static time sequence analysis method and a static time sequence analysis system. The static time sequence analysis method comprises the following steps: obtaining a standard component library file describing a plurality of standard components; performing circuit structure analysis on the standard element library file to find a target sequence element from the standard elements, wherein the target sequence element comprises a logic gate, a selection circuit and a register circuit; executing a logic test program to find pin combinations with non-controllable relationships, and regarding the timing constraints related to the pin combinations in the standard component library file as redundant timing constraints to be removed from the standard component library file so as to generate an optimized standard component library file; and performing static time sequence analysis on the target circuit design according to the optimization standard element library file.

Description

Static time sequence analysis method and static time sequence analysis system

Technical Field

The present invention relates to a static timing analysis method and a static timing analysis system, and more particularly, to a static timing analysis method and a static timing analysis system capable of reducing redundancy timing constraint.

Background

Static timing analysis (Static Timing Analysis, STA) can be used in integrated circuit (Integrated Circuit, IC) mass production to evaluate correct chip operating speed and to confirm whether the chip can be used and mass produced normally. However, the wrong STA will have an impact on chip operation.

For example, when the chip design is modified to meet the timing constraint of the error in the STA, the Performance, power consumption and Area (PPA) of the chip are reduced, which affects the chip competitiveness and wastes more costs for correcting the chip design.

In addition, whether using computer-aided or manual debug methods, it is only possible to determine if any pin relationships result in redundant timing constraints (Redundant Timing Constraint) from the circuit architecture of the input STA, which is time consuming and difficult to find for standard component library files with thousands of circuits.

Disclosure of Invention

The invention aims to solve the technical problem of providing a static time sequence analysis method and a static time sequence analysis system capable of reducing redundant time sequence limitation aiming at the defects of the prior art.

In order to solve the above technical problems, one of the technical solutions adopted in the present invention is to provide a static timing analysis method, which includes: obtaining a standard cell library (standard cell library) file describing a plurality of standard cells, wherein the standard cell library file defines a plurality of timing constraints (timing constraints) associated with the standard cells; performing circuit structure analysis (Topology Mapping) on the standard component library file to find at least one target sequential component from the standard components, wherein the at least one target sequential component comprises a logic gate, a selection circuit and a register circuit which are sequentially connected, the logic gate is provided with a plurality of first input ends, and the selection circuit is provided with a selection end; executing a logic test procedure for each of the at least one target sequence element to find out at least one pin combination having a Non-controllable relationship between the first input terminals and the selection terminal; regarding the timing constraints associated with the at least one pin combination in the standard component library file as redundant timing constraints according to the at least one pin combination, and removing the redundant timing constraints from the standard component library file to generate an optimized standard component library file; and performing a static timing analysis on a target circuit design according to the optimization standard component library file to obtain data of a critical path of the target circuit design.

In order to solve the above-mentioned problems, another technical solution adopted by the present invention is to provide a static timing analysis system for integrated circuit layout, which includes a memory and a processor. The memory is configured to store a plurality of computer-executable instructions. The processor is electrically coupled to the memory and configured to obtain and execute the computer-executable instructions to perform a static timing analysis method comprising: obtaining a standard cell library (standard cell library) file describing a plurality of standard cells, wherein the standard cell library file defines a plurality of timing constraints (timing constraints) associated with the standard cells; performing circuit structure analysis (Topology Mapping) on the standard component library file to find at least one target sequential component from the standard components, wherein the at least one target sequential component comprises a logic gate, a selection circuit and a register circuit which are sequentially connected, the logic gate is provided with a plurality of first input ends, and the selection circuit is provided with a selection end; executing a logic test procedure for each of the at least one target sequence element to find out at least one pin combination having a Non-controllable relationship between the first input terminals and the selection terminal; regarding the timing constraints associated with the at least one pin combination in the standard component library file as redundant timing constraints according to the at least one pin combination, and removing the redundant timing constraints from the standard component library file to generate an optimized standard component library file; and performing a static timing analysis on a target circuit design according to the optimization standard component library file to obtain data of a critical path of the target circuit design.

The static time sequence analysis method and the static time sequence analysis system provided by the invention have the beneficial effects that the circuit elements which need to be corrected due to the redundant time sequence limitation in the prior circuit design can be effectively found, so that the time course of debugging and repeatedly modifying the circuit is reduced, the development time course can be accelerated, and the method and the system have high reliability and high efficiency.

In addition, performance-Power-Area (PPA) degradation due to modification for redundancy timing constraint can be avoided, and cost required for modifying chip design can be avoided.

On the other hand, the optimized standard component library obtained after removing the redundant time sequence limitation can be provided for all circuit designs using the same standard component library to be reused, so that the data has reusability.

For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the invention.

Drawings

FIG. 1 is a functional block diagram of a static timing analysis system according to an embodiment of the present invention.

Fig. 2 is a flowchart of a static timing analysis method according to an embodiment of the invention.

FIG. 3 is a functional block diagram of a target sequential element according to an embodiment of the invention.

FIG. 4 is a flow chart of a logic test procedure according to an embodiment of the present invention.

Symbol description

1: static time sequence analysis system

10: memory device

100: computer readable instructions

101: standard component library archive

102: logic test program

103: static time sequence analysis tool

104: time sequence analysis result

105: circuit design description file

11: processor and method for controlling the same

12: network element

13: memory cell

14: input/output interface

3: target sequence element

30: logic gate (logic gate)

300: a first output end

301. 302, …, 30n: a first input end

32: selection circuit

321: a second input terminal

322: a third input end

323: a second output end

324: selection terminal

34: register circuit

341: fourth input terminal

342: clock terminal

out: an output terminal

CK: clock signal

SE: selection signal

SI: scanning signal

Q: output signal

Detailed Description

The following specific embodiments are presented to illustrate the embodiments of the present invention related to a static timing analysis method and a static timing analysis system, and those skilled in the art will be able to understand the advantages and effects of the present invention from the disclosure herein. The invention is capable of other and different embodiments and its several details are capable of modification and variation in various respects, all from the point of view and application, all without departing from the spirit of the present invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention. In addition, the term "or" as used herein shall include any one or combination of more of the associated listed items as the case may be.

FIG. 1 is a functional block diagram of a static timing analysis system according to an embodiment of the invention. Referring to fig. 1, an embodiment of the invention provides a static timing analysis system 1, which includes a memory 10, a processor 11, a network unit 12, a storage unit 13, and an input/output interface 14. The elements described above may communicate with each other via, for example, but not limited to, bus 15.

Memory 10 is any storage device that may be used to store data, such as, but not limited to, random access memory (random access memory; RAM), read Only Memory (ROM), flash memory, hard disk, or other storage device that may be used to store data. The memory 10 is configured to store at least a plurality of computer readable instructions 100. In one embodiment, the memory 10 may also be used to store temporary data generated during operation of the processor 11.

The processor 11 is electrically coupled to the memory 10 and configured to access the computer readable instructions 100 from the memory 10 to perform the steps of the static timing analysis method as described below.

Wherein the network element 12 is configured to access the network under control of the processor 11. The storage unit 13 may be, for example, but is not limited to, a magnetic disk or an optical disk, for storing data or instructions under the control of the processor 11. The input/output unit 14 is operable by a user to communicate with the processor 11 for inputting and outputting data.

FIG. 2 is a flow chart of a static timing analysis method according to an embodiment of the invention. Fig. 2 provides a static timing analysis method, which can be applied to the static timing analysis system 1 shown in fig. 1, or implemented by other hardware elements such as databases, general processors, computers, servers, or other unique hardware devices with specific logic circuits or devices with specific functions, such as integrating program codes and processors/chips into unique hardware. In more detail, the static timing analysis method can be implemented using a computer program to control the elements of the static timing analysis system 1. The computer program may be stored in a non-transitory computer readable recording medium, such as a rom, a flash memory, a floppy disk, a hard disk, an optical disk, a usb disk, a magnetic tape, a database accessible by a network, or a computer readable recording medium having the same functions as those of ordinary skill.

Referring to fig. 2, an embodiment of the invention provides a margin correction method for static timing analysis, which includes the following steps:

step S20: a standard cell library (standard cell library) file describing a plurality of standard cells is obtained. The standard cell library file 101 may be stored in the memory 10, and is used to define a plurality of timing constraints (timing constraints) associated with the standard cells.

In detail, standard components in the standard component library can be divided into two major classes, one class is used to form circuits (such as AND, OR, etc.), AND the other class is used as auxiliary functions in the Physical layout (Physical layout) of the chip. In the circuit design process, the standard component library provides information necessary for users and integrated circuit design automation software, and the general standard component library comprises information such as Physical layout (Physical layout), logic (Logic), timing (Timing), power (Power) and the like. The timing information of the standard Cell library further includes a Cell Delay (Timing Constraint) and a timing constraint.

To ensure that the device is properly functioning, the input signal to the Sequential Cell must remain stable for a period of time. The time required to maintain stability is dictated by timing constraints, and timing constraints will play an important role in static timing analysis (Static Timing Analysis).

Step S21: a circuit structure analysis (Topology Mapping) is performed on the library file to find at least one target sequence element from the standard elements.

In detail, this step is to find out the target sequential element with specific characteristics by means of circuit inspection, such as register circuit with multi-terminal input. Such register circuits are chosen because some pins in their circuit architecture may have a Non-controllable relationship with each other, and these pins in turn correspond to a partially redundant timing constraint that may exist.

Reference may further be made to fig. 3, which is a functional block diagram of a target sequential element of an embodiment of the present invention. As shown in fig. 3, the target sequential element 3 mentioned in the present embodiment includes a logic gate 30, a selection circuit 32, and a register circuit 34 connected in sequence. The logic gate 30 has first input terminals 301 to 30n and a first output terminal 300, the selection circuit 32 has a second input terminal 321, a third input terminal 322, a second output terminal 323 and a selection terminal 324, and the register circuit 34 has a fourth input terminal 341, a clock terminal 342 and an output terminal out.

As shown in fig. 3, the first output terminal 300 is connected to the second input terminal 321, the third input terminal 322 is connected to the scan signal SI, the selection terminal 324 of the selection circuit 32 is connected to a selection signal SE, and the clock terminal 342 of the register circuit 34 is connected to the clock signal CK.

In the embodiment of fig. 3, the register circuit 34 is a flip-flop (FF), the selection circuit 32 is a multiplexer (mux), and the logic gate 30 is a NAND gate (NAND gate). The foregoing is merely exemplary and the present invention is not limited thereto. The logic gate 30 may also be, for example, an AND gate (AND gate), an OR gate (OR gate), a NOT gate (NOT gate), a NOR gate (NOT gate) or an XOR NOT gate (XOR gate) that implements other digital logic.

In addition, so-called circuit structure analysis (Topology Mapping) is to first find a Physical layout (Physical layout) file from a Standard component library file, for example, a Verilog file describing signal connection relationships between individual Standard components (Standard cells) using a circuit description language netlist (Verilog's net list), and then find a circuit component (or module) name, a related description of signals, signal directions and pins related to the circuit component from the file, so as to distinguish the target sequence component 3 having the logic gate 30, the selection circuit 32 and the register circuit 34 from the circuit architecture of the Standard components.

Step S22: for each of at least one target sequential element, a logic test procedure is performed to find out at least one pin combination having a Non-controllable relationship between the first input terminals and the selection circuit. In some embodiments, the logic test program 102 may be implemented in software, such as by a computer program, and may be stored in the memory 10.

Reference may further be made to FIG. 4, which is a flow chart of a logic test procedure according to an embodiment of the present invention. Wherein the logic test program comprises the following steps:

step S220: it is determined whether a logical relationship between each of the first inputs and the select terminal results in the output of the register circuit being inactive.

In this step, a test signal set is inputted to the first input terminals 301 to 30n and the selection terminal 324 in an analog manner, and it is determined whether the output signal Q of the output terminal out of the register circuit 34 is changed. In an alternative embodiment, the circuit architecture of at least one target sequential element may be directly determined, and a manner of inputting a test signal set in an analog manner may be omitted, which is not limited thereto.

It should be noted that, in the embodiment of fig. 3, when the selection signal SE is at the first level, for example, the high level, the selection circuit 32 may select the second input terminal 321 to output the signal received by the second input terminal 321 to the second output terminal 321. When the selection signal SE is at the second level, for example, at the low level, the selection circuit 32 selects the third input terminal 322 to output the scan signal SI received by the third input terminal 321 to the second output terminal 321. However, the present invention is not limited thereto, and in other embodiments, the first level may be a low level, and the second level may be a high level.

Therefore, when the select signal SE is at the second level, no change is generated on the output signal Q of the output terminal out no matter what signal combination is inputted to the first input terminals 301 to 30n, and the output signal Q is only related to the scan signal SI. In other words, there is a non-controllable relationship between the first input terminal (301, 302, …, or 30 n) and the selection terminal 324.

In response to determining that the output out of the register circuit 34 is inactive, the logic test procedure proceeds to step S221: judging that the corresponding first input end and the selection end have a non-mutually controllable relationship to be used as one of at least one pin combination, and returning to the step S220 to judge the next input end. For example, when the select signal SE of the select terminal 324 is at a low level, the first input terminal 301 and the select terminal 324 are pin combinations having a non-controllable relationship with each other.

In response to determining that the output out of the register circuit 34 is changed, the logic test procedure proceeds to step S222: judging that the corresponding input end and the selection end have no non-controllable relation, returning to step S220 to judge the next input end.

Step S23: and regarding the timing constraints related to the at least one pin combination in the standard component library file as redundant timing constraints according to the at least one pin combination, and removing the redundant timing constraints from the standard component library file to generate an optimized standard component library file.

For example, when the select signal SE at the select terminal 324 is low, the timing constraints associated with the first input terminal 301 and the select terminal 324 are considered as removable redundant timing constraints, and the standard cell library file 101 can be modified accordingly.

Step S24: and performing static time sequence analysis on the target circuit design according to the optimization standard element library file so as to obtain the data of the critical path of the target circuit design.

It will be appreciated by those skilled in the art that static timing analysis is a workflow for calculating, predicting the timing of a digital circuit during a circuit design process to measure the delay of the circuit at different stages of operation and to test the ability of the circuit to operate at a specified rate.

For example, in the embodiment of the present invention, the target circuit design may be described by the circuit design description file 105, and the target circuit design may include a plurality of signal transmission paths, and after performing static timing analysis (for example, the processor 11 performs the static timing analysis tool 103 and analyzes the target circuit according to the optimized standard component library file 101), the path that causes the maximum signal transmission delay in the signal transmission paths is regarded as a critical path. In this step, the relevant information of the critical path is obtained by simulation as the timing analysis result 104, and may be stored in the memory 10.

Advantageous effects of the embodiment

The above disclosure is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention, so that all equivalent technical changes made by the application of the specification and the drawings of the present invention are included in the claims of the present invention.

Claims

1. A static timing analysis method, comprising:

obtaining a standard component library file describing a plurality of standard components, wherein the standard component library file defines a plurality of timing constraints associated with the plurality of standard components;

performing circuit structure analysis on the standard element library file to find at least one target sequential element from the standard elements, wherein the at least one target sequential element comprises a logic gate, a selection circuit and a register circuit which are connected in sequence, the logic gate is provided with a plurality of first input ends, and the selection circuit is provided with a selection end;

executing a logic test program for each of the at least one target sequence element to find out at least one pin combination having a non-controllable relationship between the plurality of first input ends and the selection end;

regarding the plurality of timing constraints associated with the at least one pin combination in the standard component library file as redundant timing constraints according to the at least one pin combination, and removing the redundant timing constraints from the standard component library file to generate an optimized standard component library file; and

and performing a static time sequence analysis on a target circuit design according to the optimization standard element library file to obtain data of a critical path of the target circuit design.

2. The method of claim 1, wherein the logic test procedure includes determining whether a logic relationship between each of the plurality of first inputs and the select terminal causes an output of the register circuit to be inactive.

3. The method of claim 2, wherein in response to determining that the output of the register circuit is inactive, determining that the non-controllable relationship exists between the corresponding first input and the select terminal as one of the at least one pin combination.

4. The method of claim 2, wherein the logic test program further comprises inputting a set of test signals to the plurality of first inputs and the select terminal, and determining whether an output signal of the output terminal of the register circuit is changed.

5. The static timing analysis method as set forth in claim 2, wherein the logic gate further has a first output terminal, the selection circuit further has a second input terminal, a third input terminal and a second output terminal, the register circuit has a fourth input terminal and a clock terminal, the first output terminal is connected to the second input terminal, the selection terminal is connected to a selection signal, the second output terminal is connected to the fourth input terminal, and the clock terminal is connected to a clock signal.

6. The method of claim 5, wherein the selection circuit selects the second input terminal when the selection signal is at a first level, and selects the third input terminal when the selection signal is at a second level.

7. The method of claim 6, wherein the non-controllable relationship exists between the plurality of first inputs and the select terminal when the select signal is at the second level.

8. The method of claim 1, wherein the register circuit is a flip-flop and the selection circuit is a multiplexer.

9. A static timing analysis system for an integrated circuit layout, comprising:

a memory configured to store a plurality of computer executable instructions; and

the processor is electrically coupled to the memory and configured to acquire and execute the plurality of computer-executable instructions to perform a static timing analysis method, the static timing analysis method comprising:

10. The static timing analysis system according to claim 9, wherein the logic test procedure includes determining whether a logic relationship between each of the plurality of first inputs and the select terminal causes an output of the register circuit to be inactive.