CN113627121A - Chip design data processing method, electronic device and computer readable medium - Google Patents
Chip design data processing method, electronic device and computer readable medium Download PDFInfo
- Publication number
- CN113627121A CN113627121A CN202110720665.XA CN202110720665A CN113627121A CN 113627121 A CN113627121 A CN 113627121A CN 202110720665 A CN202110720665 A CN 202110720665A CN 113627121 A CN113627121 A CN 113627121A
- Authority
- CN
- China
- Prior art keywords
- design program
- conductive pattern
- source data
- chip
- chip substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a processing method of chip design data, electronic equipment and a computer readable medium, wherein the method comprises the steps of configuring a first process parameter of a chip substrate layout design program, wherein the first process parameter is adapted to a second process parameter of a PCB (printed circuit board) level design program; executing a chip substrate layout design program based on a first process parameter to obtain conductive pattern source data; and performing parameter character processing adapted to a PCB (printed Circuit Board) level design program on the conductive pattern source data to generate and output processed conductive pattern source data. The invention can carry out the chip packaging substrate design and the BALL MAP design in the chip substrate layout design program, and can realize the data multiplexing between the chip substrate layout design program and the PCB board level design program, thereby improving the efficiency and the accuracy of the whole chip substrate design.
Description
Technical Field
The present invention relates to the field of chip development technologies, and in particular, to a method for processing chip design data, an electronic device, and a computer-readable medium.
Background
The Substrate (SUB) for packaging chip can provide the effects of electric connection, protection, support, heat dissipation, assembly and the like for the chip, so as to realize the purposes of multi-pin, reduction of the volume of the packaged product, improvement of the electric performance and the heat dissipation, and ultrahigh density or multi-chip modularization.
At present, chip package substrate design and BALL MAP (distribution diagram of chip signal pins) design belong to different design teams, the chip package substrate design is carried out in a chip substrate layout design program, and because platform project design needs to be carried out in a PCB board level design program, the BALL MAP design also needs to be carried out in the PCB board level design program. Therefore, the design parameters need to be exported and imported for multiple times, and PCB (printed circuit board) board level packaging needs to be regenerated to support the placement of the BALL MAP and the Fan Out design (referring to the punching wiring design of the chip).
However, by adopting the current design mode, the scheme and the parameters which need to be adjusted about the PCB board level packaging BALL MAP design can not be fed back to a chip substrate design engineer in time, because the scheme and the parameters are not on the same layout design platform, the communication efficiency and the communication accuracy are also reduced, risk factors which need to be judged manually and subjectively are increased, and the chip substrate design efficiency and the accuracy are low.
Disclosure of Invention
The invention aims to overcome the defects of low efficiency and accuracy of chip substrate design in the prior art, and provides a chip design data processing method, electronic equipment and a computer readable medium.
The invention solves the technical problems through the following technical scheme:
according to an embodiment of the present invention, a method for processing chip design data is provided, including:
configuring a first process parameter of a chip substrate layout design program, wherein the first process parameter is adapted to a second process parameter of a PCB (printed circuit board) level design program;
executing the chip substrate layout design program based on the first process parameter to obtain conductive pattern source data; and
and performing parameter character processing adapted to the PCB board level design program on the conductive pattern source data to generate and output processed conductive pattern source data.
Optionally, the first process parameter includes first stack information;
the step of configuring the first process parameter of the chip substrate layout design program comprises the following steps:
configuring first lamination information of a chip substrate layout design program so as to adapt the first lamination information to second lamination information of a PCB (printed circuit board) level design program.
Optionally, the step of executing the chip substrate layout design program includes:
and executing PCB board level packaging BALL MAP arrangement in the chip substrate layout design program.
Optionally, the step of executing the chip substrate layout design program to obtain source data of the conductive pattern further includes:
and executing PCB board level packaging BALL MAP arrangement and Fan Out design in the chip substrate layout design program to obtain the source data of the conductive pattern.
Optionally, the method further comprises:
receiving chip interface data information and IP layout planning information;
and executing the chip substrate layout design program according to the chip interface data information and the IP (semiconductor IP core (intellectual property core)) layout planning information based on the first process parameter so as to obtain conductive pattern source data.
Optionally, the step of performing parameter character processing adapted to the PCB board level design program on the conductive pattern source data to generate processed conductive pattern source data includes:
screening a first predefined parameter number from the conductive pattern source data;
converting the first predefined character to a second predefined parameter character adapted to the PCB board level design program to generate character converted conductive graphics source data.
Optionally, the first predefined parameter character includes a character for characterizing a predefined parameter name in the chip substrate layout design program.
Optionally, the method further comprises:
outputting the processed conductive pattern source data to a storage area running the PCB level design program so as to reuse the processed conductive pattern source data when the PCB level design program is executed.
According to another embodiment of the present invention, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the method for processing chip design data as described above is implemented.
According to another embodiment of the present invention, there is provided a computer-readable medium having stored thereon computer instructions which, when executed by a processor, implement the method of processing chip design data as described above.
On the basis of the common knowledge in the field, the preferred conditions can be combined randomly to obtain the preferred embodiments of the invention.
The positive progress effects of the invention are as follows:
according to the invention, the chip packaging substrate design and the BALL MAP design can be carried out in the chip substrate layout design program, the data multiplexing between the chip substrate layout design program and the PCB level design program can be realized, the platform closed loop is effectively realized, the quality risk factors caused by unnecessary external manual actions are eliminated, the communication efficiency and precision are improved, and the efficiency and the accuracy of the whole chip substrate design are improved.
Drawings
The features and advantages of the present disclosure will be better understood upon reading the detailed description of embodiments of the disclosure in conjunction with the following drawings. In the drawings, components are not necessarily drawn to scale, and components having similar relative characteristics or features may have the same or similar reference numerals.
Fig. 1 is a flowchart illustrating a method for processing chip design data according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram of a substrate portion of a chip package.
Fig. 3 is a schematic structural diagram of an electronic device implementing a method for processing chip design data according to another embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
In order to overcome the above existing defects, the present embodiment provides a method for processing chip design data, including the following steps: configuring a first process parameter of a chip substrate layout design program, wherein the first process parameter is adapted to a second process parameter of a PCB (printed circuit board) level design program; executing a chip substrate layout design program based on a first process parameter to obtain conductive pattern source data; and performing parameter character processing adapted to a PCB (printed Circuit Board) level design program on the conductive pattern source data to generate and output processed conductive pattern source data.
Referring to fig. 2, fig. 2 mainly shows a chip solder ball, a substrate, a BGA (ball grid array) solder ball, a PCB, and so on, and this embodiment mainly describes a co-designed portion of the substrate, the BGA solder ball, and the PCB.
In the design of a large-scale high-integration chip, the embodiment can effectively improve the collaborative design efficiency of the chip packaging substrate and the BALL MAP and simultaneously reduce the complete interactive forming risk of the collaborative design parameters, effectively realize the closed loop of a platform, eliminate the quality risk factors caused by unnecessary external manual actions, and improve the communication efficiency and precision, thereby improving the design efficiency and accuracy of the whole chip substrate and reducing the design accuracy.
Specifically, as an alternative embodiment, as shown in fig. 1, the method for processing chip design data provided in this embodiment mainly includes the following steps:
In this step, a first process parameter of the chip substrate layout design program is configured, wherein the first process parameter is adapted to a second process parameter of the PCB board level design program.
Specifically, as an alternative embodiment, the first process parameter may include first stack information, that is, stack information of the chip substrate.
In this step, first overlay information of the chip substrate layout design program is configured to adapt the first overlay information to second overlay information of the PCB board level design program, where the second overlay information is overlay information of the PCB board, that is, overlay information of the chip substrate is changed to adapt to the overlay information of the PCB board. Because the number of chip platforms is large, the lamination information of the chip substrate and the PCB level is different, and therefore the lamination information of the PCB is adapted by changing the lamination information of the chip substrate.
Of course, the present embodiment does not specifically limit the types of the process parameters, and can be selected and adjusted according to actual requirements.
And 102, executing a chip substrate layout design program to acquire source data of the conductive pattern.
In this step, based on the configured first process parameter, a chip substrate layout design program is executed according to the received chip interface data information and the IP layout planning information to obtain conductive pattern source data.
Specifically, as an optional implementation manner, in this step, the PCB board level package BALL MAP layout and Fan Out design in the chip substrate layout design program are executed to obtain the source data of the conductive pattern.
In this embodiment, the stage of BALL MAP layout and Fan Out design is directly transferred to the chip substrate layout design program suite, and the stage of BALL MAP layout and Fan Out design directly and synchronously participates in the BALL MAP layout and Fan Out design from the initial substrate design drawing without starting the PCB board level design program suite.
And 103, performing parameter character conversion processing on the conductive pattern source data to generate processed conductive pattern source data.
In this step, the conductive pattern source data is subjected to parameter character processing adapted to the PCB board level design program to generate processed conductive pattern source data.
As an optional implementation manner, in this step, a first predefined parameter character is screened from the conductive pattern source data, where the first predefined parameter character includes a character used for representing a predefined parameter name in a chip substrate layout design program; the first predefined character is converted into a second predefined parameter character adapted to a PCB board level design program to generate character converted conductive pattern source data.
Specifically, in this embodiment, in order to implement the rapid normalized configuration of the design environment, some programming language platforms and open-source secondary development tools provided by design program manufacturers are used to write a program script for executing the steps of the processing method provided by this embodiment, so as to implement one-key configuration in place, and only one-key start is required, and batch conversion of the parameter characters can be implemented without manual setting each time.
And 104, outputting the processed conductive pattern source data to a storage area for running a PCB (printed circuit board) level design program.
In this step, the processed part of the conductive pattern source data (i.e., the data required by the PCB board level design program) is output to a storage area where the PCB board level design program is run, so that the processed conductive pattern source data is reused when the PCB board level design program is executed, thereby achieving safe and fast reuse to the platform project.
The method for processing chip design data provided by the embodiment mainly has the following beneficial effects:
1. the steps of the whole chip design flow are greatly simplified, so that the design efficiency is improved;
2. the simulation process parameters are not extracted separately from a chip substrate layout design program and a PCB design program, so that the labor cost and the project subject occupation progress are effectively saved, and the network name is not required to be manually filled in the PCB design program in a comparison manner, so that the quality risk factor of the link is effectively eliminated;
3. the chip packaging substrate design and the BALL MAP design can be carried out in the chip substrate layout design program, data multiplexing between the chip substrate layout design program and the PCB board level design program can be realized, the platform closed loop is effectively realized, quality risk factors caused by unnecessary external manual actions are eliminated, the communication efficiency and precision are improved, and the efficiency and accuracy of the whole chip substrate design are improved.
Fig. 3 is a schematic structural diagram of an electronic device according to this embodiment. The electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the processing method of the chip design data as in the above embodiments when executing the program. The electronic device 30 shown in fig. 3 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiment of the present invention.
As shown in fig. 3, the electronic device 30 may be embodied in the form of a general purpose computing device, which may be, for example, a server device. The components of the electronic device 30 may include, but are not limited to: the at least one processor 31, the at least one memory 32, and a bus 33 connecting the various system components (including the memory 32 and the processor 31).
The bus 33 includes a data bus, an address bus, and a control bus.
The memory 32 may include volatile memory, such as Random Access Memory (RAM)321 and/or cache memory 322, and may further include Read Only Memory (ROM) 323.
The processor 31 executes the computer program stored in the memory 32, thereby executing various functional applications and data processing, such as the processing method of the chip design data in the above embodiments of the present invention.
The electronic device 30 may also communicate with one or more external devices 34 (e.g., keyboard, pointing device, etc.). Such communication may be through input/output (I/O) interfaces 35. Also, model-generating device 30 may also communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet) via network adapter 36. As shown in FIG. 3, network adapter 36 communicates with the other modules of model-generating device 30 via bus 33. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the model-generating device 30, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.
It should be noted that although in the above detailed description several units/modules or sub-units/modules of the electronic device are mentioned, such a division is merely exemplary and not mandatory. Indeed, the features and functionality of two or more of the units/modules described above may be embodied in one unit/module according to embodiments of the invention. Conversely, the features and functions of one unit/module described above may be further divided into embodiments by a plurality of units/modules.
The present embodiment also provides a computer-readable storage medium on which a computer program is stored, which when executed by a processor implements the steps in the processing method of chip design data as in the above embodiments.
More specific examples, among others, that the readable storage medium may employ may include, but are not limited to: a portable disk, a hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.
In a possible embodiment, the invention may also be implemented in the form of a program product comprising program code for causing a terminal device to perform the steps of the processing method implementing the chip design data as in the above embodiments, when the program product is executed on the terminal device.
Where program code for carrying out the invention is written in any combination of one or more programming languages, the program code may execute entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device and partly on a remote device or entirely on the remote device.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (10)
1. A method for processing chip design data, comprising:
configuring a first process parameter of a chip substrate layout design program, wherein the first process parameter is adapted to a second process parameter of a PCB (printed circuit board) level design program;
executing the chip substrate layout design program based on the first process parameter to obtain conductive pattern source data; and
and performing parameter character processing adapted to the PCB board level design program on the conductive pattern source data to generate and output processed conductive pattern source data.
2. The process of claim 1, wherein the first process parameter comprises first stack information;
the step of configuring the first process parameter of the chip substrate layout design program comprises the following steps:
configuring first lamination information of a chip substrate layout design program so as to adapt the first lamination information to second lamination information of a PCB (printed circuit board) level design program.
3. The process of claim 1, wherein said step of executing said chip substrate layout design program comprises:
and executing PCB board level packaging BALL MAP arrangement in the chip substrate layout design program.
4. The process of claim 3, wherein said step of executing said chip substrate layout design program to obtain conductive pattern source data, further comprises:
and executing PCB board level packaging BALL MAP arrangement and Fan Out design in the chip substrate layout design program to obtain the source data of the conductive pattern.
5. The processing method of claim 1, further comprising:
receiving chip interface data information and IP layout planning information;
and executing the chip substrate layout design program according to the chip interface data information and the IP layout planning information based on the first process parameter so as to obtain the source data of the conductive pattern.
6. The process of claim 1, wherein said step of subjecting said conductive pattern source data to parametric character processing adapted to said PCB board level design program to generate processed conductive pattern source data comprises:
screening a first predefined parameter number from the conductive pattern source data;
converting the first predefined character to a second predefined parameter character adapted to the PCB board level design program to generate character converted conductive graphics source data.
7. The process of claim 6, wherein the first predefined parameter character comprises a character used to characterize a predefined parameter name in the chip substrate layout design program.
8. The processing method of claim 1, further comprising:
outputting the processed conductive pattern source data to a storage area running the PCB level design program so as to reuse the processed conductive pattern source data when the PCB level design program is executed.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method for processing chip design data according to any one of claims 1 to 8 when executing the computer program.
10. A computer-readable medium, on which computer instructions are stored, which, when executed by a processor, implement a method of processing chip design data according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110720665.XA CN113627121B (en) | 2021-06-28 | 2021-06-28 | Chip design data processing method, electronic device and computer readable medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110720665.XA CN113627121B (en) | 2021-06-28 | 2021-06-28 | Chip design data processing method, electronic device and computer readable medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113627121A true CN113627121A (en) | 2021-11-09 |
| CN113627121B CN113627121B (en) | 2023-01-20 |
Family
ID=78378574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110720665.XA Active CN113627121B (en) | 2021-06-28 | 2021-06-28 | Chip design data processing method, electronic device and computer readable medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113627121B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114330212A (en) * | 2022-02-28 | 2022-04-12 | 湖北芯擎科技有限公司 | Chip pin arrangement method and device, computer equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610585A (en) * | 2011-12-19 | 2012-07-25 | 佛山市蓝箭电子有限公司 | Lead frame for silicon chip encapsulation, encapsulation method and formed electronic element |
| CN110197019A (en) * | 2019-05-20 | 2019-09-03 | 上海望友信息科技有限公司 | Process design method, system, medium and equipment based on system encapsulation technology |
| CN111339724A (en) * | 2020-02-21 | 2020-06-26 | 全芯智造技术有限公司 | Method, apparatus and storage medium for generating data processing model and layout |
| CN111950226A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Chip back end design and layout design method, tool, chip and storage medium |
-
2021
- 2021-06-28 CN CN202110720665.XA patent/CN113627121B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610585A (en) * | 2011-12-19 | 2012-07-25 | 佛山市蓝箭电子有限公司 | Lead frame for silicon chip encapsulation, encapsulation method and formed electronic element |
| CN110197019A (en) * | 2019-05-20 | 2019-09-03 | 上海望友信息科技有限公司 | Process design method, system, medium and equipment based on system encapsulation technology |
| CN111339724A (en) * | 2020-02-21 | 2020-06-26 | 全芯智造技术有限公司 | Method, apparatus and storage medium for generating data processing model and layout |
| CN111950226A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Chip back end design and layout design method, tool, chip and storage medium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114330212A (en) * | 2022-02-28 | 2022-04-12 | 湖北芯擎科技有限公司 | Chip pin arrangement method and device, computer equipment and storage medium |
| CN114330212B (en) * | 2022-02-28 | 2022-06-21 | 湖北芯擎科技有限公司 | Chip pin arrangement method and device, computer equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113627121B (en) | 2023-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106940428B (en) | Chip verification method, device and system | |
| US7039892B2 (en) | Systems and methods for ensuring correct connectivity between circuit designs | |
| CN107220036A (en) | A kind of visual development method and system of component and template | |
| US20210406443A1 (en) | Verification platform for system on chip and verification method thereof | |
| CN113627121B (en) | Chip design data processing method, electronic device and computer readable medium | |
| CN112034947A (en) | Backboard design system for enhancing server hard disk compatibility and parameter tuning method | |
| US20110154277A1 (en) | Method and apparatus for generating substrate layout | |
| CN114895915A (en) | Layout code automatic generation method, system, equipment and computer readable storage medium | |
| CN114117985B (en) | Intelligent verification method, system, medium and terminal equipment for integrated operational amplifier | |
| CN113466733A (en) | Power performance testing method and device, electronic equipment and storage medium | |
| CN101364174A (en) | Test file generation system and method for printed circuit board | |
| CN111400169A (en) | Method and system for automatically generating netlist file for testing software and hardware | |
| US8464200B1 (en) | Thermal relief optimization | |
| CN111427582B (en) | RTL code management method, device, equipment and computer readable storage medium | |
| US20130304413A1 (en) | Computing device and method for testing electromagnetic compatiblity of printed circuit board | |
| CN116011368A (en) | Method for automatically generating script through EDA layout | |
| CN113948950B (en) | Communication method and device suitable for high-power fiber laser control system | |
| CN109783134B (en) | Front-end page configuration method and device and electronic equipment | |
| CN107092716A (en) | The implementation method and device of a kind of Electronic Design | |
| CN112446182A (en) | Method and equipment for optimizing signal integrity | |
| JP4817121B2 (en) | Device test system, server, device tester, and pattern data setting method | |
| CN112749526A (en) | Power rail design method, apparatus and non-transitory computer readable medium thereof | |
| CN114896919B (en) | FPGA-based integrated circuit prototype verification system and method | |
| US11036909B1 (en) | Method and apparatus for designing multi-board electrical and electronic circuits | |
| WO2022266881A1 (en) | Printed circuit board pin field signal routing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |