WO2004046975A1

WO2004046975A1 - Electronic circuit design timing improvement method, program, and apparatus

Info

Publication number: WO2004046975A1
Application number: PCT/JP2002/012001
Authority: WO
Inventors: Hiroyuki Sugiyama; Hiroshi Ikeda
Original assignee: Fujitsu Limited
Priority date: 2002-11-18
Filing date: 2002-11-18
Publication date: 2004-06-03
Also published as: JPWO2004046975A1

Abstract

It is possible to improve the electronic circuit design timing after cell arrangement and wiring are complete. Firstly, slack information indicating a delay shortage and delay over obtained from the timing verification result in the electronic circuit design is input. Next, attention is paid on the slack information on a pin of a cell on a route not satisfying the timing constrain and search is made for an object candidate, i.e., such a cell that after replacement of the cell, another route passing through the replacing cell will not cause a timing error. The cell searched as the object candidate is replaced by a cell satisfying the timing constrain, thereby eliminating the timing error. Furthermore, nets on the error path are narrowed down by a plurality of specification conditions and are searched as a candidate, thereby thickening the line and improving the timing.

Description

Method and program for improving timing of electronic circuit design

The present invention relates to a method, a program, and an apparatus for improving timing of an electronic circuit design of an LSI or VLSI automatically designed by computer assistance, and particularly to an electronic circuit design that has been subjected to logic design, cell arrangement and wiring processing. The present invention relates to a method, a program, and a device for improving timing of electronic circuit design for checking and improving timing errors. book

Background art

Conventionally, in automatic electronic circuit design with LSI or VLSI computer assistance, timing analysis of the automatically created electronic circuit design is performed after the logic design, cell placement, and wiring processing are completed, and the analysis results are analyzed. ing.

In analyzing the timing analysis results, if a path that does not satisfy the timing conditions, for example, a path that causes a racing error or an over-delay error, is found, the error cause in the cells existing on the path is determined. It is necessary to identify the defective cell and replace the cell to meet the timing requirements. However, in the analysis of the conventional timing analysis results, it is possible to identify the cells existing on the path that does not satisfy the timing conditions, but it is necessary to determine which cell on the path can be replaced to improve the timing. There is a problem of not knowing. For this reason, cells on a path that does not satisfy the timing conditions are randomly selected and exchanged.However, another path passing through the exchanged cell may cause a timing error, and the timing constraint of the entire circuit may be reduced. It was necessary to repeat the trials of cell exchange and timing analysis many times to satisfy this, and there was a problem that the processing load of timing improvement was large and time-consuming. Disclosure of the invention

The present invention utilizes the slack information of cells obtained as a result of timing verification. It is an object of the present invention to provide a timing improvement method, a program, and a device capable of efficiently eliminating a evening-imaging error by specifying and changing a cell / net that does not satisfy the evening-imaging condition.

(Cell optimization)

The present invention relates to a method for improving timing of an electronic circuit design after logic design, cell placement, and wiring processing.

An input step of inputting slack information obtained from a timing verification result in an electronic circuit design by an input unit;

The cell search unit focuses on the slack information at the pins of the cells on the path that does not satisfy the evening-imaging constraint. A cell search step to search for cells that do not occur as replacement candidates;

A cell replacement unit that replaces a cell searched as a replacement candidate with a cell that satisfies a timing constraint,

It is characterized by having.

As described above, the present invention focuses on the slack information of the pins of the cells on the path that does not satisfy the timing constraint, and replaces the cell. The error is improved, and a timing error does not occur in another path through the replaced cell, so that the timing error in the final stage of electronic circuit design can be efficiently improved.

Here, for cell optimization to improve the hold time error included in the racing error,

In the input step, input the slack value, which is the margin value of the setup time check, obtained from the timing verification result in the electronic circuit design, and the slack value, which is the margin value of the hold time check,

In the cell search step, for a path in which a hold time error has occurred due to insufficient delay, a cell having a positive slack value of a setup time check of all pins that is equal to or greater than a predetermined value is searched for as a replacement candidate.

In the cell switching step, cells searched as replacement candidates are replaced with cells having a large delay time. Replace with

In addition, for cell optimization to improve setup time errors included in overdelay errors,

In the input step, enter the slack value, which is the margin value for the setup time check, and the slack value, which is the margin value for the hold time check.

In the cell search step, a cell having a positive slack value of the hold time check of all pins that is equal to or greater than a predetermined value is searched as a replacement candidate for a path that causes a setup time error due to delay over,

The cell switching step is characterized in that cells searched as replacement candidates are replaced with cells having a small delay time.

In addition, the net search step determines the timing error by temporarily calculating the net delay after changing the delay parameter of the cell searched as an exchange candidate to the value of the cell after the exchange, and if no timing error occurs, the exchange candidate is determined. To decide.

By repeating the verification for cells searched as candidates in this way, it is possible to improve only the circuits that are most needed. In addition, by preparing a library of cell parameters with the same logic and different delays for cell replacement verification, delay calculation can be performed without actually replacing cells, and based on the change mac and mouth information output simultaneously. Finally, logic change, cell placement and wiring processing are performed.

(Net thickening part 1)

The input section inputs the slack value, which is the margin value of the hold time check obtained from the timing verification result in the electronic circuit design, and the net search section causes a setup time error due to delay overlap A net search step of searching nets having pins with positive slack values and satisfying a predetermined condition from among nets on the path as thickening candidates; and searching by the thickening unit as thickening candidates. A bolding step to replace the net routing with a bold line with a small delay time;

It is characterized by having. Here, in the net search step, nets whose net wiring length and driver driving capability are equal to or greater than the specified values are searched as nets satisfying the specified conditions as thick line candidates. According to the present invention, in order to improve the setup time error resulting in delay overlap by reducing the delay by thickening the net, according to the present invention, the target net is limited by the wiring length of the net and the driving capability of the driver. As a result, many nets that are not very effective when viewed as a whole path are targeted, resulting in a shortage of wiring channels, and an increase in wiring capacity due to the thicker wiring, resulting in an increase in delay for drivers with small driving capacity. It is possible to eliminate the inconvenience that occurs.

In the net search step, the line capacitance and the line resistance of the nets searched as candidates for thickening are changed to the thickened values, then the net delay is temporarily calculated to determine the setup time error, and errors can be eliminated. The net is determined as a thick line candidate. By repeating the verification on the nets searched as candidates in this way, it is possible to improve only the nets that are most needed. In addition, as a verification of net thickening, by changing the wiring resistance and wiring capacitance of candidate nets to values with thicker lines, delay calculation can be performed without actually thickening the nets and output at the same time Finally, based on the bold net information, logic change, cell placement and wiring processing are performed.

(Net thickening 2),

An input step of inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in an electronic circuit design by an input unit;

A net search step of searching a net satisfying a predetermined condition as a bold line candidate from all nets on the path where a setup time error due to delay over has occurred by a net search unit;

A bolding step in which the bolding unit replaces the wiring of the net searched as a bolding candidate with a bold line having a small delay time;

It is characterized by having.

Here, the net search step is performed from the nets that cause setup time errors. Search for nets whose net wiring length, driver driving capacity, net delay, waveform dullness on the receiver side, and fan count are larger than the specified values as thickening candidates. For this reason, among the paths causing timing errors, the effect of improvement is expected in the selected error path by the specified conditions of the wiring length, driver driving capability, net delay, waveform dullness on the receiver side, and the number of fan bits One possible net can be determined.

In the net search step, a predetermined number of high-order worst paths having a large delay time are selected from nets in which a setup time error has occurred, and the search for a thick line candidate is repeated. For this reason, by thickening the net from the path where the improvement effect is large, the timing error can be improved with the necessary minimum net thickening.

(Program)

The present invention provides a program for improving the timing of electronic circuit design after logic design, cell placement, and wiring processing.

First of all, the program of the present invention that improves evening imaging by cell optimization

An input step of inputting slack information obtained from a timing verification result in an electronic circuit design;

Focusing on slack information at the pins of the cells on the path that does not satisfy the timing constraints, cells that do not cause timing errors on other paths that pass through the replaced cell even if cells are replaced to improve timing are considered as replacement candidates. A cell search step for searching; a cell replacement step for replacing cells searched as replacement candidates with cells satisfying timing constraints;

And execute.

Also, the program of the present invention that improves the timing by thickening the net

An input step of inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in an electronic circuit design;

Of the nets on the path where the setup time error occurs due to the delay over, the net having the pin whose slack value is positive and satisfying the specified condition is specified. A net search step of searching for a set as a thick line candidate,

A bolding step of replacing the wiring of the net searched as a bolding candidate with a bold line having a small delay time;

Is executed.

In addition, the program of the present invention, which is another form of improving evening imitation by thickening the net, has a computer

A net search step of searching, as a bold line candidate, a net satisfying a predetermined condition from all nets on the path where a setup time error due to delay over has occurred;

Is executed. The details of the program of the present invention are basically the same as those of the timing improvement method.

(Equipment)

The present invention provides an apparatus for improving the timing of electronic circuit design after logic design, cell placement, and wiring processing.

First, the device of the present invention, which improves evening timing by cell optimization, comprises an input unit for inputting slack information obtained from a timing verification result in an electronic circuit design, and a pin at a cell pin on a path that does not satisfy timing constraints. Focusing on slack information, even if cells are exchanged to improve evening, a cell search unit that searches for cells that do not cause timing errors on other routes through the exchanged cells as replacement candidates, and a replacement candidate And a cell replacement unit that replaces the searched cell with a cell satisfying the timing constraint.

In addition, the device of the present invention for improving evening imaging by thickening the net has an input unit for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in an electronic circuit design, and a delay overlap. Among the nets on the path that causes the setup time error, there is a pin whose slack value is positive and A net search unit that searches for a net satisfying one specified condition as a thick line candidate, and a thick line unit that replaces a wire of the net searched as a thick line candidate with a thick line having a small delay time. .

In addition, the apparatus of the present invention as another mode for improving evening imaging by thickening the net has an input unit for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in electronic circuit design. From all nets on the path where a setup time error has occurred due to delay overrun, a net search unit that searches nets satisfying the specified conditions as thickening candidates and searches as net thickening candidates And a thick line replacing section for replacing the net wiring with a thick line having a small delay time.

The details of the device of the present invention are basically the same as those of the timing improvement method. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a functional configuration showing an embodiment of the present invention;

FIG. 2 is a flowchart of an electronic circuit design to which the present invention is applied;

FIG. 3 is an explanatory diagram of hardware resources of a computer to which the embodiment of FIG. 1 is applied; FIG. 4 is a block diagram of a cell size optimizing unit of FIG. 2;

Figure 5 is a schematic diagram of a basic cell net generated by electronic circuit design;

Figure 6 is an illustration of the setup time check in the circuit of Figure 5;

Figure 7 is an explanatory diagram of the hold time check in the circuit of Figure 5;

Fig. 8 is an illustration of the electronic circuit and the slack value to which the cell size optimization processing of Fig. 4 is applied;

Figure 9 is an illustration of the calculation method of setup slack value in Figure 8;

FIG. 10 is an explanatory view of the calculation method of the hold slack value in FIG. 8;

FIG. 11 is a flowchart of the cell size optimizing process according to the present invention;

FIG. 12 is a flowchart of the cell size optimization process following FIG. 11;

Figure 13 is a block diagram of the net thickening part in Figure 2;

FIG. 14 is a flowchart of the net thickening process according to the present invention;

FIG. 15 is a flow chart of the net thickening process following FIG. 14; FIG. 16 is a flowchart of another embodiment of the net thickening process according to the present invention; FIG. 17 is a flowchart of the net thickening process following FIG. 16;

FIG. 1 is a block diagram of a functional configuration of an electronic circuit design system to which the timing improvement method of the present invention is applied. In FIG. 1, the electronic circuit design system includes a logic design unit 10, a cell placement unit 11, a wiring processing unit 12, an evening analysis unit 14, and an evening analysis result analysis unit 16. In addition to the above, the present invention further includes a cell size optimizing unit 18 and a net thickening unit 20. For the cell size optimizing unit 18, a cell parameter library 24 and a cell replacement information file 22 are provided. The net thickening unit 20 is provided with a thick net information file 26. Further, the logic design unit 10 is provided with an output file 28 for storing the created electronic circuit design data.

FIG. 2 is a schematic flowchart of a processing procedure in the electronic circuit design system of FIG. In FIG. 2, logic design is performed based on the design information input in step S1, cell placement is performed in step S2, and wiring processing is performed in step S3. These steps S1 to S3 are the basic processing of electronic circuit design usually performed. Next, in step S4, the timing analysis is performed on the created electronic circuit design.After that, the timing analysis result is analyzed in step S5. If a racing error or an over-delay error occurs, According to the present invention, as part of the process associated with the cell arrangement adjustment in step S6, the slack-based cell optimization process in step S7 and the thickening of the net on the worst path in step S8 are performed. Perform processing to improve timing errors. The slack-based cell optimization processing according to the present invention in step S7 is performed by inputting slack information obtained from timing verification results in electronic circuit design, and slack information at a pin of a cell on a path that does not satisfy the timing constraint. Focusing on, if even if a cell is exchanged to improve the evening, if other routes through the exchanged cell do not cause timing errors, this cell is searched for as an exchange candidate and is searched for as an exchange candidate. Replaced cells with cells that satisfy the timing constraints. Specifically, hold evenings where there is insufficient delay A cell candidate to be exchanged is searched for the route causing the error based on slack information, and the searched cell is replaced with a cell having a long delay time. It also searches for a cell as a replacement candidate for a path that causes a setup time error due to delay over, and replaces the searched cell with a cell with a small delay time. On the other hand, in the thickening processing of the net on the worst path in step S8, the slack value, which is the margin value of the hold time check obtained from the timing verification result in the electronic circuit design, is inputted, and the setup due to the delay over time is performed. From the nets on the path causing the time error, search the nets to be bolded to reduce the delay time as candidates for bolding to reduce the delay time, and find the routing of the searched nets with a small delay time. Replace with a bold line. Furthermore, in steps S7 and S8, the cell exchange and the net thickening are performed without changing the cells or making the net thicker, and changing the parameters of the cell and making the net thicker. Provisional calculation of the delay by changing the capacitance and resistance value accompanying the above, checks whether the timing error can be eliminated by cell exchange and net thickening, and if the timing error can be eliminated, replaces the cell or thickens the line. Has been determined as a candidate. In Steps S7 and S8, when the cell replacement candidate and the net thickening candidate are determined, finally, based on the cell change macro information and the thickened net information, Steps S9, S10, S 11 Perform logic design, cell placement and wiring processing in step 1. After performing timing analysis in step S12, analyze the timing analysis result in step S13. If the delay error has not been improved, the series of processing ends. If a timing error is determined in step S14, the process returns to step S6 to adjust the cell arrangement again, and repeats the processing from step S7. The system of the present invention in FIG. 1 is realized by hardware resources of a computer as shown in FIG. 3, for example. In the computer shown in Fig. 3, the CPU 100 has a bus 101 with a RAM 102, a hard disk controller (software) 104, a floppy disk driver (software) 110, and a CD-ROM. Driver (software) 114, mouse controller 118, keyboard controller 122, display controller 126, communication port 130 are connected. The hard disk controller 104 connects the hard disk drive 106 to the electronic circuit of the present invention. The application program that executes the design is spoken.

— At the start-up in the evening, call up the necessary program from the hard disk drive 106, expand it on the RAM 102, and execute it with the CPU 100. A floppy disk drive (hardware) 112 is connected to the floppy disk driver 110, which can read from and write to a floppy disk (R). A CD drive (hardware) 116 is connected to the CD-ROM driver 114 so that data and programs stored in the CD can be read. The mouse controller 118 communicates the input operation of the mouse 120 to the CPU 100. The keyboard controller 122 transmits the input operation of the keyboard 124 to the CPU 100. The display controller 1 26 performs display on the display section 1 28. The communication board 130 uses a communication line 132 including wireless, and communicates with other users and servers via a network such as the Internet.

FIG. 4 is a block diagram of a functional configuration of the cell size optimizing unit 18 of the present invention provided in the electronic circuit design system of FIG. The cell size optimizing unit 18 includes input units 3 and 6, a cell searching unit 38, and a cell replacing unit 40. The input unit 36 inputs slack information obtained from the timing verification result in the electronic circuit design. The cell search unit 38 focuses on the slack information at the pins of the cells on the path that does not satisfy the timing constraint, and even if cells are exchanged to improve timing, other paths that pass through the exchanged cells may have timing errors. The cell is searched as a replacement candidate, provided that it does not wake up. The cell replacement unit 40 replaces the cell searched as a replacement candidate with a cell satisfying the timing constraint. Further, the cell replacement section 40 is provided with a cell parameter overnight library 24 and a cell replacement information file 22 in order to perform a provisional delay calculation for a cell replacement candidate. In such a cell size optimizing unit 18 of the present invention, cell replacement for eliminating a hold time error and cell replacement for eliminating a setup time error are performed using slack information. .

Cell optimization processing to eliminate setup time errors is performed in the following procedure. '

(1) Set adapter obtained from timing verification results in electronic circuit design Enter the slack value, which is the margin for the time check, and the slack value, which is the margin for the hold time check.

(2) For the path in which a setup time error has occurred due to delay over, cells with slack values of the hold time check of all pins that are positive or more than a predetermined value are searched as replacement candidates.

(3) Replace the cell searched as a replacement candidate with a cell having a small delay time. The cell optimization process for eliminating the hold time error is performed in the following procedure.

(1) Enter the slack value that is the margin for the setup time check and the slack value that is the margin for the hold time check.

(2) For the path where a hold time error has occurred due to insufficient delay, search for cells whose slack values in all pins' setup time checks have positive values equal to or greater than a predetermined value as replacement candidates.

(3) Replace the cell searched as a replacement candidate with a cell having a long delay time. ■ Therefore, the case of improving the hold time error due to insufficient delay will be described first. As shown in the flowchart of FIG. 2, at the stage of performing the cell optimization processing in step S7, the current timing verification of the already processed electronic circuit design is performed, and the slack of each pin in the cell is determined. Information (margin value in timing verification) is required. The slack information referred to here is calculated based on the MAX delay in the setup time check, and calculated based on the MIN delay in the hold time check. In both cases, the slack value has a positive value when there is room. . Here, each slack information in the setup time check and the hold time check will be described.

Figure 5 shows an example of a basic circuit generated by electronic circuit design, in which DFF 30, 32 cells are connected in two stages. In FIG. 5, the delay time of the net from the clock terminal CK1 to the clock input terminal CK in the preceding DFF 30 is Tc1, and the delay time of the net between the input D of the preceding DFF 30 and the subsequent input D is Suppose that the delay time from the clock terminal CK2 to the clock input terminal CK in the subsequent DFF 32 is Tc2. Setup time check in this case The parameters to be checked are as shown in Figs. 6 (A) to 6 (D). That is, CK1 in FIG. 6B has a delay time Tc1 with respect to the basic clock in FIG. In addition, the signal change with respect to the input D of the DFF 32 at the latter stage of FIG. 6C has a delay time Td from the rise of the clock CK1. Further, the clock CK 2 in FIG. 6D is input to the clock terminal CK of the DFF 32 with a delay time Tc 2. Here, the setup time T setup of the clock CK2 in Fig. 6 (D) is defined as the time for preparing data for the clock edge, and when the setup time T setup is shorter than this, When data arrives, DFF 32 will not work. Here, if the conditions as shown in Fig. 6 (E) are satisfied during each time in this setup time check, the circuit in Fig. 5 operates normally without generating a setup error. From the conditions in Fig. 6 (E), the margin in the setup time check given by the following equation can be obtained. Margin = (Tc2 _max + r) One (Tcl _max + Td _max + Tsetup _max ) FIG. 7 is a time chart showing the time for the hold time check in the circuit of FIG. 5, and FIG. The waveform in D) is the same as in Figs. 6 (A) to 6 (D). In this case, as shown in Fig. 6 (D), the hold time Thold is set for the clock CK2 with respect to the rising edge of the clock at the clock input terminal CK of DFF 32. The hold time Thold is a time for holding data with respect to a clock edge. In this hold time check, if the condition as shown in Fig. 7 (E) is satisfied, the circuit in Fig. 5 can operate normally. From the condition of FIG. 7 (E), the margin in the hold time check is given by the following equation. Margin _{_{= (Tcl min + Thold min)}} - (Tcl mi n + Td mi n) Figure 8 is circuit cell optimization is applied to improve the cell optimization and set-up time error to improve the hold time error aspect of the present invention This is a specific example. Note that the net delay is set to 0 for simplicity. In Figure 8, the circuit Eight cells A to H are arranged between the start point 48 and the end point 50. Each of cells A to H displays the parameters shown in block 52 at the lower left. That is, the cell name X and the delay d of the cell itself are shown inside the cells A to H. The setup slack value sX is shown above the output lines of cells A to H, and the hold slack value sn is shown below the output lines. Further, an end point 50 indicates a set-up constraint value and a hold constraint value in this circuit. This set-up constraint value is calculated based on the MAX delay as shown in the timing chart of FIG. The hold constraint value is calculated based on the MIN delay as shown in the timing chart of FIG. In this example, the setup constraint value is 12 and the hold constraint value is 8. Each numerical value in FIG. 8 has a unit of time, for example, a unit of microsecond. In the circuit of Fig. 8, the following three paths are provided between the starting point 48 and the ending point 50.

Pass 1 (A, B, E, G, H)

Pass 2 (A, C, F, G, H)

Pass 3 (A, D, G, H)

Also, if you look at the delay time of the path,

Pass 1 = 9

Pass 2 = 1 0

Pass 3 = 7

It becomes. Therefore, regarding the path delay, the path 2 is the MAX path and the path delay is 10, and the path 3 is the MIN path and the path delay is 7.

FIG. 9 is an explanatory diagram of a calculation procedure of the setup slack s X in FIG. This setup slack s X is calculated by the following equation.

s x = {(setup constraint value one (end point integrated delay))

1. (Starting point accumulated delay) (1) Here, cells A to H in FIG. 9 show numerical values of the parameters shown in box 54 at the lower left. That is, the cells A to H show the cell name X and the cell delay d, the setup slack s X is shown above the cell output line, and the integrated delay from the starting point 48 is shown below the output line. Is shown. In the calculation of the setup slack for determining the setup error due to the delay over, the path 2 indicated by the arrow 56 at which the path delay becomes the maximum becomes a problem. Therefore, a specific example of the setup slack calculation for cells A, C, F, G, and H that make up path 2 is as follows. It is easier to calculate the setup slack from the end point 50 side. Focusing on cell H now,

Setup constraint value = 1 2,

End point integration delay = 0

Start-side accumulated delay = 1 0

Therefore, the slack value is

s x = 1 2-1 0 = 2

Is calculated as

In the next cell G,

Setup constraint value = 1 2,

End point integration delay = 2

Start point integration delay = 8

Therefore, the setup slack value is

s x = (12— 2) — 8 = 2

It becomes.

In the next cell F,

Set-up constraint = 1 2,

End point total delay = 2 + 1

Start-side accumulated delay = 7

Therefore, the setup slack value is

s x = (1 2-2-1)-7 = 2

It becomes.

The next cell C

Setup constraint value = 12,

End point total delay = 2 + 1 + 2

Start point integrated delay = 5 Therefore, the setup slack value is

s x = (12-2-1-2)-5 = 2

It becomes. In cell A,

Setup constraint value = 12,

End point total delay = 2 + 1 + 2 + 3

Starting point integrated delay = 2

Therefore, the setup slack value is

s x = (1 2-2-1-2-3)-2 = 2

It becomes. Similarly, the setup slack can be calculated for the remaining cells B, E, and D.

FIG. 10 is an explanatory diagram of the calculation procedure of the hold slack in the circuit of FIG. The hold slack has a margin when it is larger than the hold constraint value, so the calculation is opposite to the setup slack. That is, the hold slack is calculated by the following equation.

Hx = (Start point integration delay) 1 Hold constraint value) 1 (End point integration delay)}

(2) For cells A to H in Fig. 10, the cell's name X and cell delay d are shown in the cell, and the hold slack hX is shown above the output line, as shown in box 58 at the lower left. The total delay Td from the starting point 48 is shown below the output line. Hold time error in hold time check using hold slack is a problem for path 3 (A, D, G, H) indicated by arrow 60 where the path delay is minimized. Therefore, a specific example of hold slack calculation for cells A, D, G, and H on path 60 is as follows. This hold slack calculation is easier to understand if you start from the end point 50 side. First, in cell H

Hold constraint value = 8

Start-side accumulated delay = 7

End point integration delay = 0

Therefore, the setup slack in this case is

hx = 7-8 =-l It becomes.

In the next cell G,

Hold constraint value = 8

Start point integrated delay = 5

End point integration delay = 2

Hold slack is

h x = 5-(8— 2) =-1

It becomes.

In the next cell D,

Hold constraint value = 8

Start point integration delay = 4

End point total delay = 2 + 1

Hold slack is

h x = 4— (8— 2— 1) = _ 1

It becomes.

In cell A

Hold constraint value = 8

Start and end integration delay = 2

End point total delay = 2 + 1 + 2

Hold slack is

h x = (2-8-2-1-2) = — 1

It becomes.

Referring again to FIG. 8, the set-up slack information calculated based on the MAX delay in the setup time check and the hold slack information calculated based on the MIN delay in the hold time check are input as described above. If this is the case, improve the timing by switching cells for the path that has a hold time error. For a path with a hold time error, the timing can be improved by increasing the delay time of the path. In other words, cells existing in the path where a hold time error has occurred have a large delay time. By replacing the cell with a new one, the hold time error can be eliminated. In this case, when a cell is replaced, the delay of another route passing through the replaced cell changes. Therefore, if the cell to be replaced is selected incorrectly, even if the hold time error of the path for which the hold time error was to be improved can be improved, a new timing for another path whose delay has changed due to the cell replacement can be performed. An error may occur. Therefore, in the present invention, an optimum replacement cell that does not cause a new evening error is obtained by replacing the cell using slack information of the cell. Specifically, for the pins of cells that are present in the path where a hold time error has occurred, check the setup slack determined by the setup time check, and check that this set-up slack is a positive value equal to or greater than the specified value. Are replaced. In this way, by replacing cells with a large setup time slack, that is, cells that have a margin for setup time error that causes delay over with an increase in delay time, the hold time error caused by insufficient delay is improved. In the setup time check, on the other hand, the timing constraint becomes stricter due to the increase in the delay time.However, in the setup time check, cells that originally had a margin, that is, cells with a positive slack value in the setup time check, are targeted. Therefore, even if the delay time increases due to cell exchange, there is no setup time error due to over-delay.

The cell optimizing process for improving the hold time error will be specifically described with reference to FIG. Among path 1 (A, B, E, G, H), path 2 (A, C, F, G, H), and path 3 (A, D, G, H) in FIG. 8, the path delay is the smallest. The MIN pass is pass 3 (A, D, G, H), with a 7 for toe evening delay. Since this total delay = 7 is smaller than the hold constraint value = 8, it is determined that a hold error has occurred. Therefore, in path 3 (A, D, G, H) that causes a hold error, the optimal cell for improving this is to have the minimum hold slack sh and the maximum setup slack s X Search for a cell. In this case, in path 3 (A, D, G, H), the output side of cells A to H The hold slack h X shown in the net is all 1 1. On the other hand, the setup slack s X has the largest net of 5 in cell D, indicating that it is the net with the most margin. Therefore, if the delay d of cell D is increased by one to eliminate hold errors and D == 2 + 1 = 3, the setup slack sx is reduced by one, and sx = 5-l = It becomes 4. If the delay d of cell D is increased by one, the total delay of the path is 8, and the hold error can be eliminated by satisfying the hold constraint value. At the same time, since the total delay 8 does not exceed the setup constraint value = 12, no setup error occurs.

Next, a case where the setup time error due to the overdelay is improved will be described. Cell replacement to improve setup time error is almost the same as that for hold time error, and the total delay becomes the maximum after calculating the setup slack and hold slack. When the setup constraint value is exceeded, the setup time error is determined, and the cell on the path where the setup time error has occurred is searched for the cell with the smallest setup slack and the largest hold slack. I do. By replacing cells searched in this way with cells having a small delay time, the total delay is reduced, thereby eliminating setup errors. At the same time, the total delay approaches the hold constraint value by reducing, but since the cell with the net with the largest hold slack value is exchanged, no hold time error occurs.

FIGS. 11 and 12 are flowcharts showing the procedure of the cell size optimizing process by the cell size optimizing unit 18 in FIG. 4. The flowchart shows a program for the cell size optimizing process according to the present invention. It is shown at the same time.

In FIG. 11, first, in step S1, the hold slack value and the setup slack value of all nets are measured and saved in a file. Subsequently, in steps S2 to S7, a cell size optimization process for improving the hold time error is performed. That is, a path is selected in step S2 to calculate a delay time, and in step S3, the path delay time is compared with a hold constraint value to determine a hold time error. Path delay time If the value is less than the hold constraint value, a hold time error occurs. In step S4, a cell having the minimum hold slack value and the maximum set-up slack value is determined as a temporary candidate. Subsequently, in step S5, a temporary delay calculation is performed without actually performing cell exchange. That is, the delay parameter of the cell having a larger delay time is obtained from the cell parameter library 24 for the temporary candidate cell, and the delay of the cell is changed. Find the total delay. Subsequently, based on the result of the delay provisional calculation, it is checked in step S6 whether the hold time error has been eliminated, the setup time error has not occurred, and the timing constraint has been satisfied. If the timing constraint is satisfied in step S6, the provisional candidate determined in step S4 is determined as a candidate cell for increasing the delay time in step S7. If the timing constraint condition is not satisfied in step S6, the processing from step S2 is repeated until the end of all paths is determined in step S13. If the timing constraint condition is not satisfied in step S6, the delay time of the temporary candidate cell is further increased and a temporary delay calculation is performed in step S5 to meet the timing constraint. In such a case, a candidate cell for increasing the delay time is determined in step S7.

On the other hand, if the hold time error is not determined in step S3, the cell size optimizing process for improving the setup time error in steps S8 to S12 in FIG. 12 is performed. That is, in step S8, the path delay time is compared with the setup constraint value. If the setup constraint value is exceeded, a setup time error is determined, and the process proceeds to step S9. In step S9, a cell having a minimum setup slack value and a maximum hold slack value is determined as a tentative candidate for cells existing on a path where a setup time error has occurred. Subsequently, in step S10, the parameter of the temporary candidate cell having a small delay time is obtained by referring to the cell parameter library 24, and the delay temporary calculation is performed. In step S11, it is determined whether or not the total delay based on the delay provisional calculation satisfies both timing constraints based on the set-up constraint value. If the timing constraint is satisfied, the delay time is reduced in step S12. Determine as a candidate cell. If the timing constraints are not satisfied in step S11, the process returns to step S2 until all paths are completed in step S13, and the next Similar processing is repeated for the path. If the timing constraint is not satisfied in step S11, the process returns to step S10, and the parameter is temporarily changed to a parameter with a smaller delay time of the temporary candidate cell, and delay temporary calculation is performed to satisfy the timing constraint. The process of judging whether or not may be repeated.

FIG. 13 is a block diagram of a functional configuration of the net thickening unit 20 of FIG. The net thickening unit 20 includes an input unit 42, a net search unit 44, and a thickening unit 46. The input unit 42 inputs the slack value of the hold time obtained from the timing verification result in the electronic circuit design. The net search unit 44 has a pin having a positive slack value among the nets on the path where the setup time error occurs due to the delay over, and the net satisfying the specified condition is set as a thick line candidate. Search for.

The specified conditions for this net search are

(1) Net wiring length

(2) Driver driving capability

The two are set.

The bolding section 46 replaces the wiring of the net searched as a bolding candidate by the net search section 44 with a bold line in order to reduce the delay time.

The improvement of the setup time error in the thickening of the net shown in FIG. 13 is intended to reduce the delay time by thickening the net having a positive hold slack in the path in which the setup time error has occurred. However, if the timing improvement was performed to increase the delay time by thickening the nets with positive hold slack by targeting the nets, many nets that were not very effective as a whole path were targeted for improvement, and as a result, the routing channel Insufficient driver performance, and the increase in wiring capacitance due to the use of thick lines with the intention of reducing delay may make it impossible to properly improve timing with a driver with a small driving capability.

Therefore, in the embodiment of FIG. 13, hold slack is achieved by limiting the net wiring length to a net whose length is equal to or more than a predetermined value and the driving capability of the driver is equal to or more than a predetermined value as a net for reducing the delay time by thickening the line. This solves the problem of searching for improved nets only by using this method. FIGS. 14 and 15 are flowcharts showing the procedure of the net thickening process by the net thickening unit in FIG. 13. This flowchart simultaneously shows the program of the net thickening process. In FIG. 14, in step S1, the hold slack value and setup slack value of all nets are calculated and saved in a file. Subsequently, in step S2, a path is selected, and the delay time, that is, the total delay of the path is calculated. Subsequently, in step S3, the path delay time is compared with the setup constraint value. If the setup delay value is exceeded, it is determined that a setup time error has occurred, and in step S4, the error is stored in a file as an error pass. Such an error pass determination in steps S2 to S4 is repeated in step S5 until all passes are completed. Next, one error path stored in the file is selected in step S6, one net on the error path is selected in step S7, and the hold slack value of the net is positive in step S8. Check if. If it is positive, it is checked in step S9 whether the net wiring length is larger than a predetermined value Ln, and if it is larger, it is checked in step S10 whether the driver driving capability is not less than a predetermined value Dn. If the driver driving capacity is equal to or greater than the predetermined value Dn, a duplicate check is performed in step S11 to determine whether or not the same net that has already been processed exists. To decide.

Then, the process proceeds to step S13 in FIG. 15 to obtain the values of the wiring capacitance C and the wiring resistance R according to the assumed wiring thickness from the thick line net information file 26, and to obtain the thickened values of the temporary candidate net. Change and perform delay tentative calculation. When the net to be improved is determined by the provisional delay calculation, the timing state after the thickening of the net can be analyzed without returning to the wiring process and actually performing the wiring in order to perform the thickening. Next, in step S14, a setup time check is performed on the total delay of the path after thickening the net obtained from the temporary delay calculation, and in step S15, the total delay of the path is determined to be less than the hold constraint value. Check that the setup time error has been resolved. If the setup time error has been eliminated, the current tentative candidate is determined as a thick line candidate net in step S16. If the setup time error has not been resolved, the provisional candidate is discarded, and it is checked in step S17 whether all nets on the path have been completed. After that, the process returns to step S7 in FIG. The same processing is repeated for the net. In step S17 in Fig. 15, all If all the nets have been processed, it is checked in step S18 whether all the paths have been processed.If not, the process returns to step S6 in Fig. 14 and selects the next error path. Then, the same processing is repeated. When the processing is completed for all error paths in step S18, net thickening processing is performed on the candidate nets determined in step S19. The net thickening process is actually performed through the processes of logic design, cell placement, wiring, timing analysis, and timing analysis result analysis in steps S9 to S14 as shown in the flowchart of FIG.

FIGS. 16 and 17 are flowcharts showing another embodiment of the net thickening process according to the present invention. Even in this embodiment, the basic configuration is the same as that of the net thickening unit 20 in FIG. 12, but is composed of the input unit 42, the net search unit 44, and the thickening unit 46. The conditions for narrowing the net to be thickened in Part 4 are different. That is, in this embodiment, a predetermined number of worst paths in the upper order are selected from the worst paths for which the setup time error has been determined, and the net thickening process is performed. As a condition for narrowing down birds

(1) Net length

(2) Driver drive capacity

(3) Net delay

(4) Dull waveform on the receiver side, (5) Number of fans

A net that satisfies the above five conditions is made a bold line candidate net and bolded. As a result, only one net can be selected as a thick line candidate from one error path. On the other hand, in the net thickening processing shown in Figs. 14 and 15, since a net with a positive hold time slack value on the error path is selected, multiple nets for one error path are selected. The difference is that the bird is bolded. The thickening processing of the net will be described below with reference to the flowcharts of FIGS. 16 and 17. First, in step S1, the hold slack value and set-up slack value of all nets are calculated and saved in a file. After that, in step S2, a path is selected and a delay time, that is, a total delay of the path is calculated. , Step S 3 Judge the setup time error by comparing the path delay time with the setup constraint value. When a set-up time error is determined, this is stored in a file as a past path in step S4. The processing of steps S2 to S4 is repeated until all the paths are completed in step S5. Next, one worst path is selected from the worst paths stored in the file in step S6 in the order of the difference in path delay time with respect to the setup constraint value. Next, one net on the worst path selected in step S7 is selected. If the net length is larger than the predetermined value Ln in step S8, the process proceeds to step S9. If the driver driving ability is larger than the predetermined value Dn, the process proceeds to step S10. Here, if the net delay is larger than the predetermined value Tn, the process proceeds to step S11. Here, if the receiver-side waveform bluntness is greater than a predetermined value (T sin) n, the process proceeds to step S12. Here, if the fan-out number is equal to or greater than the predetermined value Fn, the bolding is regarded as a net, and in step S13, it is checked whether or not the same net is targeted. Register as a net. Next, in step S15 in FIG. 17, the wiring capacity C and the wiring resistance R based on the wiring thickness assumed for the tentative candidate net from the thick line net information 24 in the thick line net information 24 are obtained from the thick line net information file 26, and the thick line is formed. After that, the delay is calculated temporarily. Next, in step S16, a setup time check using the result of the delay provisional calculation is performed, and if the setup time error is eliminated in step S17, the provisional candidate is changed to a thick candidate net in step S18. To decide. Subsequently, the process returns to step S7 in FIG. 16 and the same processing is repeated until all nets on the path are completed in step S19. When all nets on the path have been completed in step S19, it is checked in step S20 whether a predetermined number of upper worst paths have been completed, and if not completed, the process proceeds to step S6 in Fig. 16. Return The next worst path is selected, and the same processing is repeated. If it is determined in step S20 that a predetermined number of upper worst paths have been completed, the flow advances to step S21 to bold the determined candidate net. This net thickening is actually processed through the logic design, cell placement, wiring, timing analysis, and timing analysis result analysis shown in steps S9 to S13 as shown in the flowchart of FIG.

In the above embodiment, as shown in the time chart of FIG. Although the cell optimization processing and the net thickening processing are sequentially performed in step S8, one of the cell optimization processing and the thickening processing may be performed. The present invention is not limited to the above embodiments, but includes appropriate modifications without impairing the objects and advantages thereof. Further, the present invention is not limited by the numerical values shown in the above embodiments. Industrial potential

As described above, according to the present invention, from the result of the timing analysis of the electronic circuit design after the logic design, the cell arrangement and the wiring processing are completed, a hold time error as a racing error or a setup error as an over-delay error is obtained. By determining the cell to be replaced for the timing line on the error path using the comparison information obtained from the result of the timing verification when determining the timing error, the timing error can be efficiently eliminated.

In addition, if cells on a path that causes an evening error are randomly selected and replaced, the intention is to improve the timing error, but the timing error on another path will cause the error to not converge. However, according to the present invention, the timing error is efficiently eliminated because the optimum cell is selected and replaced so that the improvement of the timing error in the cell exchange does not cause the timing error on another path. be able to.

In addition, the setup time error that causes over-delay error is reduced by reducing the delay time for thickening the net wiring. At that time, the thickest line is used for the net with the minimum necessary and most effective effect. Timing errors can be eliminated by thickening the net without causing shortage of the wiring channel. _f

In addition, when the cell or net to be replaced is determined, the timing error is eliminated by the delay calculation using the improved cell and net parameters without actually performing cell exchange or net thickening. Actual cell replacement after verifying whether or not the network is thickened, the repetition of cell replacement, net thickening and timing verification is minimized, and processing time is reduced. Can be shortened.

Claims

The scope of the claims

1. In the timing improvement method of electronic circuit design after logic design, cell placement and wiring processing,

An input unit for inputting slack information obtained from a timing verification result in the electronic circuit design,

The cell search unit focuses on slack information at the pins of the cells on the path that does not satisfy the timing constraints. Even if the cell is replaced to improve the timing, other paths that pass through the replaced cell will cause timing errors. A cell search step of searching for a cell not to be replaced as a replacement candidate

A timing improvement method comprising:

2. In the timing improvement method of claim 1,

In the input step, a slack value that is a margin value of a setup time check and a slack value that is a margin value of a hold time check obtained from a timing verification result in an electronic circuit design are input,

In the cell search step, a cell having a positive slack value of a hold time check of all pins that is equal to or greater than a predetermined value is searched as a replacement candidate for a path causing a setup time error due to delay over,

In the cell switching step, a cell searched as a replacement candidate is replaced with a cell having a small delay time, and a method for improving evening timing is provided.

3. In the timing improvement method of claim 1,

In the input step, a slack value that is a margin value for a setup time check and a slack value that is a margin value for a hold time check are input,

In the cell search step, a slack value of a setup time check of all pins is determined for a path causing a hold time error due to insufficient delay. Cell with a positive value greater than or equal to

The cell improvement step is characterized in that a cell searched as a replacement candidate is replaced with a cell having a large delay time.

4. In the timing improvement method according to claim 1, the net search step includes a step of temporarily calculating a net delay after changing a delay parameter of a cell searched as a replacement candidate to a value of a cell after replacement, and then calculating a timing error. A timing improvement method comprising: determining a replacement candidate when no timing error occurs;

5. In the timing improvement method of electronic circuit design after logic design, cell placement and wiring processing,

An input step of inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design by the input unit; and a net search unit causing a setup time error due to over-delay. A net having a pin whose slack value is positive and satisfying a specified condition as a candidate for thickening, from the nets on the path where the slack value is positive; A thick line step of replacing the routed net with a thick line with a small delay time,

A timing improvement method comprising:

6. In the timing improvement method according to claim 5, in the net search step, as nets satisfying the specified condition, nets whose net wiring length and driver driving capability are equal to or larger than specified values are searched as thick line candidates. A timing improvement method that features

7. In the timing improvement method according to claim 5, in the net search step, the net delay is temporarily calculated after changing the line capacitance and the line resistance of the net searched as the thick line candidate to the thick line values. A setup time error is determined, and a net in which the setup time error has been eliminated is determined as a thick line candidate. Timing improvement method.

8. In the timing improvement method of electronic circuit design after logic design, cell placement and wiring processing,

An input step of inputting a slack value, which is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design, and a setup time error due to over-delay caused by a net search unit; A net search step of searching, as a bold line candidate, a net satisfying a predetermined condition from all nets on the path that

A bolding step of replacing the net wiring searched as a bolding candidate by a bolding part with a bold line having a small delay time;

A timing improvement method comprising:

9. In the timing improvement method according to claim 8, the net search step includes, among nets having a setup time error, a net wiring length, a driver driving capability, a net delay, and a waveform blunting on a receiver side. And a method for retrieving a net having a fanout number larger than a specified value as a bolding candidate.

10. In the timing improvement method according to claim 8, the net search step selects a predetermined number of upper worst paths having a large delay time from nets in which a setup time error has occurred, and forms a thick line. A timing improvement method characterized by repeating the search for candidates.

11. In the timing improvement method according to claim 8, in the net search step, the net delay is temporarily calculated after changing the line capacitance and the line resistance of the net searched as a thick line candidate to the thick line values. A timing improvement method characterized in that a setup time error is determined by using the method, and a net in which the setup time error has been eliminated is determined as a thick line candidate.

1 2. In a program to improve the timing of electronic circuit design after logic design, cell placement and wiring processing,

An input step of inputting slack information obtained from a timing verification result in the electronic circuit design;

A program characterized by executing

1 3. In the program of claims 1 2,

In the cell search step, for a path in which a setup time error has occurred due to over-delay, a cell whose slack value of the hold time check of all pins is a positive value equal to or greater than a predetermined value is searched for as a replacement candidate,

The program, wherein the cell switching step replaces a cell searched as a replacement candidate with a cell having a long delay time.

1 4. In the program of claims 1 2,

In the cell search step, for a path having a hold time error due to insufficient delay, a cell having a positive slack value of a setup time check of all pins that is equal to or greater than a predetermined value is searched as a replacement candidate,

The cell exchange step includes the steps of: A program characterized by replacing cells.

15. In the program according to claim 12, the net search step temporarily changes the delay parameter of the cell searched as a replacement candidate to the value of the cell after the replacement and temporarily sets the net and gate delay. A program for calculating and determining a timing error, and determining a candidate for replacement when no evening error occurs.

16 6. In a program to improve the timing of electronic circuit design after logic design, cell placement and wiring,

An input step of inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design;

A net search step of searching a net having a pin whose slack value is positive and satisfying a predetermined condition as a thick line candidate from nets on a path having a setup time error due to delay over,

A program characterized by executing

17. The program according to claim 16, wherein the net search step includes, as nets satisfying the specified conditions, nets having a net wiring length and a driver driving capability that are equal to or larger than specified values as thick line candidates. A program characterized by searching.

18. In the program according to claim 16, in the net search step, the net delay is temporarily calculated after changing the wiring capacitance and the wiring resistance of the net searched as the thickening candidate to the thickened values. A program characterized by determining a setup time error and determining a net in which the setup time error has been eliminated as a thick line candidate.

1 9. Revise the timing of electronic circuit design after logic design, cell placement and wiring processing. In programs that improve,

A program characterized by comprising:

20. In the program according to claim 19, the net search step includes, among the nets causing a setup time error, a net wiring length, a driver driving capability, a net delay, and a waveform blunting on a receiver side. A program characterized by searching for nets whose fanout number is smaller than a specified value as thickening candidates.

21. In the program according to claim 19, in the net search step, a predetermined number of high-order worst paths having a large delay time are selected from nets having a setup time error, and a bold line is selected. A program that repeats the search for conversion candidates.

22. In the program according to claim 19, in the net search step, the net delay is temporarily calculated after changing the wiring capacitance and the wiring resistance of the net searched as a thickening candidate to thickened values. A program characterized by determining a setup time error and determining a net in which the setup time error has been eliminated as a thick line candidate.

23. In a device for improving the timing of electronic circuit design after logic design, cell placement and wiring processing, An input unit for inputting slack information obtained from a timing verification result in the electronic circuit design;

Focusing on slack information at the pins of cells on the path that does not satisfy the timing constraints, even if cells are exchanged for timing improvement, cells that do not cause timing errors on other paths that pass the exchanged cells are candidates for exchange. A cell search unit that searches for a cell as a candidate, a cell replacement unit that replaces a cell searched as a replacement candidate with a cell that satisfies timing constraints,

An apparatus comprising:

24. In the apparatus of claims 23,

The input unit inputs a slack value that is a margin value of a setup time check and a slack value that is a margin value of a hold time check, obtained from a timing verification result in an electronic circuit design,

The cell search unit searches for a cell having a positive slack value of a hold time check of all pins equal to or more than a predetermined value as a replacement candidate for a path in which a setup time error has occurred due to delay over,

The apparatus, wherein the cell switching unit replaces a cell searched as a replacement candidate with a cell having a small delay time.

25. In the device of claims 23,

The input unit inputs a slack value which is a margin value for a setup time check and a slack value which is a margin value for a hold time check,

The cell search unit searches for a cell having a positive value equal to or more than a predetermined value for a slack value of a setup time check of all pins as a replacement candidate for a path having a hold time error due to insufficient delay,

The cell switching unit replaces a cell searched as a replacement candidate with a cell having a long delay time.

26. In the apparatus according to claim 23, the net search unit searches for a replacement candidate. After the delay parameter of the searched cell is changed to the value of the cell after the exchange, the net delay is tentatively calculated to determine a timing error, and when no timing error occurs, it is determined as an exchange candidate. apparatus.

27. In a device to improve the timing of electronic circuit design after logic design, cell placement and wiring,

An input unit for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design;

A net search unit for searching, as a thick line candidate, a net having a pin whose slack value is negative and satisfying a specified condition from among nets on a path in which a setup time error due to delay over time has occurred. ,

A thick line section that replaces the wiring of the net searched as a thick line candidate with a thick line having a small delay time;

An apparatus comprising:

28. In the apparatus according to claim 27, in the net search step, as nets satisfying the specified conditions, nets whose net wiring length and driver driving capability are equal to or larger than specified values are searched as thick line candidates. An apparatus characterized in that:

29. In the apparatus according to claim 27, in the net searching step, the line delay and the line resistance of the net searched as a thickening candidate are changed to thickened values, and then the net delay is temporarily calculated and set up. An apparatus characterized by determining a time error and determining a net in which a setup time error has been eliminated as a thick line candidate.

30. In a device to improve the timing of electronic circuit design after logic design, cell placement and wiring processing,

All of the paths on the path causing setup time error due to delay over A net search unit for searching nets satisfying a specified condition from the nets as candidates for bolding;

An apparatus comprising:

31. In the apparatus according to claim 30, the net search unit is configured to select a net wiring length, a driver driving capability, a net delay, a waveform dullness on a receiver side, from among nets having a setup time error. An apparatus that searches for nets with a fanout number greater than a specified value as thickening candidates.

32. In the apparatus according to claim 30, the net search unit selects a predetermined number of higher-order worst paths having a large delay time from nets in which a setup time error has occurred, and selects a thick line candidate. An apparatus characterized by repeating a search.

33. In the apparatus according to claim 30, the net search unit tentatively calculates the net delay after changing the wiring capacitance and the wiring resistance of the net searched as the thickening candidate to the thickened values. An apparatus characterized by determining a setup time error and determining a net in which the setup time error has been eliminated as a thick line candidate.