CN107194075A

CN107194075A - The connecting line construction and distributing system and method for PLD

Info

Publication number: CN107194075A
Application number: CN201710374646.XA
Authority: CN
Inventors: 文化; 董辰; 谢丁; 王元; 黄志军
Original assignee: Shanghai Anlogic Information Science & Technology Co Ltd
Current assignee: Shanghai Anlu Information Technology Co.,Ltd.
Priority date: 2017-05-24
Filing date: 2017-05-24
Publication date: 2017-09-22
Anticipated expiration: 2037-05-24
Also published as: CN107194075B

Abstract

The present invention relates to PLD layout design and software systems, the connecting line construction and distributing system and method for a kind of PLD are disclosed.In the connecting line construction of the PLD of the application, adjacent lines rail in only same line rail group is connected by programmable transmission gate, eliminate the programmable transmission gate of cross-line rail group, the line rail of not collinear rail group can be accessed logic unit by increasing a new MUX as line rail group selector, there is provided wired rail group degree of communication, so as to reduce chip area, power consumption and cost while the degree of communication of each line rail group is kept.In addition, being improved to the place and route of the PLD of the application, so as to further improve the completion rate of connecting line construction, reduce the usage quantity of MUX.

Description

The connecting line construction and distributing system and method for PLD

Technical field

The present invention relates to the company of PLD layout design and software systems, more particularly to PLD Cable architecture and distributing system and method.

Background technology

Application specific integrated circuit is the integrated circuit for realizing specific function of user's customization, wherein, all integrated circuit devices Part and device line are not all preset, and can be needed to be arranged according to actual circuit.But line and function are once setting Count into, it is impossible to change.PLD is that device and interconnection resource in chip are arranged in advance, but device Function can be by programming the integrated circuit being reconfigured.All IC chips (including PLD) Production, is to rely on processing of the photoetching technique to wafer and metal level.Different chips has a series of independent lay photoetching mask plates (Mask).Layout design be exactly Integrated circuit designers according to different circuit structures and requirement, determine corresponding mask The process of version.The lay photoetching mask plate of current integrated circuit generally comprises tens layer datas, and often layer data is again by the various of mistake hundred million Figure constitution, it is extremely complex.

In the layout design of PLD, the connection between different lines is disconnected or connected by can be configured to Logical transmission gate is realized.This point be with the IC-components of other non-programmable logical devices it is entirely different, these Other adhesive integrated circuit devices and commonly known as application specific integrated circuit.This different connection implementations such as Fig. 1 a and Fig. 1 b It is shown.

In application specific integrated circuit, different lines (such as the line A and line B in Fig. 1 a) are connected by through hole 's.Area shared by through hole is very small, and can almost appear in any position, so the advantage bag of application specific integrated circuit Include that line degree of communication is very high, the shortcoming brought is no alterability, two lines just can not once being connected by through hole Disconnect them.In the programmable logic device, different lines (such as the line A and line B in Fig. 1 b) be can by one The transmission gate of programming is connected.By applying positive/negative voltage to the transmission gate grid, it is possible to achieve the company between two lines On and off is opened.This connected mode, has the disadvantage that each connection will realize that advantage is the company with area very big transmission gate The relation of connecing can be programmed.So this has been resulted in the layout design of PLD, it is contemplated that chip area Limited with power consumption etc., it is impossible to introduce excessive transmission gate to realize mutual connection between all lines.In practice, one Line can only selectively be realized with peripheral part line and connected.The transmission gate of introducing is more, and the degree of communication of line is bigger, cloth Line difficulty is reduced, and the problem of causing is that the area of device can also become big, so that cost rises.In turn, if the transmission of design Door is fewer, and the degree of communication of line will diminish, and wiring difficulty is improved, but the area of device also diminishes, and manufacturing cost also declines.

The content of the invention

It is an object of the invention to provide a kind of connecting line construction of PLD and distributing system and side Method, chip area, power consumption and cost are reduced while the degree of communication of each line rail group is kept.

In order to solve the above technical problems, embodiments of the present invention disclose a kind of line knot of PLD Structure, prewiring rail is divided into multiple line rail groups, and the adjacent lines rail of only same line rail group is connected by programmable transmission gate；

At least one logic unit of PLD is included in multiple MUXs, multiple MUXs Each input of first MUX connects the line rail of multiple line rail groups respectively, and the output end of the first MUX is accessed to Line bus in a few logic unit, one of line bus and each MUX in other MUXs is defeated Enter end connection.

Embodiments of the present invention also disclose a kind of layout method of PLD, in PLD Middle to use above-mentioned connecting line construction, layout method comprises the following steps：

Before detailed placement, a score rail group is randomly assigned to every gauze, each line rail group corresponds to average The gauze of amount；And

Detailed placement is carried out to PLD so that the expense summation for placing all logic units is minimum；

Wherein, expense summation includes the line rail alignment expense of each logic unit, and the line rail alignment of each logic unit takes With being that each logic unit is placed on all of each logic unit when on the corresponding programmable gate position of PLD The line rail alignment expense summation of port,

The line rail alignment expense of the port of each logic unit is calculated according in the following manner：

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the gauze Score rail group it is consistent, then the line rail alignment expense of port is zero；

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the gauze Score rail group it is inconsistent, then port line rail alignment expense be the first predetermined positive number.

After detailed placement is carried out to PLD, to place institute by mobile and/or exchange logic unit There is the expense summation of logic unit minimum；

Wherein, expense summation includes the line rail alignment expense of each logic unit, and the line rail alignment of each logic unit takes With being that each logic unit is placed on all of each logic unit when on the corresponding programmable gate position of PLD The line rail alignment expense summation of input port,

The line rail alignment expense of the input port of each logic unit is calculated according in the following manner：

If the driving port of input port of the gauze in logic unit and the gauze belongs to same line rail group, defeated The line rail alignment expense of inbound port is zero；

If the driving port of input port of the gauze in logic unit and the gauze belongs to not collinear rail group, input The line rail alignment expense of port is the second predetermined positive number.

Embodiments of the present invention also disclose a kind of wiring method of PLD, in PLD Middle to use above-mentioned connecting line construction, PLD is FPGA, and wiring method comprises the following steps：

Before wiring, by the connection for reconfiguring look-up table and gauze built in the programmable gate of PLD Information exchanges input port；

Wherein, input port is exchanged according in the following manner：

If first input port of the driving port of the first gauze with the first gauze on programmable gate position is not belonging to The second input port in same line rail group, programmable gate position belongs to for vacant port and with the driving port of the first gauze In same line rail group, needed for swapping first input port and the second input port in the look-up table built in programmable gate Configuration modification, and first input port of first gauze on programmable gate position is repaiied in the link information of the first gauze It is changed to the second input port；

If first input port of the driving port of the first gauze with the first gauze on programmable gate position is not belonging to The driving port category of the second input port and the first gauze of same line rail group and the second gauze on programmable gate position In same line rail group, then the drive end of second input port and second gauze of second gauze on programmable gate position is judged Whether mouth belongs to same line rail group, if it is not, then swapping first input end in the look-up table built in programmable gate Mouthful with the configuration modification needed for the second input port, and in the link information of the first gauze by the first gauze in programmable gate The first input port put is revised as the second input port, by the second gauze programmable in the link information of the second gauze The second input port on door position is revised as first input port, otherwise without exchanging.

If the gauze connected up the target input on the corresponding programmable gate position of PLD mouthful Same line rail group is not belonging to the driving port of gauze, judges to whether there is vacant input on corresponding programmable gate position Mouthful；

If there is vacant input port on corresponding programmable gate position, virtualphase is answered all vacant on programmable gate position Otherwise gauze is connected to target input mouthful by input port to the connection of target input mouthful；

Judge to whether there is the driving port category with gauze in all vacant input ports on corresponding programmable gate position In the first vacant input port of same line rail group, if in the presence of being swapped in the look-up table built in corresponding programmable gate Target input mouthful and the configuration modification needed for the first vacant input port, and gauze is connected to the first vacant input port, it is no Gauze is then connected to target input mouthful.

Embodiments of the present invention also disclose a kind of layout system of PLD, in PLD Middle to use above-mentioned connecting line construction, layout system includes：

Distribute module, for before detailed placement, being randomly assigned a score rail group, each line rail group to every gauze Corresponding to the gauze of par；And

Detailed placement module, for carrying out detailed placement to PLD so that place all logic units Expense summation is minimum；

Detailed placement module calculates the line rail alignment expense of the port of each logic unit according in the following manner：

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with distribute module Score rail group to the gauze is consistent, then the line rail alignment expense of port is zero；

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with distribute module Score rail group to the gauze is inconsistent, then the line rail alignment expense of port is the first predetermined positive number.

It is mobile to exchange module, for after detailed placement is carried out to PLD, being patrolled by mobile and/or exchange Collect unit and make it that the expense summation for placing all logic units is minimum；

It is mobile to exchange the line rail alignment expense that module calculates the input port of each logic unit according in the following manner：

Embodiments of the present invention also disclose a kind of wiring system of PLD, in PLD Middle to use above-mentioned connecting line construction, PLD is FPGA, and wiring system includes：

Switching Module, for before wiring, by reconfiguring the lookup built in the programmable gate of PLD The link information of table and gauze exchanges input port；And

Interconnection module, for being connected up to PLD；

Wherein, Switching Module exchanges input port according in the following manner：

If first input port of the driving port of the first gauze with the first gauze on programmable gate position is not belonging to The driving port category of the second input port and the first gauze of same line rail group and the second gauze on programmable gate position In same line rail group, then the drive end of second input port and second gauze of second gauze on programmable gate position is judged Whether mouth belongs to same line rail group, if it is not, then swapping first input end in the look-up table built in programmable gate Mouthful with the configuration modification needed for the second input port, and in the link information of the first gauze by the first gauze in programmable gate The first input port put is revised as the second input port, by the second gauze programmable in the link information of the second gauze The second input port on door is revised as first input port, otherwise without exchanging.

First judge module, for when the gauze connected up is in the corresponding programmable gate position of PLD Target input mouthful and the driving port of gauze when being not belonging to same line rail group, judge on corresponding programmable gate position whether There is vacant input port；

Virtual module, if determining there is vacant input on corresponding programmable gate position for first judge module Mouthful, virtualphase answers all vacant input ports of programmable gate to the connection of the target input mouthful；

Second judge module, for judging to whether there is and gauze in all vacant ports on corresponding programmable gate position Driving port belong to the first vacant input port of same line rail group；

Switching Module, if determine to exist the first vacant input port for the second judge module, in corresponding programmable gate Target input mouthful and the configuration modification needed for the first vacant input port are swapped in built-in look-up table；And

Link block, for the first judge module determine on corresponding programmable gate position be not present vacant input port or Gauze is connected to target input mouthful when second judge module determines to be not present the first vacant input port, and judged first Module determines to have vacant input port on corresponding programmable gate position and the determination of the second judge module is vacant defeated in the presence of first Gauze is connected to the first vacant input port during inbound port.

Compared with prior art, the main distinction and its effect are embodiment of the present invention：

In the connecting line construction of the PLD of the application, adjacent lines rail in only same line rail group is by can Transmission gate connection is programmed, the programmable transmission gate of cross-line rail group is eliminated, line is used as by increasing a new MUX Rail group selector the line rail of not collinear rail group can be accessed logic unit there is provided wired rail group degree of communication so that Keep reducing chip area, power consumption and cost while the degree of communication of each line rail group.

In the layout method of the PLD of the application, by the way that line rail alignment expense is added into detailed placement Expense summation in, can improve gauze input port and driving port between line rail group match, so as to improve line knot The completion rate of structure, the usage quantity for reducing MUX, further reduce chip area, power consumption and cost.

In the layout method of the PLD of the application, after detailed placement, by by line rail align expense It is added to the expense summation of detailed placement further to adjust logic unit, input port and the driving port of gauze can be improved Between line rail group matching so that improve the completion rate of connecting line construction, reduce MUX usage quantity, further reduce Chip area, power consumption and cost.

In the wiring method of the PLD of the application, by reconfiguring the look-up table built in programmable gate Input port is exchanged with the link information of gauze, the line rail group degree of registration of gauze can be improved, so as to improve connecting line construction Completion rate, reduce MUX usage quantity, further reduce chip area, power consumption and cost.

Brief description of the drawings

Fig. 1 a and 1b are the different line connected modes of existing application specific integrated circuit and PLD；

Fig. 2 is existing full-mesh structure；

Fig. 3 is a kind of connectivity structure of existing prewiring rail；

Fig. 4 a, Fig. 4 c are a kind of structural representations of the connecting line construction of PLD in first embodiment of the invention Figure；

Fig. 4 b are a kind of structural representations of the connecting line construction of existing PLD；

Fig. 5 a-5d are the layout explanation figures of existing PLD；

Fig. 6 is a kind of schematic flow sheet of the layout method of PLD in second embodiment of the invention；

Fig. 7 is a kind of schematic flow sheet of the layout method of PLD in third embodiment of the invention；

Fig. 8 a-8b are the input commutativities of FPGA programmable gate；

Fig. 9 is a kind of schematic flow sheet of the wiring method of PLD in four embodiment of the invention；

Figure 10 is a kind of schematic flow sheet of the wiring method of PLD in fifth embodiment of the invention；

Figure 11 a-11c are a kind of schematic diagrames of the wiring method of PLD in fifth embodiment of the invention；

Figure 12 is a kind of structural representation of the layout system of PLD in sixth embodiment of the invention；

Figure 13 is a kind of structural representation of the layout system of PLD in seventh embodiment of the invention；

Figure 14 is a kind of structural representation of the wiring system of PLD in eighth embodiment of the invention；

Figure 15 is a kind of structural representation of the wiring system of PLD in ninth embodiment of the invention.

Embodiment

In the following description, in order that reader more fully understands the application and proposes many ins and outs.But, this Even if the those of ordinary skill in field is appreciated that many variations without these ins and outs and based on following embodiment And modification, each claim of the application technical scheme claimed can also be realized.

To make the object, technical solutions and advantages of the present invention clearer, the implementation below in conjunction with accompanying drawing to the present invention Mode is described in further detail.

Various all kinds of of quantity are included in PLD (such as field programmable gate array (FPGA) device) Interconnection resources, and these lines will be positioned in line rail preset on chip according to certain rule packet.In FPGA academias In research, there is the connecting line construction of some high degrees of communication, the every prewiring rail other line rails formation full-mesh adjacent with it is this The cloth of structure is very good, but there is no that FPGA can be used in actual applications.Full-mesh rule is as shown in Figure 2.

Because full-mesh rule can introduce too many line transmission gate, excessively complicated circuit design is caused, how to be protected On the premise of the considerable degree of cloth of card, simplify connection rule, become the key problem of FPGA interconnection resource research and designs One of.In current international mainstream FPGA, relatively current bus connection method is, by all prewiring rail packets, to belong to same group Adjacent prewiring rail between have a complete degree of communication, and come real according to certain rule between the adjacent prewiring rail of different groups Now part is connected.A kind of mode is as follows：

In the example in figure 3, prewiring rail A1 and A2 belongs to A groups, and B1 and B2 belong to B groups, and C1 and C2 belong to C groups, D1 and D2 belongs to D groups.Belonging between the adjacent gauze A1- ＞ A2 with group, B1- ＞ B2, C1- ＞ C2, D1- ＞ D2 can be passed by programmable Defeated door have also been devised the reconfigurable interconnection between some different groups, such as A1- ＞ B2, B1- ＞ C2, C1- ＞ D2, D1- ＞ to connect, in addition A2.In the design of such line, signal can just be transferred to other any one group of prewiring rail from any one group of prewiring rail On.Compared with Fig. 2 full-mesh structure, transmission gate is reduced to 8 from 16, and circuit structure, area and cost are obtained greatly Simplify.

Because in the application of actual PLD, output driving pin and input pin always occurs in user's gauze Not in the situation of same line rail group, current prewiring rail line rule requires that a prewiring rail will not only be connected together The adjacent lines rail of group, will also connect a number of different group adjacent lines rails.It is more across the connection of group, the connection journey of interconnection resource Degree is better, but the programmable transmission gate introduced is also more.Excessive programmable transmission gate will bring chip area to increase, chip The problem of power consumption increases and manufacturing cost rises.So the manufacturer of PLD generally can all face such choice： It is the cloth line-connectivity for increasing chip area, power consumption, cost to have exchanged for, or sacrifices cloth line-connectivity to reduce chip Area, power consumption and costIn fact, cloth line-connectivity need not infinitely pursue high degree of communication, it need only ensure in user's electricity Completion rate is still can guarantee that in the case of the intensive use device logical resource in road, the connection in many use shown in Fig. 3 Rule and its some variants are just enough.The present invention continues the connection rule of simplification figure 3, by across the programmable transmission of group Door is saved, by strengthening the connection of design programmable logic cells device input mouthful, strengthening the software of PLD The implementation method for being laid out, connecting up in system, to keep the connecting degree of the lower circuit of original connection rule.So as to programmable in reduction The cost of logical device, while improve power consumption performance, can cloth come keep original structure by strengthening placement-and-routing's software Property.

First embodiment of the invention is related to a kind of connecting line construction of PLD.Fig. 4 a, Fig. 4 c are that this can be compiled The structural representation of the connecting line construction of journey logical device.As shown in fig. 4 a, in the connecting line construction of the PLD, in advance Wiring rail is divided into multiple line rail groups (such as line rail group A-D), and the adjacent lines rail of only same line rail group passes through programmable biography Defeated door connection, adjacent gauze A1-A2, B1-B2, C1-C2, D1-D2 for example belonged to group can be connected by programmable transmission gate Connect, the gauze of difference group can not be connected by programmable transmission gate.Prewiring rail is exemplarily illustrated in Fig. 4 a and is divided into four Prewiring rail, can also be divided into by individual line rail group, it will be understood that in the other embodiment of the application according to actual needs The line rail group of other quantity.

Connection rule shown in Fig. 4 a, it is impossible to complete connection of the gauze port across several not collinear rail groups.Currently may be used In the elementary cell design of programmed logic device, input is all to realize programmable requirement in the form of MUX. General MUX design, can allow unit input to connect the line rail of some difference groups consciously, so that between offer group The flexibility of selection.But the area for being due to MUX be it is limited, the selection path that it can be provided be also it is limited, We can not possibly allow the MUX of each unit input to receive the path of whole line rail groups, Zhi Nengxuan in practical application Allow to selecting property partial line rail group.Such as, (connected as shown in Figure 4 b before the improvement of unit access), unit input can be with By line rail group A and B access, another input can be accessed by A and C, and also one input is accessed by B and C etc..Pre- cloth The simplification of line rail connection rule, undoubtedly reduces the cloth of whole system, is that we increase by one this in each elementary cell A little new MUXs, the effect of these MUXs is exactly to be swapped between different line rail groups, such as following institute State.

(connected as illustrated in fig. 4 c after the improvement of unit access), at least one logic unit of PLD includes (such as being located at shown in Fig. 4 c is nethermost for the first MUX in multiple MUXs, multiple MUXs MUX) each input connect the line rails (such as the line rail A-D shown in Fig. 4 c) of multiple line rail groups respectively, more than first Line bus (as illustrated in fig. 4 c, at least one logic list that the output end of road selector is accessed at least one logic unit Other lines in member can also be connected to the line bus), line bus is selected with each multichannel in other MUXs Select the input connection of device.The output of other MUXs is inputted (for example unit inputs 1-4) as unit.

An input and the company of each MUX in other MUXs are schematically illustrated in Fig. 4 c Line bus connect, another two input respectively different from belonging to groups two line rails connection.It is appreciated that the application other In embodiment, it (for example can also be allowed) to set each MUX according to the area of each MUX according to actual needs An input, three inputs are attached even without input with corresponding line rail.

Above-mentioned connecting line construction can apply to include in FPGA various PLDs, in various FPGAs The driving port of input port of the gauze of at least one in device at least one logic unit and at least one gauze is not Belong to same line rail group.

In the connecting line construction of the PLD of present embodiment, the adjacent lines rail in only same line rail group leads to Programmable transmission gate connection is crossed, the programmable transmission gate of cross-line rail group is eliminated, is made by increasing a new MUX The line rail of not collinear rail group can be accessed to logic unit there is provided the degree of communication of wired rail group for line rail group selector, from And reduce chip area, power consumption and cost while the degree of communication of each line rail group is kept.

As shown in Figure 4 b, before improvement, because the path of MUX is limited, each input of unit can only be selected Select the line of ground introducing portion separated time rail group；As illustrated in fig. 4 c, after improvement, we add a new MUX (title For line rail group selector), then the line bus allowed in the line rail access unit of not collinear rail group passes through internal line bus Different units are accessed by original MUX again to input.Each so increased line rail group selector can be one Individual optional unit input provides the degree of communication of the wired rail group of institute, solves the cross-line rail group connectivity problem that the unit is inputted.So

In order to further reduce chip area, power consumption and cost, it is intended that the basis of a PLD is single The line input of member belongs to same line rail group with the driving output of its gauze as far as possible, with improve connecting line construction completion rate and Reduce the usage quantity of MUX.

PLD needs different subscriber's line circuits being converted into the different configurations of inherent logic device and connected up The different connections of resource, to realize design requirement that user is different.Therefore all Design for Programmable Logic companies all can The software development system based on oneself device is provided for client.Divided according to the flow of most broad sense, FPGA The software systems of device can be divided into：Integrated system, logic optimization system and physics realization system.Wherein, integrated system is By the design requirement of user, the soft of the logic unit that PLD can be supported is converted into from common hardware description language Part instrument；Logic optimization system is by merging, splitting, ghost image the means such as penetrates and reprocesses comprehensive logic unit out, to subtract Few logical unit number, improves the performance of circuit and the power consumption of reduction circuit；Physics realization system is by the final of logic optimization As a result it is configured in PLD, specifically determines the logic state of each program bit.It can further be divided again For layout system and the major class of wiring system two.

Layout system is by the logic unit in logic optimization result, according to chip frame, is placed into chip particular location Go, each logic unit will obtain the position of a non-overlapping copies.The configuration of the position, it should optimize user system as far as possible The design performance of system.Wiring system is according to logic optimization circuit interconnected relationship, and the logic unit position that layout is determined, configuration Different line switches, is electrically connected with the signal realized between logic unit.The configuration of line switch, it should be ensured that different Electrical signal it is not short-circuit, and as much as possible optimize custom system design performance.In the design of any circuit line net, drive end Line rail component cloth between mouth and input port is very random.For the line knot for the PLD for improving the application The completion rate of structure, we further improve the software systems (cloth of traditional PLD in the following embodiments Office system and wiring system), it is contemplated that the line rail group matching problem between driving port and input port.

Second embodiment of the invention is related to a kind of layout method of PLD.Fig. 6 is the FPGA The schematic flow sheet of the layout method of device.

Second embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile In the layout method of journey logical device, by the way that line rail alignment expense is added in the expense summation of detailed placement, it can improve Line rail group between the input port of gauze and driving port is matched, so as to improve the completion rate of connecting line construction, reduce multichannel choosing The usage quantity of device is selected, chip area, power consumption and cost is further reduced.Specifically：

The flow of the layout system of one standard is broadly divided into total arrangement and the step of detailed placement two, and it illustrates figure as schemed Shown in 5a-5d.Wherein, Fig. 5 a show the circuit design of user；Fig. 5 b show that user logic has been converted into compiling before layout The logic unit (look-up table Lut 1, Lut 2 and Lut 3) of journey logical device, as shown in Figure 5 b, on PLD Physical location (16 rooms (Slot)) is not also corresponding with logic unit；Fig. 5 c show total arrangement, i.e., by user logic list Member is placed into the approximate location of PLD according to the design needs of user；Fig. 5 d show detailed placement, i.e. root According to the positional information of total arrangement, user logic unit is accurately placed on PLD.

Before layout starts, the front end integrated software of PLD is by the circuit (as shown in Figure 5 a) of user Each gate (as shown in Figure 5 b) of PLD support is converted into, place function is exactly further by these logics Door is placed into the rational position of device, is optimal the performance of subscriber's line circuit.Total arrangement (as shown in Figure 5 c) is generally used The algorithm of mathematical optimization, determine each user logic door on PLD should best region, it is and detailed Gate is specifically accurately placed PLD by layout (as fig 5d) by according to the result of total arrangement Programmable gate at.Also a small amount of layout system there was only detailed placement, without total arrangement, it is represented as being based on simulated annealing The layout system of method：First each user logic door is placed on the programmable gate of PLD immediately, Ran Houzai Moved by unit, unit is exchanged etc., and means optimize subscriber's line circuit performance.

The application is simplifying the connecting line construction of PLD (such as the connecting line construction in first embodiment) While, detailed placement system is improved to increase the cloth of gauze.Various different detailed placement system, there is one Individual general character, i.e. system can assess the expense that each user logic unit is placed on the programmable gate of different PLDs With then on the premise of no any two user logic unit takes same programmable gate, what all units were placed takes It is minimum with summation.It is expressed as follows：

F (layout)=min ∑ f (cell i), st. any cell i and cell the j not overlapping usual f (cell in position I) it is defined as relevant with the result of total arrangement, the result gap of unit cell i and total arrangement is bigger, and expense is higher.This Shen Please propose, in order to improve line degree of communication, in said units expense, should adding unit be in diverse location when, its line The alignment expense of line rail group.But because all units are all in mobile status, so the alignment expense of line rail is very difficult to Calculate.Following processing method is proposed for this application：

In the programmable logic device use first embodiment connecting line construction, as shown in fig. 6, layout method include with Lower step：

In step 601, before detailed placement, a score rail group, each line rail group are randomly assigned to every gauze Corresponding to the gauze of par, i.e., each line rail group obtains the gauze of par, and (gauze is logic unit and logic list Port line between member, and).If for example, a total of 100 gauzes, 4 line rail groups, then random to each gauze Distribution score rail group after cause each line rail group obtain 25 gauzes, by taking 4 line rail groups in Fig. 4 a as an example, line rail group A, B, Each line rail group in C, D obtains 25 gauzes.It is appreciated that in the other embodiment of the application, can also be to each Line rail group is allocated or other methods of salary distribution using different weights, as long as being conducive to line rail to align.

Then into step 602, detailed placement is carried out to PLD so that place taking for all logic units It is minimum with summation.Wherein, expense summation includes the line rail alignment expense of each logic unit, the line rail alignment of each logic unit Expense is the institute that each logic unit is placed on each logic unit when on the corresponding programmable gate position of PLD There is the line rail alignment expense summation of port (for example, three ends when the logic unit LUT1 in Fig. 5 d is placed on Slot10 positions The line rail alignment expense summation of mouth),

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the gauze Score rail group it is consistent, then the line rail alignment expense of port is zero (for example, the output port of the LUT1 in Fig. 5 d is put in LUT1 Put the line that the line rail group belonging to when on Slot10 positions is distributed in step 601 for the gauze on A, and the output port Rail group is also A, then zero) the line rail alignment expense of the output port is；

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the gauze Score rail group it is inconsistent, then port line rail alignment expense be the first predetermined positive number (for example, the output of the LUT1 in Fig. 5 d Line rail group of the port belonging to when LUT1 is placed on Slot10 positions is the gauze on A, and the output port in step 601 Middle distributed line rail group is B, then 5) the line rail alignment expense of the output port is.

If the line rail alignment expense of LUT1 three ports is respectively 5,0,5, logic unit LUT1 line rail alignment Expense is 10；If LUT1, LUT2, LUT3 line rail alignment expense are respectively 10,5,15,30 are added in expense summation Line rail alignment expense.In above-mentioned example, the first predetermined positive number is illustrated as 5, it will be understood that in the other embodiment of the application In the first predetermined positive number can also be set as other positives according to actual needs.

It is shown below, is by the target modification of detailed placement：

((cell i, st. any cell i and cell j position is not overlapping by f (cell i)+g by F (layout)=min ∑s

Wherein：G (cell i)=∑ g (cell i, net j)

Each increased g (cell i) of unit be exactly the unit on a certain device programmable gate position, its all of the port The summation of the line rail alignment expense of line.And the alignment cost design of line rail is as follows：

Wherein, a certain reasonable positive number herein corresponds to the above-mentioned first predetermined positive number, and the first predetermined positive number can be according to reality Border needs to be set.

It can see by upper, use be added to not collinear rail, and by this information by pre-allocating gauze in detailed placement During family unit is calculated for the expense of different components programmable gate position, layout is optimized.

Third embodiment of the invention is related to a kind of layout method of PLD.Fig. 7 is the FPGA The schematic flow sheet of the layout method of device.

3rd embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile It is total by the expense that line rail alignment expense is added to detailed placement after detailed placement in the layout method of journey logical device With further adjust logic unit, the line rail group that can be improved between the input port of gauze and driving port is matched so that Improve the completion rate of connecting line construction, reduce the usage quantity of MUX, further reduce chip area, power consumption and make Valency.Specifically：

In the programmable logic device use first embodiment connecting line construction, as shown in fig. 7, layout method include with Lower step：

In step 701, after detailed placement is carried out to PLD, pass through mobile and/or exchange logic list Member make it that the expense summation for placing all logic units is minimum.

Wherein, expense summation includes the line rail alignment expense of each logic unit, and the line rail alignment of each logic unit takes With being that each logic unit is placed on all of each logic unit when on the corresponding programmable gate position of PLD The line rail of input port aligns expense summation (for example, two when the logic unit LUT1 in Fig. 5 d is placed on Slot10 positions The line rail alignment expense summation of input port),

If the driving port of input port of the gauze in logic unit and the gauze belongs to same line rail group, defeated The line rail alignment expense of inbound port is zero (for example, an input port of the LUT1 in Fig. 5 d is placed on Slot10 in LUT1 Line rail group belonging to when putting is that the line rail group belonging to the driving port of the gauze on A, and an input port is also A, Then zero) the line rail alignment expense of an input port is；

If the driving port of input port of the gauze in logic unit and the gauze belongs to not collinear rail group, input The line rail alignment expense of port is the second predetermined positive number (for example, an input port of the LUT1 in Fig. 5 d is placed in LUT1 Line rail group belonging to when on Slot10 positions is the line rail belonging to the driving port of the gauze on A, and an input port Group is B, then 3) the line rail alignment expense of an input port is.

If the line rail alignment expense of LUT1 two input ports is respectively 3,0, logic unit LUT1 line rail pair Neat expense is 3；If LUT1, LUT2, LUT3 line rail alignment expense are respectively 3,0,6,9 line is added in expense summation Rail alignment expense.In above-mentioned example, the second predetermined positive number is illustrated as 3, it will be understood that in the other embodiment of the application Second predetermined positive number can also be set as other positives according to actual needs, and the second predetermined positive number can make a reservation for first Positive number is identical or different.

By upper it can be seen that, and unlike the layout method of the application second embodiment, in above-mentioned detailed placement knot Shu Hou, because each user logic unit has defined location, we can decontrol the constraint of gauze prewiring rail, select Arbitrary logic unit, recalculates the expense of its line rail alignment：

F (layout)=min ∑s (f (cell i)+g* (cell i)), st. any cell i and cell j position is not weighed It is folded

G* (cell i)=∑ g* (cell i, net j), ports of the net j on unit cell i is input port

Wherein, a certain positive number herein corresponds to the above-mentioned second predetermined positive number.

With this new expense mode, we can pass through movement of user's logic unit in regional area, exchange Or further improve the line rail degree of registration of layout result by the way of low temperature simulated annealing.That is, detailed After layout terminates, the line rail group matching degree of every gauze is recalculated, moves and exchanges by the small range of unit, to improve Line rail group is matched, to be optimized to layout.It is appreciated that it is mobile, exchange logic unit can using existing any movement, Exchange method (such as low temperature simulated annealing), as long as making minimum using the expense summation of new paragon.

Four embodiment of the invention is related to a kind of wiring method of PLD.Fig. 9 is the FPGA The schematic flow sheet of the wiring method of device.

4th embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile In the wiring method of journey logical device, exchanged by reconfiguring the link information of look-up table built in programmable gate and gauze Input port, can improve the line rail group degree of registration of gauze, so as to improve the completion rate of connecting line construction, reduce MUX Usage quantity, further reduce chip area, power consumption and cost.Specifically：

In addition to the improvement of layout, the application have also been devised the port equivalents by using FPGA programmable units Property, the input port of programmable unit is exchanged, so as to increase the method for system cloth.Port on FPGA programmable units Equivalent characterizations, can be illustrated with Fig. 8 a-8b.

FPGA programmable gate, be by built-in look-up table, by the way that input port is converted into corresponding address information, Then, the look-up table numerical value that prestores is searched to realize the logic function of any input.So when input port is exchanged, I As long as the look-up table built in programmable gate according to corresponding address change information again data storage, can just obtain and port Logic function of equal value before exchanging.Fig. 8 a gauze annexation (i.e. former gauze annexation) can be mapped as figure by we 8b annexation (connectivity port can be exchanged, obtain new connection of equal value), then by reconfiguring in programmable gate Look-up table numerical value is the logic function that can obtain equivalence.

The connecting line construction of first embodiment is used in the programmable logic device, and PLD is that scene can be compiled Journey gate array device, as shown in figure 9, wiring method comprises the following steps：

In step 901, before wiring, by reconfiguring the look-up table built in the programmable gate of PLD Input port is exchanged with the link information of gauze, to reach that the input port for making each gauze drives port to exist with it as far as possible In same line rail group.

Hereafter, PLD is connected up.

In step 901, input port is exchanged according in the following manner：

If first input port of the driving port of the first gauze with the first gauze on programmable gate position is not belonging to The second input port in same line rail group, programmable gate position belongs to for vacant port and with the driving port of the first gauze In same line rail group, needed for swapping first input port and the second input port in the look-up table built in programmable gate Configuration modification, and first input port of first gauze on programmable gate position is repaiied in the link information of the first gauze Be changed to the second input port (for example, the driving port of gauze 1 belongs to line rail group C, gauze 1 on programmable gate position first The second input port that input port belongs on line rail group A, the programmable gate position is vacant port and belongs to line rail group C, Then first input port is swapped with the second input port, to cause the driving port of gauze 1 to belong to same with input port One line rail group).

If first input port of the driving port of the first gauze with the first gauze on programmable gate position is not belonging to The driving port category of the second input port and the first gauze of same line rail group and the second gauze on programmable gate position In same line rail group, then the drive end of second input port and second gauze of second gauze on programmable gate position is judged Whether mouth belongs to same line rail group, if it is not, then swapping first input end in the look-up table built in programmable gate Mouthful with the configuration modification needed for the second input port, and in the link information of the first gauze by the first gauze in programmable gate The first input port put is revised as the second input port, by the second gauze programmable in the link information of the second gauze The second input port on door position is revised as first input port (for example, the driving port of gauze 1 belongs to line rail group B, gauze 1 first input port on programmable gate position belongs to line rail group A, second input of the gauze 2 on the programmable gate position Port belongs to line rail group B and the driving port of gauze 2 is not belonging to line rail group B, then by first input port and the second input Mouth is swapped, to cause the driving port of gauze 1 to belong to same line rail group with input port), otherwise without exchanging.

That is, after layout terminates, all gauzes have driving port, the line rail component of input port to match somebody with somebody. When the line rail group where driving port and part (or whole) input port is different, we can by exchanging input port, By input port as much as possible be adjusted to drive port where line rail group in.Exchange is carried out as follows：

Exchange target：Gauze i will be exchanged in unit j port on score rail group k.

Exchanged form：1. the port m for belonging to line rail group k on unit j is not belonging to any other gauze, then our direct handles Input ports of the gauze i on unit j changes to port m.

2. the port m for belonging to line rail group k on unit j has been connected to gauze n, then if exchanging gauze i and n in unit Input port on j does not cause gauze n line rail group alignment to be deteriorated, then just exchange the two ports.

3. other situations, which are exchanged, to be occurred.

By upper it can be seen that, after layout terminates, before wiring starts, by the port and the gauze that exchange programmable gate Between corresponding relation, come improve gauze line rail group match, to be optimized to follow-up wiring.

Fifth embodiment of the invention is related to a kind of wiring method of PLD.Figure 10 and Figure 11 a-11c are The schematic flow sheet of the wiring method of the PLD.

5th embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile In the wiring method of journey logical device, exchanged by reconfiguring the link information of look-up table built in programmable gate and gauze Input port, can improve the line rail group degree of registration of gauze, so as to improve the completion rate of connecting line construction, reduce MUX Usage quantity, further reduce chip area, power consumption and cost.Specifically：

By way of being exchanged port, the line rail group degree of registration of gauze after layout is further improved.We are right It is internal that the improvement of wiring is deep into wiring.When we connect up to certain root gauze, its all input port institutes are traveled through Programmable gate, virtually from the vacant port on programmable gate to the connecting line rail of target port, so wiring is with regard to that can pass through Any vacant port connects target port.

The connecting line construction of first embodiment is used in the programmable logic device, and PLD is that scene can be compiled Journey gate array device, as shown in Figure 10, wiring method comprises the following steps：

In step 1001, if the gauze connected up is on the corresponding programmable gate position of PLD The driving port of target input mouthful and gauze is not belonging to same line rail group, judges to whether there is on corresponding programmable gate position Vacant input port.

If there is vacant input port on corresponding programmable gate position, then into step 1002, otherwise into step 1005。

In step 1002, virtualphase answers all vacant input ports on programmable gate position to target input mouthful Connection.It is appreciated that being virtually well known to those skilled in the art herein, will not be repeated here.

Then into step 1003, judge in all vacant input ports on corresponding programmable gate position whether there is with The driving port of gauze belongs to the first vacant input port of same line rail group, if in the presence of into step 1004, otherwise entering Step 1005.

In step 1004, target input mouthful and the first sky are swapped in the look-up table built in corresponding programmable gate The configuration modification needed for input port is put, and gauze is connected to the first vacant input port.

In step 1005, gauze is connected to target input mouthful.

As shown in fig. 11a, in initial line relation, gauze 1 is even toward input port A, and gauze 2 connects toward input port B, C and D are vacant for port.When we will connect gauze 1, we as shown in Figure 11 (b) the virtual connecting line rail from port C to A, And the connecting line rail from port D to A.Then we connect up to gauze 1, in this example, it has been found that one passes through port D A access path is arrived again.Line success after, we using programmable gate input exchange characteristic, by switching port A and D come Realization removing dummy line rail " D- ＞ A ", and complete the line rail alignment of gauze 1.

It can see by upper, in wiring is carried out, by virtually from the vacant port of programmable gate to wiring target port Line rail so that wiring can be realized when necessary by vacant port connection and port exchange, to carry out Wiring optimization.

The better embodiment that the present invention is formed after each embodiment combination (is for example implemented second embodiment with the 3rd Mode is combined into layout method, and/or the 4th embodiment and the 5th embodiment are combined into wiring method), but each implementation Mode can also be used respectively.

A series of comprehensive layouts recited above, the improvement of wiring, we, which can realize, is simplifying programmable logic device In the case of the connecting line construction of part, the connection effect similar to original structure.By hardware, the corrdinated adjustment of software, obtain Device area, power consumption and the manufacturing cost of smaller PLD.

The each method embodiment of the present invention can be realized with modes such as software, hardware, firmwares.No matter the present invention be with Software, hardware or firmware mode realize that instruction code may be stored in the addressable memory of any kind of computer In (such as it is permanent or revisable, it is volatibility or non-volatile, it is solid-state or non-solid, it is fixed or Replaceable medium of person etc.).Equally, memory may, for example, be programmable logic array (Programmable Array Logic, referred to as " PAL "), random access memory (Random Access Memory, referred to as " RAM "), programmable read-only deposit Reservoir (Programmable Read Only Memory, referred to as " PROM "), read-only storage (Read-Only Memory, letter Claim " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, referred to as " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, referred to as " DVD ") etc..

Sixth embodiment of the invention is related to a kind of layout system of PLD.Figure 12 is the FPGA The structural representation of the layout system of device.

6th embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile In the layout system of journey logical device, by the way that line rail alignment expense is added in the expense summation of detailed placement, it can improve Line rail group between the input port of gauze and driving port is matched, so as to improve the completion rate of connecting line construction, reduce multichannel choosing The usage quantity of device is selected, chip area, power consumption and cost is further reduced.Specifically：

The connecting line construction of first embodiment is used in the programmable logic device, and as shown in figure 12, layout system includes：

Detailed placement module, for carrying out detailed placement to PLD so that place all logic units Expense summation is minimum.

Second embodiment is the method embodiment corresponding with present embodiment, and present embodiment can be implemented with second Mode is worked in coordination implementation.The relevant technical details mentioned in second embodiment are still effective in the present embodiment, in order to Reduce and repeat, repeat no more here.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in the second implementation In mode.

Seventh embodiment of the invention is related to a kind of layout system of PLD.Figure 13 is the FPGA The structural representation of the layout system of device.

7th embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile It is total by the expense that line rail alignment expense is added to detailed placement after detailed placement in the layout system of journey logical device With further adjust logic unit, the line rail group that can be improved between the input port of gauze and driving port is matched so that Improve the completion rate of connecting line construction, reduce the usage quantity of MUX, further reduce chip area, power consumption and make Valency.Specifically：

The connecting line construction of first embodiment is used in the programmable logic device, and as shown in figure 13, layout system includes：

It is mobile to exchange module, for after detailed placement is carried out to PLD, being patrolled by mobile and/or exchange Collect unit and make it that the expense summation for placing all logic units is minimum.

3rd embodiment is the method embodiment corresponding with present embodiment, and present embodiment can be implemented with the 3rd Mode is worked in coordination implementation.The relevant technical details mentioned in 3rd embodiment are still effective in the present embodiment, in order to Reduce and repeat, repeat no more here.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in the 3rd implementation In mode.

Eighth embodiment of the invention is related to a kind of wiring system of PLD.Figure 14 is the FPGA The structural representation of the wiring system of device.

8th embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile In the wiring system of journey logical device, exchanged by reconfiguring the link information of look-up table built in programmable gate and gauze Input port, can improve the line rail group degree of registration of gauze, so as to improve the completion rate of connecting line construction, reduce MUX Usage quantity, further reduce chip area, power consumption and cost.Specifically：

The connecting line construction of first embodiment is used in the programmable logic device, and PLD is that scene can be compiled Journey gate array device, as shown in figure 14, wiring system includes：

Interconnection module, for being connected up to PLD.

4th embodiment is the method embodiment corresponding with present embodiment, and present embodiment can be implemented with the 4th Mode is worked in coordination implementation.The relevant technical details mentioned in 4th embodiment are still effective in the present embodiment, in order to Reduce and repeat, repeat no more here.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in the 4th implementation In mode.

Ninth embodiment of the invention is related to a kind of wiring system of PLD.Figure 15 is the FPGA The structural representation of the wiring system of device.

9th embodiment is improved on the basis of first embodiment, is mainly theed improvement is that：It can compile In the wiring system of journey logical device, exchanged by reconfiguring the link information of look-up table built in programmable gate and gauze Input port, can improve the line rail group degree of registration of gauze, so as to improve the completion rate of connecting line construction, reduce MUX Usage quantity, further reduce chip area, power consumption and cost.Specifically：

The connecting line construction of first embodiment is used in the programmable logic device, and PLD is that scene can be compiled Journey gate array device, as shown in figure 15, wiring system includes：

Virtual module, if determining there is vacant input on corresponding programmable gate position for first judge module Mouthful, virtualphase answers all vacant input ports on programmable gate position to the connection of the target input mouthful；

5th embodiment is the method embodiment corresponding with present embodiment, and present embodiment can be implemented with the 5th Mode is worked in coordination implementation.The relevant technical details mentioned in 5th embodiment are still effective in the present embodiment, in order to Reduce and repeat, repeat no more here.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in the 5th implementation In mode.

The implementation in addition, each embodiment of the above can work in coordination.The relevant technical details mentioned in any embodiment It is all still effective in other embodiments, in order to reduce repetition, repeat no more here.

To sum up, the application design is changed, layout method is adjusted, cloth with less transmission gate by a series of layout designs Line method is adjusted, to obtain the effect similar with more transmission gate, the high device connected, so that effectively reduction device is manufactured into This.Compared with the prewiring rail annexation of other current PLDs, coordinated and optimized by hardware and software, we Simplification connected mode disclosure satisfy that the logical sum timing requirements of design circuit, at the same time produced interface unit is minimum, So that the area of PLD is minimum, least in power-consuming, manufacturing cost is minimum.

It should be noted that each module mentioned in each equipment embodiment of the invention is all logic module, physically, One logic module can be a part for a physical module or a physical module, can also be with multiple physics The combination of module realizes that the Physical realization of these logic modules in itself is not most important, and these logic modules institute is real The combination of existing function is only the key for solving technical problem proposed by the invention.In addition, the innovation in order to protrude the present invention Part, the above-mentioned each equipment embodiment of the present invention not by with to solve technical problem relation proposed by the invention less close Module introduce, this is not intended that the said equipment embodiment and in the absence of other modules.

It should be noted that in the claim and specification of this patent, such as first and second or the like relation Term is used merely to make a distinction an entity or operation with another entity or operation, and not necessarily requires or imply There is any this actual relation or order between these entities or operation.Moreover, term " comprising ", "comprising" or its Any other variant is intended to including for nonexcludability so that process, method, article including a series of key elements or Equipment not only includes those key elements, but also other key elements including being not expressly set out, or also include be this process, Method, article or the intrinsic key element of equipment.In the absence of more restrictions, by wanting that sentence " including one " is limited Element, it is not excluded that also there is other identical element in the process including the key element, method, article or equipment.

Although by referring to some of the preferred embodiment of the invention, being shown and described to the present invention, It will be understood by those skilled in the art that can to it, various changes can be made in the form and details, without departing from this hair Bright spirit and scope.

Claims

1. a kind of connecting line construction of PLD, it is characterised in that prewiring rail is divided into multiple line rail groups, only together The adjacent lines rail of one line rail group is connected by programmable transmission gate；

At least one logic unit of the PLD includes multiple MUXs, the multiple MUX In each input of the first MUX connect the line rail of the multiple line rail group respectively, first MUX Line bus at least one described logic unit of output end access, the line bus with it is every in other MUXs The input connection of individual MUX.

2. the connecting line construction of PLD according to claim 1, it is characterised in that at least one gauze is in institute The driving port for stating input port and at least one gauze at least one logic unit is not belonging to same line rail group.

3. a kind of layout method of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the layout method comprises the following steps：

Before detailed placement, a score rail group is randomly assigned to every gauze, each line rail group corresponds to par Gauze；And

Detailed placement is carried out to the PLD so that the expense summation for placing all logic units is minimum；

Wherein, the expense summation includes the line rail alignment expense of each logic unit, and the line rail alignment of each logic unit takes With being each logic unit when each logic unit is placed on the corresponding programmable gate position of the PLD The line rail alignment expense summation of all of the port,

If the mesh that line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the gauze Graticule rail group is consistent, then the line rail alignment expense of the port is zero；

If the mesh that line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the gauze Graticule rail group is inconsistent, then the line rail alignment expense of the port is the first predetermined positive number.

4. a kind of layout method of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the layout method comprises the following steps：

After detailed placement is carried out to the PLD, to place institute by mobile and/or exchange logic unit There is the expense summation of logic unit minimum；

Wherein, the expense summation includes the line rail alignment expense of each logic unit, and the line rail alignment of each logic unit takes With being each logic unit when each logic unit is placed on the corresponding programmable gate position of the PLD The line rail alignment expense summation of all input ports,

If the driving port of input port of the gauze in logic unit and the gauze belongs to same line rail group, described defeated The line rail alignment expense of inbound port is zero；

If the driving port of input port of the gauze in logic unit and the gauze belongs to not collinear rail group, the input The line rail alignment expense of port is the second predetermined positive number.

5. a kind of wiring method of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the PLD is FPGA, the wiring method Comprise the following steps：

Before wiring, by the connection for reconfiguring look-up table and gauze built in the programmable gate of the PLD Information exchanges input port；

Wherein, input port is exchanged according in the following manner：

If first input port of the driving port of the first gauze with first gauze on programmable gate position is not belonging to The second input port in same line rail group, the programmable gate position for vacant port and with the drive of first gauze Moved end mouthful belongs to same line rail group, first input port is swapped in the look-up table built in the programmable gate and described Configuration modification needed for second input port, and in the link information of first gauze by first gauze it is described can First input port on programming door position is revised as second input port；

If first input port of the driving port of the first gauze with first gauze on programmable gate position is not belonging to The drive of the second input port of same line rail group and the second gauze on the programmable gate position and first gauze Moved end mouthful belongs to same line rail group, then judge second input port of second gauze on the programmable gate position with Whether the driving port of second gauze belongs to same line rail group, if it is not, then in looking into built in the programmable gate Look in table and swap first input port and the configuration modification needed for second input port, and in first gauze First input port of first gauze on the programmable gate position is revised as second input in link information Port, the second input in the link information of second gauze by second gauze on the programmable gate position Mouth is revised as the first input port, otherwise without exchanging.

6. a kind of wiring method of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the PLD is FPGA, the wiring method Comprise the following steps：

If the gauze connected up the target input on the corresponding programmable gate position of the PLD mouthful Same line rail group is not belonging to the driving port of the gauze, is judged on the corresponding programmable gate position with the presence or absence of vacant Input port；

It is all on the virtual corresponding programmable gate position if there is vacant input port on the corresponding programmable gate position Otherwise the gauze is connected to the target input mouthful by vacant input port to the connection of the target input mouthful；

Judge in all vacant input ports on the corresponding programmable gate position with the presence or absence of the drive end with the gauze Mouth belongs to the first vacant input port of same line rail group, if in the presence of in the look-up table built in the corresponding programmable gate Swap target input mouthful and the configuration modification needed for the described first vacant input port, and described in the gauze is connected to First vacant input port, is otherwise connected to the target input mouthful by the gauze.

7. a kind of layout system of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the layout system includes：

Distribute module, for before detailed placement, being randomly assigned a score rail group, each line rail group correspondence to every gauze In the gauze of par；And

Detailed placement module, for carrying out detailed placement to the PLD so that place all logic units Expense summation is minimum；

The detailed placement module calculates the line rail alignment expense of the port of each logic unit according in the following manner：

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the distribute module Score rail group to the gauze is consistent, then the line rail alignment expense of the port is zero；

If line rail group of port of the gauze in logic unit on corresponding programmable gate position is distributed with the distribute module Score rail group to the gauze is inconsistent, then the line rail alignment expense of the port is the first predetermined positive number.

8. a kind of layout system of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the layout system includes：

It is mobile to exchange module, for after detailed placement is carried out to the PLD, being patrolled by mobile and/or exchange Collect unit and make it that the expense summation for placing all logic units is minimum；

The mobile line rail alignment expense for exchanging module according to the input port of each logic unit of in the following manner calculating：

9. a kind of wiring system of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the PLD is FPGA, the wiring system Including：

Switching Module, for before wiring, by reconfiguring the lookup built in the programmable gate of the PLD The link information of table and gauze exchanges input port；And

Interconnection module, for being connected up to the PLD；

Wherein, the Switching Module exchanges input port according in the following manner：

If first input port of the driving port of the first gauze with first gauze on programmable gate position is not belonging to The second input port in same line rail group, the programmable gate position for vacant port and with the drive of first gauze Moved end mouthful belongs to same line rail group, swapped in the look-up table built in the programmable gate first input port with it is described Configuration modification needed for second input port, and in the link information of first gauze by first gauze it is described can First input port on programming door position is revised as second input port；

If first input port of the driving port of the first gauze with first gauze on programmable gate position is not belonging to The drive of the second input port of same line rail group and the second gauze on the programmable gate position and first gauze Moved end mouthful belongs to same line rail group, then judge second input port of second gauze on the programmable gate position with Whether the driving port of second gauze belongs to same line rail group, if it is not, then in looking into built in the programmable gate Look in table and swap first input port and the configuration modification needed for second input port, and in first gauze First input port of first gauze on the programmable gate position is revised as second input in link information Port, repaiies second input port of second gauze on the programmable gate in the link information of second gauze The first input port is changed to, otherwise without exchanging.

10. a kind of wiring system of PLD, it is characterised in that right is used in the PLD It is required that the connecting line construction described in 1 or 2, the PLD is FPGA, the wiring system Including：

First judge module, for when the gauze connected up is in the corresponding programmable gate position of the PLD The driving port of target input mouthful and gauze when being not belonging to same line rail group, judge the corresponding programmable gate Put with the presence or absence of vacant input port；

Virtual module, if determining there is vacant input on the corresponding programmable gate position for first judge module Mouthful, virtually connection of all vacant input ports on the corresponding programmable gate position to the target input mouthful；

Second judge module, for judge in all vacant ports on the corresponding programmable gate position whether there is with it is described The driving port of gauze belongs to the first vacant input port of same line rail group；

Switching Module, if determine to have the first vacant input port for second judge module, described corresponding Target input mouthful is swapped in look-up table built in programmable gate to repair with the configuration needed for the described first vacant input port Change；And

Link block, for determining that vacant input is not present on the corresponding programmable gate position in first judge module Mouthful or second judge module determine the gauze is connected into the target when the first vacant input port is not present it is defeated Inbound port, and determine there is vacant input port and institute on the corresponding programmable gate position in first judge module The second judge module is stated to determine that the gauze is connected into the described first vacant input when there is the first vacant input port Mouthful.