CN107194075B

CN107194075B - Wiring structure of programmable logic device and wiring layout system and method

Info

Publication number: CN107194075B
Application number: CN201710374646.XA
Authority: CN
Inventors: 文化; 董辰; 谢丁; 王元; 黄志军
Original assignee: Shanghai Anlogic Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co.,Ltd.
Priority date: 2017-05-24
Filing date: 2017-05-24
Publication date: 2020-11-17
Anticipated expiration: 2037-05-24
Also published as: CN107194075A

Abstract

The invention relates to a layout design and a software system of a programmable logic device, and discloses a connecting line structure of the programmable logic device, a wiring layout system and a wiring layout method. In the wiring structure of the programmable logic device, only adjacent wire rails in the same wire rail group are connected through the programmable transmission gate, the programmable transmission gate of a wire rail crossing group is omitted, the wire rails of different wire rail groups can be connected into the logic unit by adding a new multiplexer serving as a wire rail group selector, the connectivity of all the wire rail groups is provided, and therefore the chip area, the power consumption and the manufacturing cost are reduced while the connectivity of each wire rail group is maintained. In addition, the layout and the wiring of the programmable logic device are improved, so that the wiring rate of the wiring structure is further improved, and the number of the multiplexers is reduced.

Description

Wiring structure of programmable logic device and wiring layout system and method

Technical Field

The invention relates to a layout design and a software system of a programmable logic device, in particular to a connecting line structure of the programmable logic device, a wiring layout system and a wiring layout method.

Background

An asic is an integrated circuit that is customized to implement a specific function, wherein all integrated circuit devices and device connections are not predetermined and can be arranged according to actual circuit requirements. But the wiring and functions cannot be changed once they are designed. Programmable logic devices are integrated circuits in which the devices in the chip and wiring resources have been prearranged, but the device functionality can be reconfigured by programming. All integrated circuit chips, including programmable logic devices, are produced by the processing of wafers and metal layers by photolithographic techniques. Different chips have separate series of lithography masks (masks). Layout design is the process in which an integrated circuit designer determines a corresponding mask according to different circuit structures and requirements. Current photolithographic reticles for integrated circuits typically contain tens of layers of data, each layer of data consisting of over a hundred million various patterns, which are very complex.

In the layout design of the programmable logic device, the connection between different connecting lines is realized through a transmission gate which can be configured to be disconnected or connected. This is in stark contrast to integrated circuit devices of other non-programmable logic devices, which are also commonly referred to as application specific integrated circuits. This different connection implementation is shown in fig. 1a and 1 b.

In an asic, different wires (e.g., wire a and wire B in fig. 1 a) are connected by vias. The area occupied by the through-holes is very small and can be present almost anywhere, so the advantages of the asic include a very high connectivity of the wires, with the drawback that no modification is possible and the two wires cannot be disconnected once they are connected through the through-holes. In a programmable logic device, the different connections (e.g., connection a and connection B in fig. 1B) are connected by a programmable transmission gate. By applying positive/negative voltage to the gate of the transfer gate, connection and disconnection between the two wirings can be realized. This connection has the disadvantage that each connection is realized with a very large area of transmission gates, which has the advantage that the connection can be programmed. Therefore, in the layout design of the programmable logic device, considering the limitations of chip area, power consumption and the like, excessive transmission gates cannot be introduced to realize the connection between all the connecting lines. In practical application, one connection can only be selectively communicated with the surrounding part. The more transmission gates are introduced, the greater the connectivity of the connection lines, and the difficulty in wiring is reduced, which causes a problem that the area of the device is also increased, thereby increasing the manufacturing cost. Conversely, if fewer transmission gates are designed, the connectivity of the connection lines is reduced, which increases the difficulty of wiring, but the area of the device is also reduced, which reduces the manufacturing cost.

Disclosure of Invention

The invention aims to provide a connecting line structure of a programmable logic device, a wiring layout system and a wiring layout method, which can reduce the area, power consumption and manufacturing cost of a chip while maintaining the connectivity of each line rail group.

In order to solve the technical problem, the embodiment of the invention discloses a wiring structure of a programmable logic device, a pre-wiring rail is divided into a plurality of rail groups, and only adjacent rails of the same rail group are connected through a programmable transmission gate;

at least one logic unit of the programmable logic device comprises a plurality of multiplexers, wherein each input end of a first multiplexer in the plurality of multiplexers is respectively connected with the line rails of the plurality of line rail groups, the output end of the first multiplexer is connected to a connecting bus in at least one logic unit, and the connecting bus is connected with one input end of each multiplexer in other multiplexers.

The embodiment of the invention also discloses a layout method of the programmable logic device, the connecting line structure is adopted in the programmable logic device, and the layout method comprises the following steps:

before detailed layout, randomly distributing a target line track group to each line network, wherein each line track group corresponds to an average number of line networks; and

the programmable logic device is laid out in detail, so that the sum of the cost for placing all logic units is minimum;

wherein the cost sum comprises a line alignment cost for each logic cell, the line alignment cost for each logic cell is the sum of the line alignment costs for all ports of each logic cell when each logic cell is placed at a corresponding programmable gate position of the programmable logic device,

the cost of alignment of the wire tracks for the ports of each logic cell is calculated according to the following:

if the line track group of the port of the network on the logic unit at the corresponding programmable gate position is consistent with the target line track group distributed by the network, the line track alignment cost of the port is zero;

if the set of line tracks of a port of a net on a logic unit at the corresponding programmable gate position does not coincide with the target set of line tracks assigned by the net, the line track alignment cost of the port is a first predetermined positive number.

after the programmable logic device is laid out in detail, the sum of the cost for placing all logic units is minimized by moving and/or interchanging the logic units;

wherein the cost sum comprises a line-track alignment cost for each logic cell, the line-track alignment cost for each logic cell is the sum of the line-track alignment costs for all input ports of each logic cell when each logic cell is placed at a corresponding programmable gate position of the programmable logic device,

the cost of alignment of the line rails for the input ports of each logic unit is calculated according to the following:

if the input port of the net on the logic unit and the drive port of the net belong to the same line track group, the line track alignment cost of the input port is zero;

if the input port of a net on a logic unit and the drive port of the net belong to different wire track groups, the wire track alignment cost of the input port is a second preset positive number.

The embodiment of the invention also discloses a wiring method of a programmable logic device, the connecting line structure is adopted in the programmable logic device, the programmable logic device is a field programmable gate array device, and the wiring method comprises the following steps:

before wiring, input ports are exchanged by reconfiguring a lookup table and connection information of a wire net which are built in a programmable gate of the programmable logic device;

wherein the input ports are swapped according to the following:

if the driving port of the first net and the first input port of the first net on the programmable door position do not belong to the same line track group, the second input port on the programmable door position is an idle port and belongs to the same line track group as the driving port of the first net, the configuration modification required for exchanging the first input port and the second input port is carried out in a built-in lookup table of the programmable door, and the first input port of the first net on the programmable door position is modified into the second input port in the connection information of the first net;

if the drive port of the first net does not belong to the same group of line rails as the first input port of the first net at the programmable gate position and the second input port of the second net at the programmable gate position belongs to the same group of line rails as the drive port of the first net, judging whether a second input port of the second net on the programmable gate position and a driving port of the second net belong to the same line rail group or not, if not, the configuration modification required to swap the first input port with the second input port is performed in a look-up table built into the programmable gate, and the first input port of the first net at the programmable gate position is modified into a second input port in the connection information of the first net, and modifying the second input port of the second net on the programmable gate position into the first input port in the connection information of the second net, otherwise, not exchanging.

if the target input port of the wired net at the corresponding programmable gate position of the programmable logic device and the driving port of the wired net do not belong to the same line track group, judging whether a vacant input port exists at the corresponding programmable gate position;

if the corresponding programmable door position has the idle input port, virtualizing the connection between all the idle input ports on the corresponding programmable door position and the target input port, and otherwise, connecting the wire net to the target input port;

and judging whether a first idle input port belonging to the same line rail group with a driving port of the line network exists in all idle input ports on the position of the corresponding programmable door, if so, carrying out configuration modification required for exchanging the target input port and the first idle input port in a built-in lookup table of the corresponding programmable door, and connecting the line network to the first idle input port, otherwise, connecting the line network to the target input port.

The embodiment of the invention also discloses a layout system of a programmable logic device, the wiring structure is adopted in the programmable logic device, and the layout system comprises:

the distribution module is used for randomly distributing a target line track group to each line network before detailed layout, wherein each line track group corresponds to an average number of line networks; and

the detailed layout module is used for performing detailed layout on the programmable logic device so that the sum of the cost for placing all the logic units is minimum;

the detailed placement module calculates the lane alignment cost of the ports of each logic cell according to the following:

if the line track group of the port of the network on the logic unit at the corresponding programmable gate position is consistent with the target line track group distributed to the network by the distribution module, the line track alignment cost of the port is zero;

if the set of line tracks of a port of a net on a logic unit at the corresponding programmable gate position does not coincide with the target set of line tracks assigned to the net by the assignment module, the line track alignment cost of the port is a first predetermined positive number.

the mobile interchange module is used for enabling the sum of the cost for placing all the logic units to be minimum by moving and/or interchanging the logic units after the programmable logic device is laid out in detail;

the mobile interchange module calculates the line-track alignment cost of the input port of each logic unit according to the following modes:

The embodiment of the invention also discloses a wiring system of a programmable logic device, the wiring structure is adopted in the programmable logic device, the programmable logic device is a field programmable gate array device, and the wiring system comprises:

the switching module is used for switching the input port by reconfiguring a lookup table built in a programmable gate of the programmable logic device and the connection information of a wire network before wiring; and

the wiring module is used for wiring the programmable logic device;

the switching module switches the input ports according to the following modes:

if the driving port of the first net and the first input port of the first net on the programmable door position do not belong to the same line track group, the second input port on the programmable door position is an idle port and belongs to the same line track group as the driving port of the first net, exchanging configuration modification required by the first input port and the second input port in a built-in lookup table of the programmable door, and modifying the first input port of the first net on the programmable door position into the second input port in the connection information of the first net;

if the driving port of the first net and the first input port of the first net on the programmable gate position do not belong to the same line track group and the second input port of the second net on the programmable gate position and the driving port of the first net belong to the same line track group, judging whether the second input port of the second net on the programmable gate position and the driving port of the second net belong to the same line track group, if not, carrying out configuration modification required for exchanging the first input port and the second input port in a built-in lookup table of the programmable gate, modifying the first input port of the first net on the programmable gate position into the second input port in the connection information of the first net, modifying the second input port of the second net on the programmable gate into the first input port in the connection information of the second net, otherwise, not carrying out exchange.

the first judgment module is used for judging whether a vacant input port exists at the corresponding programmable gate position when a target input port of a wired network at the corresponding programmable gate position of the programmable logic device and a driving port of the wired network do not belong to the same line rail group;

the virtual module is used for virtualizing the connection between all the vacant input ports of the corresponding programmable gates and the target input port if the first judging module determines that the vacant input ports exist at the positions of the corresponding programmable gates;

the second judgment module is used for judging whether a first idle input port which belongs to the same line rail group with the drive port of the line network exists in all idle ports on the corresponding programmable door position;

the switching module is used for carrying out configuration modification required by a switching target input port and the first vacant input port in a built-in lookup table of the corresponding programmable gate if the second judging module determines that the first vacant input port exists; and

and the connection module is used for connecting the wire net to the target input port when the first judgment module determines that the corresponding programmable door does not have the idle input port or the second judgment module determines that the first idle input port does not exist, and connecting the wire net to the first idle input port when the first judgment module determines that the corresponding programmable door does not have the idle input port and the second judgment module determines that the first idle input port exists.

Compared with the prior art, the implementation mode of the invention has the main differences and the effects that:

in the wiring structure of the programmable logic device, only adjacent wire rails in the same wire rail group are connected through the programmable transmission gate, the programmable transmission gate of a wire rail crossing group is omitted, the wire rails of different wire rail groups can be connected into the logic unit by adding a new multiplexer serving as a wire rail group selector, the connectivity of all the wire rail groups is provided, and therefore the chip area, the power consumption and the manufacturing cost are reduced while the connectivity of each wire rail group is maintained.

In the layout method of the programmable logic device, the line track alignment cost is added to the sum of the cost of detailed layout, so that the line track group matching between the input port and the driving port of the line network can be improved, the wiring rate of a wiring structure is improved, the using number of multiplexers is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced.

In the layout method of the programmable logic device, after detailed layout, the logic unit is further adjusted by adding the alignment cost of the wire track to the sum of the cost of the detailed layout, so that the wire track group matching between the input port and the driving port of the wire network can be improved, the wiring rate of a wiring structure is improved, the using number of multiplexers is reduced, and the area, the power consumption and the manufacturing cost of a chip are further reduced.

In the wiring method of the programmable logic device, the input port is exchanged by reconfiguring the built-in lookup table of the programmable gate and the connection information of the net, and the line-rail group alignment degree of the net can be improved, so that the wiring rate of the wiring structure is improved, the use number of the multiplexers is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced.

Drawings

FIGS. 1a and 1b illustrate different interconnection schemes for conventional ASIC and programmable logic devices;

FIG. 2 is a prior art fully connected structure;

FIG. 3 is a prior art communication structure of a pre-wired rail;

fig. 4a and 4c are schematic structural diagrams of a connection structure of a programmable logic device according to a first embodiment of the present invention;

FIG. 4b is a schematic diagram of a conventional interconnect structure of a programmable logic device;

FIGS. 5a-5d are layout illustrations of a prior art programmable logic device;

FIG. 6 is a flow chart illustrating a layout method of a programmable logic device according to a second embodiment of the present invention;

FIG. 7 is a flow chart illustrating a layout method of a programmable logic device according to a third embodiment of the present invention;

8a-8b are input switching characteristics of programmable gates of an FPGA;

fig. 9 is a schematic flowchart of a wiring method of a programmable logic device according to a fourth embodiment of the present invention;

fig. 10 is a schematic flowchart of a wiring method of a programmable logic device according to a fifth embodiment of the present invention;

FIGS. 11a-11c are schematic diagrams of a wiring method of a programmable logic device according to a fifth embodiment of the present invention;

fig. 12 is a schematic structural diagram of a layout system of a programmable logic device according to a sixth embodiment of the present invention;

fig. 13 is a schematic structural diagram of a layout system of a programmable logic device according to a seventh embodiment of the present invention;

fig. 14 is a schematic configuration diagram of a wiring system of a programmable logic device according to an eighth embodiment of the present invention;

fig. 15 is a schematic diagram of a wiring system of a programmable logic device according to a ninth embodiment of the present invention.

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application can be implemented without these technical details and with various changes and modifications based on the following embodiments.

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Programmable logic devices (e.g., Field Programmable Gate Array (FPGA) devices) include a large number of various connection resources, and these connections are grouped and placed in a predetermined trace on a chip according to a certain rule. In the research of the FPGA academic world, a plurality of connecting line structures with high connectivity exist, each pre-wiring rail is in full communication with other adjacent wire rails, the distributability of the structure is very good, but basically no FPGA can be adopted in practical application. The rule of full connectivity is shown in fig. 2.

Because the full-connection rule can introduce too many connecting transmission gates, the circuit design is too complicated, and how to simplify the connection rule on the premise of ensuring the considerable degree of distributability becomes one of the core problems of the research and design of FPGA wiring resources. In the current international mainstream FPGA, a relatively popular connection method is to group all the pre-wiring rails, where adjacent pre-wiring rails belonging to the same group have a complete connectivity, and adjacent pre-wiring rails of different groups are partially connected according to a certain rule. One way is as follows:

in the example of fig. 3, pre-wiring rails a1 and a2 belong to group a, B1 and B2 belong to group B, C1 and C2 belong to group C, and D1 and D2 belong to group D. The adjacent nets belonging to the same group A1- > A2, B1- > B2, C1- > C2 and D1- > D2 can be connected through programmable transmission gates, and in addition, programmable connections among different groups are designed, such as A1- > B2, B1- > C2, C1- > D2 and D1- > A2. In such a wiring scheme, signals can be transferred from any one set of pre-wired rails to any other set of pre-wired rails. Compared with the fully-connected structure of fig. 2, the number of the transmission gates is reduced from 16 to 8, and the circuit structure, the area and the cost are greatly simplified.

In practical application of programmable logic devices, a user line network always has the situation that an output driving pin and an input pin are not in the same line rail group, and the current connection rule of pre-wiring rails requires that one pre-wiring rail not only be connected with the adjacent line rails in the same group, but also be connected with a certain number of adjacent line rails in different groups. The more connections across the bank, the better the connectivity of the routing resources, but the more programmable pass gates are introduced. Too many programmable transmission gates will cause problems of increased chip area, increased chip power consumption and increased manufacturing cost. Manufacturers of programmable logic devices are often faced with such trade-offs: increase chip area, power consumption, and cost in exchange for good wiring connectivity, or sacrifice wiring connectivity to reduce chip area, power consumption, and cost? In fact, the wiring connectivity does not need to seek high connectivity indefinitely, and only needs to guarantee that the connectivity rate can still be guaranteed under the condition that the user circuit intensively uses the logic resource of the device, and the connectivity rule shown in fig. 3 and some variants thereof are enough in many applications. The invention continuously simplifies the connection rule of fig. 3, omits the cross-group programmable transmission gate, and maintains the connection degree of the circuit under the original connection rule by enhancing the connection of the input port of the programmable logic unit device and the implementation methods of layout and wiring in the software system of the programmable logic device. Therefore, the cost of the programmable logic device is reduced, the power consumption performance is improved, and meanwhile, the layout and wiring software is enhanced to keep the layout of the original structure.

The first embodiment of the present invention relates to a wiring structure of a programmable logic device. Fig. 4a and 4c are schematic structural diagrams of the connection line structure of the programmable logic device. As shown in fig. 4a, in the wiring structure of the programmable logic device, the pre-wiring rail is divided into a plurality of rail groups (e.g., rail groups a-D), only the adjacent rails of the same rail group are connected through the programmable transmission gate, for example, the adjacent nets a1-a2, B1-B2, C1-C2, and D1-D2 belonging to the same group can be connected through the programmable transmission gate, and the nets of different groups cannot be connected through the programmable transmission gate. The pre-wiring rails are exemplarily shown in fig. 4a to be divided into four rail groups, and it is understood that in other embodiments of the present application, the pre-wiring rails may be divided into other number of rail groups according to actual needs.

The connectivity rule shown in FIG. 4a does not allow the completion of a net port connection across several different sets of wire tracks. In the basic cell design of current programmable logic devices, the input terminals are all in the form of multiplexers to achieve the programmable requirements. A typical multiplexer design intentionally connects the cell inputs to different sets of traces to provide flexibility in group-to-group selection. However, since the area of the multiplexer is limited, the selection paths that can be provided by the multiplexer are also limited, and in practical applications, it is impossible for the multiplexer at the input end of each cell to accept the paths of all the line rail sets, and only part of the line rail sets can be selectively allowed. For example, as shown in fig. 4B (modified pre-connection of cell accesses), one cell input may be accessed by rail sets a and B, another input may be accessed by a and C, yet another input may be accessed by B and C, and so on. The simplification of the rule of pre-routing rail connectivity undoubtedly reduces the overall system routability, for which we add new multiplexers in each elementary unit, whose role is to switch between different sets of rails, as described below.

As shown in fig. 4c (modified connection of cell access), at least one logic cell of the programmable logic device includes a plurality of multiplexers, each input terminal of a first multiplexer (e.g., the lowest multiplexer shown in fig. 4 c) in the plurality of multiplexers is connected to a wire (e.g., wire a-D shown in fig. 4 c) of the plurality of wire sets, respectively, and an output terminal of the first multiplexer is connected to a wire bus in at least one logic cell (as shown in fig. 4c, other wires in the at least one logic cell may also be connected to the wire bus), and the wire bus is connected to one input terminal of each multiplexer in the other multiplexers. The outputs of the other multiplexers serve as cell inputs (e.g., cell inputs 1-4).

Fig. 4c shows, by way of example, that one input of each of the other multiplexers is connected to the connection bus, and the other two inputs are connected to two lines belonging to different groups. It will be appreciated that in other embodiments of the present application, one input, three inputs or even no input of each multiplexer may be connected to the corresponding rail according to actual needs (e.g. as allowed by the area of each multiplexer).

The wiring structure can be applied to various programmable logic devices including an FPGA, and an input port of at least one net on at least one logic unit and a driving port of the at least one net in the various programmable logic devices do not belong to the same line rail group.

In the connection structure of the programmable logic device according to this embodiment, only the adjacent line rails in the same line rail group are connected through the programmable transmission gate, so that the programmable transmission gate across the line rail group is omitted, the line rails of different line rail groups can be connected to the logic unit by adding a new multiplexer as the line rail group selector, and the connectivity of all the line rail groups is provided, thereby reducing the chip area, power consumption, and manufacturing cost while maintaining the connectivity of each line rail group.

As shown in fig. 4b, before the modification, each input of the cell can only be selectively introduced into the wiring of a partial group of tracks due to the path limitation of the multiplexer; as shown in fig. 4c, after the modification, a new multiplexer (called a track group selector) is added to allow the tracks of different track groups to access the wiring bus in the cell, and then access the wiring bus inside to the input of different cells through the original multiplexer. Each of the added line rail group selectors can provide the connectivity of all line rail groups for an optional unit input, and the problem of cross-line rail group connection of the unit input is solved. Therefore, it is not only easy to use

To further reduce chip area, power consumption, and cost, it is desirable to have the wiring inputs of the basic unit of a programmable logic device belong to the same rail group as possible as the net drive outputs of the basic unit, so as to increase the routing rate of the wiring structure and reduce the number of multiplexers.

The programmable logic device needs to convert different user circuits into different configurations of the logic device and different connections of wiring resources, so as to realize different design requirements of users. Therefore, all programmable logic device design companies provide software development systems based on their own devices for customers. According to the most widely-significant flow division, the software system of the programmable logic device can be divided into: a comprehensive system, a logic optimization system and a physical implementation system. The integrated system is a software tool for converting the design requirements of a user from a general hardware description language into a logic unit which can be supported by a programmable logic device; the logic optimization system reprocesses the synthesized logic units by means of combination, splitting, remapping and the like so as to reduce the number of the logic units, improve the performance of the circuit and reduce the power consumption of the circuit; the physical implementation system configures the final result of the logic optimization into the programmable logic device, and specifically determines the logic state of each programmed bit. It can be further divided into two broad categories, placement system and wiring system.

The layout system places the logic units in the logic optimization result into specific positions of the chip according to the chip architecture, and each logic unit obtains a position which is not overlapped with each other. The configuration of the location should optimize the design performance of the user system as much as possible. The wiring system configures different wiring switches according to the interconnection relation of the logic optimization circuit and the logic unit position determined by the layout so as to realize the signal electrical connection between the logic units. The configuration of the line switch should ensure that different electrical signals are not short-circuited and optimize the design performance of the user system as much as possible. In any circuit net design, the distribution of the wire track groups between the drive port and the input port is very random. In order to improve the routing rate of the wiring structure of the programmable logic device of the present application, we further improve the software system (placement system and routing system) of the conventional programmable logic device in the following embodiments, and consider the problem of matching the line-rail groups between the driver ports and the input ports.

The second embodiment of the invention relates to a layout method of a programmable logic device. Fig. 6 is a flow chart illustrating a layout method of the programmable logic device.

The second embodiment is improved on the basis of the first embodiment, and the main improvement lies in that: in the layout method of the programmable logic device, the line track alignment cost is added into the total cost of detailed layout, so that the line track group matching between the input port and the driving port of a line network can be improved, the wiring rate of a connecting line structure is improved, the use number of multiplexers is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced. Specifically, the method comprises the following steps:

the flow of a standard layout system can be roughly divided into two steps of general layout and detailed layout, and the explanatory diagrams thereof are shown in fig. 5a to 5 d. Wherein FIG. 5a shows a circuit design of a user; fig. 5b shows that the user logic has been converted into the logic cells (lookup tables Lut1, Lut2, and Lut 3) of the programmable logic device before layout, and as shown in fig. 5b, the physical cells (16 slots) on the programmable logic device do not correspond to the logic cells yet; FIG. 5c shows the overall layout, i.e., the placement of user logic cells into the general location of the programmable logic device according to the user's design needs; fig. 5d shows a detailed layout, i.e. the accurate placement of the user logic cells onto the programmable logic device according to the location information of the overall layout.

Before layout begins, the front-end synthesis software of the programmable logic device converts the user's circuit (as shown in fig. 5 a) into various logic gates (as shown in fig. 5 b) supported by the programmable logic device, and the layout function is to further place the logic gates at reasonable positions of the device, so that the performance of the user's circuit is optimized. The overall layout (as shown in fig. 5 c) typically employs a mathematically optimized algorithm to determine the optimal area on the programmable logic device where each user logic gate should be, and the detailed layout (as shown in fig. 5 d) will precisely place the logic gates at the programmable gates of the programmable logic device, in particular, according to the results of the overall layout. There are also a few layout systems with only detailed layouts, no overall layouts, which are represented by the layout system based on the simulated annealing method: each user logic gate is firstly placed on a programmable gate of a programmable logic device, and then the performance of a user circuit is optimized through means of unit movement, unit interchange and the like.

While the present application simplifies the wiring structure of the programmable logic device (e.g., the wiring structure of the first embodiment), the present application improves the detailed layout system to increase the routability of the nets. There is a commonality in the various detailed layout systems that the system will evaluate the cost of each custom logic cell being placed on the programmable gates of different programmable logic devices, and then the sum of the costs of all cell placements will be minimal without any two custom logic cells occupying the same programmable gate. It is expressed as follows:

f (layout) ═ min Σ F (cell i), st. no overlap of the position of any cell i and cell j is usually defined as related to the result of the overall layout, with larger differences between the results of cell i and the overall layout, higher costs. In order to improve the connection communication degree, the cost of aligning the connection track groups of the units at different positions should be increased in the cost of the units. However, since all units are in motion, the alignment cost of the wire track is very difficult to calculate. For this purpose, the following processing methods are proposed:

with the wiring structure of the first embodiment adopted in the programmable logic device, as shown in fig. 6, the layout method includes the following steps:

in step 601, before detailed layout, each net is randomly assigned with a target line track group, each line track group corresponds to an average number of nets, that is, each line track group obtains an average number of nets (a net is a port connection between logic cells and is on). For example, if there are 100 nets and 4 line rail groups, each line rail group gets 25 nets after randomly allocating the target line rail group to each net, and each line rail group in the line rail group A, B, C, D gets 25 nets as an example of 4 line rail groups in fig. 4 a. It is understood that in other embodiments of the present application, different weights may be used for assigning or other assigning manners to each line track group, as long as line track alignment is facilitated.

Step 602 is then entered to perform a detailed layout of the programmable logic device such that the sum of the costs of placing all logic cells is minimized. Wherein the cost sum includes a line track alignment cost per logic cell, the line track alignment cost per logic cell is a sum of line track alignment costs for all ports of each logic cell when each logic cell is placed in a corresponding programmable gate position of the programmable logic device (e.g., a sum of line track alignment costs for three ports when logic cell LUT1 in FIG. 5d is placed in a Slot10 position),

if the set of line tracks of the port of the net on the logic unit at the corresponding programmable gate position is consistent with the target set of line tracks allocated to the net, the line track alignment cost of the port is zero (for example, if the output port of the LUT1 in fig. 5d belongs to the set of line tracks when the LUT1 is placed at the Slot10 position, and the set of line tracks allocated to the net on the output port in the step 601 is also a, the line track alignment cost of the output port is zero);

if the set of line tracks of a port of a net on the logic cell at the corresponding programmable gate position does not coincide with the target set of line tracks assigned by the net, the line track alignment cost for the port is a first predetermined positive number (e.g., the line track set to which the output port of the LUT1 in fig. 5d belongs when the LUT1 is placed at the Slot10 position is a, and the line track set assigned by the net on the output port in step 601 is B, the line track alignment cost for the output port is 5).

If the line track alignment costs of the three ports of the LUT1 are 5, 0, and 5, respectively, the line track alignment cost of the logic unit LUT1 is 10; if the line track alignment costs of

LUTs

1, 2, and 3 are 10, 5, and 15, respectively, then a line track alignment cost of 30 is added to the total cost. In the above example, the first predetermined positive number is shown as 5, and it is understood that the first predetermined positive number can be set to other positive values according to actual needs in other embodiments of the present application.

That is, the target of the detailed layout is modified as shown below:

f (layout) ═ min ∑ (F (cell i)) + g (cell i, st. no overlap in the position of any cell i and cell j

Wherein: g (cell i) ═ Σ g (cell i, net j)

The added g (cell i) of each cell is the sum of the alignment cost of all the ports of the cell in the programmable gate position of a certain device. The alignment cost of the wire track is designed as follows:

here, a certain reasonable positive number corresponds to the first predetermined positive number, and the first predetermined positive number may be set according to actual needs.

It can be seen from the above that the layout is optimized by pre-distributing the wiring net to different tracks during detailed layout and adding this information to the cost calculation of the subscriber unit for different device programmable gate positions.

The third embodiment of the invention relates to a layout method of a programmable logic device. Fig. 7 is a flow chart illustrating a layout method of the programmable logic device.

The third embodiment is an improvement on the first embodiment, and the main improvement lies in that: in the layout method of the programmable logic device, after the detailed layout, the logic unit is further adjusted by adding the alignment cost of the wire track to the sum of the cost of the detailed layout, so that the wire track group matching between the input port and the driving port of a wire network can be improved, the wiring rate of a wiring structure is improved, the using number of multiplexers is reduced, and the area, the power consumption and the manufacturing cost of a chip are further reduced. Specifically, the method comprises the following steps:

with the wiring structure of the first embodiment adopted in a programmable logic device, as shown in fig. 7, the layout method includes the following steps:

in step 701, after the programmable logic device is laid out in detail, the sum of the costs of placing all logic cells is minimized by moving and/or interchanging the logic cells.

Wherein the cost sum comprises a line-track alignment cost per logic cell, the line-track alignment cost per logic cell being the sum of the line-track alignment costs of all input ports per logic cell when each logic cell is placed in a corresponding programmable gate position of the programmable logic device (e.g., the sum of the line-track alignment costs of two input ports when logic cell LUT1 in fig. 5d is placed in Slot10 position),

if the input port of a net on a logic unit and the drive port of the net belong to the same line-track group, the line-track alignment cost of the input port is zero (for example, if one input port of the LUT1 in fig. 5d belongs to the line-track group a when the LUT1 is placed at the Slot10, and the line-track group to which the drive port of the net on the one input port belongs is also a, the line-track alignment cost of the one input port is zero);

if the input port of a net on a logic unit and the drive port of that net belong to different sets of line tracks, the line track alignment cost of the input port is a second predetermined positive number (e.g., if one input port of the LUT1 in fig. 5d belongs to a set of line tracks when the LUT1 is placed at the Slot10 position, and the drive port of the net on that one input port belongs to a set of line tracks is B, the line track alignment cost of that one input port is 3).

If the line track alignment costs of the two input ports of the LUT1 are 3 and 0, respectively, the line track alignment cost of the logic unit LUT1 is 3; if the line track alignment costs of LUT1, LUT2, LUT3 are 3, 0, 6, respectively, a line track alignment cost of 9 is added to the sum of the costs. In the above example, the second predetermined positive number is shown as 3, it is understood that in other embodiments of the present application, the second predetermined positive number may be set to other positive values according to actual needs, and the second predetermined positive number may be the same as or different from the first predetermined positive number.

From the above, it can be seen that, unlike the layout method of the second embodiment of the present application, after the above detailed layout is completed, since each user logic unit has a certain position, we can release the constraint of pre-wiring tracks of the net, select any logic unit, and recalculate the cost of aligning the line tracks:

f (layout) ═ min ∑ (F (cell i) + g (cell i)), st. no overlapping of the positions of any cell i and cell j

g (cell i) ═ Σ g (cell i, net j), the port of net j on the cell i is the input port

Wherein a positive number here corresponds to the second predetermined positive number.

With the new cost mode, the line rail alignment degree of the layout result can be further improved by moving and interchanging the user logic unit in a local area or adopting a low-temperature simulated annealing mode. That is, after the detailed layout is finished, the matching degree of the line track group of each net is recalculated, and the line track group matching is improved through the small-range movement and exchange of the units so as to optimize the layout. It is understood that any existing move, swap method (e.g., low temperature simulated annealing, etc.) may be used to move, swap logic cells, so long as the sum of the costs of using the new approach is minimized.

A fourth embodiment of the present invention relates to a wiring method of a programmable logic device. Fig. 9 is a flowchart illustrating a wiring method of the programmable logic device.

The fourth embodiment is an improvement on the first embodiment, and the main improvement lies in that: in the wiring method of the programmable logic device, the input port is exchanged by reconfiguring the built-in lookup table of the programmable gate and the connection information of the net, so that the line-rail group alignment degree of the net can be improved, the wiring rate of the wiring structure is improved, the use number of the multi-path selectors is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced. Specifically, the method comprises the following steps:

in addition to layout improvement, the application also designs a method for exchanging input ports of the programmable units by utilizing the port equivalent characteristics of the FPGA programmable units so as to increase the system distribution. The port equivalent nature of the FPGA programmable cell can be illustrated with reference to figures 8a-8 b.

The programmable gate of the FPGA realizes the logic function of any input by converting an input port into corresponding address information through a built-in lookup table and then searching a prestored lookup table value. Therefore, when the input port is switched, the logic function equivalent to that before the port switching can be obtained only by storing the data again in the built-in lookup table of the programmable gate according to the corresponding address change information. We can map the net connectivity (i.e., the original net connectivity) of fig. 8a to the connectivity of fig. 8b (the ports can be switched to obtain a new equivalent connection), and then obtain equivalent logic functions by reconfiguring the values of the lookup tables in the programmable gates.

The wiring structure of the first embodiment is employed in a programmable logic device, the programmable logic device is a field programmable gate array device, and as shown in fig. 9, the wiring method includes the steps of:

in step 901, before routing, input ports are exchanged by reconfiguring lookup tables built in programmable gates of the programmable logic device and connection information of nets so that the input port of each net is within the same group of wire rails as much as possible as its driving port.

After that, the wiring is performed on the programmable logic device.

In step 901, input ports are swapped according to the following:

if the drive port of the first net does not belong to the same set of line rails as the first input port of the first net at the programmable gate position, the second input port at the programmable gate position is an idle port and belongs to the same set of line rails as the drive port of the first net, the configuration modifications required to swap the first input port and the second input port are made in a look-up table built into the programmable gate, and modifying the first input port of the first net at the programmable gate position into a second input port in the connection information of the first net (for example, if the driving port of the net 1 belongs to a line-rail group C, the first input port of the net 1 at the programmable gate position belongs to a line-rail group a, and the second input port at the programmable gate position is an idle port and belongs to a line-rail group C, the first input port and the second input port are exchanged, so that the driving port and the input port of the net 1 belong to the same line-rail group).

If the driving port of the first net and the first input port of the first net at the programmable gate position do not belong to the same line track group and the second input port of the second net at the programmable gate position and the driving port of the first net belong to the same line track group, judging whether the second input port of the second net at the programmable gate position and the driving port of the second net belong to the same line track group, if not, performing configuration modification required for exchanging the first input port and the second input port in a look-up table built in the programmable gate, modifying the first input port of the first net at the programmable gate position into the second input port in the connection information of the first net, modifying the second input port of the second net at the programmable gate position into the first input port in the connection information of the second net (for example, the driving port of net 1 belongs to line track group B, a first input port of the net 1 at the programmable gate position belongs to the line and rail group a, a second input port of the net 2 at the programmable gate position belongs to the line and rail group B, and a driving port of the net 2 does not belong to the line and rail group B, the first input port and the second input port are exchanged, so that the driving port of the net 1 and the input port belong to the same line and rail group), otherwise, the exchange is not performed.

That is, after the layout is completed, all nets have the line track group allocation of the driving port and the input port. When the line track group where the driving port and part (or all) of the input ports are located are different, we can adjust as many input ports as possible into the line track group where the driving port is located by exchanging the input ports. The exchange is carried out according to the following steps:

exchanging targets: net i is to be switched on to the destination line track group k at the port of cell j.

The exchange mode is as follows: 1. the port m on element j belonging to the group k of line rails does not belong to any other net, then we directly swap the input port of net i on element j to port m.

2. Port m on cell j, which belongs to line track group k, has connected net n, then both ports are switched if the input ports of switch nets i and n on cell j do not cause the line track group alignment of net n to deteriorate.

3. Other case exchanges cannot occur.

From the above, it can be seen that the wire track group matching of nets is improved by exchanging the correspondence between the ports of the programmable gates and the nets after the placement is finished and before the routing is started, so as to optimize the subsequent routing.

A fifth embodiment of the present invention relates to a wiring method for a programmable logic device. Fig. 10 and 11a-11c are flow diagrams of a routing method for the programmable logic device.

The fifth embodiment is an improvement on the first embodiment, and the main improvement lies in that: in the wiring method of the programmable logic device, the input port is exchanged by reconfiguring the built-in lookup table of the programmable gate and the connection information of the net, so that the line-rail group alignment degree of the net can be improved, the wiring rate of the wiring structure is improved, the use number of the multi-path selectors is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced. Specifically, the method comprises the following steps:

to further increase the alignment of the net tracks after placement by way of port swapping. Our improvements to wiring are deep inside the wiring. When a certain net is wired, all the programmable gates where the input ports are located are traversed, and the connecting line rails from the vacant ports on the programmable gates to the target ports are virtualized, so that the wiring can be connected with the target ports through any vacant port.

The wiring structure of the first embodiment is employed in a programmable logic device, the programmable logic device is a field programmable gate array device, and as shown in fig. 10, the wiring method includes the steps of:

in step 1001, if the target input port of the wired net at the corresponding programmable gate position of the programmable logic device and the driving port of the wired net do not belong to the same line rail group, it is determined whether there is a vacant input port at the corresponding programmable gate position.

If there is a vacant input port at the corresponding programmable gate position, then go to step 1002, otherwise go to step 1005.

In step 1002, the connections of all the vacant input ports at the corresponding programmable gate positions to the target input port are virtualized. It is understood that the virtualization herein is well known to those skilled in the art and will not be described in detail herein.

Then, step 1003 is performed, it is determined whether there is a first idle input port belonging to the same line track group as the driving port of the net in all the idle input ports at the corresponding programmable gate position, if yes, step 1004 is performed, otherwise, step 1005 is performed.

In step 1004, configuration modifications required to swap the target input port with the first vacant input port are made in a lookup table built into the corresponding programmable gate, and the net is connected to the first vacant input port.

In step 1005, a net is connected to the target input port.

As shown in FIG. 11a, in the initial wiring relationship, net 1 is connected to input port A, net 2 is connected to input port B, and ports C and D are left empty. When we want to connect net 1, we have virtualized the connection rail from port C to A, and the connection rail from port D to A as shown in FIG. 11 (b). We then route net 1 and in the example we find a connection path through port D to a. After the connection is successful, the virtual line track 'D- > A' is cleared through the switching ports A and D by utilizing the characteristic of programmable gate input switching, and the line track alignment of the line network 1 is completed.

From the above, it can be seen that in the process of wiring, by virtualizing a wire rail from the vacant port of the programmable gate to the wiring target port, the wiring can realize connection and port exchange through the vacant port when necessary, so as to perform wiring optimization.

The embodiments are combined to form a preferred embodiment of the present invention (for example, the second embodiment and the third embodiment are combined to form a layout method, and/or the fourth embodiment and the fifth embodiment are combined to form a wiring method), but the embodiments may be used separately.

By combining a series of layout and wiring improvements, the connection effect similar to the original structure can be realized under the condition of simplifying the connection structure of the programmable logic device. And the device area, the power consumption and the manufacturing cost of the smaller programmable logic device are obtained through the cooperative adjustment of hardware and software.

The method embodiments of the present invention may be implemented in software, hardware, firmware, etc. Whether the present invention is implemented as software, hardware, or firmware, the instruction code may be stored in any type of computer-accessible memory (e.g., permanent or modifiable, volatile or non-volatile, solid or non-solid, fixed or removable media, etc.). Also, the Memory may be, for example, Programmable Array Logic (PAL), Random Access Memory (RAM), Programmable Read Only Memory (PROM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), a magnetic disk, an optical disk, a Digital Versatile Disk (DVD), or the like.

A sixth embodiment of the present invention relates to a layout system of a programmable logic device. Fig. 12 is a schematic diagram of the structure of the layout system of the programmable logic device.

The sixth embodiment is an improvement on the first embodiment, and the main improvement lies in that: in the layout system of the programmable logic device, the line track alignment cost is added into the cost sum of detailed layout, so that the line track group matching between the input port and the driving port of a line network can be improved, the wiring rate of a connecting line structure is improved, the using number of multiplexers is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced. Specifically, the method comprises the following steps:

in a programmable logic device employing the wiring structure of the first embodiment, as shown in fig. 12, a layout system includes:

and the detailed layout module is used for performing detailed layout on the programmable logic device so that the sum of the cost for placing all the logic units is minimum.

The second embodiment is a method embodiment corresponding to the present embodiment, and the present embodiment can be implemented in cooperation with the second embodiment. The related technical details mentioned in the second embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the second embodiment.

A seventh embodiment of the present invention relates to a layout system of a programmable logic device. Fig. 13 is a schematic diagram of the structure of the layout system of the programmable logic device.

The seventh embodiment is an improvement on the first embodiment, and the main improvement lies in that: in the layout system of the programmable logic device, after detailed layout, the logic unit is further adjusted by adding the alignment cost of the wire track to the sum of the cost of the detailed layout, so that the wire track group matching between the input port and the driving port of a wire network can be improved, the wiring rate of a wiring structure is improved, the using number of multiplexers is reduced, and the area, the power consumption and the manufacturing cost of a chip are further reduced. Specifically, the method comprises the following steps:

in a programmable logic device employing the wiring structure of the first embodiment, as shown in fig. 13, a layout system includes:

and the mobile interchange module is used for minimizing the sum of the cost for placing all the logic units by moving and/or interchanging the logic units after the programmable logic device is subjected to detailed layout.

The third embodiment is a method embodiment corresponding to the present embodiment, and the present embodiment can be implemented in cooperation with the third embodiment. The related technical details mentioned in the third embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the third embodiment.

An eighth embodiment of the present invention relates to a wiring system of a programmable logic device. Fig. 14 is a schematic diagram of the structure of the wiring system of the programmable logic device.

The eighth embodiment is an improvement on the first embodiment, and the main improvement is that: in a wiring system of a programmable logic device, an input port is exchanged by reconfiguring a built-in lookup table of a programmable gate and connection information of a net, and the alignment degree of the line track group of the net can be improved, so that the wiring rate of a wiring structure is improved, the use number of multiplexers is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced. Specifically, the method comprises the following steps:

the wiring structure of the first embodiment is employed in a programmable logic device, which is a field programmable gate array device, and as shown in fig. 14, the wiring system includes:

and the wiring module is used for wiring the programmable logic device.

The switching module switches the input ports according to the following modes:

The fourth embodiment is a method embodiment corresponding to the present embodiment, and the present embodiment and the fourth embodiment can be implemented in cooperation with each other. The related technical details mentioned in the fourth embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the fourth embodiment.

A ninth embodiment of the present invention relates to a wiring system of a programmable logic device. Fig. 15 is a schematic diagram of the structure of the wiring system of the programmable logic device.

The ninth embodiment is an improvement on the first embodiment, and the main improvement lies in that: in a wiring system of a programmable logic device, an input port is exchanged by reconfiguring a built-in lookup table of a programmable gate and connection information of a net, and the alignment degree of the line track group of the net can be improved, so that the wiring rate of a wiring structure is improved, the use number of multiplexers is reduced, and the chip area, the power consumption and the manufacturing cost are further reduced. Specifically, the method comprises the following steps:

the wiring structure of the first embodiment is employed in a programmable logic device, which is a field programmable gate array device, and as shown in fig. 15, the wiring system includes:

the virtual module is used for virtualizing the connection between all the idle input ports on the corresponding programmable door position and the target input port if the first judging module determines that the idle input ports exist on the corresponding programmable door position;

The fifth embodiment is a method embodiment corresponding to the present embodiment, and the present embodiment and the fifth embodiment can be implemented in cooperation with each other. The related technical details mentioned in the fifth embodiment are still valid in this embodiment, and are not described herein again to reduce the repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the fifth embodiment.

Further, the above embodiments may be implemented in cooperation with each other. The related technical details mentioned in any embodiment are still valid in other embodiments, and are not described herein again in order to reduce repetition.

In summary, the application uses fewer transmission gates, and obtains the effect similar to that of a device with more transmission gates and high communication through a series of layout design changes, layout method adjustment and wiring method adjustment, thereby effectively reducing the manufacturing cost of the device. Compared with the pre-wiring rail connection relation of other programmable logic devices at present, the simplified connection mode can meet the logic and time sequence requirements of a designed circuit through software and hardware coordination optimization, and meanwhile, the generated connection devices are the least, so that the area of the programmable logic device is the smallest, the power consumption is the lowest, and the manufacturing cost is the lowest.

It should be noted that, in each device embodiment of the present invention, each module is a logic module, and physically, one logic module may be one physical module, or may be a part of one physical module, or may be implemented by a combination of multiple physical modules, and the physical implementation manner of the logic modules itself is not the most important, and the combination of the functions implemented by the logic modules is the key to solve the technical problem provided by the present invention. Furthermore, in order to highlight the innovative part of the present invention, the above-mentioned embodiments of the device of the present invention do not introduce modules which are not so closely related to solve the technical problems proposed by the present invention, which does not indicate that there are no other modules in the above-mentioned embodiments of the device.

It is to be noted that in the claims and the description of the present patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A connecting line structure of a programmable logic device is characterized in that pre-wiring tracks are divided into a plurality of line track groups, and only adjacent line tracks of the same line track group are connected through a programmable transmission gate;

at least one logic unit of the programmable logic device comprises a plurality of multiplexers, wherein each input end of a first multiplexer in the plurality of multiplexers is respectively connected with the line rails of the plurality of line rail groups, the output end of the first multiplexer is connected to a connection bus in the at least one logic unit, and the connection bus is connected with one input end of each multiplexer in other multiplexers;

the input port of at least one net on the at least one logic unit and the drive port of the at least one net do not belong to the same line rail group.

2. A layout method of a programmable logic device in which the wiring structure of claim 1 is employed, the layout method comprising the steps of:

wherein the cost sum includes a line alignment cost per logic cell, the line alignment cost per logic cell being the sum of the line alignment costs for all ports per logic cell when each logic cell is placed in a corresponding programmable gate position of the programmable logic device,

if the line track group of the port of the net on the logic unit at the corresponding programmable gate position is not consistent with the target line track group allocated by the net, the line track alignment expense of the port is a first preset positive number.

3. A layout method of a programmable logic device in which the wiring structure of claim 1 is employed, the layout method comprising the steps of:

wherein the cost sum comprises a line-track alignment cost per logic cell, the line-track alignment cost per logic cell being the sum of the line-track alignment costs of all input ports per logic cell when each logic cell is placed in a corresponding programmable gate position of the programmable logic device,

if the input port of the net on the logic unit and the drive port of the net belong to different line track groups, the line track alignment cost of the input port is a second preset positive number.

4. A wiring method of a programmable logic device in which the wiring structure of claim 1 is employed, the programmable logic device being a field programmable gate array device, the wiring method comprising the steps of:

before wiring, input ports are exchanged by reconfiguring a lookup table and connection information of a wire net which are arranged in a programmable gate of the programmable logic device;

wherein the input ports are swapped according to the following:

if the drive port of a first net and the first input port of the first net on a programmable gate position do not belong to the same line track group, the second input port on the programmable gate position is an idle port and the drive port of the first net belongs to the same line track group, carrying out configuration modification required for exchanging the first input port and the second input port in a lookup table built in the programmable gate, and modifying the first input port of the first net on the programmable gate position into the second input port in the connection information of the first net;

if the drive port of a first net and the first input port of the first net at a programmable door position do not belong to the same line track group and the second input port of a second net at the programmable door position and the drive port of the first net belong to the same line track group, judging whether the second input port of the second net at the programmable door position and the drive port of the second net belong to the same line track group, if not, performing configuration modification required for exchanging the first input port and the second input port in a lookup table built in the programmable door, modifying the first input port of the first net at the programmable door position into the second input port in connection information of the first net, and modifying the second input port of the second net at the programmable door position into the first input port in connection information of the second net, otherwise, no swap is performed.

5. A wiring method of a programmable logic device in which the wiring structure of claim 1 is employed, the programmable logic device being a field programmable gate array device, the wiring method comprising the steps of:

if the target input port of the wired net at the corresponding programmable gate position of the programmable logic device and the driving port of the wired net do not belong to the same line rail group, judging whether an idle input port exists at the corresponding programmable gate position;

if the corresponding programmable gate position has a null input port, virtualizing the connection between all null input ports on the corresponding programmable gate position and the target input port, otherwise, connecting the wire net to the target input port;

and judging whether a first idle input port belonging to the same line rail group as the driving port of the line network exists in all idle input ports on the corresponding programmable door position, if so, carrying out configuration modification required for exchanging a target input port and the first idle input port in a lookup table built in the corresponding programmable door, and connecting the line network to the first idle input port, otherwise, connecting the line network to the target input port.

6. A layout system for a programmable logic device in which the wiring structure of claim 1 is employed, the layout system comprising:

the detailed placement module calculates a lane alignment cost for the port of each logic cell according to the following:

if the group of line tracks of a port of a net on a logic unit at the corresponding programmable gate position is not consistent with the target group of line tracks assigned to the net by the assignment module, the line track alignment cost of the port is a first predetermined positive number.

7. A layout system for a programmable logic device in which the wiring structure of claim 1 is employed, the layout system comprising:

the mobile interchange module is used for enabling the sum of the cost for placing all the logic units to be minimum by moving and/or interchanging the logic units after the programmable logic device is subjected to detailed layout;

8. A wiring system of a programmable logic device in which the wiring structure of claim 1 is employed, the programmable logic device being a field programmable gate array device, the wiring system comprising:

the switching module is used for switching the input port by reconfiguring a lookup table and connection information of a wire net built in a programmable gate of the programmable logic device before wiring; and

the wiring module is used for wiring the programmable logic device;

wherein the switching module switches input ports according to the following manner:

if the drive port of a first net and the first input port of the first net on a programmable door position do not belong to the same line track group and the second input port of a second net on the programmable door position and the drive port of the first net belong to the same line track group, judging whether the second input port of the second net on the programmable door position and the drive port of the second net belong to the same line track group, if not, carrying out configuration modification required for exchanging the first input port and the second input port in a lookup table built in the programmable door, modifying the first input port of the first net on the programmable door position into the second input port in the connection information of the first net, and modifying the second input port of the second net on the programmable door into the first input port in the connection information of the second net, otherwise, no swap is performed.

9. A wiring system of a programmable logic device in which the wiring structure of claim 1 is employed, the programmable logic device being a field programmable gate array device, the wiring system comprising:

the first judgment module is used for judging whether a vacant input port exists at the corresponding programmable gate position when a target input port of a wired network at the corresponding programmable gate position of the programmable logic device and a driving port of the wired network do not belong to the same line track group;

the virtual module is used for virtualizing the connection between all the idle input ports at the corresponding programmable door position and the target input port if the first judging module determines that the idle input ports exist at the corresponding programmable door position;

the switching module is configured to, if the second determining module determines that the first vacant input port exists, perform configuration modification required for switching the target input port and the first vacant input port in the lookup table built in the corresponding programmable gate; and

a connection module to connect the net to the target input port when the first determination module determines that no idle input port exists at the corresponding programmable door position or the second determination module determines that the first idle input port does not exist, and to connect the net to the first idle input port when the first determination module determines that an idle input port exists at the corresponding programmable door position and the second determination module determines that the first idle input port exists.