CN112115667B

CN112115667B - FPGA layout method, device, electronic equipment and computer readable medium

Info

Publication number: CN112115667B
Application number: CN202010779209.8A
Authority: CN
Inventors: 刘世仁; 谭宇泉; 夏炜
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Filing date: 2020-08-05
Publication date: 2024-07-12
Anticipated expiration: 2040-08-05

Abstract

The embodiment of the application provides an FPGA layout method, an FPGA layout device, electronic equipment and a computer readable medium, wherein the method comprises the following steps: performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result; acquiring the time allowance of each path, and taking a path with the time allowance smaller than a time threshold as a first path; determining a first logic unit on the first path, and searching a second logic unit positioned on a second path according to the first logic unit; if a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit positioned on a third path; and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit. The application effectively shortens the circuit connection length and reduces the time sequence delay of the circuit by acquiring the third logic unit when the logic unit block exists between the first logic unit and the second logic unit.

Description

FPGA layout method, device, electronic equipment and computer readable medium

Technical Field

Embodiments of the present application relate to the field of integrated circuit design, and in particular, but not limited to, an FPGA layout method, apparatus, electronic device, and computer readable medium.

Background

An FPGA (Field-Programmable gate array) is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurable capability, and these features make the FPGA increasingly widely used in many fields such as data processing, communication, networks, etc.

With the expansion of the chip scale of the FPGA, the layout of the chip becomes more critical and important, and the complexity of the chip wiring and the success rate of the wiring are directly determined, and the area, frequency and other performances of the chip are affected. Therefore, comprehensive consideration of various costs is needed in the chip layout, and how to better layout the FPGA under the condition of meeting various constraints is a problem to be solved.

Disclosure of Invention

The FPGA layout method, the device, the electronic equipment and the computer readable medium mainly solve the technical problem of how to reduce the time sequence delay time of the FPGA circuit and improve the working efficiency of the FPGA circuit.

In a first aspect, an embodiment of the present application provides an FPGA layout method, where the method includes: performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit; obtaining a time margin of each path, and taking a path with the time margin smaller than a time threshold as a first path, wherein the time margin of the path is a difference value between consumed time of a circuit signal transmitted from a starting point of the path to an end point of the path and the time threshold; determining a first logic unit on the first path, and searching a second logic unit positioned in a second path according to the first logic unit, wherein the time allowance of the second path is larger than that of the first path; if a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit positioned on a third path, wherein the third logic unit and the first logic unit are positioned on the same side of the logic unit block; and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit.

Optionally, after searching the second logic unit located in the second path according to the first logic unit, the method includes: acquiring a cost value of the second logic unit, wherein the cost value is used for representing the time sequence characteristic corresponding to the second logic unit; and when the cost value of the second logic unit is larger than a cost threshold value, judging whether a logic unit block exists between the second logic unit and the first logic unit.

Optionally, the second logic unit includes a plurality of logic subunits, each logic subunit corresponds to a sub-path, and obtaining the cost value of the second logic unit includes: obtaining time allowance of a critical sub-path and a non-critical sub-path corresponding to the second logic unit; and acquiring the cost value of the second logic unit according to the time allowance of the critical sub-path and the non-critical sub-path corresponding to the second logic unit.

Optionally, the calculation formula of the cost value is as follows:

wherein Cost _site is a Cost value, W is a weight factor, slack _{critical_inst} and For the time allowance of the critical sub-path and the non-critical sub-path corresponding to the same logic unit, the value of slot _wors+margint is the sum of the minimum time allowance value and the empirical value in the FPGA, margin is the empirical value, and k is the number of the non-critical sub-paths.

Optionally, searching for the second logic unit located in the second path according to the first logic unit includes: judging whether the first path or the first logic unit meets a preset condition; and if the preset condition is met, not executing the searching operation of the second logic unit.

Optionally, determining whether the first path or the first logic unit meets a preset condition includes: judging whether the first logic unit is positioned on different paths or not; and/or determining whether the first path is located on a loop circuit; and/or judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units.

Optionally, the searching the second logic unit located in the second path according to the first logic unit includes: determining a first position of the first logic unit, and determining a search range according to the first position; and determining a second logic unit meeting preset conditions in the searching range.

In a second aspect, an embodiment of the present application further provides an FPGA layout apparatus, where the apparatus includes: the system comprises an initial layout module, a first path acquisition module, a first search module, a second search module and a unit exchange module. The initial layout module is used for carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit; the first path acquisition module is used for acquiring the time allowance of each path and taking a path with the time allowance smaller than a time threshold as a first path, wherein the time allowance of the path is the difference value between the consumed time of the circuit signal transmitted from the starting point of the path to the end point of the path and the time threshold; the first searching module is used for determining a first logic unit on the first path and searching a second logic unit positioned in a second path according to the first logic unit, and the time allowance of the second path is larger than that of the first path; the second searching module is used for acquiring a third logic unit positioned on a third path if a logic unit block exists between the second logic unit and the first logic unit, and the third logic unit and the first logic unit are positioned on the same side of the logic unit block; the unit exchange module is used for replacing the logic unit on the first path with a third logic unit and replacing the logic unit on the third path with the first logic unit.

In a third aspect, an embodiment of the present application provides an electronic device, including: one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications configured to perform the method provided in the first aspect above.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium having stored therein program code that is callable by a processor to perform the method provided in the first aspect above.

The method can effectively reduce the time sequence delay time of the FPGA circuit by exchanging the obtained third logic unit with the first logic unit, so as to improve the working efficiency of the circuit. The application effectively shortens the circuit connection length and reduces the time sequence delay of the circuit by acquiring the third logic unit when the logic unit block exists between the first logic unit and the second logic unit.

Additional features and corresponding advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a flow chart of an FPGA layout method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a grid in an FPGA layout method according to an embodiment of the present application;

fig. 3 is a schematic flow chart of step S130 in an FPGA layout method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a logic cell block existing between a first logic cell and a second logic cell in an FPGA layout method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a relationship between a first logic unit and a second logic unit in an FPGA layout method according to an embodiment of the present application;

FIG. 6 is a schematic diagram illustrating the switching between the first logic unit and the second logic unit in an FPGA layout method according to an embodiment of the present application;

FIG. 7 is a flowchart of an FPGA layout method according to another embodiment of the present application;

FIG. 8 is a block diagram of an FPGA layout device according to an embodiment of the present application;

FIG. 9 is a block diagram of an electronic device according to an embodiment of the present application;

Fig. 10 is a block diagram of a computer readable storage medium according to an embodiment of the present application.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

The FPGA chip mainly comprises a programmable unit, an input/output unit and programmable wiring resources, in the prior art, people mainly utilize a software development tool of the FPGA to sequentially perform logic synthesis, layout wiring and configuration bit stream generation on application design, then compile a logic circuit program written in a hardware description language and generate a bit stream download file for configuring the chip, and finally download the file onto the chip to construct a circuit capable of realizing corresponding logic functions. The number of logic units of the existing FPGA reaches the hundred million levels, namely, the existing FPGA has more resources and large programs, so that the compiling and running time of a software tool is continuously increased, further, the application and development efficiency of the FPGA is too low, and therefore, the reduction of the time sequence delay time of an FPGA circuit and the improvement of the working speed of the circuit become keys of the design of the FPGA circuit. In the workflow of FPGA software, it can be determined by layout which logic units are used to implement the circuit functions of the user, i.e., the layout processing effect affects the software compilation run time and the timing of the FPGA circuit to a great extent.

In the prior art, positions on a chip are required to be continuously traversed in an iterative mode so as to find a placement position meeting the requirements, but most candidate positions cannot pass legal detection due to design per se, resource limitation and the like in an expanded iterative process, so that legal positions are required to be continuously searched in a larger range; or the need to remove and re-layout a large number of placed logic cells in performance optimization of each logic cell block can result in excessively long software tool compile time. In addition, when logic cells on both sides of one large logic cell block are connected, the timing delay of the circuit is relatively large because of limitation of wiring resources.

In order to solve the above problems, the inventor proposes an FPGA layout method, an apparatus, an electronic device, and a computer readable medium according to an embodiment of the present application, where the embodiment of the present application effectively shortens a circuit connection length and reduces a timing delay of a circuit by acquiring a third logic unit.

Referring to fig. 1, a flowchart of a method for layout of an FPGA according to an embodiment of the application is shown, where the method includes steps S110 to S140.

Step S110: and carrying out initial layout on the FPGA according to the global layout algorithm to obtain an initial layout result.

In some embodiments, the global layout algorithm calculates the optimal layout scheme of the FPGA according to the circuit parameter requirements and the circuit optimization method, so that the logic unit (Instance) designed by the user can be placed at an ideal position of the chip, and the ideal position can be called as an initial placement position. Obviously, after the FPGA is initially laid out by using the global layout algorithm, an initial position can be allocated to logic units designed by a user, and the initial positions of the logic units can form an initial layout result.

As a way, when the global layout algorithm is used to perform initial layout on the FPGA, the chip resources of the FPGA may be first uniformly divided into a plurality of logic unit blocks, where the logic unit blocks may further include a plurality of logic units, and a resource grid table may be formed through the initial layout, where the resource grid table is used to describe a two-dimensional distribution position of each logic unit in the chip, that is, the position of the logic unit may be represented by two-dimensional coordinates. The resource grid representation intention is shown in fig. 2, and it can be known from fig. 2 that before the initial layout is performed, the FPGA chip needs to be uniformly divided into a plurality of grids, and each grid can be correspondingly provided with a different Instance.

As a way, the embodiment of the application can utilize a global layout algorithm to lay out the circuit designed by the user, so as to obtain an initial layout result. Specifically, a circuit for obtaining a user input may include a plurality of logic units (instances), and then performing an initial layout on the plurality of instances, that is, assigning a chip placement location to each Instance, where the placement location may be referred to as an initial placement location of the logic unit. For ease of description, the present application refers to Instance as a logical unit, which may also be referred to as a logical unit in a user design program, each logical unit may include a plurality of logical subunits.

In some embodiments, an FPGA is initially laid out according to a global layout algorithm, and after an initial layout result is obtained, the initial layout result may be analyzed, and placement information of a logic unit on a critical path is obtained, where the critical path refers to a path with the smallest time margin in multiple timing paths. The timing path mainly refers to a circuit signal transmission path formed by a main input of a circuit with a starting point, a transmission path passing through a logic unit and a main output of the circuit with an end point, namely, the critical path refers to a timing path with a great influence on the working frequency of the circuit.

In the embodiment of the present application, the initial layout result may include a plurality of paths, and each path may include a logic unit, where the plurality of paths may be a plurality of critical paths, that is, different logic units may be correspondingly placed on different critical paths.

Step S120: and acquiring the time allowance of each path, and taking the path with the time allowance smaller than the time threshold as a first path.

In an embodiment of the present application, each path corresponds to a time margin (slot) value that is the difference of the clock period minus the time spent by the circuit signal to travel from the start of the path to the end of the path. The time spent by the circuit signal from the start of the path to the end of the path may be referred to as the delay time, and the time threshold may be referred to as the clock period. If the time allowance is positive, the circuit can complete the preset action in a specified clock period, and if the time allowance is negative, the circuit cannot complete the preset action in the specified clock period. Therefore, the larger the time margin corresponding to a path, the better the timing of the path, and the smaller the time margin corresponding to the path, the worse the timing of the path, which may affect the timing of the entire circuit to some extent. In addition, the time margin may include a setup time margin and a hold time margin, that is, the time margin in the embodiment of the present application may be a sum of the setup time margin and the hold time margin, or may refer to the hold time margin or the like.

In order to optimize the primary layout result, the method can sort the time margins of a plurality of paths, select paths with poorer time margins, and replace logic units on the paths with poorer time margins, namely find a better placement position for the logic units on the paths, so as to reduce the delay time of the FPGA circuit time sequence.

In one mode, the application can take a path with a time margin smaller than a time threshold as a first path, the time threshold can be set according to actual conditions, for example, the minimum time margin values at different moments are obtained, the obtained values can be used as the time threshold by weighting and averaging the time margins, in addition, the time threshold can also be an empirical value, and the specific setting of the time threshold is not limited explicitly and can be set according to actual requirements.

As another way, the present application may also order all paths from small to large according to the size of the time margin, and use the paths corresponding to the first N time margins as the first paths. In addition, the application can also be used for acquiring the first path by combining the time allowance of the critical path and the node grade, wherein the node grade is mainly used for describing the number of logic units through which signals are transmitted from the main input of the circuit to the current logic unit, and simultaneously the node grade is also used for representing the transmission direction of the signals in the circuit path. In other words, the application can order the logic units of the critical path according to the criteria of the time margin from small to large and the node level from high to low. For example, the initial layout result includes a logic unit a, a logic unit B, and a logic unit C, where the time margins of the paths corresponding to the logic unit a and the logic unit C are equal to 0.1S, and the time margin of the paths corresponding to the logic unit C is 0.2S, and the node level corresponding to the logic unit a is 1 level, and the node level corresponding to the logic unit B is 2 level, and the three logic units are ordered at this time, so that the result is a logic unit B, a logic unit a, and a logic unit C, and the time margin and the node level of the logic unit B all conform to the preset conditions, so that the path corresponding to the logic unit B can be used as the first path.

Step S130: and determining a first logic unit on the first path, and searching a second logic unit positioned on the second path according to the first logic unit.

In some embodiments, after taking a path with a time margin smaller than a time threshold as a first path, a first logic unit on the first path may be determined, where the first logic unit is a logic unit in a user design program, and the first logic unit may include a plurality of logic sub-units, and each of the logic sub-units corresponds to a path, where the sub-paths may be divided into a critical sub-path and a non-critical sub-path, and in an embodiment of the present application, the first logic unit may correspond to one critical sub-path and to a plurality of non-critical sub-paths.

As a way, after determining the first logic unit on the first path, the second logic unit located on the second path may be searched according to the first logic unit, specifically, an extended iteration location searching area and range are set, and the first location of the first logic unit is taken as a grid center, and a second logic unit meeting a preset condition is found by spreading around the grid, where the second logic unit is located on the second path. The time margin of the second path is greater than the time margin of the first path, that is, after the second logic unit is acquired, whether the time margin of the second path corresponding to the second logic unit is greater than the time margin of the first path or not can be judged first, and if the time margin of the second path is greater than the time margin of the first path, whether a logic unit block exists between the second logic unit and the first logic unit or not is judged. And if the time allowance of the second path is smaller than or equal to that of the first path, searching a new second logic unit again according to the first logic unit, wherein the new second logic unit and the old second logic unit are positioned on different paths.

Alternatively, when the time margin of the second path is greater than the time margin of the first path, it may be further detected whether the time margin of the second path is greater than a time threshold, and if the time margin of the second path is greater than the time threshold, it is determined whether a logic unit block exists between the second logic unit and the first logic unit; if the time margin of the second path is less than or equal to the time threshold, a new second logic unit is retrieved, the new second logic unit being located on a different path than the old second logic unit.

Referring to fig. 3, the step of searching for the second logic unit located in the second path according to the first logic unit may include steps S131 to S132.

Step S131: a first location of the first logical unit is determined and a search range is determined from the first location.

In some embodiments, after determining the first location of the first logic unit, a search range may be determined centering on the first location, where the search range may be a partial area of the FPGA chip, and when no eligible second logic unit is found in the partial area, a search range may be redetermined, i.e., the search range may be enlarged. In the embodiment of the application, the searching range can be the whole area of the FPGA chip, the searching range specifically refers to the area of the chip, or the area of the searching range is specifically large, and the searching range can be selected according to actual situations without specific limitation.

Step S132: and determining a second logic unit meeting preset conditions in the searching range.

In one mode, after the searching range of the first position is determined, the method can expand and search the second logic unit meeting the preset condition around the grid by taking the first logic unit as the grid center, wherein the preset condition can be whether the time allowance of the second path corresponding to the second logic unit is larger than a time threshold or whether the time allowance of the second path corresponding to the second logic unit is larger than the time allowance of the first logic unit or not, and the node level of the second logic unit is lower than the node level of the first logic unit.

In order to more clearly illustrate the acquisition process of the second logic unit, the application provides an example shown in fig. 2, a first position denoted by "1" in fig. 2 is provided, the first position is provided with the first logic unit, when the time allowance of the path corresponding to the first logic unit is found to be smaller than the allowance threshold value through analysis, or the node level corresponding to the first logic unit is higher, the second logic unit can be found by expanding around the grid with the "1" as the center, the finding order is 2, 3,4, 5, 6, 7, 8, 9, 10, 11, 12, 13. For example, the logical unit at position "4" may be referred to as the second logical unit by finding that the time margin of the path of the logical unit at position "4" is greater than the time margin of the path of the logical unit at position "1".

In another way, after finding the second logic unit meeting the condition, determining whether the finding operation exceeds the finding range, if the finding operation is detected to exceed the finding range, ending the finding operation, if the finding operation does not exceed the finding range, continuing to find the second logic unit meeting the condition, so that a plurality of second logic units meeting the condition are possible, and when a plurality of second logic units meeting the condition are present, selecting an optimal second logic unit from the plurality of second logic units as a final second logic unit. In the embodiment of the application, the logic unit block can be a large logic unit, namely, the logic unit block occupies a larger area of a chip compared with the logic unit, and plays a larger role in an FPGA circuit.

For the programmable wiring resource, the wiring resource is used for connecting two logic units distributed on two sides of the logic unit block, when the wiring resource is used for wiring, the logic unit block cannot be traversed, and the wiring delay is relatively large when the logic unit resource in the logic unit block is used for wiring, so that the relative positions of the two logic units need to be finely adjusted. Therefore, in order to avoid the increase of the circuit delay, after the second logic unit is acquired, the present application can first determine whether a logic unit block exists between the second logic unit and the first logic unit, and if a logic unit block exists between the first logic unit and the second logic unit, then search for a third logic unit located in a third path, i.e. go to step S140.

In another way, when the second logic unit located in the second path is found according to the first logic unit, the application can also judge whether the connection relationship exists between the first logic unit and the second logic unit, if the connection relationship exists between the first logic unit and the second logic unit, a third logic unit located on the third path is found, and the connection relationship does not exist between the third logic unit and the first logic unit, so that when the first logic unit and the third logic unit are exchanged, the circuit time sequence delay is not caused, and the speed of expanding iteration can be accelerated to a certain extent.

Step S140: if a logic unit block exists between the second logic unit and the first logic unit, a third logic unit located on a third path is searched.

In some embodiments, after finding the second logic unit located in the second path, the embodiment of the present application may determine whether a logic unit block exists between the second logic unit and the first logic unit, and if a logic unit block exists between the first logic unit and the second logic unit, find a third logic unit located in the third path, where the third logic unit and the first logic unit are located on the same side of the logic unit block, and the third logic unit and the second logic unit are located on different sides of the logic unit block, where the same side refers to that the first logic unit and the third logic unit are connected to the same side port of the logic unit block, and the different side refers to that the second logic unit and the third logic unit are connected to the different side port of the logic unit block. The embodiment of the application can analyze the distribution positions and the connection relations of the first logic unit, the second logic unit and the logic unit blocks by using the Floorplan block.

In some embodiments, when a logic unit block exists between the second logic unit and the first logic unit, it may be first determined whether the first logic unit is connected to the logic unit block through a target connection port, where the target connection port is located on the logic unit block and the target connection port is located on the same side as the first logic unit, and if the first logic unit is connected to the logic unit block through the target connection port, a third logic unit located on a third path is searched.

In other embodiments, when a logic unit block exists between the second logic unit and the first logic unit, it may be first determined whether the first logic unit is connected to the logic unit block through the target connection port, and simultaneously determine whether the second logic unit is connected to the logic unit block through the target connection port, and if the first logic unit is connected to the logic unit block through the target connection port and the second logic unit is also connected to the logic unit through the target connection port, then search for a third logic unit located on the third path.

Referring to fig. 4, the logic unit block 105 may be a multiplier, and the first logic unit 101, the second logic unit 102, the third logic unit 103 and the fourth logic unit 104 are simple logic unit blocks, which are hardware resources in a certain area of the FPGA chip. As can be seen from fig. 4, the logic unit block 105 exists between the logic units 101 and 102, which would result in waste of connection resources if the logic units are exchanged, so that the third logic unit 103 needs to be acquired, where the third logic unit 103 and the first logic unit 101 are located on the same side of the logic unit block 105, and the third logic unit 103 and the second logic unit 102 are located on the different side of the logic unit block 105. Obviously, the connection between the first logic unit 101 and the third logic unit 103 is shorter, and the connection between the first logic unit 101 and the second connection unit 102 is longer, so that the logic unit on the first path may be replaced with the third logic unit 103, and the logic unit on the third path may be replaced with the first logic unit 101, i.e. step S150 is performed.

Step S150: and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit.

In some embodiments, after searching for the third logical unit located on the third path, the present application may replace the logical unit on the first path with the third logical unit and replace the logical unit on the third path with the first logical unit. In one manner, when the first logic unit does not include other sub-logic units, the logic unit on the first path may be replaced with the third logic unit after the third logic unit is acquired, and the logic unit on the third path may be replaced with the first logic unit.

In general, the first logic unit may include a plurality of sub-logic units, and each sub-logic unit corresponds to one sub-path, when a time margin of the sub-path corresponding to one sub-logic unit in the first logic unit is smaller than a time threshold, the second path unit located on the second path may be searched according to the first logic unit, and if a logic unit block exists between the second logic unit and the first logic unit, the third logic unit located on the third path may be searched. To more clearly understand the relationship between logic cells and logic sub-cells, the present application presents a diagram as shown in fig. 5, where 101 in fig. 5 may be referred to as a first logic cell, while instra, instrb, and InstC may be referred to as logic sub-cells, and instra, instrb, and InstC are respectively located on different paths, and since the time margin of the path corresponding to InstA is the smallest, the path corresponding to the path may be referred to as a critical sub-path, and the paths corresponding to InstB and InstC may be referred to as non-critical sub-paths. When a logic unit block exists between the first logic unit and the second logic unit, the method can expand and search the third logic unit 103 meeting the condition around the grid by taking the first logic unit 101 as the center, and can expand and search the third logic unit 103 meeting the condition around the grid by taking the sub-logic unit InstA under the first logic unit 101 as the center. Taking InstA as an example, taking it as a center, the third logic unit 103 that is in line with the condition is found out in an expanding way, and the third logic unit 103 may include a plurality of sub logic units, which are respectively instrd, instre and InstF. The search condition of the third logical unit is found InstD to be met by the search. Then InstD is moved up from position 102 to position InstA of 101 while InstA is moved up from position 101 to position InstD of 102.

In other embodiments, in order to reduce the connection resources between logic units and shorten the connection length, a plurality of sub-logic units with large correlation are usually placed under the same logic unit, so that correlation among InstA, instB and InstC is relatively large and correlation among InstD, instE and InstF is relatively large, and in order to avoid the connection conflict caused by exchange to increase the circuit timing delay, the present application may replace the first logic unit 101 and the third logic unit 103 integrally, i.e. perform lattice exchange. Specifically, all logic subunits in the first logic unit 101 and the third logic unit 103 are exchanged in a one-to-one correspondence manner, that is, the positions of the first logic unit 101 are exchanged for InstA, instB and InstC and the positions of the first logic unit 103 are exchanged for InstD, instE and InstF, the positions of the exchanged first logic unit 101 are placed for InstD, instE and InstF, and the positions of the exchanged third logic unit 103 are placed for InstA, instB and InstC, as shown in fig. 6 in detail, the speed of expansion iteration can be increased through the whole lattice exchange, and the time sequence delay of a circuit can be reduced.

According to the FPGA layout method, the time sequence delay time of the FPGA circuit can be effectively reduced by exchanging the obtained third logic unit with the first logic unit, and the working efficiency of the circuit is improved. The application effectively shortens the circuit connection length and reduces the time sequence delay of the circuit by acquiring the third logic unit when the logic unit block exists between the first logic unit and the second logic unit.

Referring to fig. 7, a flowchart of a method for layout of an FPGA according to another embodiment of the application is shown, where the method includes steps S210 to S260.

Step S210: and carrying out initial layout on the FPGA according to the global layout algorithm to obtain an initial layout result.

Step S220: and acquiring the time allowance of each path, and taking the path with the time allowance smaller than the time threshold as a first path.

For details of steps S210 to S220, please refer to the description of the embodiments of the above application.

Step S230: and judging whether the first path or the first logic unit meets a preset condition.

As one way, determining whether the first path or the first logic unit satisfies a preset condition includes: judging whether the first logic unit is positioned on different paths or not; and/or determining whether the first path is located on a loop circuit; and/or judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units. Specifically, the present application can obtain the first path with smaller time margin by comparing the time margins of the paths, and on the basis, it is firstly determined whether the first path and/or the first logic unit on the first path meet the preset condition, if so, the first logic unit is removed, and the obtaining operation of the second logic unit is not executed, namely, step S240 is entered. If the first path or the first logic unit does not meet the preset condition, determining the first logic unit on the first path, and searching the second logic unit positioned on the second path according to the first logic unit.

As a way, after the first path and the first logic unit are acquired, the method can firstly judge whether the first logic unit is positioned on different paths, and if so, the method does not perform searching operation on the first logic unit; if the first path is located on the same path, judging whether the first path is located on a loop circuit or not, namely determining whether the first logic unit has different node grades, and if so, not executing search operation on the first logic unit; if not, judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units, if so, not executing search operation on the first logic unit, and if not, proceeding to step S250. The embodiment of the application can also judge whether the first path is positioned on the loop circuit or not, then judge whether the first logic unit is positioned on different paths or not, and particularly judge which one is not limited explicitly, and can select according to actual conditions.

Step S240: the lookup operation of the second logical unit is not performed.

Step S250: and determining a first logic unit on the first path, and searching a second logic unit positioned on the second path according to the first logic unit.

In the embodiment of the application, after the second logic unit located in the second path is searched according to the first logic unit, the cost value of the second logic unit can be obtained, and the cost value is used for representing the time sequence characteristic corresponding to the second logic unit, wherein the time sequence characteristic refers to the speed of signal transmission or data processing of the second logic unit, and the better the time sequence of the second logic unit is, the larger the corresponding time allowance is. And judging whether the cost value of the second logic unit is larger than a cost threshold value or not on the basis, and judging whether a logic unit block exists between the second logic unit and the first logic unit or not when the cost value of the second logic unit is larger than the cost threshold value. The second logic unit may include a plurality of logic subunits, and each logic subunit corresponds to one path, where obtaining the cost value of the second logic unit may include: and obtaining the time allowance of the critical sub-path and the non-critical sub-path corresponding to the second logic unit, and then obtaining the cost value of the second logic unit according to the time allowance of the critical sub-path and the non-critical sub-path corresponding to the second logic unit.

As one way, the calculation formula of the cost value of the second logic unit is as follows:

wherein Cost _site is a Cost value, W is a weight factor, slack _{critical_inst} and For the time allowance of the critical sub-path and the non-critical sub-path corresponding to the same logic unit, the value of slot _wors+margint is the sum of the minimum time allowance value and the empirical value in the FPGA, margin is the empirical value, and k is the number of the non-critical sub-paths. In the embodiment of the application, the margin is taken as an empirical value and is a constant, and can be set according to actual requirements. For example, it is set to 100 or 1000 or the like. The higher the cost value, the better the timing of the path corresponding to the logic unit.

Step S260: if a logic unit block exists between the second logic unit and the first logic unit, a third logic unit located on a third path is searched.

Step S270: and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit.

According to the FPGA layout method, the time sequence delay time of the FPGA circuit can be effectively reduced by exchanging the obtained third logic unit with the first logic unit, and the working efficiency of the circuit is improved. The application effectively shortens the circuit connection length and reduces the time sequence delay of the circuit by acquiring the third logic unit when the logic unit block exists between the first logic unit and the second logic unit. In addition, the method can eliminate the first logic units meeting the conditions, reduce time sequence fluctuation to a certain extent, and ensure that the logic units on different paths or the same path are optimized and not interfered with each other.

Referring to fig. 8, a block diagram of an FPGA layout apparatus according to an embodiment of the present application is shown, where the FPGA layout apparatus 300 includes: an initial layout module 310, a first path acquisition module 320, a first lookup module 330, a second lookup module 340, and a unit exchange module 350.

The initial layout module 310 is configured to perform initial layout on the FPGA according to a global layout algorithm, so as to obtain an initial layout result, where the initial layout result includes a plurality of paths, and each path includes a logic unit.

A first path obtaining module 320, configured to obtain a time margin of each path, and take a path with a time margin smaller than a time threshold as a first path, where the time margin of the path is a difference between a time consumed for a circuit signal to be transmitted from a start point of the path to an end point of the path and the time threshold.

Further, the first path obtaining module 320 is further configured to determine a first location of the first logic unit, determine a search range according to the first location, and determine a second logic unit that meets a preset condition within the search range.

The first search module 330 is configured to determine a first logic unit on the first path, and search a second logic unit located in a second path according to the first logic unit, where a time margin of the second path is greater than a time margin of the first path.

Further, the first lookup module 330 is further configured to determine whether the first path or the first logic unit meets a preset condition; and if the preset condition is met, not executing the searching operation of the second logic unit.

Further, the first lookup module 330 is further configured to determine whether the first logic unit is located on a different path; and/or determining whether the first path is located on a loop circuit; and/or judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units.

And the second search module 340 is configured to obtain a third logic unit located on a third path if a logic unit block exists between the second logic unit and the first logic unit, where the third logic unit and the first logic unit are located on the same side of the logic unit block.

Further, the second lookup module 340 is further configured to obtain a cost value of the second logic unit, where the cost value is used to characterize a timing characteristic corresponding to the second logic unit, and determine whether a logic unit block exists between the second logic unit and the first logic unit when the cost value of the second logic unit is greater than a cost threshold.

Further, the unit exchange module 340 is further configured to obtain time margins of a critical sub-path and a non-critical sub-path corresponding to a second logic unit, and obtain a cost value of the second logic unit according to the time margins of the critical sub-path and the non-critical sub-path corresponding to the second logic unit. The calculation formula of the cost value: wherein Cost _site is a Cost value, W is a weight factor, slack _{critical_inst} and For the time allowance of the critical sub-path and the non-critical sub-path corresponding to the same logic unit, the value of slot _wors+margint is the sum of the minimum time allowance value and the empirical value in the FPGA, margin is the empirical value, and k is the number of the non-critical sub-paths.

The unit exchange module 350 is configured to replace a logic unit on the first path with a second logic unit, and replace the logic unit on the second path with the first logic unit.

In summary, according to the method, the device, the electronic device and the computer readable medium for laying out the FPGA provided by the embodiments of the present application, the time sequence delay time of the FPGA circuit can be effectively reduced by exchanging the third logic unit obtained by the method with the first logic unit, so as to improve the working efficiency of the circuit. The application effectively shortens the circuit connection length and reduces the time sequence delay of the circuit by acquiring the third logic unit when the logic unit block exists between the first logic unit and the second logic unit.

Referring to fig. 9, based on the above-mentioned FPGA layout method, apparatus, electronic device and computer readable medium, another electronic device 400 capable of executing the above-mentioned FPGA layout method is provided in the embodiment of the present application. The electronic device 400 includes one or more (only one shown) processors 410 and memory 420 coupled to each other. The memory 420 stores therein a program capable of executing the contents of the foregoing embodiments, and the processor 410 may execute the program stored in the memory 420, and the memory 420 includes the apparatus described in the foregoing embodiments.

Wherein the processor 410 may include one or more processing cores. The processor 410 utilizes various interfaces and lines to connect various portions of the overall electronic device 400, perform various functions of the electronic device 400, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 420, and invoking data stored in the memory 420. Alternatively, the processor 410 may be implemented in hardware in at least one of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 410 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), a video image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for being responsible for rendering and drawing of display content; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 410 and may be implemented solely by a single communication chip.

Memory 420 may include random access Memory (Random Access Memory, RAM) or Read-Only Memory (ROM). Memory 420 may be used to store instructions, programs, code sets, or instruction sets. The memory 420 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (e.g., a touch function, a sound playing function, a video image playing function, etc.), instructions for implementing the various method embodiments described above, and the like. The storage data area may also store data created by the electronic device 400 in use (e.g., phonebook, audiovisual data, chat log data), and the like.

It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 9 is merely illustrative and is not intended to limit the configuration of the electronic device described above. For example, electronic device 400 may also include more or fewer components than shown in FIG. 9, or have a different configuration than shown in FIG. 9.

Referring to fig. 10, a block diagram of a computer readable storage medium according to an embodiment of the present application is shown. The computer readable storage medium 500 has stored therein program code that can be invoked by a processor to perform the methods described in the method embodiments described above.

The computer readable storage medium 500 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer readable storage medium 500 comprises a non-volatile computer readable medium (non-transitory computer-readable storage medium). The computer readable storage medium 500 has storage space for program code 510 that performs any of the method steps described above. The program code can be read from or written to one or more computer program products. Program code 510 may be compressed, for example, in a suitable form.

It will be apparent to one skilled in the art that all or some of the steps of the methods, systems, functional modules/units in the systems disclosed above may be implemented in software (which may be implemented in computer program code executable by a computing system), firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.

Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and may include any information delivery media. Therefore, the present invention is not limited to any specific combination of hardware and software.

The foregoing is a further detailed description of embodiments of the invention in connection with the specific embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. A method of FPGA layout, the method comprising:

Performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit;

Obtaining a time margin of each path, and taking a path with the time margin smaller than a time threshold as a first path, wherein the time margin of the path is a difference value of clock cycles minus consumed time of circuit signals transmitted from a starting point of the path to an end point of the path;

determining a first logic unit on the first path, and searching a second logic unit positioned in a second path according to the first logic unit, wherein the time allowance of the second path is larger than that of the first path;

If a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit positioned on a third path, wherein the third logic unit and the first logic unit are positioned on the same side of the logic unit block;

and replacing the first logic unit on the first path with a third logic unit, and replacing the third logic unit on the third path with the first logic unit.

2. The method of claim 1, wherein the determining the first logical unit on the first path and the looking up the second logical unit on the second path according to the first logical unit further comprises:

acquiring a cost value of the second logic unit, wherein the cost value is used for representing the time sequence characteristic corresponding to the second logic unit;

And when the cost value of the second logic unit is larger than a cost threshold value, judging whether a logic unit block exists between the second logic unit and the first logic unit.

3. The method of claim 2, wherein the second logic unit comprises a plurality of logic sub-units, each of the logic sub-units corresponding to a sub-path;

the obtaining the cost value of the second logic unit includes:

Obtaining time allowance of a critical sub-path and a non-critical sub-path corresponding to the second logic unit;

and acquiring the cost value of the second logic unit according to the time allowance of the critical sub-path and the non-critical sub-path corresponding to the second logic unit.

4. A method according to claim 3, wherein the cost value is calculated as:

wherein Cost _site is a Cost value, W is a weight factor, slack _{critical_inst} and For the time allowance of the critical sub-path and the non-critical sub-path corresponding to the same logic unit, the value of slot _worst+margin is the sum of the minimum time allowance value and the empirical value in the FPGA, margin is the empirical value, and k is the number of the non-critical sub-paths.

5. The method of claim 1, wherein the looking up the second logical unit located in the second path based on the first logical unit includes:

Judging whether the first path or the first logic unit meets a preset condition;

and if the preset condition is met, not executing the searching operation of the second logic unit.

6. The method of claim 5, wherein the determining whether the first path or the first logic unit satisfies a preset condition comprises:

Judging whether the first logic unit is positioned on different paths or not; and/or

Judging whether the first path is positioned on a loop circuit or not; and/or

And judging whether the first logic unit on the first path is formed by cascading a plurality of sub logic units.

7. The method of claim 1, wherein the looking up a second logical unit located in a second path from the first logical unit comprises:

Determining a first position of the first logic unit, and determining a search range according to the first position;

and determining a second logic unit meeting preset conditions in the searching range.

8. An FPGA layout device, the device comprising:

The initial layout module is used for carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit;

A first path obtaining module, configured to obtain a time margin of each path, and take a path with the time margin smaller than a time threshold as a first path, where the time margin of the path is a difference value of clock cycles minus time spent by a circuit signal transmitted from a start point of the path to an end point of the path;

the first searching module is used for determining a first logic unit on the first path and searching a second logic unit positioned in a second path according to the first logic unit, and the time allowance of the second path is larger than that of the first path;

the second searching module is used for acquiring a third logic unit positioned on a third path if a logic unit block exists between the second logic unit and the first logic unit, and the third logic unit and the first logic unit are positioned on the same side of the logic unit block;

And the unit exchange module is used for replacing the first logic unit on the first path with a third logic unit and replacing the third logic unit on the third path with the first logic unit.

9. An electronic device, comprising:

One or more processors;

A memory;

one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications configured to perform the method of any of claims 1-7.

10. A computer readable medium, characterized in that the computer readable medium has stored therein a program code, which is callable by a processor for executing the method according to any of the claims 1-7.