CN112115667A - FPGA layout method, device, electronic equipment and computer readable medium - Google Patents

FPGA layout method, device, electronic equipment and computer readable medium Download PDF

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Publication number
CN112115667A
CN112115667A CN202010779209.8A CN202010779209A CN112115667A CN 112115667 A CN112115667 A CN 112115667A CN 202010779209 A CN202010779209 A CN 202010779209A CN 112115667 A CN112115667 A CN 112115667A
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logic unit
path
logic
time
fpga
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刘世仁
谭宇泉
夏炜
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Shenzhen Ziguang Tongchuang Electronics Co ltd
Shenzhen Pango Microsystems Co Ltd
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Shenzhen Ziguang Tongchuang Electronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Abstract

An embodiment of the application provides an FPGA layout method, an FPGA layout device, an electronic device and a computer readable medium, wherein the method comprises the following steps: performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result; acquiring the time allowance of each path, and taking the path with the time allowance smaller than a time threshold as a first path; determining a first logic unit on the first path, and searching a second logic unit on a second path according to the first logic unit; searching for a third logic unit located on a third path if a logic unit block exists between the second logic unit and the first logic unit; and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit. According to the method and the device, when the logic unit block exists between the first logic unit and the second logic unit, the third logic unit is obtained to effectively shorten the circuit connection length and reduce the time sequence delay of the circuit.

Description

FPGA layout method, device, electronic equipment and computer readable medium
Technical Field
The embodiment of the application relates to the field of integrated circuit design, in particular to but not limited to an FPGA layout method, an FPGA layout device, an electronic device and a computer readable medium.
Background
An FPGA (Field-Programmable Gate Array) is a logic device with rich hardware resources, strong parallel processing capability and flexible reconfigurable capability, and these features make the FPGA get more and more widely applied in many fields such as data processing, communication, network, and the like.
With the expansion of the scale of the FPGA chip, the layout of the chip becomes more critical and important, the wiring complexity and the wiring success rate of the chip are directly determined, and the performance of the chip, such as the area, the frequency and the like, is influenced. Therefore, cost in multiple aspects needs to be comprehensively considered in chip layout, and how to better layout the FPGA is a problem to be solved urgently under the condition of satisfying multiple constraints.
Disclosure of Invention
The FPGA layout method, the FPGA layout device, the electronic equipment and the computer readable medium mainly solve the technical problem of how to reduce the time sequence delay time of the FPGA circuit and improve the working efficiency of the FPGA circuit.
In a first aspect, an embodiment of the present application provides an FPGA layout method, where the method includes: performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit; acquiring a time margin of each path, and taking the path with the time margin smaller than a time threshold as a first path, wherein the time margin of the path is a difference value between consumed time for transmitting a circuit signal from a starting point of the path to an end point of the path and the time threshold; determining a first logic unit on the first path, and searching a second logic unit on a second path according to the first logic unit, wherein the time margin of the second path is greater than that of the first path; if a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit located on a third path, wherein the third logic unit and the first logic unit are located on the same side of the logic unit block; and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit.
Optionally, after searching for the second logic unit located in the second path according to the first logic unit, the method includes: obtaining a cost value of the second logic unit, wherein the cost value is used for representing a time sequence characteristic corresponding to the second logic unit; and when the cost value of the second logic unit is greater than a cost threshold value, judging whether a logic unit block exists between the second logic unit and the first logic unit.
Optionally, the second logic unit includes a plurality of logic sub-units, each of the logic sub-units corresponds to one sub-path, and the obtaining the cost value of the second logic unit includes: acquiring the time margins of a critical sub-path and a non-critical sub-path corresponding to the second logic unit; and obtaining the cost value of the second logic unit according to the time margins of the critical sub-path and the non-critical sub-path corresponding to the second logic unit.
Optionally, the formula for calculating the cost value is as follows:
Figure BDA0002619591010000021
among them, CostsiteAs cost value, W is a weight factor, Slackcritical_instAnd Slacknon_critical_instkThe time margins, Slack, of critical sub-paths and non-critical sub-paths corresponding to the same logic cellwors+margintThe value of (d) is the sum of the minimum time margin value and the empirical value in the FPGA, margin is the empirical value, and k is the number of non-critical sub-paths.
Optionally, searching for a second logic unit located in a second path according to the first logic unit includes: judging whether the first path or the first logic unit meets a preset condition; and if the preset condition is met, the searching operation of the second logic unit is not executed.
Optionally, the determining whether the first path or the first logic unit meets a preset condition includes: judging whether the first logic unit is positioned on different paths or not; and/or determining whether the first path is on a loop circuit; and/or judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units.
Optionally, the searching for the second logic unit located in the second path according to the first logic unit includes: determining a first position of the first logic unit, and determining a search range according to the first position; and determining a second logic unit meeting a preset condition in the search range.
In a second aspect, an embodiment of the present application further provides an FPGA layout apparatus, where the apparatus includes: the device comprises an initial layout module, a first path acquisition module, a first search module, a second search module and a unit exchange module. The initial layout module is used for performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit; the first path acquisition module is used for acquiring a time margin of each path and taking the path with the time margin smaller than a time threshold as a first path, wherein the time margin of the path is a difference value between consumed time for transmitting a circuit signal from a starting point of the path to an end point of the path and the time threshold; the first searching module is used for determining a first logic unit on the first path and searching a second logic unit on a second path according to the first logic unit, wherein the time margin of the second path is greater than that of the first path; the second searching module is used for acquiring a third logic unit positioned on a third path if a logic unit block exists between the second logic unit and the first logic unit, and the third logic unit and the first logic unit are positioned on the same side of the logic unit block; the unit switching module is configured to replace the logic unit on the first path with a third logic unit, and replace the logic unit on the third path with the first logic unit.
In a third aspect, an embodiment of the present application provides an electronic device, including: one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method provided by the first aspect above.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a program code is stored in the computer-readable storage medium, and the program code may be called by a processor to execute the method provided in the first aspect.
The method comprises the steps of firstly carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, then obtaining the time allowance of each path based on the initial layout result, taking the path with the time allowance smaller than a time threshold value as a first path, determining the first logic unit on the first path on the basis, searching the second logic unit on the second path according to the first path unit, and searching the third logic unit on the third path if a logic unit block exists between the second logic unit and the first logic unit at the moment, the third logic unit and the first logic unit are positioned at the same side of the logic unit block, and finally the logic unit on the first path is replaced by the third logic unit, and the logic unit on the third path is replaced by the first logic unit. According to the method and the device, when the logic unit block exists between the first logic unit and the second logic unit, the third logic unit is obtained to effectively shorten the circuit connection length and reduce the time sequence delay of the circuit.
Additional features and corresponding advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic flowchart of an FPGA layout method according to an embodiment of the present application;
fig. 2 is a schematic diagram of a grid in an FPGA layout method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of step S130 in an FPGA layout method according to an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a logic cell block existing between a first logic cell and a second logic cell in an FPGA layout method according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating a relationship between a first logic unit and a second logic unit in an FPGA layout method according to an embodiment of the present application;
fig. 6 is a schematic diagram illustrating exchange between a first logic unit and a second logic unit in an FPGA layout method according to an embodiment of the present application;
fig. 7 is a schematic flowchart of an FPGA layout method according to another embodiment of the present application;
fig. 8 is a block diagram of an FPGA layout apparatus according to an embodiment of the present disclosure;
fig. 9 is a block diagram of an electronic device provided in an embodiment of the present application;
fig. 10 is a block diagram of a computer-readable storage medium according to an embodiment of the present application.
Detailed Description
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
In the prior art, people mainly utilize a software development tool of the FPGA to sequentially perform logic synthesis, layout and wiring and configuration bit stream generation on application design, compile a logic circuit program written by a hardware description language and generate a bit stream download file for configuring the chip, and finally download the file to the chip to construct a circuit capable of realizing corresponding logic functions. The number of logic units of the existing FPGA reaches the hundred million gate level, namely the existing FPGA has more resources and large programs, so that the compiling and running time of a software tool is continuously increased, the application and development efficiency of the FPGA is low, and the key of FPGA circuit design is to reduce the time sequence delay time of an FPGA circuit and improve the working speed of the circuit. In the FPGA software workflow, which logic cells are used to implement the circuit function of the user can be determined through layout, that is, the layout processing effect greatly affects the software compiling running time and the timing sequence of the FPGA circuit.
In the prior art, positions on a chip need to be continuously traversed in an iteration mode so as to find a placement position meeting requirements, but in an extended iteration process, due to design, resource limitation and the like, most candidate positions cannot pass legal detection, so that legal positions need to be continuously searched in a larger range; or when optimizing the performance of each logic cell block, a large number of placed logic cells need to be removed and rearranged, which results in a too long compiling time of the software tool. In addition, when logic cells on both sides of a large logic cell block are connected, the timing delay of the circuit is relatively large due to the limitation of the connection resources.
In view of the above problems, the inventor proposes an FPGA layout method, an apparatus, an electronic device, and a computer readable medium according to embodiments of the present application.
Referring to fig. 1, a flowchart of a method for FPGA layout according to an embodiment of the present application is shown, where the method includes steps S110 to S140.
Step S110: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.
In some embodiments, the global layout algorithm mainly calculates an optimal layout scheme of the FPGA according to the circuit parameter requirements and the circuit optimization method, so that a logic unit (Instance) designed by a user can be placed on an ideal position of the chip, which may be referred to as an initial placement position in the present application. Obviously, after the FPGA is initially laid out by using a global layout algorithm, an initial position can be allocated to the logic units designed by the user, and the initial positions of the logic units can form an initial layout result.
As a mode, when an initial layout is performed on an FPGA by using a global layout algorithm, firstly, a chip resource of the FPGA may be uniformly divided into a plurality of logic unit blocks, where the logic unit blocks may include a plurality of logic units, and a resource grid table may be formed by the initial layout, where the resource grid table is used to describe a two-dimensional distribution position of each logic unit in the chip, that is, the position of the logic unit may be represented by a two-dimensional coordinate. As fig. 2 shows a resource grid representation, it can be known from fig. 2 that before the initial layout, the FPGA chip needs to be uniformly divided into multiple grids, and different instances can be correspondingly placed at each grid.
As a manner, the embodiment of the present application may use a global layout algorithm to layout a circuit designed by a user, so as to obtain an initial layout result. Specifically, a circuit input by a user is obtained, where the circuit may include a plurality of logic units (instances), and then the plurality of instances are initially laid out, that is, each Instance is assigned a chip placement position, where the placement position may be referred to as an initial placement position of a logic unit. For convenience of description, the present application refers to an Instance as a logical unit, which may also be referred to as a logical unit in a user design program, and each logical unit may include a plurality of logical sub-units.
In some embodiments, the FPGA is initially laid out according to a global layout algorithm, the initial layout result is analyzed after the initial layout result is obtained, and placement information of a logic unit on a critical path is obtained, where the critical path refers to a path with a minimum time margin among a plurality of timing paths. The timing path mainly refers to a circuit signal transmission path which is composed of a circuit main input at a starting point, a transmission path passing through a logic unit and a circuit main output at an end point, namely, a critical path refers to a timing path which has a large influence on the working frequency of a circuit.
In this embodiment of the application, the initial layout result may include a plurality of paths, and each of the paths may include one logic unit, and the plurality of paths may be a plurality of critical paths, that is, different logic units may be correspondingly placed on different critical paths.
Step S120: and acquiring the time margin of each path, and taking the path with the time margin smaller than a time threshold as a first path.
In the embodiment of the present application, each path corresponds to a time margin (slack) value, which is a difference between a time consumed for a circuit signal to be transmitted from a start point of the path to an end point of the path and a time threshold. The time consumed by the circuit signal to travel from the start point of the path to the end point of the path may be referred to as a delay time, the time threshold may be referred to as a clock period, and the time margin in the embodiment of the present application may be a value obtained by subtracting the delay time from the clock period. If the time margin is positive, the circuit can complete the preset action within the specified clock period, and if the time margin is negative, the circuit cannot complete the preset action within the specified clock period. Therefore, the larger the time margin corresponding to a path, the better the timing of the path, and the smaller the time margin corresponding to a path, the worse the timing of the path, which may affect the timing of the entire circuit to some extent. In addition, the time margin may include a setup time margin and a hold time margin, that is, the time margin in the embodiment of the present application may be a sum of the setup time margin and the hold time margin, and may also refer to the hold time margin and the like.
In order to optimize the primary layout result, the method and the device can sort the time margins of the paths, select the paths with poor time margins, and then replace the logic units on the paths with poor time margins, namely search a better placement position for the logic units on the paths, so as to reduce the delay time of the FPGA circuit timing sequence.
As a manner, the present application may use a path with a time margin smaller than a time threshold as the first path, where the time threshold may be set according to an actual situation, for example, minimum time margin values at different times are obtained, and the time margins are weighted and averaged, and the obtained value may be used as the time threshold, and in addition, the time threshold may also be an empirical value, and how to set the time threshold specifically, without explicit limitation, may be set according to an actual requirement.
As another mode, all paths may be sorted from small to large according to the size of the time margins, and the paths corresponding to the first N time margins are used as the first path. In addition, the first path can also be obtained by combining the time margin of the critical path and the node level, wherein the node level is mainly used for describing the number of logic units through which signals are transmitted from the main input of the circuit to the current logic unit, and meanwhile, the node level is also used for indicating the direction of the signals transmitted in the circuit path. In other words, the present application may order the logical units of the critical path according to the criteria of the time margin from small to large and the node level from high to low. For example, a logic unit a, a logic unit B, and a logic unit C exist in the initial layout result, the same time margins of the paths corresponding to the logic unit a and the logic unit C are all 0.1S, the time margin of the path corresponding to the logic unit C is 0.2S, the node level corresponding to the logic unit a is obtained as level 1, the node level corresponding to the logic unit B is obtained as level 2, and the three logic units are sorted at this time, so that the obtained result is the logic unit B, the logic unit a, and the logic unit C.
Step S130: and determining a first logic unit on the first path, and searching a second logic unit on a second path according to the first logic unit.
In some embodiments, after a path with a time margin smaller than a time threshold is taken as a first path, a first logic unit on the first path may be determined, where the first logic unit is a logic unit in a user design program, where the first logic unit may include a plurality of logic sub-units, each of the logic sub-units corresponds to one path, and the sub-paths may be divided into a critical sub-path and a non-critical sub-path.
As a manner, after determining a first logic unit on a first path, a second logic unit on a second path may be searched according to the first logic unit, specifically, a location search area and a range of extended iteration are set, and a second logic unit meeting a preset condition is searched by spreading around a grid with a first location of the first logic unit as a grid center, where the second logic unit is located on the second path. The time margin of the second path is greater than the time margin of the first path, that is, after the second logic unit is obtained, it may be determined whether the time margin of the second path corresponding to the second logic unit is greater than the time margin of the first path, and if the time margin of the second path is greater than the time margin of the first path, it is determined whether a logic unit block exists between the second logic unit and the first logic unit. And if the time margin of the second path is less than or equal to the time margin of the first path, re-searching a new second logic unit according to the first logic unit, wherein the new second logic unit and the old second logic unit are positioned on different paths.
As another mode, when the time margin of the second path is greater than the time margin of the first path, it may be further detected whether the time margin of the second path is greater than a time threshold, and if the time margin of the second path is greater than the time threshold, it is determined whether a logic cell block exists between the second logic unit and the first logic unit; and if the time margin of the second path is less than or equal to the time threshold, a new second logic unit is searched again, and the new second logic unit and the old second logic unit are located on different paths.
Referring to fig. 3, searching for a second logic unit located in a second path according to the first logic unit may include steps S131 to S132.
Step S131: and determining a first position of the first logic unit, and determining a search range according to the first position.
In some embodiments, after determining the first location of the first logic unit, a search range may be determined centering on the first location, where the search range may be a partial area of the FPGA chip, and when a second logic unit meeting the condition is not found in the partial area, the search range may be determined again, that is, the search range is expanded. In this embodiment of the present application, the search range may also be the entire area of the FPGA chip, where the search range specifically refers to that area of the chip, or how large the area of the search range is, and the search range may be selected according to an actual situation without explicit limitation.
Step S132: and determining a second logic unit meeting a preset condition in the search range.
As a manner, after determining the search range of the first location, the present application may use the first logic unit as a grid center to search for a second logic unit meeting a preset condition by extending around the grid, where meeting the preset condition may be whether a time margin of a second path corresponding to the second logic unit is greater than a time threshold, or whether the time margin of the second path corresponding to the second logic unit is greater than a time margin of the first logic unit, and a node level of the second logic unit is lower than a node level of the first logic unit.
To more clearly illustrate the acquisition process of the second logic unit, the present application provides an example as shown in fig. 2, where a first logic unit is placed at a first position represented by "1" in fig. 2, and when it is found through analysis that the time margin of a path corresponding to the first logic unit is smaller than a margin threshold, or the node level corresponding to the first logic unit is higher, the second logic unit may be found by expanding around the grid with "1" as a center, the search sequence is 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13. For example, the logical unit at the position "4" may be referred to as a second logical unit by finding that the time margin of the path of the logical unit at the position "4" is greater than the time margin of the path of the logical unit at the position "1".
As another mode, after the second logic units meeting the condition are found, whether the search operation exceeds the search range is determined, if the search operation is detected to exceed the search range, the search operation is ended, and if the search operation does not exceed the search range, the second logic units meeting the condition are continuously searched, so that a plurality of second logic units meeting the condition are possible, and when the plurality of second logic units meeting the condition exist, an optimal second logic unit can be selected from the plurality of second logic units to serve as a final second logic unit. In the embodiment of the present application, the logic unit block may be a large logic unit, that is, the logic unit block occupies a larger area of a chip than the logic unit, and plays a larger role in the FPGA circuit.
For programmable wiring resources, two logic units distributed on two sides of a logic unit block are connected by using a wiring resource, the wiring resource cannot traverse the logic unit block when performing wiring, and the wiring delay is relatively large by using the logic unit resource in the logic unit block or performing wiring, so that the relative positions of the two logic units need to be finely adjusted. Therefore, in order to avoid an increase in circuit delay, the present application may first determine whether a logic cell block exists between the second logic unit and the first logic unit after acquiring the second logic unit, and if a logic cell block exists between the first logic unit and the second logic unit, search for a third logic unit located in the third path, that is, enter step S140.
As another way, when the second logic unit located in the second path is found according to the first logic unit, the present application may also determine whether a connection relationship exists between the first logic unit and the second logic unit, and if the connection relationship exists between the first logic unit and the second logic unit, the present application searches for a third logic unit located in the third path, where the connection relationship does not exist between the third logic unit and the first logic unit, so that when the first logic unit and the third logic unit are exchanged, a circuit timing delay is not caused, and the speed of the extended iteration may also be accelerated to a certain extent.
Step S140: and if a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit on a third path.
In some embodiments, after finding the second logic unit located in the second path, the embodiment of the present application may determine whether a logic unit block exists between the second logic unit and the first logic unit, and if a logic unit block exists between the first logic unit and the second logic unit, find a third logic unit located in a third path, where the third logic unit and the first logic unit are located on a same side of the logic unit block, and the third logic unit and the second logic unit are located on different sides of the logic unit block, where the same side refers to a side port where the first logic unit and the third logic unit are connected to the logic unit block, and the different side refers to a side port where the second logic unit and the third logic unit are connected to the logic unit block. The distribution positions and the connection relations of the first logic unit, the second logic unit and the logic unit blocks can be analyzed by using the Florplan block.
In some embodiments, when a logic unit block exists between the second logic unit and the first logic unit, it may be determined whether the first logic unit is connected to the logic unit block through a target connection port, where the target connection port is located on the logic unit block, and the target connection port and the first logic unit are located on the same side, and if the first logic unit is connected to the logic unit block through the target connection port, a third logic unit located on a third path is searched.
In other embodiments, when a logic unit block exists between the second logic unit and the first logic unit, it may be determined whether the first logic unit is connected to the logic unit block through the target connection port, and at the same time, it may be determined whether the second logic unit is connected to the logic unit block through the target connection port, and if the first logic unit is connected to the logic unit block through the target connection port and the second logic unit is also connected to the logic unit through the target connection port, a third logic unit located on a third path is searched.
Referring to fig. 4, the logic unit block 105 may be a multiplier, and the first logic unit 101, the second logic unit 102, the third logic unit 103, and the fourth logic unit 104 are simple logic unit blocks, which are hardware resources in a certain area of the FPGA chip. Fig. 4 shows that the logic unit block 105 exists between the logic unit 101 and the logic unit 102, and if the logic unit 101 and the logic unit 102 are exchanged, the connection resources are wasted, so that the third logic unit 103 needs to be obtained, where the third logic unit 103 is located on the same side of the logic unit block 105 as the first logic unit 101, and the third logic unit 103 and the second logic unit 102 are located on different sides of the logic unit block 105. Obviously, the connection between the first logic unit 101 and the third logic unit 103 is shorter, and the connection between the first logic unit 101 and the second connection unit 102 is longer, at this time, the logic unit on the first path may be replaced by the third logic unit 103, and the logic unit on the third path may be replaced by the first logic unit 101, that is, the process proceeds to step S150.
Step S150: and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit.
In some embodiments, after finding the third logic unit located on the third path, the present application may replace the logic unit on the first path with the third logic unit, and replace the logic unit on the third path with the first logic unit. As one mode, when the first logic unit does not include other sub-logic units, after the third logic unit is acquired, the logic unit on the first path may be replaced by the third logic unit, and the logic unit on the third path may be replaced by the first logic unit.
In general, the first logic unit may include a plurality of sub-logic units, each sub-logic unit corresponds to one sub-path, when a time margin of a sub-path corresponding to one sub-logic unit in the first logic unit is smaller than a time threshold, the second logic unit located on the second path may be searched according to the first logic unit, and if a logic unit block exists between the second logic unit and the first logic unit, the third logic unit located on the third path may be searched. In order to more clearly understand the relationship between the logic unit and the logic subunit, the present application provides a diagram as shown in fig. 5, where 101 in fig. 5 may be referred to as a first logic unit, and InstA, InstB, and InstC may all be referred to as logic subunits, and InstA, InstB, and InstC are located on different paths, respectively, and since the time margin of the path corresponding to InstA is minimum, the path corresponding to InstA may be referred to as a critical subpath, and the paths corresponding to InstB and InstC may be referred to as a non-critical subpath. When a logic unit block exists between the first logic unit and the second logic unit, the method and the device can expand to the periphery of the grid by taking the first logic unit 101 as a center to search for the third logic unit 103 meeting the condition, and can also expand to the periphery of the grid by taking the sub-logic unit InstA under the first logic unit 101 as a center to search for the third logic unit 103 meeting the condition. Taking InstA as an example, the third logic unit 103 meeting the condition is found by extending around the InstA, and the third logic unit 103 may include a plurality of sub-logic units, which are InstD, InstE, and InstF, respectively. And finding that the InstD meets the searching condition of the third logic unit through searching. InstD is then moved from the position of 102 to InstA at 101, while InstA is moved from the position of 101 to InstD at 102.
In other embodiments, in order to reduce the wiring resources between logic units and shorten the wiring length, a plurality of sub-logic units with large correlation are usually placed under the same logic unit, so that the correlation between InstA, InstB and InstC is relatively large, and the correlation between InstD, InstE and InstF is relatively large, so as to avoid the wiring conflict caused by the switching to increase the circuit timing delay, the present application may replace the first logic unit 101 and the third logic unit 103 as a whole, i.e., lattice point switching. Specifically, all logic subunits in the first logic unit 101 and the third logic unit 103 are exchanged in a one-to-one correspondence manner, that is, the first logic unit 101 is InstA, InstB, and InstC, and the third logic unit 103 is InstD, InstE, and InstF, so that the first logic unit 101 after exchange is placed with InstD, InstE, and InstF, and the third logic unit 103 after exchange is placed with InstA, InstB, and InstC, as shown in fig. 6 in detail, the speed of extension iteration can be increased by the integral lattice point exchange, and the timing delay of the circuit can be reduced at the same time.
In the FPGA layout method provided in the embodiments of the present application, the second logic unit obtained by the FPGA layout method is exchanged with the first logic unit, so as to effectively reduce the time delay time of the FPGA circuit, and further improve the working efficiency of the circuit, specifically, the FPGA can be initially laid out according to a global layout algorithm to obtain an initial layout result, then the time margin of each path is obtained based on the initial layout result, and a path with the time margin smaller than a time threshold is used as a first path, the first logic unit on the first path is determined on the basis, the second logic unit on the second path is searched according to the first path unit, if a logic unit block exists between the second logic unit and the first logic unit at this time, the third logic unit on the third path is searched, and the third logic unit and the first logic unit are located on the same side of the logic unit block, and finally, replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit. According to the method and the device, when the logic unit block exists between the first logic unit and the second logic unit, the third logic unit is obtained to effectively shorten the circuit connection length and reduce the time sequence delay of the circuit.
Referring to fig. 7, a flowchart of a method for FPGA layout according to another embodiment of the present application is shown, where the method includes steps S210 to S260.
Step S210: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.
Step S220: and acquiring the time margin of each path, and taking the path with the time margin smaller than a time threshold as a first path.
Please refer to the description of the above embodiments for the details of steps S210 to S220.
Step S230: and judging whether the first path or the first logic unit meets a preset condition.
As a mode, determining whether the first path or the first logic unit satisfies a preset condition includes: judging whether the first logic unit is positioned on different paths or not; and/or determining whether the first path is on a loop circuit; and/or judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units. Specifically, a first path with a smaller time margin can be obtained by comparing the time margins of the paths, and on the basis, it is first determined whether the first path and/or a first logic unit on the first path meet a preset condition, and if the preset condition is met, the first logic unit is removed, and the obtaining operation of a second logic unit is not performed, that is, the process proceeds to step S240. And if the first path or the first logic unit does not meet the preset condition, determining the first logic unit on the first path, and searching a second logic unit positioned on a second path according to the first logic unit.
As a manner, after acquiring a first path and a first logic unit, the present application may first determine whether the first logic unit is located on a different path, and if the first logic unit is located on a different path, the present application does not perform a lookup operation on the first logic unit; if the first path is located on the same path, judging whether the first path is located on a loop circuit, namely determining whether the first logic unit has different node levels, and if so, not executing searching operation on the first logic unit; if not, judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units, if so, not executing the searching operation on the first logic unit, and if not, entering the step S250. In the embodiment of the present application, it may also be determined whether the first path is located on the loop circuit first, and then it is determined whether the first logic unit is located on a different path, specifically, it is determined which path is not specifically limited, and the first logic unit may be selected according to an actual situation.
Step S240: no look-up operation of the second logic unit is performed.
Step S250: and determining a first logic unit on the first path, and searching a second logic unit on a second path according to the first logic unit.
In this embodiment of the application, after searching for the second logic unit located in the second path according to the first logic unit, a cost value of the second logic unit may be obtained, where the cost value is used to characterize a timing characteristic corresponding to the second logic unit, the timing characteristic refers to how fast the second logic unit transmits a signal or processes data, and the better the timing of the second logic unit is, the larger the corresponding time margin is. And judging whether the cost value of the second logic unit is greater than a cost threshold value or not on the basis, and judging whether a logic unit block exists between the second logic unit and the first logic unit or not when the cost value of the second logic unit is greater than the cost threshold value. The second logic unit may include a plurality of logic subunits, and each logic subunit corresponds to one path, where obtaining the cost value of the second logic unit may include: and acquiring the time margins of the critical sub-path and the non-critical sub-path corresponding to the second logic unit, and then acquiring the cost value of the second logic unit according to the time margins of the critical sub-path and the non-critical sub-path corresponding to the second logic unit.
As one way, the cost value of the second logic unit is calculated as follows:
Figure BDA0002619591010000171
among them, CostsiteAs cost value, W is a weight factor, Slackcritical_instAnd
Figure BDA0002619591010000172
the time margins, Slack, of critical sub-paths and non-critical sub-paths corresponding to the same logic cellwors+margintThe value of (1) is the sum of the minimum time margin value and the empirical value in the FPGA, margin is the empirical value, and k is irrelevantThe number of key sub-paths. In the embodiment of the application, margin is a constant as an empirical value and can be set according to actual requirements. For example, it is set to 100 or 1000, etc. The larger the cost value is, the better the timing sequence of the path corresponding to the logic unit is.
Step S260: and if a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit on a third path.
Step S270: and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit.
In the FPGA layout method provided in this embodiment, the second logic unit obtained by the FPGA layout method is exchanged with the first logic unit, so as to effectively reduce the time delay time of the FPGA circuit, and further improve the working efficiency of the circuit, specifically, the FPGA can be initially laid out according to a global layout algorithm to obtain an initial layout result, then the time margin of each path is obtained based on the initial layout result, and a path with the time margin smaller than a time threshold is used as a first path, the first logic unit on the first path is determined on the basis, the second logic unit on the second path is searched according to the first path unit, if a logic unit block exists between the second logic unit and the first logic unit at this time, the third logic unit on the third path is searched, and the third logic unit and the first logic unit are located on the same side of the logic unit block, and finally, replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit. According to the method and the device, when the logic unit block exists between the first logic unit and the second logic unit, the third logic unit is obtained to effectively shorten the circuit connection length and reduce the time sequence delay of the circuit. In addition, the first logic units meeting the conditions can be removed, time sequence fluctuation can be reduced to a certain extent, and the optimization of the logic units on different paths or the same path is guaranteed not to interfere with each other.
Referring to fig. 8, a block diagram of an FPGA layout apparatus according to an embodiment of the present disclosure is shown, where the FPGA layout apparatus 300 includes: an initial layout module 310, a first path acquisition module 320, a first lookup module 330, a second lookup module 340, and a cell exchange module 350.
The initial layout module 310 is configured to perform initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, where the initial layout result includes multiple paths, and each path includes a logic unit.
A first path obtaining module 320, configured to obtain a time margin of each path, and use a path with a time margin smaller than a time threshold as the first path, where the time margin of the path is a difference between a time consumed for the circuit signal to be transmitted from the start point of the path to the end point of the path and the time threshold.
Further, the first path obtaining module 320 is further configured to determine a first position of the first logic unit, determine a search range according to the first position, and determine a second logic unit meeting a preset condition in the search range.
The first searching module 330 is configured to determine a first logic unit on the first path, and search, according to the first logic unit, a second logic unit located in a second path, where a time margin of the second path is greater than a time margin of the first path.
Further, the first searching module 330 is further configured to determine whether the first path or the first logic unit meets a preset condition; and if the preset condition is met, the searching operation of the second logic unit is not executed.
Further, the first searching module 330 is further configured to determine whether the first logic unit is located on a different path; and/or determining whether the first path is on a loop circuit; and/or judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units.
The second searching module 340 is configured to, if a logic unit block exists between the second logic unit and the first logic unit, obtain a third logic unit located on a third path, where the third logic unit and the first logic unit are located on the same side of the logic unit block.
Further, the second searching module 340 is further configured to obtain a cost value of the second logic unit, where the cost value is used to characterize a timing characteristic corresponding to the second logic unit, and when the cost value of the second logic unit is greater than a cost threshold, determine whether a logic unit block exists between the second logic unit and the first logic unit.
Further, the unit exchanging module 340 is further configured to obtain time margins of a critical sub-path and a non-critical sub-path corresponding to a second logic unit, and obtain a cost value of the second logic unit according to the time margins of the critical sub-path and the non-critical sub-path corresponding to the second logic unit. The formula for calculating the cost value is as follows:
Figure BDA0002619591010000191
among them, CostsiteAs cost value, W is a weight factor, Slackcritical_instAnd
Figure BDA0002619591010000192
the time margins, Slack, of critical sub-paths and non-critical sub-paths corresponding to the same logic cellwors+margintThe value of (d) is the sum of the minimum time margin value and the empirical value in the FPGA, margin is the empirical value, and k is the number of non-critical sub-paths.
A unit exchanging module 350, configured to replace the logic unit on the first path with a second logic unit, and replace the logic unit on the second path with the first logic unit.
To sum up, the method can effectively reduce the time delay time of the FPGA circuit by exchanging the second logic unit with the first logic unit, thereby improving the working efficiency of the circuit, and specifically, the method can firstly perform initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, then obtain the time margin of each path based on the initial layout result, and use the path with the time margin smaller than a time threshold as a first path, determine the first logic unit on the first path on the basis, and search for the second logic unit located on the second path according to the first path unit, and search for the third logic unit located on the third path if a logic unit block exists between the second logic unit and the first logic unit at this time, the third logic unit and the first logic unit are positioned at the same side of the logic unit block, and finally the logic unit on the first path is replaced by the third logic unit, and the logic unit on the third path is replaced by the first logic unit. According to the method and the device, when the logic unit block exists between the first logic unit and the second logic unit, the third logic unit is obtained to effectively shorten the circuit connection length and reduce the time sequence delay of the circuit.
Referring to fig. 9, based on the FPGA layout method, the FPGA layout apparatus, the electronic device, and the computer readable medium, another electronic device 400 capable of performing the FPGA layout method is provided in the embodiments of the present application. The electronic device 400 includes one or more processors 410 (only one shown) and a memory 420 coupled to each other. The memory 420 stores therein a program that can execute the contents of the foregoing embodiments, and the processor 410 can execute the program stored in the memory 420, where the memory 420 includes the apparatuses described in the foregoing embodiments.
Processor 410 may include one or more processing cores, among other things. The processor 410 interfaces with various components throughout the electronic device 400 using various interfaces and circuitry to perform various functions of the electronic device 400 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 420 and invoking data stored in the memory 420. Alternatively, the processor 410 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 410 may integrate one or more of a Central Processing Unit (CPU), a video image processor (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 410, but may be implemented by a communication chip.
The Memory 420 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 420 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 420 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, a video image playing function, etc.), instructions for implementing the various method embodiments described above, and the like. The data storage area may also store data created by the electronic device 400 during use (e.g., phone books, audio-video data, chat log data), and the like.
It will be understood by those skilled in the art that the structure shown in fig. 9 is merely an illustration and is not intended to limit the structure of the electronic device. For example, electronic device 400 may also include more or fewer components than shown in FIG. 9, or have a different configuration than shown in FIG. 9.
Referring to fig. 10, a block diagram of a computer-readable storage medium according to an embodiment of the present application is shown. The computer-readable storage medium 500 has stored therein program code that can be called by a processor to execute the method described in the above-described method embodiments.
The computer-readable storage medium 500 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 500 includes a non-volatile computer-readable storage medium. The computer readable storage medium 500 has storage space for program code 510 for performing any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. The program code 510 may be compressed, for example, in a suitable form.
It will be apparent to those skilled in the art that all or some of the steps of the methods, systems, functional modules/units in the systems disclosed above may be implemented as software (which may be implemented in computer program code executable by a computing system), firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.
In addition, communication media typically embodies computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to one of ordinary skill in the art. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. An FPGA placement method, the method comprising:
performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit;
acquiring a time margin of each path, and taking the path with the time margin smaller than a time threshold as a first path, wherein the time margin of the path is a difference value between consumed time for transmitting a circuit signal from a starting point of the path to an end point of the path and the time threshold;
determining a first logic unit on the first path, and searching a second logic unit on a second path according to the first logic unit, wherein the time margin of the second path is greater than that of the first path;
if a logic unit block exists between the second logic unit and the first logic unit, searching a third logic unit located on a third path, wherein the third logic unit and the first logic unit are located on the same side of the logic unit block;
and replacing the logic unit on the first path with a third logic unit, and replacing the logic unit on the third path with the first logic unit.
2. The method of claim 1, wherein replacing the logic cells on the first path with second logic cells and replacing the logic cells on the second path with the first logic cells comprises:
obtaining a cost value of the second logic unit, wherein the cost value is used for representing a time sequence characteristic corresponding to the second logic unit;
and when the cost value of the second logic unit is greater than the cost threshold value, replacing the logic unit on the first path with the second logic unit, and replacing the logic unit on the second path with the first logic unit.
3. The method of claim 2, wherein the second logical unit comprises a plurality of logical sub-units, and wherein each of the logical sub-units corresponds to one of the sub-paths;
the obtaining the cost value of the second logic unit includes:
acquiring the time margins of a critical sub-path and a non-critical sub-path corresponding to the second logic unit;
and obtaining the cost value of the second logic unit according to the time margins of the critical sub-path and the non-critical sub-path corresponding to the second logic unit.
4. The method of claim 3, wherein the cost value is calculated as follows:
Figure FDA0002619589000000021
among them, CostsiteAs cost value, W is a weight factor, Slackcritical_instAnd
Figure FDA0002619589000000022
the time margins, Slack, of critical sub-paths and non-critical sub-paths corresponding to the same logic cellwors+margintThe value of (d) is the sum of the minimum time margin value and the empirical value in the FPGA, margin is the empirical value, and k is the number of non-critical sub-paths.
5. The method of claim 1, wherein said searching for a second logical unit located in a second path according to the first logical unit comprises:
judging whether the first path or the first logic unit meets a preset condition;
and if the preset condition is met, the searching operation of the second logic unit is not executed.
6. The method of claim 5, wherein the determining whether the first path or the first logic unit satisfies a predetermined condition comprises:
judging whether the first logic unit is positioned on different paths or not; and/or
Judging whether the first path is positioned on a loop circuit or not; and/or
And judging whether the logic unit on the first path is formed by cascading a plurality of sub-logic units.
7. The method of claim 1, wherein said searching for a second logical unit located on a second path according to the first logical unit comprises:
determining a first position of the first logic unit, and determining a search range according to the first position;
and determining a second logic unit meeting a preset condition in the search range.
8. An FPGA layout apparatus, the apparatus comprising:
the initial layout module is used for carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result, wherein the initial layout result comprises a plurality of paths, and each path comprises a logic unit;
the first path acquisition module is used for acquiring the time margin of each path and taking the path with the time margin smaller than a time threshold as a first path, wherein the time margin of the path is the difference between the consumed time for transmitting the circuit signal from the starting point of the path to the end point of the path and the time threshold;
a first searching module, configured to determine a first logic unit on the first path, and search, according to the first logic unit, a second logic unit located in a second path, where a time margin of the second path is greater than a time margin of the first path;
a second searching module, configured to, if a logic unit block exists between the second logic unit and the first logic unit, obtain a third logic unit located on a third path, where the third logic unit and the first logic unit are located on the same side of the logic unit block;
and the unit switching module is used for replacing the logic unit on the first path with a third logic unit and replacing the logic unit on the third path with the first logic unit.
9. An electronic device, comprising:
one or more processors;
a memory;
one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-7.
10. A computer-readable storage medium having program code stored therein, the program code being invoked by a processor to perform the method of any of claims 1 to 7.
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