CN111931447A

CN111931447A - FPGA layout method and device, electronic equipment and storage medium

Info

Publication number: CN111931447A
Application number: CN202010711217.9A
Authority: CN
Inventors: 蒋涛
Original assignee: Shenzhen Ziguang Tongchuang Electronics Co ltd
Current assignee: Shenzhen Ziguang Tongchuang Electronics Co ltd; Shenzhen Pango Microsystems Co Ltd
Priority date: 2020-07-22
Filing date: 2020-07-22
Publication date: 2020-11-13

Abstract

The application discloses a Field Programmable Gate Array (FPGA) layout method, a device, electronic equipment and a storage medium, wherein the FPGA layout method comprises the following steps: performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result; determining a layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result; determining the movement priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit, wherein the movement priority is positively correlated with the layout proportion; and moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority. The method can determine the moving priority of the laid unit according to the unit layout condition in each unit area, and then adjust the laid unit according to the moving priority, thereby ensuring the uniform layout proportion of each laid unit, avoiding the increase of the length of a wiring line, and further improving the time sequence of the FPGA.

Description

FPGA layout method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of integrated circuit design technologies, and in particular, to a method and an apparatus for FPGA layout, an electronic device, and a storage medium.

Background

An FPGA (Field-Programmable Gate Array) is a logic device with rich hardware resources, strong parallel processing capability and flexible reconfigurable capability, and the FPGA is used to develop a digital Circuit, so that the design time can be greatly shortened, the Circuit area of a Printed Circuit Board (PCB) can be reduced, and the feasibility and stability of the system can be improved.

The layout and wiring of the FPGA are important parts in the development of digital circuits, and the performance of the FPGA has a great influence on the reliability of the digital circuits. After the traditional FPGA layout is carried out, the number of the cells laid out in different unit areas is not uniform, for example, the number of the cells possibly laid out in some unit areas is large, while the number of the cells laid out in some unit areas is small, so that the wire length is increased when the wiring is carried out, and the time sequence of the FPGA is reduced.

Disclosure of Invention

In view of the above problems, the present application provides an FPGA layout method, an FPGA layout device, an electronic device, and a storage medium, which can determine a moving priority of a laid-out unit according to a unit layout condition in each unit area, and then adjust the laid-out unit according to the moving priority, thereby ensuring that a layout proportion of each laid-out unit is uniform, avoiding an increase in a wiring line length, and further improving a timing sequence of an FPGA.

In a first aspect, an embodiment of the present application provides an FPGA layout method, including: performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result; determining a layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result, wherein the layout proportion corresponding to each laid-out unit is obtained according to the ratio of the number of all laid-out units in the unit area where each laid-out unit is located to the number of laid-out units in the unit area where each laid-out unit is located; determining the movement priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit, wherein the movement priority is positively correlated with the layout proportion; and moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority.

In a second aspect, an embodiment of the present application provides an FPGA layout apparatus, including: the initial layout module is used for carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result; the first determining module is used for determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result, wherein the layout proportion corresponding to each laid-out unit is obtained according to the ratio of the number of all laid-out units in the unit area where each laid-out unit is located to the number of laid-out units in the unit area where each laid-out unit is located; the second determining module is used for determining the movement priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit, and the movement priority is positively correlated with the layout proportion; and the layout unit moving module is used for moving each laid unit according to the moving priority of each laid unit until the moving priority of each laid unit is lower than the preset priority.

In a third aspect, an embodiment of the present application provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the FPGA layout method provided in the first aspect is implemented.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a program code is stored in the computer-readable storage medium, and the program code may be called by a processor to execute the FPGA layout method provided in the first aspect.

According to the scheme provided by the application, the FPGA is initially laid out according to a global layout algorithm to obtain an initial layout result, then the layout proportion corresponding to each laid-out unit in each unit area on the FPGA is determined according to the initial layout result, then the moving priority of each laid-out unit is determined according to the layout proportion corresponding to each laid-out unit, each laid-out unit is moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, therefore, the moving priority of the laid-out unit is determined according to the unit layout condition in each unit area, and then the laid-out units are adjusted according to the moving priority, so that the layout proportion of each laid-out unit is uniform, the increase of wiring lines can be avoided, and the time sequence of the FPGA is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic flowchart of FPGA validity detection provided in an embodiment of the present application;

fig. 2 is a schematic layout diagram before the validity of an FPGA is detected according to an embodiment of the present disclosure;

fig. 3 shows a schematic layout diagram after the validity of an FPGA is detected according to an embodiment of the present application;

FIG. 4 is a flow chart illustrating an FPGA layout method according to an embodiment of the present application;

fig. 5 shows a schematic diagram of dividing a unit area of an FPGA according to an embodiment of the present application;

fig. 6 shows a schematic layout diagram of an FPGA unit area according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a layout of an FPGA unit area according to an embodiment of the present disclosure;

FIG. 8 is a schematic flow chart diagram illustrating a method for FPGA layout according to another embodiment of the present application;

fig. 9 is a schematic layout diagram illustrating a target area on an FPGA according to an embodiment of the present disclosure;

FIG. 10 is a schematic flow chart diagram illustrating a FPGA layout method according to yet another embodiment of the present application;

fig. 11 is a schematic flowchart illustrating an FPGA layout method according to still another embodiment of the present application;

FIG. 12 is a schematic flow chart diagram illustrating a FPGA layout method according to yet another embodiment of the present application;

FIG. 13 is a schematic flow chart diagram illustrating a FPGA layout method according to yet another embodiment of the present application;

FIG. 14 is a schematic structural diagram of an FPGA layout device according to an embodiment of the present application;

fig. 15 shows a block diagram of an electronic device according to an embodiment of the present application;

fig. 16 illustrates a storage unit for storing or carrying program codes for implementing the FPGA layout method according to the embodiment of the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

In view of the increasing technology and technology, the user demand is greatly expanded, the scale of digital circuit development is explosively increased, the efficiency and performance of the FPGA face unprecedented challenges, and the performance of the FPGA is usually measured by the running time of the layout and wiring process, the efficiency of the wiring, and the time sequence after the layout and wiring. In the legality detection of the FPGA, all layout units are sequentially placed in a certain proper unit area of the FPGA, in the process, time sequence, density and routability are not considered, the layout units are only used as centers to diffuse all around until a unit area capable of being laid out is found on the FPGA, and the unit area is not moved after the layout is successful. Referring to fig. 1, a schematic flow diagram of FPGA validity detection is shown, where each digital region represents a unit region, the size of the number is the moving sequence of the layout unit, and the number 1 represents the unit region after layout, i.e., the initial unit region of validity detection, the numbers 2 to 5 are the same iteration process, the numbers 6 to 13 are the same iteration process, the numbers 14 to 25 are the same iteration process, and if a legal unit region is not found in one iteration process for layout, the iteration is continued.

After the traditional FPGA is arranged, the average number of the layout units in the unit area on the FPGA is not accurate enough, for example, the number of the layout units arranged in some unit areas is large, and the number of the layout units arranged in some unit areas is small, which will cause the average number of the layout units in the unit area on the FPGA to be low, and when the average number is lower than the set threshold, the initial unit area for detecting the legality cannot be detected. In addition, the legality detection may cause an excessive number of cells laid out in a certain cell area, so that a wire length during wiring is increased, thereby causing a decrease in timing of the FPGA.

It can be understood that after the FPGA is arranged, when the density of the layout units in some unit areas on the FPGA is higher than the preset density, in the validity detection process, several layout units with strong connection relationship in the unit area with the high density of the layout units may be arranged far away, so that the wire length is increased when the wiring is performed, thereby reducing the time sequence of the FPGA. Referring to FIG. 2, a layout diagram of the FPGA before validity detection is shown, for example, Y in FIG. 2₁-Y₁₇Region denotes a unit region that can be laid out, N₁-N₈The area indicates a unit area that cannot be laid out, the X area indicates a unit area currently being subjected to validity detection, and Z₁-Z₁₀The region indicates laid out unit regions each of which can be laid out only 4 layout cells, and Z₁Zone and Z₂All areas are laid out with 5 layout units with strong connection relation and X area is laid out with 6 layout units, when validity detection is carried out, 2 layout units in X area are respectively laid out to Y₁Region and Y₂After the region, only Y remains at the position where the layout can be performed₃Region and Y₄In region, then Z₁Zone and Z₂The redundant two layout cells in the region can only be laid out to Y₃Region and Y₄In the area, two layout units originally having a strong connection relation are not laid in two adjacent unit areas but are laid in two unit areas far away from each other, so that the wire length during wiring is increased, and the time sequence of the FPGA is reduced. On the basis of fig. 2, as shown in fig. 3, fig. 3 is a layout schematic diagram after the FPGA validity detection.

In view of the above problems, the inventor has studied and proposed a method, an apparatus, an electronic device, and a storage medium for FPGA layout according to an embodiment of the present application for a long time, so as to determine a moving priority of a laid-out unit according to a unit layout condition in each unit area, and then adjust the laid-out unit according to the moving priority, thereby ensuring that a layout proportion of each laid-out unit is uniform, avoiding an increase in a wiring line length, and further improving a timing sequence of the FPGA.

The following describes an application scenario provided in the embodiment of the present application.

Referring to fig. 4, which shows a schematic flowchart of an FPGA layout method according to an embodiment of the present application, the flowchart shown in fig. 4 will be described in detail below, where the FPGA layout method may include the following steps:

step S101: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.

In the embodiment of the present application, before the placed cells are moved, the FPGA may be initially placed according to a global placement algorithm to obtain an initial placement result, so as to determine a placement ratio of each placed cell. The layout unit may include a Look-Up-Table (LUT) unit, a Flip-Flop (FF) unit, an Arithmetic Processing (APM) unit, a Dedicated memory (DRM) unit, and the like, which are not limited herein, and the unit of a specific layout may be determined according to actual requirements.

In some embodiments, the global layout algorithm mainly calculates an optimal layout scheme of the FPGA according to the circuit parameter requirements and the circuit optimization method, so that the layout unit designed by the user can be laid out at an ideal position of the chip, which may be referred to as an initial layout position in the present application. Obviously, after the FPGA is initially laid out by using the global layout algorithm, an initial position can be allocated to the layout units designed by the user, and the initial layout positions of the layout units can form an initial layout result.

As a mode, when an initial layout is performed on an FPGA by using a global layout algorithm, firstly, a chip resource of the FPGA may be uniformly divided into a plurality of unit regions having the same size, where each unit region may further include a plurality of layout units, and a resource grid table may be formed by the initial layout, where the resource grid table is used to describe a two-dimensional distribution position of each layout unit in the chip, that is, the position of each layout unit may be represented by a two-dimensional coordinate. Referring to fig. 1 again, as fig. 1 shows a schematic diagram of a resource grid table, it can be known from fig. 1 that before initial layout, an FPGA chip needs to be uniformly divided into a plurality of grids, each grid corresponds to a unit area, and each grid can be correspondingly laid out with different layout units. It can be understood that the unit area is set according to a specific FPGA and an actual use effect, referring to fig. 5, the FPGA chip may also be uniformly divided into 12 same basic units, each basic unit may be regarded as one unit area, two horizontally or vertically adjacent basic units may be regarded as one unit area, 3 × 3 basic units with a certain layout position as a center may also be regarded as one unit area, and the unit area may also be set to the size of one layout position, which is not limited herein.

As another way, the embodiment of the present application may use a global layout algorithm to layout a circuit designed by a user, so as to obtain an initial layout result. Specifically, the circuit for acquiring the user input may include a plurality of unit areas, and then perform initial layout on the plurality of unit areas, that is, lay out the layout cells in the plurality of unit areas.

Step S102: and determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result.

In the embodiment of the present application, after obtaining the initial layout result, a layout proportion corresponding to each laid-out cell in each unit area on the FPGA may be determined according to the initial layout result, so as to determine a moving priority of each laid-out cell according to the layout proportion. The layout proportion corresponding to each laid-out unit is obtained according to the ratio of the number of all laid-out units in the unit area where each laid-out unit is located to the number of laid-out units in the unit area where each laid-out unit is located. The layout proportion corresponding to the laid-out cells can reflect the number of the laid-out cells on the unit area where the laid-out cells are located, the density of the laid-out cells on the unit area and the like to a certain extent, so that the layout proportion can be used as a basis for moving the laid-out cells subsequently.

In some embodiments, the laid-out units in the unit area on the FPGA may be the same type of layout units, and the layout proportion corresponding to each laid-out unit is obtained according to a ratio of the number of all laid-out units in the unit area where each laid-out unit is located to the number of laid-out units in the unit area where each laid-out unit is located, that is, the layout proportion of each laid-out unit in the same unit area is the same. For example, as shown in fig. 6, 4 LUT units may be laid out in each unit area on the FPGA, and 4 LUT units are laid out in the unit area a, and 2 LUT units are laid out in the unit area B, so that the layout ratio of each laid out unit in the unit area a is 1:1, and the layout ratio of each laid out unit in the unit area B is 1: 2.

In other embodiments, the laid-out units in the unit area on the FPGA may be different types of layout units, and the layout proportion corresponding to each laid-out unit is obtained according to a ratio of the number of all laid-out units of the type corresponding to the laid-out unit in the unit area where each laid-out unit is located to the number of laid-out units of the type corresponding to the laid-out unit in the unit area where each laid-out unit is located. For example, as shown in fig. 7, 4 LUT cells and 8 FF cells may be placed in each unit area on the FPGA, and 4 LUT cells and 4 FF cells have been placed in the unit area a ', and 2 LUT cells and 2 FF cells have been placed in the unit area B', so that a placement ratio of the placed LUT cells in the unit area a 'is 1:1, a placement ratio of the placed FF cells in the unit area a' is 1:2, a placement ratio of the placed LUT cells in the unit area B 'is 1:2, and a placement ratio of the placed FF cells in the unit area B' is 1: 4.

In still other embodiments, when obtaining the layout proportion for the laid-out cells on each unit region, the layout proportion corresponding to the laid-out cells on the unit region may also be obtained directly according to the ratio of the number of the laid-out cells on the unit region to the number of all the laid-out cells without distinguishing the types of the laid-out cells. In this embodiment, the layout proportions of all the laid-out cells in a unit area should be the same.

Of course, in the embodiment of the present application, the type and the number of the placeable units in each unit area on the FPGA may not be limited.

Step S103: and determining the moving priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit.

In this embodiment of the application, after determining the layout proportion corresponding to each laid-out cell in each unit area on the FPGA, the moving priority of each laid-out cell may be determined according to the layout proportion corresponding to each laid-out cell, so that each laid-out cell is moved according to the moving priority. The movement priority is positively correlated with the layout proportion, and the larger the layout proportion is, the higher the movement priority is.

In some embodiments, the layout proportion of each laid-out cell may be Density, the shift priority of each laid-out cell is priority, and the shift priority has a relationship priority with the layout proportion Density of k × Density, where k is equal to or greater than 1, if Density (i) > Density (j), (i, j) ≧ 1, i ≠ j, then priority (i) > priority (j), (i, j) ≧ 1, i ≧ j, where Density (i) is the layout proportion corresponding to the ith laid-out cell, Density (j) is the layout proportion corresponding to the jth laid-out cell, priority (i) is the shift priority of the ith laid-out cell, and priority (j) is the shift priority of the jth laid-out cell; when the layout proportion corresponding to the ith laid-out cell is greater than the layout proportion corresponding to the jth laid-out cell, the movement priority of the ith laid-out cell is greater than the movement priority of the jth laid-out cell, that is, the ith laid-out cell moves preferentially.

Step S104: moving each laid out cell according to the moving priority of each laid out cell.

In the embodiment of the present application, after the moving priority of each laid-out unit is determined, each laid-out unit may be moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, and since the moving priority is positively correlated with the layout proportion, the layout proportion corresponding to each laid-out unit is not too large, the layout proportion of each laid-out unit is ensured to be uniform, the increase of the length of a wiring line can be avoided, and the timing sequence can be further improved.

Specifically, after determining the moving priority of each laid-out unit, the laid-out units may be sorted according to the moving priority of each laid-out unit, and only the laid-out units with the moving priority not lower than the preset priority threshold value are moved, and the moving process of the laid-out units may refer to the method shown in fig. 1.

In some embodiments, after each laid-out unit is moved according to the movement priority of each laid-out unit, the step of determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA may be performed again until each laid-out unit is moved according to the movement priority of each laid-out unit, and the process is repeated continuously, so that the movement priority of each laid-out unit is lower than the preset priority.

Referring to fig. 8, which shows a schematic flowchart of an FPGA layout method according to an embodiment of the present application, and as will be described in detail with reference to the flowchart shown in fig. 8, the FPGA layout method may include the following steps:

step S201: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.

Step S202: and determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result.

In the embodiment of the present application, step S201 and step S202 may refer to the content of the foregoing embodiment, and are not described herein again.

Step S203: and acquiring the number of target areas around each laid-out unit in each unit area on the FPGA.

In the embodiment of the present application, in order to determine the moving priority of each laid-out cell, the number of target regions around each laid-out cell in each unit region on the FPGA may be obtained, where the target regions are used to represent that there are different laid-out cells in two adjacent unit regions, so as to calculate the moving priority of each laid-out cell according to the target regions, and thus when the laid-out cells are moved according to the moving priority, it may be avoided that any two laid-out cells having a strong connection relationship are laid out to two unit regions that are far away, and the wiring length of the FPGA may be shortened, thereby improving the timing sequence of the FPGA.

It can be understood that, when a target area exists on the FPGA and the layout units with strong connection relations are respectively laid out around the target area, since there is no layout unit for direct wiring between the target areas, the target area needs to be bypassed in the wiring process, which results in increasing the wire length of the FPGA wiring, thereby reducing the timing sequence. As shown in fig. 9, a layout diagram of a unit region on an FPGA with a target region is shown, where a placed cell C and a placed cell D are respectively placed on two sides of the target region, and the placed cell C and the placed cell D need routing during routing, such as a connection line between the placed cell C and the placed cell D in fig. 9. In the related art, the placed cell C and the placed cell D are usually placed on the same side of the target area, so that the wiring between the placed cell C and the placed cell D does not need to be far around, and at this time, the wiring length of the FPGA can be shortened, thereby improving the timing of the FPGA. However, if the cell C that has been placed or the cell D that has been placed is a cell having a strong connection relationship with the cell located at the previous position, the cell having the strong connection relationship is placed in a far-away area. And the moving priority of each layout unit is determined according to the target area, and then the layout units with strong connection relation are moved according to the moving priority, so that the layout units with strong connection relation can be prevented from being arranged to two unit areas with long distance, and the line length can be prevented from being too long, so that the time sequence is reduced.

For example, in any two adjacent unit areas E and F on the FPGA, if the LUT unit and the FF unit are arranged in the unit area E and the LUT unit and the APM unit are arranged in the unit area F, the unit area E and the unit area F are target areas; if the LUT cells and FF cells are arranged in the unit area E and no cells are arranged in the unit area F, the unit area E and the unit area F also serve as target areas.

In some embodiments, the laid-out cells in all unit areas on the FPGA may be the same type of layout cells, and for each laid-out cell in each unit area, the number of unit areas without layout cells may be obtained from all unit areas adjacent to the unit area, that is, the number of target areas around each laid-out cell in each unit area on the FPGA.

In other embodiments, the laid-out cells in the unit area on the FPGA may be different types of laid-out cells, and for each laid-out cell in each unit area, the number of unit areas having laid-out cells different from those in the unit area may be obtained from all unit areas adjacent to the unit area, and/or the number of unit areas having no laid-out cells is the number of target areas around each laid-out cell in each unit area on each FPGA.

Step S204: determining the distance from each laid out unit in each unit area on the FPGA to the boundary of the FPGA.

In the embodiment of the application, in order to determine the moving priority of each laid-out unit, the distance from each laid-out unit in each unit area on the FPGA to the boundary of the FPGA may be determined, so as to calculate the moving priority of each laid-out unit according to the distance from each laid-out unit to the boundary of the FPGA, and when the laid-out units are moved according to the moving priority, the layout units in the unit area on the boundary of the FPGA are prevented from being too dense, so that the local congestion of the layout can be improved, and the uniform layout proportion of each laid-out unit is ensured.

It can be understood that laid-out cells in the boundary area of the FPGA are most likely to diffuse toward the boundary of the FPGA during the validity checking process, so that the laid-out cells in the boundary area or the corner of the FPGA are clustered, and local routing congestion is caused, so that the timing of the FPGA is degraded, and even routing failure is caused.

It should be noted that, in this embodiment of the application, there is no sequence among step S202, step S203, and step S204, the number of target areas around each laid-out unit in each unit area on the FPGA may be obtained after determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA and the distance to the boundary of the FPGA, the number of target areas around each laid-out unit in each unit area on the FPGA may be obtained, the layout proportion corresponding to each laid-out unit in each unit area on the FPGA and the distance to the boundary of the FPGA may be determined after obtaining the number of target areas around each laid-out unit in each unit area on the FPGA, and so on, and details are not repeated here.

Step S205: and calculating the moving priority value of each laid-out unit according to a priority calculation formula, a layout proportion, the number of target areas and the distance from each laid-out unit to the boundary of the FPGA.

In the embodiment of the application, after the number of the target areas around each laid-out unit in each unit area on the FPGA is obtained and the distance from each laid-out unit in each unit area on the FPGA to the boundary of the FPGA is determined, a moving priority value of each laid-out unit can be calculated according to a priority calculation formula, a layout proportion, the number of the target areas and the distance from each laid-out unit to the boundary of the FPGA, and the moving priority value is used for representing the moving priority, so that each laid-out unit can be moved successively according to the moving priority of each laid-out unit, the layout proportion of each laid-out unit can be ensured to be uniform, the increase of wiring lines can be avoided, and the timing sequence can be further improved.

The mobile priority calculation formula is as follows:

the method comprises the steps of determining the layout unit, and determining the layout unit according to the layout unit, wherein the layout unit comprises a plurality of layout units, the number of layout units is equal to the number of target areas, the number of target areas is equal to the number of target areas.

In some embodiments, each laid out cell in a unit area on the FPGA may be a same type of layout cell, and then the layout proportion of each laid out cell in the unit area is the same as the average layout proportion of the laid out cells in the unit area, the number of target areas of each laid out cell in the unit area is the same as the average number of target areas of the laid out cells in the unit area, and the distance from each laid out cell in the unit area to the boundary of the FPGA is the same as the average distance from the laid out cell in the unit area to the boundary of the FPGA. Therefore, the movement priority value of each laid out cell can be calculated according to the movement priority formula.

In other embodiments, each laid-out cell in a unit area on the FPGA may be a different type of laid-out cell, the layout proportion, the number of target areas, and the distance to the boundary of the FPGA of each laid-out cell may be calculated first, then the average layout proportion, the number of average target areas, and the average distance to the boundary of the FPGA of each laid-out cell may be calculated respectively, and then the average priority value of the laid-out cells in the unit area where each laid-out cell is located, that is, the moving priority value of each laid-out cell, is calculated according to the moving priority calculation formula, the average layout proportion, the number of average target areas, and the average distance to the boundary of the FPGA.

Step S206: moving each laid out cell according to the moving priority of each laid out cell.

In the embodiment of the present application, step S206 may refer to the contents of the foregoing embodiments, which are not described herein again.

According to the scheme provided by the application, the FPGA is initially laid out according to a global layout algorithm to obtain an initial layout result, then the layout proportion corresponding to each laid-out unit in each unit area on the FPGA is determined according to the initial layout result, then the moving priority of each laid-out unit is determined according to the layout proportion corresponding to each laid-out unit, each laid-out unit is moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, therefore, the moving priority of the laid-out unit is determined according to the unit layout condition in each unit area, and then the laid-out units are adjusted according to the moving priority, so that the layout proportion of each laid-out unit is uniform, the increase of wiring lines can be avoided, and the time sequence of the FPGA is improved. Moreover, the movement priority of each laid-out unit is calculated according to the number of target areas around each laid-out unit, and then each laid-out unit is moved according to the movement priority, so that the wiring length of the FPGA can be shortened, and the time sequence of the FPGA is improved; and calculating the moving priority of each laid-out unit according to the distance from each laid-out unit to the boundary of the FPGA, and then moving each laid-out unit according to the moving priority, so that the local congestion of the layout can be improved, and the uniform layout proportion of each laid-out unit is ensured.

Referring to fig. 10, which shows a schematic flowchart of an FPGA layout method according to an embodiment of the present application, and as will be described in detail with reference to the flowchart shown in fig. 10, the FPGA layout method may include the following steps:

step S301: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.

Step S302: and determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result.

Step S303: and determining the moving priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit.

In the embodiment of the present application, step S301, step S302, and step S303 may refer to the contents of the foregoing embodiments, and are not described herein again.

Step S304: the moving object has cells laid out.

In this embodiment of the application, after determining the moving priority of each laid-out cell according to the layout proportion corresponding to each laid-out cell, the target laid-out cell may be moved, where the target laid-out cell is any laid-out cell.

Step S305: and when the moving times of the target laid-out unit reach the corresponding preset time threshold, acquiring all the unit areas which can be laid out in the unit areas passed by the target laid-out unit in the moving process.

In the embodiment of the present application, after the target laid-out unit is moved, it may be determined whether the number of times of movement of the target laid-out unit reaches a corresponding preset number threshold, so as to obtain the unit area capable of being laid out according to the determination result. When the moving times of the target laid-out unit reach the corresponding preset time threshold value, acquiring all the laying-out unit areas in the unit areas passing through in the moving process of the target laid-out unit so as to determine the target unit area corresponding to the target laid-out unit according to the laying-out unit areas; and when the moving times of the target laid-out units are judged not to reach the corresponding preset time threshold, continuing to move the target laid-out units until the moving times of the target laid-out units reach the corresponding preset time threshold. It is understood that the preset threshold may be set to 1, may also be set to 10, and may also be set to 100, and the specific value of the preset threshold is not limited herein.

Step S306: and determining a target unit area corresponding to the target layout unit from all the unit areas capable of being laid out according to the preset layout position selection condition.

In this embodiment of the application, after all the unit areas capable of being laid out are obtained in the unit area through which the target laid out unit passes in the moving process, the target unit area corresponding to the target laid out unit is determined from all the unit areas capable of being laid out according to the preset layout position selection condition, so that the target laid out unit is laid out in the target unit area.

In some embodiments, the preset layout position selection condition includes: selecting a unit region which can be laid out and has the minimum cost function value of the unit region in all the unit regions which can be laid out; after all the unit areas which can be laid out and pass through in the moving process of the target laid out unit are obtained, the cost function values of the unit areas of all the unit areas which can be laid out can be calculated according to the cost function formula, and then the unit area which can be laid out and has the minimum cost function value of the unit areas is selected from all the unit areas which can be laid out according to the cost function values of the unit areas as the target unit area. Wherein, the cost function formula is: the Cost is a Cost function value of the unit region, the wirelength is a line length of the unit region, the sigma is a weight corresponding to the line length of the unit region, the slope is a delay margin of the unit region, and the tau is a weight corresponding to the delay margin of the unit region.

Step S307: and laying out the target laid-out unit in the target unit area.

In the embodiment of the present application, after the target unit area corresponding to the target laid-out cell is determined, the target laid-out cell may be laid out in the target unit area, so that the same laid-out cell may be prevented from being repeatedly moved for multiple times, thereby improving the layout efficiency.

According to the scheme provided by the application, the FPGA is initially laid out according to a global layout algorithm to obtain an initial layout result, then the layout proportion corresponding to each laid-out unit in each unit area on the FPGA is determined according to the initial layout result, then the moving priority of each laid-out unit is determined according to the layout proportion corresponding to each laid-out unit, each laid-out unit is moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, therefore, the moving priority of the laid-out unit is determined according to the unit layout condition in each unit area, and then the laid-out units are adjusted according to the moving priority, so that the layout proportion of each laid-out unit is uniform, the increase of wiring lines can be avoided, and the time sequence of the FPGA is improved. And according to the preset times threshold value and the preset layout position selection condition of the target laid-out unit, the target laid-out unit is laid out in the unit area which can be laid out and has the smallest cost function value of the passed unit area in the moving process of the target laid-out unit, so that the same laid-out unit can be prevented from being repeatedly moved for many times, and the layout efficiency is improved.

Referring to fig. 11, which shows a flowchart of an FPGA layout method according to an embodiment of the present application, the flowchart shown in fig. 11 will be described in detail below, where the FPGA layout method may include the following steps:

step S401: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.

In the embodiment of the present application, step S401 may refer to the contents of the foregoing embodiments, and is not described herein again.

Step S402: and judging whether a target area exists in the unit area on the FPGA according to the initial layout result.

In this embodiment of the present application, before determining a value of a moving priority of each laid-out cell, whether a target region exists in a unit region on the FPGA may be determined according to an initial layout result, where the target region is used to represent that different laid-out cells exist in two adjacent unit regions, so as to move the laid-out cells around the target region according to the determination result. When different types of laid units exist in two adjacent unit areas, judging that the unit areas on the FPGA have target areas; and when the types of the laid units in the two adjacent unit areas are the same, judging that no target area exists in the unit area on the FPGA.

Step S403: when the unit area on the FPGA has the target area, the layout units around the target area are moved to the same side of the target area.

In the embodiment of the application, when the unit area on the FPGA is judged to have the target area according to the initial layout result, the laid units around the target area are moved to the same side of the target area, so that the wiring length of the FPGA can be shortened, and the time sequence of the FPGA can be improved.

Step S404: and determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result.

Step S405: and determining the value of the moving priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit.

In the embodiment of the present application, step S404 and step S405 may refer to the contents of the foregoing embodiments, and are not described herein again.

Step S406: and moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority and no target area exists on the FPGA.

In the embodiment of the application, after the laid-out units around the target area are moved to the same side of the target area, each laid-out unit can be moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority and the target area does not exist on the FPGA, so that the wiring line length of the FPGA can be shortened, and the time sequence can be improved.

The layout proportion of the laid-out units is calculated after the laid-out units around the target area are arranged to the same side of the target area, then the moving priority is determined according to the layout proportion of each laid-out unit, and then the target area is generated on the FPGA in the process of moving the laid-out units possibly according to the moving priority, so that the step of ' judging whether the unit area on the FPGA has the target area ' is executed ' is returned, the step ' moving each laid-out unit according to the moving priority of each laid-out unit ', and after the laid-out units are moved and adjusted by continuously repeating the processes, the moving priority of each laid-out unit on the FPGA is lower than the preset priority, and the target area does not exist on the FPGA.

According to the scheme provided by the application, the FPGA is initially laid out according to a global layout algorithm to obtain an initial layout result, then the layout proportion corresponding to each laid-out unit in each unit area on the FPGA is determined according to the initial layout result, then the moving priority of each laid-out unit is determined according to the layout proportion corresponding to each laid-out unit, each laid-out unit is moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, therefore, the moving priority of the laid-out unit is determined according to the unit layout condition in each unit area, and then the laid-out units are adjusted according to the moving priority, so that the layout proportion of each laid-out unit is uniform, the increase of wiring lines can be avoided, and the time sequence of the FPGA is improved. And before determining the value of the moving priority of each laid-out unit, when the unit area on the FPGA is judged to have the target area according to the initial layout result, the laid-out units around the target area are moved to the same side of the target area, so that the wiring length of the FPGA can be shortened, and the time sequence of the FPGA is improved.

Referring to fig. 12, which shows a flowchart of an FPGA layout method according to an embodiment of the present application, the flowchart shown in fig. 12 will be described in detail below, and the FPGA layout method may include the following steps:

step S501: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.

In the embodiment of the present application, step S501 may refer to the contents of the foregoing embodiments, and is not described herein again.

Step S502: and acquiring the average distance from all the laid-out units of the FPGA to the boundary of the FPGA according to the initial layout result.

In this embodiment of the present application, before determining the value of the moving priority of each laid-out cell, an average distance from all laid-out cells of the FPGA to the boundary of the FPGA may be obtained according to the initial layout result, so as to move at least part of laid-out cells in the boundary area of the FPGA according to the average distance.

Step S503: and when the average distance is smaller than the preset distance threshold, moving at least part of the laid units in the boundary area of the FPGA to a unit area close to the center of the FPGA until the average distance is larger than or equal to the preset distance threshold.

In the embodiment of the present application, after obtaining the average distance from all the laid out units of the FPGA to the boundary of the FPGA, at least part of the laid out units in the boundary region of the FPGA may be moved according to the average distance and the preset distance threshold, where the boundary region is a region in a preset range adjacent to the boundary on the FPGA. When the average distance is smaller than the preset distance threshold, at least part of the laid-out units in the boundary area of the FPGA are moved to the unit area close to the center of the FPGA until the average distance is larger than or equal to the preset distance threshold, so that the local congestion of the laid-out units can be improved, the layout proportion of the laid-out units is relatively uniform, and the wiring efficiency is improved.

Step S504: and determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result.

Step S505: and determining the value of the moving priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit.

In the embodiment of the present application, step S504 and step S505 may refer to the contents of the foregoing embodiments, and are not described herein again.

Step S506: and moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority and the average distance from all laid-out units to the boundary of the FPGA is greater than or equal to the preset distance threshold.

In the embodiment of the present application, after at least part of the laid-out units in the boundary area of the FPGA are moved to the unit area close to the center of the FPGA until the average distance is greater than or equal to the preset distance threshold, each laid-out unit may be moved according to the movement priority of each laid-out unit until the movement priority of each laid-out unit is lower than the preset priority, and the average distance between all laid-out units and the boundary of the FPGA is greater than or equal to the preset distance threshold, so that the laid-out units may be prevented from being closely laid out in the boundary area of the FPGA, thereby avoiding local congestion in the layout, and making the layout proportion of the laid-out units relatively uniform, thereby improving the wiring efficiency.

According to the scheme provided by the application, the FPGA is initially laid out according to a global layout algorithm to obtain an initial layout result, then the layout proportion corresponding to each laid-out unit in each unit area on the FPGA is determined according to the initial layout result, then the moving priority of each laid-out unit is determined according to the layout proportion corresponding to each laid-out unit, each laid-out unit is moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, therefore, the moving priority of the laid-out unit is determined according to the unit layout condition in each unit area, and then the laid-out units are adjusted according to the moving priority, so that the layout proportion of each laid-out unit is uniform, the increase of wiring lines can be avoided, and the time sequence of the FPGA is improved. And before determining the value of the moving priority of each laid-out unit, the average distance from all laid-out units of the FPGA to the boundary of the FPGA can be obtained according to the initial layout result, when the average distance is smaller than a preset distance threshold, at least part of laid-out units in the boundary area of the FPGA are moved to a unit area close to the center of the FPGA until the average distance is larger than or equal to the preset distance threshold, the laid-out units can be prevented from being closely laid out in the boundary area of the FPGA, so that local congestion in the layout is avoided, the layout proportion of the laid-out units is relatively uniform, and the wiring efficiency is improved.

Referring to fig. 13, which shows a schematic flowchart of an FPGA layout method according to an embodiment of the present application, and the flowchart shown in fig. 13 will be described in detail below, where the FPGA layout method may include the following steps:

step S601: and carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result.

Step S602: and determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result.

Step S603: and acquiring the number of target areas around each laid-out unit in each unit area on the FPGA.

Step S604: determining the distance from each laid out unit in each unit area on the FPGA to the boundary of the FPGA.

Step S605: and calculating the moving priority value of each laid-out unit according to a priority calculation formula, a layout proportion, the number of target areas and the distance from each laid-out unit to the boundary of the FPGA.

In the embodiment of the present application, step S601, step S602, step S603, step S604, and step S605 may refer to the foregoing embodiment, and are not described herein again.

Step S606: and judging whether the moving priority of each laid out unit is lower than the preset priority.

In the embodiment of the present application, after the moving priority value of each laid-out unit is calculated, it may be determined whether the moving priority of each laid-out unit is lower than a preset priority, so as to determine whether to move each laid-out unit according to the moving priority of each laid-out unit according to the priority determination result of each laid-out unit. When the movement priority of the laid-out units is judged to be not lower than the preset priority, moving each laid-out unit according to the movement priority of each laid-out unit; and when the moving priority of each laid-out unit is judged to be lower than the preset priority, the layout is terminated.

Step S607: and when the moving priority of the laid-out units is not lower than the preset priority, acquiring the target laid-out unit with the highest moving priority, and moving the target laid-out unit.

In the embodiment of the application, when it is determined that the moving priority of the laid-out unit is not lower than the preset priority, the target laid-out unit with the highest moving priority can be obtained, and the target laid-out unit is moved, so that the moving priority of each moved laid-out unit is lower than the preset priority, and therefore the laid-out units are adjusted according to the moving priority of the laid-out units, the uniform layout proportion of each laid-out unit is ensured, the increase of the length of a wiring line can be avoided, and the time sequence of the FPGA is further improved.

Step S608: and judging whether the moving times of the target laid-out unit reach a preset time threshold value or not.

In the embodiment of the present application, when the target laid-out cell is moved, the unit region that can be laid out may be acquired according to the number of times the target laid-out cell is moved. Specifically, the unit region capable of layout may be acquired according to whether the number of times of movement of the target laid-out unit reaches a preset number threshold.

Step S609: and when the moving times of the target laid-out unit do not reach the preset time threshold, continuously moving the target laid-out unit until the moving times of the target laid-out unit reach the preset time threshold.

In this embodiment of the present application, when it is determined that the number of times of movement of the target laid-out unit does not reach the preset number threshold, it indicates that the unit area capable of being laid out is not acquired, and the target laid-out unit may be continuously moved until the number of times of movement of the target laid-out unit reaches the preset number threshold, that is, it indicates that the unit area capable of being laid out is acquired.

Step S610: when the moving times of the target laid-out unit reach a preset time threshold, all the unit areas which can be laid out in the unit areas passed by the target laid-out unit in the moving process are obtained.

Step S611: and calculating the cost function value of the unit area of all the unit areas capable of being laid out according to the cost function formula.

Step S612: and selecting the unit area which can be laid out and has the minimum cost function value of the unit area from all the unit areas which can be laid out as the target unit area according to the cost function value of the unit area.

In the embodiment of the present application, step S610, step S611, and step S612 may refer to the contents of the foregoing embodiments, and are not described herein again.

Step S613: the target laid-out cells are laid out in the target unit area, and step S602 is repeatedly executed until the moving priority of each laid-out cell is lower than the preset priority.

In the embodiment of the present application, after determining the target unit area corresponding to the target laid-out unit, the target laid-out unit may be laid out in the target unit area, and step S602 may be performed again until the moving priority of each laid-out unit is lower than the preset priority, so that the same laid-out unit may be prevented from being repeatedly moved multiple times, thereby improving the layout efficiency.

Step S614: and when the moving priority of each laid out unit is lower than the preset priority, terminating the layout.

According to the scheme provided by the application, the FPGA is initially laid out according to a global layout algorithm to obtain an initial layout result, then the layout proportion corresponding to each laid-out unit in each unit area on the FPGA is determined according to the initial layout result, then the moving priority of each laid-out unit is determined according to the layout proportion corresponding to each laid-out unit, each laid-out unit is moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, therefore, the moving priority of the laid-out unit is determined according to the unit layout condition in each unit area, and then the laid-out units are adjusted according to the moving priority, so that the layout proportion of each laid-out unit is uniform, the increase of wiring lines can be avoided, and the time sequence of the FPGA is improved. And after each laid-out unit is moved, the moving priority of each laid-out unit is updated in time, and each laid-out unit is moved according to the updated moving priority of each laid-out unit, so that the layout efficiency can be improved.

Referring to fig. 14, which shows a schematic structural diagram of an FPGA layout apparatus according to an embodiment of the present application, in the embodiment of the present application, an FPGA layout apparatus 700 may include:

an initial layout module 701, configured to perform initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result;

a first determining module 702, configured to determine, according to an initial layout result, a layout proportion corresponding to each laid-out cell in each unit area on the FPGA, where the layout proportion corresponding to each laid-out cell is obtained according to a ratio of the number of all laid-out cells in the unit area where each laid-out cell is located to the number of placeable cells in the unit area where each laid-out cell is located;

a second determining module 703, configured to determine, according to a layout proportion corresponding to each laid-out unit, a movement priority of each laid-out unit, where the movement priority is positively correlated with the layout proportion;

a layout unit moving module 704, configured to move each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority.

In some embodiments, FPGA layout apparatus 700 may further include:

a first obtaining module, configured to obtain, before the second determining module 703 determines the moving priority of each laid-out unit according to the layout proportion corresponding to each laid-out unit, the number of target areas around each laid-out unit in each unit area on the FPGA, where the target areas are used to represent that different laid-out units exist in two adjacent unit areas;

and the third determining module is used for determining the distance from each laid-out unit in each unit area on the FPGA to the boundary of the FPGA.

In this embodiment, the second determining module 703 may include:

the calculation unit is used for calculating the moving priority value of each laid-out unit according to the priority calculation formula, the layout proportion, the number of the target areas and the distance from each laid-out unit to the boundary of the FPGA, and the moving priority value is used for representing the moving priority;

wherein, the priority calculation formula is as follows:

the priority is α · Density + β · Block _ num + γ · Edge _ dist, the priority is the moving priority value of each laid-out cell, the Density is the layout proportion, Block _ num is the number of target regions, Edge _ dist is the distance from each laid-out cell to the boundary of the FPGA, α is the weight of the layout proportion, β is the weight of the number of target regions, γ is the weight of the distance from each laid-out cell to the boundary of the FPGA, and α, β, γ ≧ 0.

In other embodiments, the placement unit moving module 704 may include:

a first moving unit for moving the target laid-out unit, the target laid-out unit being any one of the laid-out units;

the acquiring unit is used for acquiring all the unit areas capable of being laid out in the unit areas passing through in the moving process of the target laid out unit when the moving times of the target laid out unit reach the corresponding preset time threshold;

the determining unit is used for determining a target unit area corresponding to the target laid-out unit from all the unit areas capable of being laid-out according to the preset layout position selection condition;

and the layout unit is used for laying out the target laid-out unit in the target unit area.

In this embodiment, the preset layout position selection condition includes: selecting a unit area that can be laid out and has the smallest cost function value of the unit areas in all the unit areas that can be laid out, wherein the determining unit may include:

the calculating subunit is used for calculating the cost function values of all unit areas capable of being laid out according to the cost function formula;

the selecting unit is used for selecting the unit area which can be laid out and has the minimum cost function value of the unit area from all the unit areas which can be laid out as a target unit area according to the cost function value of the unit area;

wherein, the cost function formula is: cost ═ alpha₁·wirelength+α₂Slack, Cost as Cost function value of unit area, wirelength as line length of unit area, α₁Is the weight corresponding to the line length of the unit area, slack is the delay margin of the unit area, alpha₂Is a weight corresponding to the delay margin of the unit region.

In still other embodiments, FPGA placement device 700 may further include:

a determining module, configured to determine whether a target area exists in a unit area on the FPGA according to an initial layout result before the first determining module 702 determines a layout proportion corresponding to each already-laid cell in each unit area on the FPGA according to the initial layout result, where the target area is used to represent that different already-laid cells exist in two adjacent unit areas;

and the target moving module is used for moving the laid units around the target area to the same side of the target area when the unit area on the FPGA has the target area.

In this embodiment, the layout unit moving module 704 may further include:

and the second moving unit is used for moving each laid unit according to the moving priority of each laid unit until the moving priority of each laid unit is lower than the preset priority and no target area exists on the FPGA.

In still other embodiments, FPGA placement device 700 may further include:

a second obtaining module, configured to obtain, according to the initial layout result, an average distance between all the laid out units of the FPGA and a boundary of the FPGA before the first determining module 702 determines, according to the initial layout result, a layout proportion corresponding to each laid out unit in each unit area on the FPGA;

and the boundary moving module is used for moving at least part of the laid units in the boundary area of the FPGA to a unit area close to the center of the FPGA when the average distance is smaller than a preset distance threshold value until the average distance is larger than or equal to the preset distance threshold value, and the boundary area is an area in a preset range adjacent to the boundary on the FPGA.

In this embodiment, the layout unit moving module 704 may further include:

and the third moving unit is used for moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority and the average distance from all laid-out units to the boundary of the FPGA is greater than or equal to the preset distance threshold.

In still other embodiments, the layout unit moving module 704 may further include:

a fourth moving unit for moving each laid out unit according to the moving priority of each laid out unit;

and the repeating unit is used for repeating the step of determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA to the step of moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority.

According to the scheme provided by the application, the FPGA is initially laid out according to a global layout algorithm to obtain an initial layout result, then the layout proportion corresponding to each laid-out unit in each unit area on the FPGA is determined according to the initial layout result, then the moving priority of each laid-out unit is determined according to the layout proportion corresponding to each laid-out unit, and each laid-out unit is moved according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority, so that the situation that each laid-out unit is automatically laid out until the moving priority is lower than the preset priority according to the moving priority of each laid-out unit is realized, the layout proportion of each laid-out unit is uniform, the increase of wiring lines can be avoided, and the time sequence of the FPGA is further improved.

Referring to fig. 15, an electronic device 800 provided in an embodiment of the present application is shown, which includes a memory 801, a processor 802, and a computer program stored in the memory 801 and executable on the processor 802, and when the computer program is executed by the processor 802, the method described in the foregoing method embodiment is implemented.

The processor 802 may include one or more processing cores. The processor 802 interfaces with various components throughout the electronic device 800 using various interfaces and circuitry to perform various functions of the electronic device 800 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 801 and invoking data stored in the memory 801. Alternatively, the processor 802 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 802 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 802, but may be implemented solely by a communication chip.

The Memory 801 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 801 may be used to store instructions, programs, code sets, or instruction sets. The memory 801 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as initial layout, determining a layout proportion corresponding to each laid-out cell, determining a movement priority of each laid-out cell, moving each laid-out cell, etc.), instructions for implementing various method embodiments described below, and the like. The storage data area may also store data created by the electronic device 800 in use (such as initial layout results, layout proportions, movement priorities, preset priorities, and number of target areas), and the like.

Referring to fig. 16, a computer-readable storage medium 900 is shown, wherein a program code is stored in the computer-readable storage medium, and the program code can be invoked by a processor to execute the method described in the foregoing method embodiments.

The computer-readable storage medium 900 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 900 includes a non-volatile computer-readable storage medium. The computer readable storage medium 900 has storage space for program code 901 for performing any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. The program code 901 may be compressed, for example, in a suitable form.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. An FPGA layout method, characterized in that the method comprises:

performing initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result;

determining a layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result, wherein the layout proportion corresponding to each laid-out unit is obtained according to the ratio of the number of all laid-out units in the unit area where each laid-out unit is located to the number of laid-out units in the unit area where each laid-out unit is located;

determining the movement priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit, wherein the movement priority is positively correlated with the layout proportion;

and moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority.

2. The method according to claim 1, wherein before said determining the moving priority of each laid out cell according to the layout proportion corresponding to each laid out cell, the method further comprises:

acquiring the number of target areas around each laid-out unit in each unit area on the FPGA, wherein the target areas are used for representing that different laid-out units exist in two adjacent unit areas;

determining the distance from each laid out unit in each unit area on the FPGA to the boundary of the FPGA;

the determining the moving priority of each laid-out unit according to the corresponding layout proportion of each laid-out unit includes:

calculating a moving priority value of each laid-out unit according to a priority calculation formula, the layout proportion, the number of the target areas and the distance from each laid-out unit to the boundary of the FPGA, wherein the moving priority value is used for representing the height of the moving priority;

wherein the priority calculation formula is as follows:

priority is α · Density + β · Block _ num + γ · Edge _ dist, priority is a moving priority value of each laid out unit, Density is the layout proportion, Block _ num is the number of the target areas, Edge _ dist is a distance from each laid out unit to a boundary of the FPGA, α is a weight of the layout proportion, β is a weight of the number of the target areas, γ is a weight of a distance from each laid out unit to a boundary of the FPGA, and α, β, γ is equal to or greater than 0.

3. The method of claim 1, wherein said moving said each laid out cell comprises:

moving a target laid-out unit, wherein the target laid-out unit is any laid-out unit;

when the moving times of the target laid-out unit reach corresponding preset time threshold values, acquiring all unit areas which can be laid out in the unit areas passed by the target laid-out unit in the moving process;

determining a target unit area corresponding to the target laid-out unit from all the unit areas capable of being laid out according to a preset layout position selection condition;

and laying out the target laid-out unit in the target unit area.

4. The method according to claim 3, wherein the preset layout position selection condition comprises: selecting a unit region which can be laid out and has the minimum cost function value of the unit region in all the unit regions which can be laid out;

the determining a target unit area corresponding to the target laid-out unit from all the placeable unit areas according to a preset layout position selection condition includes:

calculating the cost function values of all unit areas capable of being laid out according to a cost function formula;

according to the cost function value of the unit area, selecting the unit area which can be laid out and has the minimum cost function value of the unit area from all the unit areas which can be laid out as the target unit area;

wherein the cost function formula is: cost ═ alpha₁·wirelength+α₂Slack, Cost is the Cost function value of the unit area, wirelength is the line length of the unit area, α₁Is the weight corresponding to the line length of the unit area, slack is the delay margin of the unit area, alpha₂And the weight is corresponding to the delay margin of the unit region.

5. The method according to claim 1, wherein before said determining a layout proportion corresponding to each laid out cell in each unit area on the FPGA according to the initial layout result, the method further comprises:

judging whether a target area exists in the unit areas on the FPGA according to the initial layout result, wherein the target area is used for representing that different laid units exist in two adjacent unit areas;

when the unit area on the FPGA has the target area, moving the laid units around the target area to the same side of the target area;

the moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than a preset priority comprises:

and moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority and no target area exists on the FPGA.

6. The method according to claim 1, wherein before said determining a layout proportion corresponding to each laid out cell in each unit area on the FPGA according to the initial layout result, the method further comprises:

acquiring the average distance from all laid out units of the FPGA to the boundary of the FPGA according to the initial layout result;

when the average distance is smaller than a preset distance threshold, moving at least part of laid units in a boundary area of the FPGA to a unit area close to the center of the FPGA until the average distance is larger than or equal to the preset distance threshold, wherein the boundary area is an area in a preset range adjacent to the boundary on the FPGA;

and moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than a preset priority and the average distance from all laid-out units to the boundary of the FPGA is greater than or equal to the preset distance threshold.

7. The method according to any one of claims 1-6, wherein said moving each laid out unit according to its moving priority until its moving priority is lower than a preset priority comprises:

moving each laid out cell according to the moving priority of each laid out cell;

repeating the step of determining the layout proportion corresponding to each laid-out unit in each unit area on the FPGA to the step of moving each laid-out unit according to the moving priority of each laid-out unit until the moving priority of each laid-out unit is lower than the preset priority.

8. An FPGA placement device, the device comprising:

the initial layout module is used for carrying out initial layout on the FPGA according to a global layout algorithm to obtain an initial layout result;

the first determining module is used for determining a layout proportion corresponding to each laid-out unit in each unit area on the FPGA according to the initial layout result, wherein the layout proportion corresponding to each laid-out unit is obtained according to the ratio of the number of all laid-out units in the unit area where each laid-out unit is located to the number of laid-out units in the unit area where each laid-out unit is located;

a second determining module, configured to determine a movement priority of each laid-out unit according to a layout proportion corresponding to each laid-out unit, where the movement priority is positively correlated to the layout proportion;

and the layout unit moving module is used for moving each laid unit according to the moving priority of each laid unit until the moving priority of each laid unit is lower than the preset priority.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of any of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 1 to 7.