CN106528923A - Global layout method for chip - Google Patents
Global layout method for chip Download PDFInfo
- Publication number
- CN106528923A CN106528923A CN201610857686.5A CN201610857686A CN106528923A CN 106528923 A CN106528923 A CN 106528923A CN 201610857686 A CN201610857686 A CN 201610857686A CN 106528923 A CN106528923 A CN 106528923A
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- density
- case
- chip
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- layout
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention relates to a global layout method for a chip. The global layout method for the chip comprises the steps of: creating multiple density boxes according to the structure of the chip, and acquiring a net list; performing initial layout for the chip according to a layout algorithm, mapping multiple instances to the corresponding density boxes respectively, and then judging whether the layout of the chip satisfies a global layout ending condition; if not satisfying, acquiring a set density of multiple box sets on the chip; taking the box sets having set densities greater than a density factor as seed box sets, sequentially expanding the seed box sets according to the set densities from high to low, till the set densities of the seed box sets are smaller than the density factor; judging whether the layout of the chip satisfies the global layout ending condition, and when the layout of the chip satisfies the global layout ending condition, ending the layout. The method greatly reduces the number of iterations of global layout of the chip, and distributes the instances more uniformly while reducing the global layout time.
Description
Technical field
A kind of the present invention relates to chip layout field, more particularly to chip global wiring method.
Background technology
Field programmable gate array (Field Programmable Gate Array, FPGA), it is as special integrated
A kind of semi-custom circuit in circuit (Application Specific Integrated Circuit, ASIC) field and go out
Existing, the deficiency of custom circuit had both been solved, the limited shortcoming of original programming device gate circuit number had been overcome again.Suitable for patrolling
The multiple fields such as volume control, signal transacting, image procossing, only in China, the market of fpga chip just more than 10,000,000,000 RMB, and
And increased with 30% annual speed, importance is self-evident.
The use of FPGA be unable to do without electric design automation (Electronic Design Automation, EDA) instrument
Cooperation, including design input, debugging, functional simulation, synthesis, the flow process such as placement-and-routing；Wherein, FPGA layouts are by circuit network
Example (instance) in table is configured to the process of logic moulding box in FPGA structure, and the good and bad of layout result directly determines chip
The quality of performance.Existing placement algorithm has certain deficiency with operation result at runtime.
The content of the invention
A kind of chip global wiring method is embodiments provided, the method includes：Create many according to chip structure
Individual density case, and obtain the netlist for including multiple examples；Initial layout is carried out for chip according to placement algorithm, so as to by multiple realities
Example is respectively mapped to corresponding density case；The geometry density of multiple case set on simultaneously computing chip is obtained, each case set includes
Multiple density casees；Using geometry density more than density factor case set as seed-box set, and according to geometry density from greatly to
Case set is sorted by little order, obtains set queue；Successively seed-box set is extended according to set queue, until planting
The geometry density of sub- case set is less than density factor, and seed-box set corresponding multiple examples are mapped to corresponding density
Case；Judge whether chip layout meets global wiring termination condition, when chip layout meets global wiring termination condition, terminate complete
Office's layout.
Alternatively, said method also includes, according to the size of seed-box set calculate the intensity of each seed-box set because
Son, to determine the pulling force suffered by each example included in seed-box set in expansion process.
Alternatively, said method also includes, when chip layout is unsatisfactory for global wiring termination condition, then obtains and calculates
The geometry density of multiple case set on chip.
Alternatively, said method also includes, after initial layout terminates, judges whether chip layout meets global wiring
Termination condition, terminates global wiring if meeting.
Alternatively, on above-mentioned computing chip each case set geometry density, including：Obtain corresponding to each case set
Multiple density casees, according to the case density of the calculation of capacity density case of the quantity of example and density case in each density case；According to
Multiple case density of the multiple case density for obtaining are calculated, the geometry density for obtaining case set is calculated.
Alternatively, on above-mentioned computing chip each case set geometry density, also include：Obtain corresponding to each case set
Multiple density casees, obtain and according in calculation of capacity each case set of the quantity of example and density case in each density case
Example quantity and the tankage of case set；Each case is calculated according to the quantity and tankage of example in each case set
The case density of set.
Alternatively, it is above-mentioned successively seed-box set to be extended according to set queue, including：It is according to set queue, excellent
The big seed-box set of first expanded set density, and in expansion process, for same seed-box set is only once expanded
Exhibition.
The method provided by the embodiment of the present invention, compared to prior art, largely reduce chip overall situation cloth
The iterations of office, reduce the global wiring time while so that example more uniformly spreads.
Description of the drawings
Fig. 1 carries out global wiring process for Force-directed algorithms in the prior art for providing of the invention to chip and shows
It is intended to；
Fig. 2 provides a kind of chip global wiring method flow schematic diagram for the embodiment of the present invention；
Fig. 3 is the seed-box set expansion process schematic of a chip A provided in an embodiment of the present invention；
Fig. 4 carries out chip global wiring process schematic by providing method using the embodiment of the present invention.
Specific embodiment
Below by drawings and Examples, technical scheme is described in further detail.
Power guiding Force-directed algorithms are to use a kind of more placement algorithm, force-directed cloth at present
Connection of the office by example (instance) and example between is regarded as spring, and under spring force, example can be fixed in spy
Positioning is put, and it is to cause the overlap of example (overlap) that force-directed layouts have a problem, for how to solve weight
Folded problem, has the algorithm based on force-directed such as RQL, FDP, FAR, mFAR, FastPlace at present.It is concrete in FPGA
Layout in, using Force-directed algorithms to the detailed process that chip is laid out be：
Fig. 1 carries out global wiring process for Force-directed algorithms in the prior art for providing of the invention to chip and shows
It is intended to, as shown in figure 1, one-to-one bin therewith is set up according to the logic moulding box array (figure a) in fpga chip structure,
After initial layout is carried out to chip, each example (instance) in netlist (netlist) is mapped in corresponding bin
(figure b)；There are multiple examples and concentrate in some bin due in an initial condition more, the example in bin is made far beyond bin
The capacity of itself, now, using each example as a node, the gauze (net) between example is used as a bullet for PDA algorithms
Spring, under the action of the spring, each node (example) can change position under force；But due to example in the bin of part
Density is excessive, it will usually set up dummy node (pseudonode) on FPGA borders, and dummy node is carried out with node (example)
Connection, so that example changes position under force, then recalculates the position of example, and is configured in corresponding bin
(figure c)；And so on, loop iteration, until meet global wiring termination condition (figure d).
The shortcoming of Force-directed algorithms is：The bin higher for density, needs multiple circular treatment, process time
It is longer；Even and if there is layout and terminate, in high density bin, the situation of the quantity of example capacity still far beyond bin is (such as
The capacity of the far super bin1 of example quantity in bin1 in d is schemed in Fig. 1), it is very unfavorable to chip partial layout or even wiring process.
The embodiment of the present invention provides a kind of chip global wiring method, by setting up density case (density bin) data
Structure, after every wheel example movement, map example to corresponding density case includes the case set of multiple density casees according to each
The size of geometry density is ranked up, case set of the expanded set density higher than density factor, and calculates each case set
Intensity factor, increases the pulling force of each example according to the size of intensity factor.The new position that each example is calculated according to pulling force is simultaneously
Move, until meeting the condition that global wiring terminates.
Fig. 2 provides a kind of chip global wiring method flow schematic diagram for the embodiment of the present invention, as shown in Fig. 2 the method
Including：
Step S101, according to the multiple density casees of Structure Creating of chip, and obtains the netlist corresponding to chip, the netlist bag
Include the multiple examples that need to be arranged in chip.
Step S102, carries out initial layout according to placement algorithm for chip, and the multiple examples in netlist are respectively mapped to
Corresponding density case, determines the position of each example.
It should be noted that the placement algorithm provided by the embodiment of the present invention is power guides (Force-directed, PDA)
Algorithm, specially
Step S103, judges whether chip layout meets global wiring and terminate, if meeting, execution step S108, otherwise
Execution step S104.
It should be noted that global wiring termination condition can be respectively less than for the geometry density of each case set on chip
(or being equal to) density factor；The density factor of the case set corresponding region can also be met for the geometry density of respective tank set.
Step S104, the multiple case set included on acquisition chip layout, and the geometry density of each case set is calculated,
Obtain multiple geometry density (ρ '1、ρ′2……ρ′m), each case set includes multiple density casees.
Optionally, the calculation of the geometry density of case set includes calculation one：It is many that acquisition case set is included
Individual density case, and calculate the case density (ρ of each density case1、ρ2……ρn), the computing formula of case density is formula (1)：
Wherein, ρiFor case density, and i=1,2 ... n, n is positive integer；The capacity (capacity) of density case refers to close
The particular number of open ended difference (or identical) example of degree case.
After the case density for obtaining each density case is calculated, the geometry density of case set, tool is calculated according to multiple case density
Body computing formula is formula (2)：
Wherein, ρ 'iFor geometry density, i is the numbering of correspondence case set, ρiThe case of the density case included by the case set
Density.
Optionally, the calculation of the geometry density of case set also includes calculation two：Obtain what case set was included
Multiple density casees, and obtain quantity m of the example included by each density casei(i is 1,2 ... n), and counted according to formula (3)
Calculate quantity M of the example included by case seti；And the capacity c of each density casei(i is 1,2 ... n), and according to formula
(4) tankage of case set, and the final case density for calculating acquisition case set according to formula (5) is calculated, specifically：
Wherein, in formula (5), i refers to the numbering of the case set.
Step S105, geometry density is more than the case set of density factor α as seed-box set, and according to each seed
The order that the geometry density of case set is descending is ranked up to seed-box set, obtains set queue.
It should be noted that density factor α is determined according to practical experience, the density factor of different chips is different, enters
One step, the density factor of same chip diverse location is also differed.
Step S106, is extended to seed-box set successively according to the order of seed-box set in set queue, until
The geometry density of seed-box set is less than density factor, and the example corresponding to each seed set is mapped to corresponding density
Case, calculates the new position for determining each example, then execution step S103.
Optionally, in the expansion process to seed-box set, need to according to shared by seed-box set the size in region etc., really
The intensity factor β of the fixed seed-box set, and determine that each example is in expansion process in the seed-box set according to intensity factor
In suffered pulling force size.In specific expansion process, region shared by seed-box set is bigger, the collection of seed-box set
Conjunction density is bigger, and the pulling force in seed-box set suffered by each example is bigger.
Optionally, during being extended to seed-box set, for same seed-box set is only once expanded
Exhibition, i.e.,：If currently wait the seed-box set for extending Already in before seed-box set extension after region when, not to work as
Before seed-box set to be extended be extended.Such as：Fig. 3 is the seed-box set of a chip A provided in an embodiment of the present invention
Expansion process schematic diagram, as shown in figure 3, during the global wiring of chip A, the set queue of acquisition is ρ '1>ρ′2>ρ′3>
ρ′4, geometry density ρ '1、ρ′2、ρ′3、ρ′4Seed-box set A1, seed-box set A2, seed-box set A3, seed is corresponded to respectively
Case set A4.Before being extended to seed-box set, the concrete placement position of each seed-box set is as shown in Fig. 3-a, then right
The concrete expansion process of the seed-box set of chip A is：According to set queue, the geometry density of seed-box set A1 is maximum, excellent
First A1 is extended, as shown in Fig. 3-b, case set A1 ' (as shown in Fig. 3-b), and A3 is obtained after being extended to A1
Have been extended to case set A1 '；Then according to set queue, (this process is not shown in the diagram) is extended to A2；According to collection
It is that A3 is extended to close queue next step, but is entered in A1 ' as A3 is expanded in the expansion process of A1, therefore not
Again A3 is extended；Finally A4 is extended (do not show in this procedure chart).
It should be noted that during the extension carried out to seed-box set, the collection of case set after expansion
Conjunction density just stops the extension to the seed-box set less than density factor, and this kind of mode can inherently reduce loop iteration
Number of times, shorten global wiring time.
Step S107, terminates global wiring.
Below in conjunction with the accompanying drawings said method is illustrated, Fig. 4 is carried out by providing method using the embodiment of the present invention
Chip global wiring process schematic, is entered to chip as shown in figure 4, illustrating in figure using the provided method of the embodiment of the present invention
The four-stage of row global wiring, further according to the Structure Creating density case (such as Fig. 4-a) of chip after, initial layout is carried out to chip
(such as Fig. 4-b), it is clear that after initial layout, the geometry density of chip section box set are excessive, are then being carried according to the present invention
(expansion process such as Fig. 4-c) is extended to the seed-box set for determining for method, final acquisition meets global wiring and terminates bar
Part terminates layout (such as Fig. 4-d), it is clear that after the provided method of the embodiment of the present invention carries out global wiring, in chip no longer
There is the excessive case set of geometry density, the distribution of example is also more uniform.
Above-described specific embodiment, has been carried out further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail, the be should be understood that specific embodiment that the foregoing is only the present invention is not intended to limit the present invention
Protection domain, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc. all should include
Within protection scope of the present invention.
Claims (7)
1. a kind of chip global wiring method, it is characterised in that methods described includes：
Multiple density casees are created according to chip structure, and obtains the netlist for including multiple examples；
Initial layout is carried out for the chip according to placement algorithm, so that the plurality of example is respectively mapped to corresponding density
Case；
The geometry density of multiple case set on the chip is obtained and calculates, each described case set includes multiple density
Case；
Using the geometry density more than density factor case set as seed-box set, and according to the geometry density from greatly to
The case set is sorted by little order, obtains set queue；
Successively the seed-box set is extended according to the set queue, until the geometry density of the seed-box set
Less than the density factor, and the seed-box set corresponding multiple examples are mapped to into the corresponding density case；
Judge whether the chip layout meets global wiring termination condition, when the chip layout meets the global wiring knot
Beam condition, terminates global wiring.
2. method according to claim 1, it is characterised in that methods described also includes：
The intensity factor of each seed-box set is calculated according to the size of the seed-box set, so as to the expansion process
Pulling force suffered by middle each example determined included in the seed-box set.
3. method according to claim 1, it is characterised in that methods described also includes：
When the chip layout is unsatisfactory for the global wiring termination condition, then multiple case collection on the chip are obtained and calculate
The geometry density of conjunction.
4. the method according to claim 1 or 3, it is characterised in that methods described also includes：
After the initial layout terminates, judge whether the chip layout meets global wiring termination condition, if meeting
Terminate global wiring.
5. method according to claim 1, it is characterised in that the set of each case set is close on the calculating chip
Degree, including：
Obtain the multiple described density case corresponding to each described case set, according to the quantity of example described in each density case with
And the case density of density case described in the calculation of capacity of the density case；
According to the multiple described case density for calculating the multiple described case density for obtaining, the set for calculating the acquisition case set is close
Degree.
6. method according to claim 1 or 5, it is characterised in that the collection of each case set on the calculating chip
Density is closed, is also included：
The multiple described density case corresponding to each described case set is obtained, is obtained and according to real described in each described density case
The quantity of the example in calculation of capacity each described case set of the quantity of example and the density case and the case collection
The tankage of conjunction；
It is close according to the case that the quantity and the tankage of example described in each described case set calculate each case set
Degree.
7. method according to claim 1, it is characterised in that it is described according to the set queue successively to the seed-box
Set is extended, including：
According to the set queue, the big seed-box set of preferential expanded set density, and in expansion process, for same
The seed-box set only carries out one extension.
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| CN201610857686.5A CN106528923B (en) | 2016-09-27 | 2016-09-27 | A kind of chip global wiring method |
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| CN201610857686.5A CN106528923B (en) | 2016-09-27 | 2016-09-27 | A kind of chip global wiring method |
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| CN111753486A (en) * | 2020-06-30 | 2020-10-09 | 无锡中微亿芯有限公司 | Novel layout method of multi-die structure FPGA |
| CN111931447A (en) * | 2020-07-22 | 2020-11-13 | 深圳市紫光同创电子有限公司 | FPGA layout method and device, electronic equipment and storage medium |
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Denomination of invention: Global layout method for chip Effective date of registration: 20200228 Granted publication date: 20190813 Pledgee: Beijing Yizhuang International Financing Guarantee Co., Ltd. Pledgor: Jingwei Qili (Beijing) Technology Co., Ltd. Registration number: Y2020990000141 |
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