CN108073740A - A kind of simulated annealing method of FPGA detailed placements - Google Patents
A kind of simulated annealing method of FPGA detailed placements Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
A kind of simulated annealing method of FPGA detailed placements, the initial temperature that initial layout calculating simulation according to being formed after the layout that legalizes is annealed, mobile unit module optimizes current arrangements, the receptance moved according to unit module, the temperature value of single goal is fixed on the basis of initial temperature the iteratively adjusting of ratio, the desired value of multiple target is normalized using normalization coefficient, iterative calculation is modified to the single goal temperature value after iteratively adjusting using temperature proportional coefficient, obtains the temperature value of multiple target.The present invention is on the basis of single object optimization, normalized has been carried out to multiple-objection optimization and proportionality coefficient is adjusted, it ensure that the uniformity of optimum results and the validity of multiple-objection optimization, influence caused by eliminating the unreasonable quality and speed layout of strategy that cool down in traditional analog method for annealing, the temperature after adjusting are more conducive to the raising of placement quality and speed.
Description
Technical field
The present invention relates to IC design field more particularly to a kind of simulated annealing methods of FPGA detailed placements.
Background technology
FPGA employs logical cell array LCA (Logic Cell Array) such a concept, and inside includes to match somebody with somebody
Put logic module CLB (Configurable Logic Block), input/output module IOB (Input Output Block) and
Three parts of interconnector (Interconnect).Field programmable gate array (FPGA) is programming device, with traditional logic
Circuit and gate array (such as PAL, GAL and CPLD device) are compared, and FPGA has different structures.FPGA utilizes small-sized look-up table
(16 × 1RAM) realize combination logic, and each look-up table is connected to the input terminal of a d type flip flop, trigger drives it again
His logic circuit or driving I/O, can not only combination logic function be realized but also can realize the basic of sequential logic function by thus constituting
Logic unit module, these intermodules are interconnected or are connected to I/O modules using metal connecting line.The logic of FPGA be pass through to
Internal stationary storage unit loads programming data come what is realized, and the value stored in a memory cell determines patrolling for logic unit
The connecting mode between function and each module or between module and I/O is collected, and finally determines the function achieved by FPGA,
FPGA allows unlimited number of programming.
The development process of typical FPGA generally comprise function definition/parts selection, design input, functional simulation, integrate it is excellent
Change, comprehensive post-simulation, layout, wiring, post-simulation, the emulation of plate grade and the key steps such as chip programming and debugging.
The automation layout of fpga chip comprises the steps of：Input and output are laid out, global clock layout, initial layout,
Total arrangement, the layout that legalizes and detailed placement.
Layout is a step relatively time-consuming in whole flow process, and the hardware primitive in logic netlist and bottom floor units is reasonable
Ground is configured on the intrinsic hardware configuration of chip internal, and generally requires to make choosing between speed is optimal and area is optimal
It selects.At present, the scale of FPGA is increasing, and structure becomes increasingly complex, and the type of wherein logic unit module is more and more, and wraps
Containing as this big logic units of DSP and RAM, and the cabling between some units is all fixed (hard) connection, such as carry
Chain (carry chain) and shift register (shift register) etc., these all limit the random pendulum of logic unit
It puts, particularly when there is Timing Constraints, since layout plays decisive role to the speed of FPGA domain speed, from cloth
Temporal constraint will be taken into account during office, and be difficult otherwise to meet the constraint of sequential by optimizations such as subsequent wirings.Cause
How this, quickly and effectively carry out automation layout, plays the role of to FPGA layout designs vital.
Traditional simulated annealing method is it is difficult to ensure that multi-goal optimizing function only optimizes simple target and single object optimization letter
Number optimizes the uniformity of simple target result, the unreasonable quality and speed to layout for the strategy that cools down in traditional analog method for annealing
Degree impacts.
The content of the invention
The present invention provides a kind of simulated annealing method of FPGA detailed placements, on the basis of single object optimization, to more mesh
Mark optimization has carried out normalized and proportionality coefficient and has adjusted, ensure that optimum results uniformity and multiple-objection optimization it is effective
Property, influence caused by eliminating the unreasonable quality and speed layout of strategy that cool down in traditional analog method for annealing is adjusted
Temperature afterwards is more conducive to the raising of placement quality and speed.
In order to achieve the above object, the present invention provides a kind of simulated annealing method of FPGA detailed placements, includes following step
Suddenly：
The initial temperature that initial layout calculating simulation according to being formed after the layout that legalizes is annealed, mobile unit module is to working as
Preceding layout optimizes, and according to the receptance that unit module moves, the temperature value of single goal is carried out on the basis of initial temperature
The iteratively adjusting of fixed proportion is normalized the desired value of multiple target using normalization coefficient, using temperature proportional coefficient
Iterative calculation is modified to the single goal temperature value after iteratively adjusting, obtains the temperature value of multiple target.
The method of the initial temperature of calculating simulation annealing comprises the steps of：
Step S1.1, multiple unit modules are chosen to be moved or exchanged；
Step S1.2, calculating target function value Total_cost；
The target function value of target function value+v2 × optimization aim 2 of Total_cost=v1 × optimization aim 1+...+vn
The target function value of × optimization aim n；
Wherein, v1~vn is the specific gravity factor of each optimization aim, v1+v2+ ...+vn=1；
Step S1.3, knots modification of the movement to target function value of each unit module is calculated；
The target function value before target function value-movement after knots modification=movement of target function value；
Step S1.4, the mean square deviation of all knots modifications is calculated, using the mean square deviation as the initial temperature of simulated annealing.
For single object optimization, by taking line length as an example, the target function value of single goal is reduced to：
Total_cost=bb_cost (1)
Wherein, bb_cost is the cost of line length, and the cost of line length is equal to gauze and connects all unit module positions
The semi-perimeter of external envelope rectangle；
For biobjective scheduling, by taking line length and time delay as an example, the target function value of Bi-objective is reduced to：
Wherein, td_cost is the cost of time delay；Pin is the pin of gauze, and num_pin is the number of pin, weight
(num_pins) be line length weight, it is related to the num numbers of pin pins；Delay be gauze driving to each by driving point
Time delay；Slack is the slackness of gauze time delay；Require_time is the maximum allowable time delay value of gauze；Max_cirt is
Maximum criticality；Exponent is index, and x_length is width of the external envelope rectangle along X-direction；Y_length is outsourcing
Width of the network rectangle along Y direction；Tradeoff is line length and the specific gravity factor of time delay；Prev_total_bb_cost is upper one
Take turns the target function value of the line length of iteration；Prev_total_td_cost is the target function value of the time delay of last round of iteration.
The method of the receptance of the computing unit module movement comprises the steps of：
Step S2.1, multiple unit modules are chosen to be moved or exchanged；
Step S2.2, knots modification of the movement to target function value of each unit module is calculated；
The target function value before target function value-movement after knots modification=movement of target function value；
Step S2.3, judge the numerical value of the knots modification of target function value, if the numerical value of knots modification is negative value, receive this
The secondary movement to unit module if the numerical value of knots modification is positive value, determines whether the numerical values recited of knots modification, if changed
The numerical value of variable is less than 1% of the target function value after movement, then receives this time movement to unit module, if knots modification
Numerical value is more than or equal to 1% of the target function value after movement, then refusal this time movement to unit module, unit module is recovered
Position before to movement；Received movement is successfully to move, and unaccredited movement is invalid movement；
Step S2.4, the total knots modification of the number and object function of successfully movement is counted；
The total knots modification of the object function be equal to the movements of all unit modules to the knots modification of target function value it
With.
The movement or the unit module of exchange include random movement sequence and specific mobile sequence, the random shifting
Dynamic sequence is the mobile sequence randomly generated, and the movement of the specific mobile sequence can reduce target function value.
The movement or exchange of the unit module are required for ensureing the legitimacy being laid out.
The method of the iteratively adjusting that ratio is fixed to the temperature value of single goal includes：
T (iter)=T (prev_iter) × Scale (success_move_rate)
0.5 ＜ Scale (success_move_rate) ＜ 1
Wherein, T is single goal temperature；Iter is current iteration number；Prev_iter is last round of iterations, if
Epicycle is first time iteration, then T (prev_iter) is the initial temperature of simulated annealing；Scale is the ratio letter that temperature reduces
Number；Success_move_rate is the receptance of unit module movement, number/total movement of mobile receptance=success movement
Number.
The normalization coefficient is the target function value of last round of iteration.
The method that iterative calculation is modified to the single goal temperature value after iteratively adjusting includes：
Wherein,It is temperature proportional coefficient, current_total_cost is last round of
The general objective functional value of iteration, previous_total_cost are the general objective functional values of epicycle iteration.
When iteration meets any one end condition, then stop being laid out；
The end condition includes：The iterations knots modification total more than object function after given threshold or iteration
Less than target function value before iteration 2% either temperature value is less than 1e-5 or the mobile number of success is less than mobile total degree
5%.
The present invention has carried out normalized and proportionality coefficient tune on the basis of single object optimization, to multiple-objection optimization
Section, ensure that the uniformity of optimum results and the validity of multiple-objection optimization, eliminates the plan that cools down in traditional analog method for annealing
Influence caused by unreasonable quality and speed layout slightly, the temperature after adjusting are more conducive to carrying for placement quality and speed
It is high.
Description of the drawings
Fig. 1 is a kind of flow chart of the simulated annealing method of FPGA detailed placements provided by the invention.
Fig. 2 is the mobile schematic diagram of unit module.
Fig. 3 is unit module movement number schematic diagram.
Specific embodiment
Below according to Fig. 1~Fig. 3, presently preferred embodiments of the present invention is illustrated.
As shown in Figure 1, the present invention provides a kind of simulated annealing method of FPGA detailed placements, comprise the steps of：
Step S1, according to the initial temperature of the initial layout calculating simulation annealing formed after the layout that legalizes；
In the step S1, the method for the initial temperature of calculating simulation annealing comprises the steps of：
Step S1.1, multiple unit modules are chosen and is moved or exchanged the (unit module that solid black lines indicate in such as Fig. 2
Mobile or exchange)；
The quantity of the unit module of selection is set as the case may be, such as：It can be set as all unit modules
1.5 times of quantity；
The multiple unit modules chosen include two parts：Most is the mobile sequence randomly generated, in addition minimum
Part is the specific mobile sequence generated according to object function, and the moving direction of these specific mobile sequences can make object function
Value reduction (for example the unit of all connections just moves directly up all above this unit, excess-three direction is just directly neglected
It omits)；
The movement of each step unit module is required for ensureing the legitimacy being laid out, type and and equipment including unit module
Some relevant firm constraints etc.；
Step S1.2, calculating target function value Total_cost；
The target function value of target function value+v2 × optimization aim 2 of Total_cost=v1 × optimization aim 1+...+vn
The target function value of × optimization aim n；
Wherein, v1~vn is the specific gravity factor of each optimization aim, v1+v2+ ...+vn=1；The optimization aim is line
Length, time delay, power consumption and heat dissipation etc., optimization aim are the forms after normalization, ensure that multiple target is comparable；
(only optimize line length for single object optimization or only optimize time delay), the target function value of single goal is reduced to (with line
Exemplified by length)：
Total_cost=bb_cost (1)
Wherein, bb_cost is the cost of line length, and the cost of line length is equal to gauze and connects all unit module positions
The semi-perimeter of external envelope rectangle；
For biobjective scheduling (while optimizing line length and time delay), the target function value of Bi-objective is reduced to：
Wherein, td_cost is the cost of time delay；Pin is the pin of gauze, and num_pin is the number of pin, weight
(num_pins) be line length weight, it is related to the num numbers of pin pins；Delay be gauze driving to each by driving point
Time delay；Slack is the slackness of gauze time delay；Require_time is the maximum allowable time delay value of gauze；Max_cirt is
Maximum criticality；Exponent is index, can according to circumstances be selected, such as 2 powers, 3 powers etc.；X_length is external envelope square
Width of the shape along X-direction；Y_length is width of the external envelope rectangle along Y direction；Tradeoff is line length and time delay
Specific gravity factor；Prev_total_bb_cost is the target function value of the line length of last round of iteration；prev_total_td_cost
It is the target function value of the time delay of last round of iteration；
Step S1.3, knots modification of the movement to target function value of each unit module is calculated；
The target function value before target function value-movement after knots modification=movement of target function value；
Wherein, no matter moving or exchange makes target function value increase or reduce, and all using the movement or exchanges as success
It is mobile；
Step S1.4, the mean square deviation of all knots modifications is calculated, using the mean square deviation as the initial temperature of simulated annealing；
Mean square deviation is bigger, and layout result is poorer, and layout state is more unstable；
Step S2, mobile unit module optimizes current arrangements to be more preferably laid out；
In the step S2, the method for optimizing layout comprises the steps of：
Step S2.1, multiple unit modules are chosen to be moved or exchanged；
The quantity of the unit module of selection is set as the case may be, such as：It can be set as all unit modules
1.5 times of quantity；
The multiple unit modules chosen include two parts：Most is the mobile sequence randomly generated, in addition minimum
Part is the specific mobile sequence generated according to object function, and the moving direction of these specific mobile sequences can make object function
Value reduction (for example the unit of all connections just moves directly up all above this unit, excess-three direction is just directly neglected
It omits)；
The movement of each step unit module is required for ensureing the legitimacy being laid out, type and and equipment including unit module
Some relevant firm constraints etc.；
Step S2.2, knots modification of the movement to target function value of each unit module is calculated；
The target function value before target function value-movement after knots modification=movement of target function value；
Step S2.3, the numerical value of the knots modification of target function value is judged, if the numerical value of knots modification (represents target for negative value
Functional value reduces), then receive this time movement to unit module, if the numerical value of knots modification, which is positive value, (represents object function
Value increases), then determine whether the numerical values recited of knots modification, if the numerical value of knots modification be less than it is mobile after target function value
1%, then receive this time movement to unit module, if the numerical value of knots modification be more than or equal to it is mobile after target function value
1%, then unit module is restored to the position before movement by the refusal this time movement to unit module；
Received movement is successfully to move, and unaccredited movement is invalid movement；
Step S2.4, the total knots modification of the number and object function of successfully movement is counted；
The total knots modification of the object function be equal to the movements of all unit modules to the knots modification of target function value it
With；
Step S3, judge whether iteration meets end condition, if satisfied, then stopping being laid out, if not satisfied, then carrying out step
S4；
The end condition includes：Iterations, which is more than given threshold, (can be set as iteration threshold in the present embodiment
30 times) either the total knots modification of object function is less than 2% or temperature value of target function value before iteration and is less than 1e- after iteration
5 or the mobile number of success be less than 5% etc. of mobile total degree；
As long as meeting any one condition in end condition, just stop layout, if all conditions in end condition
It is all unsatisfactory for, then carries out step S4, continue to iterate to calculate；
Step S4, the temperature value of simulated annealing is updated, carries out step S2；
In the step S4, the method for updating the temperature value of simulated annealing specifically comprises the steps of：
Step S4.1, the temperature that ratio is fixed is adjusted, according to the receptance that unit module moves to the temperature of single goal
Angle value is iterated calculating：
T (iter)=T (prev_iter) × Scale (success_move_rate)
0.5 ＜ Scale (success_move_rate) ＜ 1
Wherein, T is single goal temperature；Iter is current iteration number；Prev_iter is last round of iterations, if
Epicycle is first time iteration, then T (prev_iter) is the initial temperature of simulated annealing；Scale is the ratio letter that temperature reduces
Number can adjust the proportionality coefficient of proportion function according to actual conditions；Success_move_rate is connecing for unit module movement
By rate, mobile receptance=number of success movement/always moves number；
In hot stage, the mobile mobile number phase also high, but that target function value is made to become smaller of number of unit module success
To relatively low, high cooling ratio also should be ensured that at this time, referring to Fig. 3 high temperatures part；
In middle thermophase, after temperature reduces to a certain extent, the scope of unit module movement becomes smaller, success movement
Although number is reduced, the unit movement number for making target function value reduction at this time is relatively high, therefore should maintain existing shape
State for a period of time, so as to should ensure that low cooling ratio, referring to isothermal segment in Fig. 3；
In cold stage, when temperature further reduces, the scope of unit module movement is smaller, effective unit module
Mobile further to reduce, so that the unit movement number of target function value reduction is maintained at relatively low state, this stage should
It is appropriate to accelerate cooling, ensure simulated annealing Fast Convergent, referring to low temperature part in Fig. 3；
Step S4.2, using the target function value of last round of iteration as normalization coefficient, the desired value of multiple target is carried out
Normalization；
During the multiple-objection optimizations such as latency model are carried out, due to the inconsistency of multiple object functions, such as gauze
Time delay reduction line length may become larger or the time delay of line length reduction gauze is not necessarily reduced, and the variable quantity of multiple targets is not
In same dimension, so each desired value should be normalized first, such as the cost of gauze and the cost values of time delay, one or two of mesh of uniting
Target dimension ensures the uniformity of result between the comparativity of result and iterative steps；
Step S4.3, based on the single goal temperature that step S4.1 is obtained, using temperature proportional coefficient to multiple target
The iterative calculation that temperature value is modified：
Wherein,It is temperature proportional coefficient, current_total_cost is last round of
The general objective functional value of iteration, previous_total_cost are the general objective functional values of epicycle iteration；
In one embodiment of the invention, by taking Bi-objective as an example, the derivation of temperature proportional coefficient is carried out：
Two desired values are normalized, using the target function value of previous round iteration as normalization coefficient, calculate this
Take turns the target function value of the Bi-objective of iteration；
Wherein, td_cost is the cost of time delay；Pin is the pin of gauze, and num_pin is the number of pin, weight
(num_pins) be line length weight, it is related to the num numbers of pin pins；Delay be gauze driving to each by driving point
Time delay；Slack is the slackness of gauze time delay；Require_time is the maximum allowable time delay value of gauze；Max_cirt is
Maximum criticality；Exponent is index, and x_length is width of the external envelope rectangle along X-direction；Y_length is outsourcing
Width of the network rectangle along Y direction；Tradeoff is line length and the specific gravity factor of time delay；Prev_total_bb_cost is upper one
Take turns the target function value of the line length of iteration；Prev_total_td_cost is the target function value of the time delay of last round of iteration；
According to the temperature iterative value of single goal temperature computation Bi-objective；
Due to the inconsistency of multiple object functions, if the temperature alternative manner of single goal directly is applied to Bi-objective
Temperature alternative manner in, biobjective scheduling result and single object optimization result can be caused inconsistent；
Single goal temperature value is multiplied by a Bi-objective proportionality coefficient, obtains the temperature iterative value of Bi-objective：
Wherein, bbn-2/bbn-1It is Bi-objective proportionality coefficient, bbn-2It is the general objective functional value of last round of iteration, bbn-1It is
The general objective functional value of epicycle iteration, the derivation method of the Bi-objective proportionality coefficient include：
Given initial layout, the cost of line length is all bb_init, as shown in formula (3)：Line length drives：total_cost
=bb_init
Latency model：Total_cost=bb_init/bb_init=1.0
(3)
During obtaining initial temperature, shown in the received probability of the movement such as formula (4) of each unit module：
Line length drives：
Latency model：
bb_driven:Δ bb=Δs bb0, T=T0, Δ bb/T=Δs bb0/T0
td_driven:Δ bb=Δs bb0/ bb_init, T=T0/ bb_init, Δ bb/T=Δs bb0/T0
Line length drives the acceptance probability identical with latency model acquisition, so step layout result still maintains consistent；
In first round layout optimization, shown in the acceptance probability such as formula (5) of unit module movement：
Line length drives：
Latency model：
Latency model has more a proportionality coefficient bb0/ bb_init, therefore cause line length driving and the movement of latency model unit
Receptance it is different, so as to cause result generate difference；
In second wheel layout optimization, shown in the acceptance probability such as formula (6) of unit module movement：
Line length drives：
Latency model：
Latency model has more a proportionality coefficient bb1/ bb_init, therefore cause line length driving and the movement of latency model unit
Receptance it is different, so as to cause result generate difference；
In n-th wheel layout optimization, and so on, latency model has more proportionality coefficient bb at this timen-1/ bb_init, though this
A ratio is gradually decreased due to the optimization of layout result, but always makes the unit movement receptance of two kinds of optimizations different, is led
Cause layout result difference；
It, be to temperature in the cooling strategy of timing driven placement therefore in order to keep objective optimization cooling strategy validity
The calculation of the variable quantity of degree or line length changes, in order to which it is made easily to expand to multiple target, to the tune of temperature
Section is more prone to it, so as to often walk temperature reduction certain proportion in latency model and then be multiplied by a proportionality coefficient bbn-2/
bbn-1, after often taking turns the adjusting of iteration temperature, as tradeoff=0, timing driven placement result is laid out with line length driving
As a result.
The present invention has carried out normalized and proportionality coefficient tune on the basis of single object optimization, to multiple-objection optimization
Section, ensure that the uniformity of optimum results and the validity of multiple-objection optimization, eliminates the plan that cools down in traditional analog method for annealing
Influence caused by unreasonable quality and speed layout slightly, the temperature after adjusting are more conducive to carrying for placement quality and speed
It is high.The present invention can not only be applied in the timing driven placement of biobjective scheduling, it is easy to expand to multiple target (such as power consumption
With heat dissipation etc.) optimization process among.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a kind of simulated annealing method of FPGA detailed placements, which is characterized in that comprise the steps of：
The initial temperature that initial layout calculating simulation according to being formed after the layout that legalizes is annealed, mobile unit module is to current cloth
Office optimizes, and according to the receptance that unit module moves, the temperature value of single goal is fixed on the basis of initial temperature
The iteratively adjusting of ratio is normalized the desired value of multiple target using normalization coefficient, using temperature proportional coefficient to warp
The single goal temperature value crossed after iteratively adjusting is modified iterative calculation, obtains the temperature value of multiple target.
2. the simulated annealing method of FPGA detailed placements as described in claim 1, which is characterized in that calculating simulation is annealed first
The method of beginning temperature comprises the steps of：
Step S1.1, multiple unit modules are chosen to be moved or exchanged；
Step S1.2, calculating target function value Total_cost；
The target function value of target function value+v2 × optimization aim 2 of Total_cost=v1 × optimization aim 1+...+vn × excellent
Change the target function value of target n；
Wherein, v1~vn is the specific gravity factor of each optimization aim, v1+v2+ ...+vn=1；
Step S1.3, knots modification of the movement to target function value of each unit module is calculated；
The target function value before target function value-movement after knots modification=movement of target function value；
Step S1.4, the mean square deviation of all knots modifications is calculated, using the mean square deviation as the initial temperature of simulated annealing.
3. the simulated annealing method of FPGA detailed placements as claimed in claim 2, which is characterized in that for single object optimization,
By taking line length as an example, the target function value of single goal is reduced to：
Total_cost=bb_cost (1)
Wherein, bb_cost is the cost of line length, and the cost of line length is equal to the outsourcing that gauze connects all unit module positions
The semi-perimeter of network rectangle；
For biobjective scheduling, by taking line length and time delay as an example, the target function value of Bi-objective is reduced to：
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<mo>&times;</mo>
<mi>w</mi>
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Wherein, td_cost is the cost of time delay；Pin is the pin of gauze, and num_pin is the number of pin, weight (num_
Pins) be line length weight, it is related to the num numbers of pin pins；Delay be gauze driving to it is each by driving point when
Prolong；Slack is the slackness of gauze time delay；Require_time is the maximum allowable time delay value of gauze；Max_cirt is maximum
Criticality；Exponent is index, and x_length is width of the external envelope rectangle along X-direction；Y_length is external envelope square
Width of the shape along Y direction；Tradeoff is line length and the specific gravity factor of time delay；Prev_total_bb_cost is last round of changes
The target function value of the line length in generation；Prev_total_td_cost is the target function value of the time delay of last round of iteration.
4. the simulated annealing method of FPGA detailed placements as claimed in claim 3, which is characterized in that the computing unit mould
The method of the receptance of block movement comprises the steps of：
Step S2.1, multiple unit modules are chosen to be moved or exchanged；
Step S2.2, knots modification of the movement to target function value of each unit module is calculated；
The target function value before target function value-movement after knots modification=movement of target function value；
Step S2.3, the numerical value of the knots modification of target function value is judged, if the numerical value of knots modification is negative value, it is this time right to receive
The movement of unit module if the numerical value of knots modification is positive value, determines whether the numerical values recited of knots modification, if knots modification
Numerical value be less than it is mobile after target function value 1%, then receive this time movement to unit module, if the numerical value of knots modification
More than or equal to 1% of the target function value after movement, then the refusal this time movement to unit module, shifting is restored to by unit module
Position before dynamic；Received movement is successfully to move, and unaccredited movement is invalid movement；
Step S2.4, the total knots modification of the number and object function of successfully movement is counted；
The total knots modification of the object function is equal to the movement of all unit modules to the sum of knots modification of target function value.
5. the simulated annealing method of the FPGA detailed placements as described in claim 2 or 4, which is characterized in that the movement or
The unit module of exchange includes random movement sequence and specific mobile sequence, and the random movement sequence is the shifting randomly generated
Dynamic sequence, the movement of the specific mobile sequence can reduce target function value.
6. the simulated annealing method of the FPGA detailed placements as described in claim 2 or 4, which is characterized in that the unit mould
The movement or exchange of block are required for ensureing the legitimacy being laid out.
7. the simulated annealing method of FPGA detailed placements as claimed in claim 4, which is characterized in that described to single goal
The method that the iteratively adjusting of ratio is fixed in temperature value includes：
T (iter)=T (prev_iter) × Scale (success_move_rate)
0.5 ＜ Scale (success_move_rate) ＜ 1
Wherein, T is single goal temperature；Iter is current iteration number；Prev_iter is last round of iterations, if epicycle
It is first time iteration, then T (prev_iter) is the initial temperature of simulated annealing；Scale is the proportion function that temperature reduces；
Success_move_rate is the receptance of unit module movement, number/total movement time of mobile receptance=success movement
Number.
8. the simulated annealing method of FPGA detailed placements as claimed in claim 7, which is characterized in that the normalization coefficient
It is the target function value of last round of iteration.
9. the simulated annealing method of FPGA detailed placements as claimed in claim 8, which is characterized in that described to passing through iteration
The method that single goal temperature value after adjusting is modified iterative calculation includes：
Wherein,It is temperature proportional coefficient, current_total_cost is last round of iteration
General objective functional value, previous_total_cost is the general objective functional value of epicycle iteration.
10. the simulated annealing method of FPGA detailed placements as claimed in claim 9, which is characterized in that when iteration meets arbitrarily
One end condition then stops being laid out；
The end condition includes：The iterations knots modification total more than object function after given threshold or iteration is less than
Either temperature value is less than 1e-5 to the 2% of target function value or the number of success movement is less than mobile total degree before iteration
5%.
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