CN113919266A

CN113919266A - Clock planning method and device for programmable device, electronic equipment and storage medium

Info

Publication number: CN113919266A
Application number: CN202111117624.8A
Authority: CN
Inventors: 刘世仁; 谭宇泉; 夏炜
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Priority date: 2021-09-23
Filing date: 2021-09-23
Publication date: 2022-01-11
Anticipated expiration: 2041-09-23
Also published as: CN113919266B

Abstract

The invention discloses a clock planning method and device of a programmable device, electronic equipment and a storage medium, and belongs to the field of integrated circuits. It includes the steps of; collecting hardware information; determining the connection relation among the clock circuit units; clustering each clock circuit unit; setting the planning sequence of each clock circuit; planning each clock circuit according to the formulated planning sequence; adjusting and optimizing the planning result of the whole clock circuit; and (6) ending. The invention simplifies the clock planning process, improves the clock planning speed, has simpler calculation method, less calculation amount and high flexibility, can reasonably place clock resources, reduces the realization difficulty of clock planning, reduces the running time and can adapt to more application scenes.

Description

Clock planning method and device for programmable device, electronic equipment and storage medium

Technical Field

The invention belongs to the technical field of integrated circuits, relates to the field programmable logic device (programmable logic device for short) integrated circuit software tool design technology, and particularly relates to a clock planning method and device of a programmable device, electronic equipment and a storage medium.

Background

At present, the clock circuit unit of a programmable device (namely, a programmable logic device) exceeds a hundred million gate level, the working frequency of the clock circuit exceeds 1GHz, and the clock circuit provides a high-frequency clock signal for other ultra-high speed processing circuits in the programmable device. In the workflow of logic synthesis, mapping, layout, wiring and bit stream generation of an EDA software tool of a programmable device, the clock planning function in the layout stage is mainly used for reasonably distributing clock resources of the programmable device and improving the working speed of a circuit system of the programmable device.

Because of the limitations of area, power consumption, cost, etc. of programmable devices (such as chips), clock resources of programmable devices are much less than other resources. In practical user design, a large amount of logic resources need clock signals, and the maximum frequency of the clock is limited when limited clock resources are not well distributed, so that the working speed of the whole programmable device circuit system is reduced.

Disclosure of Invention

The embodiment of the invention provides a clock planning method and device for a programmable device, electronic equipment and a storage medium, and aims to solve the problem that the existing clock planning method cannot simultaneously meet the requirements of small calculated amount and high flexibility.

The technical scheme of the invention is as follows: a method of clock planning for a programmable device is provided, the method comprising the steps of:

dividing a programmable device into a plurality of clock areas, and acquiring hardware information of each clock area;

acquiring clock information of a clock circuit to be planned, dividing the clock circuit into a plurality of clock circuit units according to the clock information, and determining the connection relation among the clock circuit units;

clustering the clock circuit units according to the connection relation among the clock circuit units to obtain a plurality of clock clustering circuits, wherein each clock clustering circuit comprises at least one clock circuit unit;

acquiring the sub-planning sequence of different clock circuit units in each clock clustering circuit and the planning sequence among different clock clustering circuits;

performing sub-layout planning on different clock circuit units in each clock clustering circuit according to the sub-planning sequence to obtain sub-planning results, and performing layout planning on different types of clock clustering circuits according to the planning sequence to obtain planning results;

and obtaining the layout density of the clock resources in each clock region according to the sub-planning result and the planning result, and adjusting and optimizing the planning result of the clock circuit according to the layout density of the clock regions.

Preferably, the obtaining of the sub-planning sequence of different clock circuit units in each clock clustering circuit and the planning sequence between different classes of clock clustering circuits includes:

determining the priority of each clock circuit unit according to the type and the structural complexity of the limiting conditions of the clock circuit units;

acquiring the sub-programming sequence of different clock circuit units in each clock clustering circuit according to the priority;

and obtaining the planning sequence of each clock clustering circuit according to the connection relation among the clock clustering circuits of different classes.

Preferably, the performing sub-layout planning on different clock circuit units in each clock clustering circuit according to the sub-planning sequence to obtain a sub-planning result includes:

acquiring currently available clock resources in the clock area according to the hardware information and the user design information;

dividing a clock clustering circuit into a plurality of small clock circuits from the center to the periphery according to a connection relation and a sub-planning sequence by taking a clock circuit unit with the highest priority as a center, wherein each small clock circuit comprises at least one clock circuit unit;

generating a candidate placing scheme of the clock clustering circuit according to the type and the number of clock resources required by each small block clock circuit and the type and the number of currently available clock resources in each clock region, wherein the candidate placing scheme comprises the clock regions placed by each small block clock circuit and the placing positions of clock circuit units in each small block clock circuit in the corresponding clock regions;

acquiring the time sequence delay size of each candidate placement scheme according to one or more of the placement position distance of each small clock circuit, the unit density of each small clock circuit in a placement area and the central position of each clock clustering circuit, and sequencing the candidate placement schemes in the sequence from small time sequence delay size to large time sequence delay size;

performing compatibility check on the candidate placing schemes in sequence according to the sequence, judging whether the candidate placing schemes are legal or not, deleting the candidate placing schemes with illegal compatibility check from the sequence, and selecting the candidate placing scheme with the first-order sequence as the best candidate placing scheme;

and performing sub-layout planning on different clock circuit units in each clock clustering circuit according to the optimal candidate placement scheme.

Preferably, when planning each circuit element in the clock circuit unit, the placement position of the clock signal source and/or the clock core element is determined first, and then the placement position of the planned load is determined.

Preferably, when the clock clustering circuit is divided into a plurality of small clock circuits, the clock resources required by the small clock circuits are smaller than the currently available clock resources in each clock region.

Preferably, the adjusting and optimizing the planning result of the clock circuit according to the layout density of the clock region includes:

drawing a layout density distribution diagram according to the layout density of the clock resources in the clock area;

acquiring the number of the residual clock resources in each clock area;

and adjusting the clock circuit unit from a clock area with high layout density to a clock area with low layout density according to the layout density distribution diagram and the number of the residual clock resources to obtain a layout result of the clock circuit on the programmable device.

Preferably, the adjusting the clock circuit unit from the clock area with high layout density to the clock area with low layout density according to the layout density distribution map and the number of the remaining clock resources to obtain the layout result of the clock circuit on the programmable device includes:

acquiring a clock area with the layout density larger than a first threshold value, and taking a small clock circuit in the clock area as a small clock circuit to be adjusted;

respectively determining an adjustable clock circuit unit and a non-adjustable clock circuit unit in the clock clustering circuit and/or the small clock circuit to be adjusted according to the limiting conditions of the clock circuit units;

acquiring a clock area adjacent to the position of the adjustable clock circuit unit;

if the layout density of the clock area is smaller than a second threshold value and the number of the remaining clock resources of the clock area is larger than the clock resources required by the adjustable clock circuit unit, moving the adjustable clock circuit unit to the adjacent clock area;

and repeating the steps until each small clock circuit to be adjusted is adjusted and optimized to obtain a layout result of the clock circuit on the programmable device.

The other technical scheme of the invention is as follows: a clock planning apparatus for a programmable device is provided, including:

the hardware information acquisition module is used for dividing the programmable device into a plurality of clock areas and acquiring hardware information of each clock area;

the clock circuit dividing module is used for acquiring clock information of a clock circuit to be planned, dividing the clock circuit into a plurality of clock circuit units according to the clock information and determining the connection relation among the clock circuit units;

the clock circuit clustering module is used for clustering the clock circuit units according to the connection relation among the clock circuit units to obtain a plurality of clock clustering circuits, and each clock clustering circuit comprises at least one clock circuit unit;

the planning sequence acquisition module is used for acquiring the sub-planning sequences of different clock circuit units in each clock clustering circuit and the planning sequences among different types of clock clustering circuits;

the clock planning module is used for carrying out layout planning on the clock clustering circuit and the clock circuit units on a plurality of clock regions according to the planning sequence and the sub-planning sequence to obtain a planning result;

and the adjusting and optimizing module is used for acquiring the layout density of the clock resources in each clock region according to the planning result and adjusting and optimizing the planning result of the clock circuit according to the layout density of the clock regions.

The other technical scheme of the invention is as follows: an electronic device is provided that includes a processor, and a memory coupled to the processor, the memory storing program instructions executable by the processor; the processor, when executing the program instructions stored by the memory, implements a method of clock planning for a programmable device as claimed in any one of claims 1 to 7.

The other technical scheme of the invention is as follows: there is provided a storage medium having stored therein program instructions which, when executed by a processor, implement a clock planning method capable of implementing a programmable device as claimed in any one of claims 1 to 7.

The invention has the beneficial effects that:

1. the invention can carry out clock planning layout aiming at the super-large scale programmable device, simplifies the clock planning process, improves the clock planning speed, has simpler calculation method, small calculation amount and high flexibility, can reasonably distribute and utilize clock resources, reduces the realization difficulty of clock planning, reduces the operation time of EDA (electronic design automation), can adapt to more application scenes and improves the time sequence of circuits in the programmable device.

2. According to the invention, the clock circuits are clustered, and are distributed according to the sizes of the clusters (the clock clustering circuits and the clock clustering circuits), and the clock clustering circuits in each clock clustering circuit are tightly connected, so that the reasonable placement of each module can be ensured, the problems of scattered placement of the clock clustering circuits and crossing among the clock clustering circuits are reduced, the wiring difficulty is reduced, and the time sequence delay is reduced. During actual work, the connection wires among the elements are long due to the fact that the clock clustering circuits are placed in a dispersed mode and crossed, and the problem of poor time sequence can occur.

3. According to the invention, the clock clustering circuits (namely intra-class circuits) belonging to the same class are segmented into the small clock circuits with the sizes smaller than the clock region specification, and the small clock circuits are arranged according to the sizes of the small clock circuits, so that the layout is more flexible, the clock planning is more universal, and the clock clustering circuit is suitable for more application scenes. Meanwhile, the invention also combines the design and the hardware in an optimal mode as much as possible, gives full play to the characteristics of the hardware and improves the overall performance of the circuit.

4. According to the invention, through carrying out global sequencing on each clock clustering circuit, planning is carried out according to the mode from complex class to simple class, the success probability of planning is improved, and the times of changing the design by a user are reduced. Meanwhile, when the clock clustering circuits are arranged (planned), the distance of the placing positions of the small clock circuits, the unit density of the small clock circuits in the placing area and the central position of the small clock circuits are fully considered, each small clock circuit is locally optimized, and finally, global optimization is carried out on all the clock clustering circuits.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic main flow chart of a clock programming method of a programmable device according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating a clock circuit in a clock planning method for a programmable device according to a first embodiment of the present invention;

fig. 3 is a schematic structural diagram of a clock planning method for a programmable device according to a first embodiment of the present invention before planning optimization;

FIG. 4 is a diagram illustrating the remaining clock resources of each clock region according to the first embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a layout density distribution of clock regions according to a first embodiment of the present invention;

fig. 6 is a schematic diagram of a layout result of a clock planning method for a programmable device according to a first embodiment of the present invention after planning optimization;

fig. 7 is a schematic flow chart of the first embodiment of the present invention when the clock circuit units are planned according to the planned sequence.

Fig. 8 is a schematic structural diagram of a clock planning apparatus of a programmable device according to a second embodiment of the present invention;

fig. 9 is a schematic structural diagram of an electronic device according to a third embodiment of the invention;

fig. 10 is a schematic structural diagram of a storage medium according to a fourth embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, a first embodiment of the present invention is a clock planning method for a programmable device, including the steps of starting, collecting chip hardware information, determining a connection relationship between clock circuit units, clustering the clock circuit units, setting a planning sequence of the clock circuits, planning the clock circuits according to the planned planning sequence, adjusting and optimizing a planning result of the entire clock circuit, and ending, the specific steps of the scheme are as follows:

s1, collecting hardware information (such as chip hardware information):

the method comprises the steps of dividing a programmable device chip into a plurality of clock areas, and acquiring hardware information of each clock area.

In actual operation, the programmable logic device described in the present application may be an FPGA (programmable logic array) or a CPLD (complex programmable logic device), and the present application mainly uses an FPGA chip as an example for explanation, and people may also use the method described in the present application to perform clock planning on the CPLD.

In actual operation, the hardware information includes clock resource information, logic resource information, input/output module information, and various clock routing information. When hardware information is obtained (collected), the clock resources can be split as uniformly as possible according to the distribution condition of the clock resources, and two-dimensional coordinates are established to mark the positions of the clock regions.

In actual work, the method mainly aims at performing clock circuit layout planning on the ultra-large-scale FPGA chip, the clock area (also called clock Region or Region) of the ultra-large-scale FPGA chip is very large, various resources of the actual FPGA chip are not necessarily uniformly distributed, and the actual FPGA chip cannot be uniformly divided into the clock areas with the same area according to the size of the chip. Therefore, when hardware information is acquired (collected), the clock resources can be uniformly divided according to the specific distribution condition of the clock resources, the FPGA chip is uniformly divided into the clock regions according to the distribution condition of the divided clock resources, and the difficulty of clock skew correction of each clock region in the follow-up process can be reduced.

During actual work, a clock area on an FPGA chip is divided into smaller clock areas, hardware information is counted and collected according to the clock areas, the distribution situation of chip resources (such as clock resource information, logic resource information, input/output module information, various clock wiring information and the like) can be counted, the counting is simple, the resource use situation of each clock area can be counted conveniently during subsequent clock layout according to the clock areas, and at the moment, a plurality of clock circuit units are arranged in each clock area.

S2, determining the connection relation among the clock circuit units:

the method comprises the steps of obtaining clock information of a clock circuit to be planned, dividing the clock circuit into a plurality of clock circuit units according to the clock information, and determining the connection relation among the clock circuit units.

In actual work, the clock information of the method can be obtained from user design data, and the clock circuit information comprises a circuit netlist, clock types, clock quantity, a clock source, load, special requirements of a user on clock layout in design and the like.

When the connection relation among the clock circuit units is determined, the connection relation among the clock circuit units is further determined mainly by analyzing the circuit netlist so as to facilitate subsequent clock clustering.

In actual operation, the connection relationship between the clock circuit units mainly includes direct connection, indirect connection and no connection, and specifically includes the following steps:

1. direct connection: the direct load and the direct load of the two clocks are directly connected, or the common load of the two clocks is connected.

2. Indirect connection: and a multi-stage clock circuit unit is connected between the direct load and the direct load of the two paths of clocks.

3. No connection: the loads of the two clocks have no connection relation with the load.

S3, clustering the clock circuit units:

and clustering the clock circuit units according to the connection relation among the clock circuit units to obtain a plurality of clock clustering circuits, wherein each clock clustering circuit comprises at least one clock circuit unit.

Furthermore, when the clock circuits are clustered, the connection relation among the clock clustering circuit units can be recorded, so that the clock circuits which are closely related to each other are planned as a whole during layout, and the whole time sequence delay is reduced.

In this step, the present application divides the clock circuit into three levels from top to bottom, specifically as follows: firstly, different types of clock circuits are used as clock clustering circuits, each clock clustering circuit internally comprises a plurality of small clock circuits, and each small clock circuit internally comprises a plurality of clock circuit units. Meanwhile, the small clock circuit and the clock circuit unit are both located inside the clock clustering circuit, so that the small clock circuit and the clock circuit unit can be called as an intra-class clock circuit (also called as clock circuit inside the clock clustering circuit for short).

In actual work, the clock clustering circuit, the small clock circuit and the clock circuit unit can be collectively called as the clock circuit, people can divide the clock circuit into different grades according to self needs, for example, the clock circuit can be divided into three grades like the clock circuit, and the clock circuit can also be divided into four grades.

During actual work, when the clock circuits are clustered, the clustering method and the clustering device can perform clustering according to the connection series and the distance of the circuit unit nodes among the clock circuits in the circuit netlist, and the nodes among the clock circuits are clustered into a class with large connection quantity and short distance.

In actual work, when the clock circuits are clustered, the clock circuits can be classified according to the connection tightness of the two clock circuits in the circuit netlist, wherein the connection tightness of the two clock circuits is described through the direct connection number and the indirect distance of the load.

In actual operation, the number of direct connections refers to the number of clock circuit units directly connected between two clock loads, and the indirect distance refers to the logic level of the clock circuit units between the two clock loads in indirect connection. In actual operation, the connection tightness strength of the two clock circuits is described by the number of the connections, the size of the average value of the indirect distance and the size of the variance of the indirect distance, and the connection tightness of the two clock circuits is indicated by the fact that the number of the connections is large, the average value of the indirect distance is small and the variance of the indirect distance is small.

In actual operation, further, the invention can also set the threshold values of the direct connection quantity and the indirect distance of the load, so that people can better classify the clock clustering circuits.

S4, determining the planning sequence of the clock circuit:

and acquiring the sub-planning sequence of different clock circuit units in each clock clustering circuit and the planning sequence among different clock clustering circuits.

During actual work, when the planning sequence of the clock circuits is determined, the specific placement positions of the clock circuits in each class on the plurality of clock regions are sequentially analyzed, then the planning sequence of the clock circuits in each class is determined, then the connection relation between the clock circuits in different classes is analyzed, and finally the planning sequence of each clock clustering circuit is determined, specifically:

and S41, determining the priority of each clock circuit unit according to the type and the structural complexity of the limiting condition of the clock circuit unit.

In actual operation, the clock circuits with more restrictions and more complex structures have higher priority, because the circuits with more restrictions have fewer optional placement positions, and are ensured not to be occupied by other clock circuits through priority planning, so the priority planning with more layout restrictions is performed.

The method mainly comprises the steps that the limiting conditions set in user design, the types of clock resources needed to be used by the clock circuits and the number of the clock resources needed to be used by the clock circuits are mainly included, the user can set various types of limiting conditions in the actual working process, the priorities of different types of limiting conditions are different, and high priority is guaranteed during planning.

In actual operation, the structure of the clock circuit can be measured according to the load number of the circuit, and the type and the number of clock resources required by the clock circuit can be measured, so that the planning sequence of the clock circuit is considered, and the clock circuit requiring more resources is preferentially planned.

S42, acquiring the sub-planning sequence of different clock circuit units in each clock clustering circuit according to the priority;

in actual operation, the sub-plan sequence is arranged from high to low according to the priority level, and when the priority level needs to be determined, the sub-plan sequence can be distinguished according to the method described in the above S41.

And S43, obtaining the planning sequence of each clock clustering circuit according to the connection relation among the clock clustering circuits of different classes.

In actual operation, when determining the planning sequence of the clock circuit, firstly ensuring the success of the clock layout, secondly ensuring the performance of the clock circuit to meet the layout planning requirement, and preferably planning the clock circuit with multiple limiting conditions and complex structure.

S5, planning each clock circuit (including a clock clustering circuit and an intra-class clock circuit) according to the formulated planning sequence:

and performing sub-layout planning on different clock circuit units in each clock clustering circuit according to the sub-layout sequence to obtain a sub-layout result, and performing layout planning on different types of clock clustering circuits according to the layout sequence to obtain a planning result.

When planning each circuit element in the clock circuit unit, firstly determining the placing position of a clock signal source and/or a clock core element, then determining the placing position of a planning load, and planning each clock circuit (including a clock clustering circuit and an in-class clock circuit) according to a sequence of high priority to low priority, specifically, the sub-layout planning comprises the following steps:

and S51, acquiring and counting the currently available clock resources in the clock area according to the hardware information and the user design information.

In this step, according to the hardware information and the user design information, the available clock resources of the current clock clustering circuit are collected (for example, the resources in the chip are checked to be occupied by other unplanned clocks), and the available resources of the current clock clustering circuit are counted, so that the success rate of clock planning is improved, iteration is reduced, and the speed is increased. Preferably, before collecting hardware information, the method can also perform a pre-clock layout so as to further improve the success rate of clock planning.

S52, segmenting the clock clustering circuit into a plurality of small clock circuits:

and taking the clock circuit unit with the highest priority as a center, and dividing the clock clustering circuit into a plurality of small clock circuits from the center to the periphery according to the connection relation and the sub-programming sequence, wherein each small clock circuit comprises at least one clock circuit unit.

The method mainly includes the steps of segmenting clock clustering circuits belonging to the same class so as to determine a sub-planning sequence of each clock circuit unit in each clock clustering circuit, and particularly, segmenting the clock clustering circuits into a plurality of small-block clock circuits from the center to the periphery according to a connection relation by taking the clock clustering circuit with the highest priority as a center, distributing each small-block clock circuit into a proper clock area, and planning the clock clustering circuits of different classes after the layout planning of the small-block clock circuits in the clock area is completed (how to plan the clock clustering circuits of different classes does not belong to the content of step S52, which is described and explained here for more clearly explaining the technical scheme of the method).

In actual work, when the clock clustering circuit is divided into a plurality of small clock circuits so as to arrange the small clock circuits into the clock regions, clock resources required by the small clock circuits during arrangement are smaller than those of a single clock region.

In actual work, a chip architecture is designed aiming at a plurality of application scenes, the architecture of the chip is possibly not optimal for the current clock-like design scene, but a clock circuit is divided into a plurality of small circuits (small clock circuits) to be distributed, so that the distribution flexibility is improved, the design and hardware can be combined in an optimal mode as far as possible, and the distribution position is more reasonable to select.

In actual work, the clock circuit can be segmented averagely according to the number of resources when being segmented, the circuit netlists of the same class can be segmented from the center to the outside according to the shape of a grid, and meanwhile, the number of the resources of each circuit is ensured to be equal as much as possible when in segmentation.

S53, generating a candidate placement scheme of the clock clustering circuit:

and generating a candidate placing scheme of the clock clustering circuit according to the type and the number of the clock resources required by each small block clock circuit and the type and the number of the currently available clock resources in each clock region, wherein the candidate placing scheme comprises the clock regions placed by each small block clock circuit and the placing positions of the clock circuit units in each small block clock circuit in the corresponding clock regions.

In actual operation, since there are often a plurality of small clock circuits and clock regions, there are often a plurality of candidate placement schemes in this step. Preferably, the method further performs a preliminary check on the candidate placement scheme, and checks whether the selected clock region meets the design requirements in terms of resources and quantity, so as to further improve the working efficiency of the method.

S54, sorting the candidate placement schemes of the small block clock circuit according to the time sequence delay:

and acquiring the time sequence delay size of each candidate placement scheme according to one or more of the placement position distance of each small clock circuit, the unit density of each small clock circuit in the placement area and the central position of each clock clustering circuit, and sequencing the candidate placement schemes in the sequence from small to large according to the time sequence delay size.

In actual operation, the center position of each clock clustering circuit is described by the placement position of the clock circuit (or small clock circuit) in the class with the highest priority. The placement distance of each small clock circuit is described by the euclidean distance between the centers of the regions and the inter-region clock signal wiring distance. The unit density of each small clock circuit in the placement area is described by the average density of the use of various resources in the area range and the average density of the use of signal routing, and during actual work, the density of the method is equal to the resource use area in the area range divided by the total area of the resources in the area range.

In actual work, in order to reduce the problem of clock asynchronism, the distances from a clock root node to each block region should be kept as consistent as possible; furthermore, under a certain unit density, the distance between the two clock clustering circuits should be as small as possible, and the selected positions of the clock clustering circuits can minimize the delay difference from the center of each block to the center of the clock, so that the layout of the application is more reasonable.

In actual operation, the long placement distance causes large transmission delay, the higher the density of the clock circuit units, the longer the wiring wire, and thus the large transmission delay, and the inconsistent and large difference between the clock center and each candidate position causes large transmission delay.

S55, selecting the candidate placement scheme with the first ranking as the best candidate placement scheme:

and sequentially carrying out compatibility check on the candidate placing schemes according to the sequence, judging whether the candidate placing schemes are legal or not, deleting the candidate placing schemes with the illegal compatibility check from the sequence, and selecting the candidate placing scheme with the first-order sequence as the best candidate placing scheme.

In actual work, compatibility check mainly checks whether the placement positions of the clock clustering circuits meet user constraint conditions, whether clock resources and logic resources meet design requirements, and whether the clock signals are transmitted from a clock source to a load placement area and have the problem of wire distribution and other conflicts.

In practice, the main purpose of steps S53-S55 is to determine which clock region divided in step S1 the tile clock circuit should be placed in according to the clock resource required by the tile clock circuit and the currently available clock resource in the clock region, wherein step S53 is to generate a series of candidate placement schemes (i.e. candidate schemes capable of placing the tile clock circuit on the clock region) according to the existing conditions (e.g. the clock resource required by the tile clock circuit and the currently available clock resource in the clock region), at this time, since the number of the series of candidate placement schemes is large, and there are some possible problems of illegal, excessive resource waste, incompatibility of the candidate placement schemes, the present application also needs to sort the series of candidate placement schemes (by the size of timing delay) through step S54 to facilitate the later planning layout, after the sorting is completed, the electronic device may select the candidate placement scheme with the first order as the best candidate placement scheme according to the compatibility, validity, and other conditions of the schemes, where the best candidate placement scheme is the scheme for placing the tile clock circuit in the clock region divided by step S1.

And S56, performing sub-layout planning on different clock circuit units in each clock clustering circuit according to the optimal candidate placement scheme.

S6, adjusting and optimizing the planning result of the clock circuit:

In actual operation, the step of adjusting and optimizing the planning result of the clock circuit comprises:

s61, drawing a layout density distribution diagram according to the layout density of the clock resources in the clock area;

in actual work, in order to more conveniently perform clock optimization layout, the global layout density distribution map of various resources in a clock region is established according to the layout density of the clock region, the planning result of a clock circuit is adjusted and optimized through the global layout density distribution map, and specifically, the global layout density distribution map is established in the following way:

counting the use condition of resources in each clock region, and dividing the total area of each resource by the area of each resource which is used to obtain the placement density of each resource in the clock region; and marking the layout density of the chip clock according to a coordinate system of the chip clock established by the two-dimensional coordinates to obtain a two-dimensional global layout distribution diagram.

And the global layout density distribution diagram is used for adjusting the position distance between circuits and the placement density of the clock circuit units, and if the placement density of various resources in the clock region is overlarge, the clock planning result is adjusted under the condition that various resources in the clock region are sufficient. And adjusting on the basis of the original clock planning result, and finely adjusting the resources in the clock area with overlarge density to the position with small density at the original position.

S62, acquiring the number of the residual clock resources in each clock area;

and S63, adjusting the clock circuit unit from the clock area with high layout density to the clock area with low layout density according to the layout density distribution diagram and the residual clock resource quantity to obtain the layout result of the clock circuit on the FPGA chip.

In actual operation, the method for adjusting the clock circuit unit from the clock area with high layout density to the clock area with low layout density comprises the following steps:

s631, acquiring a clock area with the layout density larger than a first threshold value, and taking the small clock circuit in the clock area (with the layout density larger than the first threshold value) as a small clock circuit to be adjusted;

in actual work, the first threshold is a preset value, people can set the threshold according to actual work needs (for example, the density is set to be 0.6 as the first threshold), when the layout density of the clock resources in the clock area is smaller than the first threshold, the small clock circuit in the clock area does not need to be adjusted, and when the layout density of the clock resources in the clock area is larger than the first threshold, the small clock circuit in the clock area needs to be adjusted.

S632, respectively determining an adjustable clock circuit unit and a non-adjustable clock circuit unit in the clock clustering circuit and/or the small clock circuit to be adjusted according to the limiting conditions of the clock circuit unit;

in actual operation, the limiting conditions in this step are the same as those in step S41, and reference may be made to step S41. The adjustable clock circuit unit refers to a clock clustering circuit and/or a clock circuit unit which can move in a small block clock circuit, the non-adjustable clock circuit unit refers to a clock circuit unit which cannot move in the clock clustering circuit and/or the small block clock circuit, and whether the clock circuit unit can move or not can be determined according to the limiting condition.

S633, acquiring a clock area adjacent to the position of the adjustable clock circuit unit;

in this step, the purpose of obtaining the clock area is mainly to check that the adjustable clock circuit unit can be adjusted (moved) to that position, so as to perform layout optimization at a later stage.

S634, if the layout density of the clock region is less than a second threshold and the remaining number of clock resources of the clock region is greater than the clock resources required by the adjustable clock circuit unit, moving the adjustable clock circuit unit to the adjacent clock region;

in actual work, the second threshold is also a preset value, people can set the second threshold according to actual work needs (for example, the density is set to be 0.4), when the layout density of the clock resources in the clock area is greater than the second threshold, the small clock circuit in the clock area does not need to be adjusted, and as long as the layout density of the clock resources in the clock area is less than the second threshold, the small clock circuit in the clock area needs to be adjusted.

And S635, repeating the steps until each small clock circuit to be adjusted is adjusted and optimized, and obtaining a layout result of the clock circuit on a programmable device (such as an FPGA chip).

When the planning result of the clock circuit is adjusted and optimized, firstly, the using condition of clock resources and the density distribution condition of the resource use after the previous clock planning are counted, and the previous clock planning is adjusted on the premise that the clock resources are sufficiently used; when the adjustment is carried out, the adjustment is carried out from high to bottom according to the principle that the relative position is kept unchanged as much as possible, the adjustment is carried out towards the periphery on the basis of the original position, and the adjustment direction of each path of clock is determined by calculating the local density gradient.

In actual work, if the clock circuit units are placed far away, the signal wires for connecting the two clock circuit units are lengthened; if the clock circuit units are crowded together, because the wiring resources in the local area are limited, the signal wires connecting the two units can be connected only after being wound far, the length of the signal wires for wiring is long, the time sequence delay is large, and the length of the total wire is used for judging whether the adjustment is reasonable or not in the process of adjusting the circuit distance by utilizing the global layout density distribution.

In order to make the technical solution of the first embodiment of the present application easier to understand, the present application further describes the technical solution of the first embodiment with reference to the accompanying drawings, which are as follows:

it should be noted that in fig. 3 to 6, the solid line is a boundary line of a chip or a clock region, and the dotted line is a region formed after the chip or the clock circuit is cut, for example, in fig. 3 to 5, the thin solid line is a boundary line of a chip, the thin dotted line divides the chip into 24 clock regions, and the thick solid line is a region occupied by each clock clustering circuit.

Meanwhile, in order to make each figure clearer, fig. 2 only lists the case that the clock circuit is divided into 3 clock clustering circuits, but in actual operation, the number of the clock clustering circuits can be adjusted according to needs, for example, the clock circuits in fig. 3 and fig. 6 are all divided into a plurality of clock clustering circuits.

In practice, fig. 2 and "fig. 3 to 6" can be understood as the result obtained by dividing two different clock circuits, fig. 2 is for explaining how the present application performs clustering, fig. 3 to 6 are for explaining how the present application performs optimal adjustment on the planned clock circuits, and fig. 2 and "fig. 3 to 6" have no necessary connection.

As shown in fig. 1, the present application aims to layout and plan an ultra-large scale clock circuit on an FPGA chip, and to reduce the amount of computation and increase the layout flexibility as much as possible during layout, and for this purpose, the present application adopts the flow steps shown in fig. 1.

As shown in fig. 2, reference numeral 1 in fig. 2 denotes a clock clustering circuit 1 (which may also be simply referred to as a class clock 1, the same applies hereinafter), reference numeral 2 in fig. 2 mainly denotes a clock clustering circuit 2, and reference numeral 3 mainly denotes a clock clustering circuit 3. In fig. 2, the clock clustering circuit 1 includes two small block clock circuits (which may also be referred to as two-way clock circuits, that is, circuits to which the BUF1 and the BUF2 are respectively connected), and each of the clock clustering circuit 2 and the clock clustering circuit 3 has only one small block clock circuit (which may also be referred to as only one-way clock circuit, that is, circuits to which the BUF3 and the BUF4 are respectively connected).

As can be seen from fig. 2, in actual operation, the clock circuits respectively connected to BUFs 1 to BUF4 may be referred to as small-block clock circuits, and since the circuit connected to BUF1 and the circuit connected to BUF2 are obtained by splitting clock clustering circuit 1, the circuit connected to BUF1 and the circuit connected to BUF2 cannot be individually referred to as clock clustering circuits, and only the clock circuit formed by combining the circuit connected to BUF1 and the circuit connected to BUF2 can be referred to as a clock clustering circuit. However, since neither the circuit to which BUF3 is connected nor the circuit to which BUF4 is connected has a circuit to which they are connected more closely, both the circuit to which BUF3 is connected and the circuit to which BUF4 is connected can be clock clustering circuits.

As shown in fig. 3 and 6, a plurality of small block clock circuits and clock clustering circuits may be arranged on the FPGA chip, and clocks 1 to 10 in fig. 3 and 6 respectively represent 10 small block clock circuits. In actual operation, whether each small clock circuit on the FPGA chip can be used as a clock clustering circuit or not needs to be divided according to actual conditions, for example, clock 1 can be used alone as a small clock circuit or a clock clustering circuit, clocks 2 to 4 can be used alone as a small clock circuit respectively, but they cannot be used alone as a clock clustering circuit respectively, clocks 2 to 4 can be used alone as a clock clustering circuit together, and clocks 5 to 10 can also be divided according to actual conditions whether they are used alone as a clock clustering circuit or not.

In actual operation, the optimized adjustment modes of the small block clock circuit and the clock clustering circuit are basically the same, and the adjustment mode of the present application is described with reference to fig. 3 to 6:

as can be seen from fig. 3 to fig. 5, the areas where the center and the lower right corner of the PFGA chip are located have less remaining clock resources and high layout density, and need to be adjusted, and the areas where the lower left corner and the upper right corner of the PFGA chip are located have less remaining clock resources and lower layout density, and can receive a part of the clock resources, that is, the clock resources in the clock areas where the center and the lower right corner of the PFGA chip are located can be partially moved to the areas where the lower left corner and the upper right corner of the PFGA chip are located.

Specifically, the positions of the

clock clustering circuits

4, 6, 8, 9, and 10 in fig. 3 need to be adjusted through analysis. It is assumed that some clock circuit units in the

clock clustering circuits

4, 6, 9, and 10 in fig. 3 cannot leave the original positions, but the clock circuit units in the clock clustering circuit 8 can be adjusted greatly, and the clock clustering circuit 10 occupies less resources. Then the adjustment is such that the position of the clock clustering circuit 10 is not adjusted. The clock clustering circuit 8 performs position shift upward as a whole. The clock clustering circuit 4 enlarges the size of the placement area to the left. The clock clustering circuits 6 and 9 enlarge the placement area size to the left and upward.

As shown in fig. 3 to fig. 6, in the present application, during the adjustment optimization, the amount of clock resources (i.e., layout density) is adjusted according to the original clock layout, that is, the clock circuits with more clock resources and higher density in the clock region are moved to a region with less clock resources and lower density, at this time, some clock circuit units in the moved clock circuits are movable (i.e., adjustable clock circuit units), and some clock circuit units are unmovable (i.e., unmodulatable clock circuit units).

The area of the movable clock circuit (namely, the adjustable clock circuit unit) left after moving can be occupied by the clock unit circuits in other clock clustering circuits (adjacent clock clustering circuits in different classes) so as to facilitate the corresponding adjustment of the other clock clustering circuits in different classes, and thus, the whole chip realizes layout optimization.

For example, as shown in fig. 3 and fig. 6, the clock resource distribution of the area where the clock 1 is located on the PFGA chip is more uniform and reasonable, that is, the remaining clock resource of the area where the clock 1 is located is more moderate and the layout density is more moderate, so that the clock 1 on the PFGA chip does not need to be adjusted, but the clock resource distribution of the area on the PFGA chip other than the clock 1 is not uniform and reasonable, the remaining clock resources of the areas where the clocks 2, 3, 7 and 8 are located are more and the layout density is smaller, and the remaining clock resources of the areas where the clocks 5, 6, 9 and 10 are located are less and the layout density is larger, so that the area on the PFGA chip other than the clock 1 needs to be adjusted, which is exemplified by the clock 4 and the clock 9 below: the clock 4 can move a part of the movable clock circuit units to the clock 2 and the clock 3, the spare part of the resources of the clock 4 after moving is occupied by the clock 9, and the spare part of the resources of the clock 9 after moving can allow the clock 10 to adjust according to the needs of the clock (for example, the spare clock resources of the clock 9 are occupied).

Fig. 8 is a schematic structural diagram of a clock planning apparatus of a programmable device according to the present invention, including: the hardware information acquisition module is used for dividing the programmable device into a plurality of clock areas and acquiring hardware information of each clock area; the clock circuit dividing module is used for acquiring clock information of a clock circuit to be planned, dividing the clock circuit into a plurality of clock circuit units according to the clock information and determining the connection relation among the clock circuit units; the clock circuit clustering module is used for clustering the clock circuit units according to the connection relation among the clock circuit units to obtain a plurality of clock clustering circuits, and each clock clustering circuit comprises at least one clock circuit unit; the planning sequence acquisition module is used for acquiring the sub-planning sequences of different clock circuit units in each clock clustering circuit and the planning sequences among different types of clock clustering circuits; the clock planning module is used for carrying out layout planning on the clock clustering circuit and the clock circuit units on a plurality of clock regions according to the planning sequence and the sub-planning sequence to obtain a planning result; and the adjusting and optimizing module is used for acquiring the layout density of the clock resources in each clock region according to the planning result and adjusting and optimizing the planning result of the clock circuit according to the layout density of the clock regions.

Fig. 9 is a schematic structural diagram of an electronic device according to the present invention. As shown in fig. 9, the electronic device 30 includes a processor 31 and a memory 32 coupled to the processor 31. The memory 32 stores program instructions for implementing the clock planning method of the programmable device of any of the embodiments described above. The processor 31 is operative to execute program instructions stored by the memory 32 to perform a clock planning layout on the FPGA.

The processor 31 may also be referred to as a CPU (Central Processing Unit). The processor 31 may be an integrated circuit chip having signal processing capabilities. The processor 31 may also be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a storage medium according to a fourth embodiment of the invention. The storage medium 40 of the fourth embodiment of the present invention stores program instructions 41 capable of implementing all the methods described above, where the program instructions 41 may be stored in the storage medium in the form of a software product, and include several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute all or part of the steps of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a mobile hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, or terminal devices, such as a computer, a server, a mobile phone, and a tablet.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A method for clock planning for a programmable device, said method comprising the steps of:

2. The method of claim 1, wherein the obtaining of the sub-programming order of different clock circuit units in each clock cluster circuit and the programming order between different classes of clock cluster circuits comprises:

3. The clock planning method of claim 2, wherein the performing the sub-layout planning on the different clock circuit units in each clock clustering circuit according to the sub-planning sequence to obtain the sub-planning result comprises:

4. The method according to claim 3, wherein when planning each circuit element in the clock circuit unit, the placement position of the clock signal source and/or the clock core element is determined, and then the placement position of the planned load is determined.

5. The clock planning method of claim 4, wherein when the clock clustering circuit is divided into a plurality of small clock circuits, the clock resources required by the small clock circuits are smaller than the clock resources currently available in each of the clock regions.

6. The clock planning method of any one of claims 1 to 5, wherein the adjusting and optimizing the planning result of the clock circuit according to the layout density of the clock region comprises:

acquiring the number of the residual clock resources in each clock area;

7. The method according to claim 6, wherein the adjusting the clock circuit units from the clock area with high layout density to the clock area with low layout density according to the layout density distribution map and the number of the remaining clock resources to obtain the layout result of the clock circuit on the programmable device comprises:

8. A clock planning apparatus for a programmable device, comprising:

9. An electronic device comprising a processor, and a memory coupled to the processor, the memory storing program instructions executable by the processor; the processor, when executing the program instructions stored by the memory, implements a method of clock planning for a programmable device as claimed in any one of claims 1 to 7.

10. A storage medium having stored therein program instructions which, when executed by a processor, implement a clock planning method capable of implementing a programmable device as claimed in any one of claims 1 to 7.