CN113627120A - Layout optimization method and apparatus for superconducting integrated circuit, storage medium, and terminal - Google Patents
Layout optimization method and apparatus for superconducting integrated circuit, storage medium, and terminal Download PDFInfo
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- CN113627120A CN113627120A CN202111094793.4A CN202111094793A CN113627120A CN 113627120 A CN113627120 A CN 113627120A CN 202111094793 A CN202111094793 A CN 202111094793A CN 113627120 A CN113627120 A CN 113627120A
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Abstract
The invention discloses a layout optimization method and device of a superconducting integrated circuit, a storage medium and a terminal, wherein the method comprises the following steps: performing modular processing on the netlist to be laid out to obtain segmentation modules, and performing layout optimization on all the segmentation modules to obtain an optimized circuit layout; wherein performing layout optimization on the segmentation module comprises: determining the size of a layout space required by a segmentation module; optimizing the position arrangement of all logic gate units in the segmentation module; mapping the result to a layout plan to obtain the layout of the segmentation module; placing all the bus buffer units in the partitioning module into the layout, optimizing the positions of all the units in the layout through a second global optimizer, and then optimizing the clocks of all the logic gate units containing the clocks in the layout; the invention realizes the automatic layout optimization of the large-scale superconducting integrated circuit, replaces the original manual design flow, improves the design scale of the superconducting integrated circuit and shortens the design iteration cycle.
Description
Technical Field
The invention relates to the technical field of layout of a superconducting integrated circuit, in particular to a layout optimization method and device of the superconducting integrated circuit, a storage medium and a terminal.
Background
Superconducting integrated circuits are integrated circuits based on josephson junctions and superconducting materials, including Single-Flux-Quantum (SFQ) circuits and the like.
An SFQ circuit is a relatively special superconducting integrated circuit, which is mainly composed of josephson junctions, and digital logic "0" and "1" are represented by the presence or absence of magnetic flux quanta. Compared with a traditional semiconductor CMOS (complementary Metal Oxide semiconductor) circuit, the micro and quantitative properties of the flux quanta obviously reduce the influence of crosstalk and power consumption, and narrow voltage pulses generated in the junctions when the flux quanta enter and exit the loop enable the flux quanta to obtain extremely high frequency. The circuit has the advantages of ultrahigh working speed and extremely low power consumption, so that the circuit has a remarkable prospect in the application of ultra-wide bandwidth Analog-to-Digital converters (ADC), superconducting computers and the like.
Because superconducting integrated circuits such as SFQ circuits and the like adopt gate-level flow water, special clock tree structures and the like, and have certain particularity, the support of the current commercial and open-source electronic design automation tools (EDA) is not enough to meet the requirement of large-scale automatic design, and for the superconducting integrated circuits such as SFQ circuits and the like with the level of ten thousand or more, manual layout optimization takes a huge amount of time, and the iteration cycle of a chip is seriously influenced.
Disclosure of Invention
The technical problem to be solved by the invention is that the existing electronic design automation tool can not meet the requirement of large-scale automatic design of superconducting integrated circuits such as SFQ circuits and the like, and manual layout optimization takes a huge amount of time and seriously influences the iteration cycle of a chip.
In order to solve the above technical problem, the present invention provides a layout optimization method for a superconducting integrated circuit, including:
obtaining a circuit netlist of a circuit to be laid out, and preprocessing the circuit netlist to obtain the netlist to be laid out;
performing modular processing on the netlist to be laid out to obtain at least one segmentation module, and performing layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module comprises:
determining and storing the size of layout space required by each level of logic depth group in the segmentation module;
based on the size of the layout space required by each level of logic depth group in the partitioning module, performing position arrangement optimization on all logic gate units in the partitioning module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result to a layout plan, and adding unit information of all the logic gate units to the layout plan to obtain the layout of the partitioning module;
placing all the bus buffer units in the partitioning module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the interconnection line length mean and the interconnection line length variance is minimum, and the constraint condition is the movement in the random y-axis direction; the optimization goal of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation item is minimum, and the constraint conditions are in the x-axis direction and the y-axis direction, rotation is carried out according to a first probability, and unit layout type replacement is carried out according to a second probability.
Optimizing, the preprocessing the circuit netlist to obtain a netlist to be laid out includes:
and removing all the interconnection line units except the bus buffer unit in the circuit netlist to obtain a netlist to be laid, and carrying out circuit statistics on the netlist to be laid.
Optimizing, the obtaining at least one partitioning module by performing modular processing on the netlist to be laid out includes:
segmenting the netlist to be laid out based on preset segmentation conditions to obtain at least one segmentation module;
the preset segmentation condition is that segmentation is carried out horizontally by using a minimum segmentation algorithm, and segmentation is carried out longitudinally by using the principle that the logic depth keeps consistent.
Optimizing, before performing layout optimization on all the segmentation modules, the method further includes:
performing layout optimization on all the segmentation modules through a third global optimizer;
wherein the optimization goal of the third global optimizer is: the product of the difference between the abscissa and the ordinate of the minimum coordinate and the maximum coordinate of each partitioning module is minimum, and the linear combination of the total distance of the Manhattan distances of the interconnection lines among all the partitioning modules and the variance of the Manhattan distances of all the interconnection lines is minimum; the constraint conditions of the third global optimizer are as follows: the difference between the abscissa of the minimum coordinate and the abscissa of the maximum coordinate of each segmentation module is smaller than a first threshold, the difference between the ordinate of the minimum coordinate and the ordinate of the maximum coordinate of each segmentation module is smaller than a second threshold, the sum of the lengths of any two segmentation modules is smaller than a third threshold, and the sum of the widths of any two segmentation modules is smaller than a fourth threshold.
Optimally, determining the required layout space size of each level of logic depth group in the partitioning module comprises:
the height acquisition mode of all the level logic depth groups is as follows: acquiring the number of units in all the level logic depth groups, selecting the maximum number of the units as a height reference value, and setting the heights of all the level logic depth groups according to the height reference value;
the width of each level of logic depth group is calculated as follows: the linear combination of the number of units, the number of clock ends and the number of signal lines in the current stage logic depth group.
Optimally, the step of placing all the bus buffer units in the segmentation module into the layout by a preset placing mode comprises:
extracting all the confluence buffer units in the segmentation module to form a temporary queue;
acquiring a first confluence buffer unit of the temporary queue as a unit to be placed;
judging whether the previous stage unit of the unit to be placed is placed or not, if so, placing the unit to be placed, otherwise, placing the unit to be placed back to the tail end of the temporary queue, and acquiring the first confluence buffer unit of the current temporary queue as the unit to be placed again, and judging the unit to be placed again;
wherein placing the unit to be placed comprises:
and acquiring the position midpoints of all the preceding stage units of the unit to be placed as reference midpoints, placing the unit to be placed on the basis of the reference midpoints, and recording the placing positions of the unit to be placed in a database of the confluence buffer unit.
Optimizing, the clock optimizing of all logic gate units including clocks in the layout includes:
if the logic gate containing the clock is called a clock unit;
calculating all leaf nodes based on the coordinate positions of the clock units and a preset fan-out value;
optimizing the position of the clock unit through a fourth global optimizer;
the optimization target of the fourth global optimizer is that the total length of all the clock unit interconnection lines is shortest; the constraint conditions of the fourth global optimizer are as follows: rotating the clock unit.
In order to solve the technical problem, the invention also provides a layout optimization device of the superconducting integrated circuit, which is characterized by comprising a preprocessing mechanism and an optimization mechanism;
the preprocessing mechanism is used for acquiring a circuit netlist of the circuit to be laid out and preprocessing the circuit netlist to acquire the netlist to be laid out;
the optimization mechanism is used for performing modular processing on the netlist to be distributed to obtain at least one segmentation module and performing layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module comprises:
determining and storing the size of layout space required by each level of logic depth group in the segmentation module;
based on the size of the layout space required by each level of logic depth group in the partitioning module, performing position arrangement optimization on all logic gate units in the partitioning module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result to a layout plan, and adding unit information of all the logic gate units to the layout plan to obtain the layout of the partitioning module;
placing all the bus buffer units in the partitioning module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the interconnection line length mean and the interconnection line length variance is minimum, and the constraint condition is the movement in the random y-axis direction; the optimization goal of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation item is minimum, and the constraint conditions are in the x-axis direction and the y-axis direction, rotation is carried out according to a first probability, and unit layout type replacement is carried out according to a second probability.
In order to solve the above technical problem, the present invention also provides a storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the layout optimization method for a superconducting integrated circuit.
In order to solve the above technical problem, the present invention further provides a terminal, including: a processor and a memory;
the memory is used for storing computer programs, and the processor is used for executing the computer programs stored by the memory so as to enable the terminal to execute the layout optimization method of the superconducting integrated circuit.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
by applying the layout optimization method of the superconducting integrated circuit provided by the embodiment of the invention, the automatic layout optimization of the large-scale superconducting integrated circuit can be realized, namely, each segmentation module is subjected to multiple optimization, the superconducting integrated circuit netlist is converted into physical layout, the original manual design process is replaced, the design scale of the superconducting integrated circuit is improved, and the design iteration cycle is shortened. After the preprocessing operation, the method can effectively generate a data structure suitable for the segmentation of the net list of the superconducting integrated circuit, and improve the operation effect of the segmentation; the circuit netlist is divided into a plurality of division modules, so that the subsequent optimized layout result is more optimal; in addition, the invention adopts a layout device optimized for the Bit-Slice structure, so that the layout result is more consistent with the structure and the data flow mode of the superconducting integrated circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic flow chart of a layout optimization method for a superconducting integrated circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an effect of preprocessing a circuit netlist according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an effect of performing a modularization process on a netlist to be placed according to a first embodiment of the present invention;
fig. 4 is a schematic diagram illustrating an effect of performing layout optimization on all the segmentation modules in the first embodiment of the present invention;
FIG. 5 is a flow chart illustrating layout optimization of a partitioning module according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating an effect of determining a size of a layout space required for each level of logic depth group in a partitioning module according to an embodiment of the present invention;
FIG. 7 is a flow chart illustrating a first global optimizer as an improved simulated annealing algorithm according to a first embodiment of the present invention;
fig. 8 is a schematic diagram illustrating an effect of optimizing a position of a clock unit by a fourth global optimizer in the first embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a layout optimization apparatus for a second superconducting integrated circuit according to an embodiment of the present invention;
fig. 10 shows a structural diagram of a four-terminal according to an embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
Because superconducting integrated circuits such as SFQ circuits and the like adopt gate-level flow water, special clock tree structures and the like, and have certain particularity, the support of the current commercial and open-source electronic design automation tools (EDA) is not enough to meet the requirement of large-scale automatic design, and for the superconducting integrated circuits such as SFQ circuits and the like with the level of ten thousand or more, manual layout optimization takes a huge amount of time, and the iteration cycle of a chip is seriously influenced.
Example one
In order to solve the technical problems in the prior art, the embodiment of the invention provides a layout optimization method for a superconducting integrated circuit.
FIG. 1 is a schematic flow chart of a layout optimization method for a superconducting integrated circuit according to an embodiment of the present invention; referring to fig. 1, a layout optimization method for a superconducting integrated circuit according to an embodiment of the present invention includes the following steps.
Step S101, obtaining a circuit netlist of a circuit to be laid out, and preprocessing the circuit netlist to obtain the netlist to be laid out.
Specifically, a circuit netlist obtained after logic synthesis of a circuit to be laid out is obtained, and then the circuit netlist is preprocessed to obtain the netlist to be laid out. FIG. 2 is a schematic diagram illustrating an effect of preprocessing a circuit netlist according to a first embodiment of the present invention; referring to fig. 2, preprocessing the circuit netlist includes: in addition to the bus buffer cells, interconnect cells in the circuit netlist are removed to facilitate optimization of subsequent global layouts. Meanwhile, circuit information statistics needs to be carried out on the netlist to be laid out at the stage, and if the netlist to be laid out has unidentifiable units, the unidentifiable units are marked as macro units; and if the condition that the circuit netlist cannot be normally analyzed is found in the modification stage, throwing out the abnormity and directly exiting the current program, and ending the circuit layout optimization of the current circuit to be laid.
Step S102, performing modularization processing on the netlist to be laid out to obtain at least one segmentation module, and performing layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout.
Specifically, the netlist to be laid out is segmented based on preset segmentation conditions, and at least one segmentation module is obtained. FIG. 3 is a schematic diagram illustrating an effect of performing a modularization process on a netlist to be placed according to a first embodiment of the present invention; referring to fig. 3, the preset division condition is controlled by the user, and if the user does not input the restriction of the division condition, the division is performed according to the default division condition of the program. Preferably, the default segmentation condition can be set to segment horizontally with a minimal segmentation algorithm and segment vertically with a principle that the logic depth is kept consistent. It should be noted that, after the division based on the preset division condition, the netlist to be laid out may be divided into a plurality of division modules, or may still be a whole (i.e. the netlist to be laid out).
When the netlist to be laid out is divided into a plurality of division modules, top-level layout optimization can be performed on all the division modules through a third global optimizer so as to obtain the position layout of each division module. Fig. 4 is a schematic diagram illustrating an effect of performing layout optimization on all the segmentation modules in the first embodiment of the present invention; referring to fig. 4, the optimization objectives of the third global optimizer are set as: the product of the difference between the abscissa and the ordinate of the minimum coordinate and the maximum coordinate of each partitioning module is minimum, that is, if the minimum coordinate of the partitioning module is (x _ min, y _ min) and the maximum coordinate of the partitioning module is (x _ max, y _ max), the requirement of each partitioning module to satisfy (y _ max-y _ min) (x _ max-x _ min) is minimum; and simultaneously, the linear combination of the total distance of the Manhattan distances of the interconnection lines among all the segmentation modules and the variance of the Manhattan distances of all the interconnection lines is minimum. And simultaneously setting the constraint conditions of the third global optimizer as follows: the difference between the abscissa of the minimum coordinate and the abscissa of the maximum coordinate of each segmentation module is smaller than a first threshold, the difference between the ordinate of the minimum coordinate and the ordinate of the maximum coordinate of each segmentation module is smaller than a second threshold, the sum of the lengths of any two segmentation modules is smaller than a third threshold, and the sum of the widths of any two segmentation modules is smaller than a fourth threshold.
Preferably, according to the optimization target and the constraint condition, the top-level layout optimization problem can be solved by using the existing convex optimization solver, and finally, the optimized positions of the segmentation modules are obtained.
Furthermore, since no constraint is added to the routing of the interconnection lines, the routing space between the layout blocks may be relatively small, and the routing space needs to be calculated according to the conditions of the interconnection lines between the layout blocks. The specific calculation method of the wiring space size includes a final relative wiring width determination process and a movement process. The final relative wiring width determining process of every two mutually connected segmentation modules is as follows: setting the initial minimum wiring space width of two interconnected segmentation modules as 1, analyzing each interconnection line between the two segmentation modules, checking a rectangular area formed by a starting point and an end point of each interconnection line, if the rectangular areas formed by the interconnection lines between the two segmentation modules are overlapped, repeating the process until the final relative wiring width of the two interconnected segmentation modules is obtained. The final relative wiring widths of all the two connected split modules are obtained in the above manner. The moving process is as follows: and finding the layout midpoint of the whole layout, taking the layout midpoint as the midpoint, and moving all the split modules towards the direction far away from the midpoint based on the final relative wiring widths of all the two split modules connected with each other.
It should be noted that, when the netlist to be laid out is divided into a division module (i.e., the netlist body to be laid out), the top-level layout optimization process may also be performed, but the netlist to be laid out after the top-level optimization still outputs the netlist body to be laid out.
After the top-level optimization of each partitioning module is completed, the layout optimization of each partitioning module needs to be performed, and the process of performing the layout optimization on each partitioning module is the same. The layout optimization of the segmentation module comprises the following steps. FIG. 5 is a flow chart illustrating layout optimization of a partitioning module according to an embodiment of the present invention; as shown with reference to fig. 5.
Specifically, the size of the layout space required by all the levels of logic depths is estimated based on the number of units, clock ends and signal lines included in each level of logic depth, and the calculation result is stored in a layout planning dictionary. FIG. 6 is a diagram illustrating an effect of determining a size of a layout space required for each level of logic depth group in a partitioning module according to an embodiment of the present invention; referring to fig. 6, the layout space size required by the logic depth of all levels is obtained by: the height acquisition mode of all the level logic depth groups is as follows: acquiring the number of units in all the level logic depth groups, selecting the maximum number of the units as a height reference value, and setting the heights of all the level logic depth groups according to the height reference value; for example: the first-level logic depth group is 5 logic gate units, the second-level logic depth group is 3 logic gate units, the third-level logic depth group is 6 logic gate units, and finally the height of all the level logic depth groups is 6. The width of each level of logic depth group is calculated as follows: the linear combination of the number of units, the number of clock ends and the number of signal lines in the current stage logic depth group. For example: the width of the current stage logic depth group is a unit number + b log2 (clock end number) + c signal line number + d compensation function.
It should be noted that the multi-core operation can be performed on all the segmentation modules, that is, the layout plans of all the segmentation modules can be calculated synchronously; after the layout planning of all the sub-modules is completed, the user can enter each segmentation module to check the optimization result according to the requirement, and the layout planning result is modified according to the design requirement.
And step S202, based on the size of the layout space required by each level of logic depth group in the partitioning module, performing position arrangement optimization on all logic gate units in the partitioning module through a first global optimizer to obtain a preliminary optimization result.
Specifically, on the basis of the known size of the layout space required by each level of logic depth group in the partitioning module, the position arrangement optimization of each logic gate unit in the partitioning module in the layout space is completed through a first global optimizer, and a preliminary optimization result is obtained. The optimization target of the first global optimizer is that the linear combination of the interconnection line length mean and the interconnection line length variance is minimum, and the constraint condition is the movement in the random y-axis direction. FIG. 7 is a flow chart illustrating a first global optimizer as an improved simulated annealing algorithm according to a first embodiment of the present invention; referring to fig. 7, the first global optimizer may preferably select a plurality of global optimizers, here, taking the improved simulated annealing algorithm as an example, and taking the minimum linear combination of the mean value of the interconnect line length and the variance of the interconnect line length as an optimization target. In the simulated annealing process, a certain number of logic gate units are selected to move in the random y-axis direction and move for a random distance, the number of units selected in a single operation and the random moving distance are gradually reduced along with the temperature reduction, and the movement of the units is stopped when the temperature reaches the minimum temperature. After a single operation, whether the operation is accepted or not is determined according to the Metropolis criterion.
Step S203, mapping the preliminary optimization result to a layout plan, adding unit information of all logic gate units to the layout plan, and obtaining the layout of the partitioning module.
Specifically, after the global layout optimization is completed, the result of the global layout optimization, i.e., the preliminary optimization result, needs to be mapped to the layout plan, and the unit information of all logic gate units is added to the layout plan to obtain the layout of the partitioning module, so as to convert the virtual circuit diagram into a layout with spatial position attributes and process attributes. The unit information comprises process information of the logic gate unit, the shape of the logic gate unit and port position distribution information.
Step S204, all the bus buffer units in the partitioning module are placed in the layout by a preset placing mode, all the units in the layout are subjected to position optimization by a second global optimizer, and then all the logic gate units containing clocks in the layout are subjected to clock optimization.
Specifically, the placement of all the sink buffer units in the partitioning module needs to be optimized first, and all the sink buffer units in the partitioning module need to be placed at appropriate positions in the layout. The placement process of all the sink buffer units specifically includes: extracting all the conflux buffer units in the segmentation module, and randomly forming a temporary queue; then, acquiring a first bus buffer unit of the temporary queue, and taking the first bus buffer unit as a unit to be placed; judging whether the previous stage unit of the unit to be placed is placed or not, if so, placing the unit to be placed, otherwise, placing the unit to be placed back to the tail end of the temporary queue, and acquiring the first confluence buffer unit of the current temporary queue as the unit to be placed again; the above process is repeated until all the sink buffer unit placements in the segmentation module are completed. Further, the process of placing the unit to be placed comprises: the method comprises the steps of obtaining the position midpoints of all preceding stage units of a unit to be placed as reference midpoints, placing the unit to be placed on the basis of the reference midpoints, namely judging whether redundant layout space exists near the reference midpoints, if not, randomly moving the unit to the periphery until a position can be placed is found, and recording the placing position of the unit to be placed in a database of the confluence buffer unit after the placement is finished.
And then optimizing the positions of all the units in the layout by a second global optimizer. The optimization goal of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation item is minimum, and the constraint conditions of the second global optimizer are the x-axis direction and the y-axis direction, rotation is carried out according to the first probability, and unit layout type replacement is carried out according to the second probability. Furthermore, the selection range of the first probability and the second probability is 0.01-0.1. Preferably, the second global optimizer may select a plurality of global optimizers, i.e. the second global optimizer may still be an improved simulated annealing algorithm as an example.
And finally, performing clock optimization on all logic gate units containing clocks in the layout. Fig. 8 is a schematic diagram illustrating an effect of optimizing a position of a clock unit by a fourth global optimizer in the first embodiment of the present invention; referring to fig. 8, in order to implement local layout optimization for the clock tree, if the partition module is a clock tree-driven module, the program will establish a virtual clock tree according to the clock tree conditions set by the user, and perform unit rotation direction optimization for the position of the virtual clock tree. Further, the clock optimization of all logic gate units including clocks in the layout includes: if the logic gate containing the clock is called a clock unit; calculating all leaf nodes based on the coordinate positions of all clock units in the layout and a preset fan-out value; and optimizing the position of the clock unit through a fourth global optimizer. The optimization target of the fourth global optimizer is that the total length of all the clock unit interconnection lines is shortest; the constraint conditions of the fourth global optimizer are as follows: rotating the clock unit.
After the layout optimization of all the segmentation modules is completed, a user can output an optimized netlist file (verilog) and layout information (DEF file or il file) as a guide information file for subsequent clock tree synthesis and wiring optimization according to needs.
The layout optimization method of the superconducting integrated circuit provided by the embodiment of the invention can realize automatic layout optimization of a large-scale superconducting integrated circuit, namely, each segmentation module is subjected to multiple optimization, the superconducting integrated circuit netlist is converted into physical layout, the original manual design process is replaced, the design scale of the superconducting integrated circuit is improved, and the design iteration cycle is shortened. After the preprocessing operation, the method can effectively generate a data structure suitable for the segmentation of the net list of the superconducting integrated circuit, and improve the operation effect of the segmentation; the circuit netlist is divided into a plurality of division modules, so that the subsequent optimized layout result is more optimal; in addition, the invention adopts a layout device optimized for the Bit-Slice structure, so that the layout result is more consistent with the structure and the data flow mode of the superconducting integrated circuit.
Example two
In order to solve the technical problems in the prior art, the embodiment of the invention provides a layout optimization device for a superconducting integrated circuit.
FIG. 9 is a schematic structural diagram of a layout optimization apparatus for a second superconducting integrated circuit according to an embodiment of the present invention; referring to fig. 9, the layout optimization apparatus for a superconducting integrated circuit according to an embodiment of the present invention includes a preprocessing mechanism and an optimization mechanism.
The preprocessing mechanism is used for acquiring a circuit netlist of the circuit to be identified and preprocessing the circuit netlist to acquire a netlist to be laid out;
the optimization mechanism carries out modular processing on the netlist to be distributed to obtain at least one segmentation module, and carries out global layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout;
wherein performing global layout optimization on the segmentation module comprises:
determining and storing the size of layout space required by each level of logic depth group in the segmentation module;
based on the size of the layout space required by each level of logic depth group in the partitioning module, performing position arrangement optimization on all logic gate units in the partitioning module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result to a layout plan, adding unit information of all logic gate units to the layout plan, and acquiring the layout of the partitioning module;
placing all the bus buffer units in the partitioning module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the interconnection line length mean value and the interconnection line length variance is minimum, and the constraint condition is the movement in the random y-axis direction; the optimization goal of the second global optimizer is to minimize the linear combination of the length of the interconnection line, the timing constraint, the congestion condition and the compensation item, and the constraint conditions are the x-axis direction and the y-axis direction, the rotation is carried out with the first probability, and the unit layout type replacement is carried out with the second probability.
The layout optimization device for the superconducting integrated circuit provided by the embodiment of the invention can realize automatic layout optimization of a large-scale superconducting integrated circuit, namely, each segmentation module is subjected to multiple optimization, the superconducting integrated circuit netlist is converted into physical layout, the original manual design process is replaced, the design scale of the superconducting integrated circuit is improved, and the design iteration cycle is shortened. After the device is subjected to preprocessing operation, a data structure suitable for partitioning the net list of the superconducting integrated circuit can be effectively generated, and the partitioning operation effect is improved; the circuit netlist is divided into a plurality of division modules, so that the subsequent optimized layout result is more optimal; in addition, the invention adopts a layout device optimized for the Bit-Slice structure, so that the layout result is more consistent with the structure and the data flow mode of the superconducting integrated circuit.
EXAMPLE III
To solve the above technical problems in the prior art, an embodiment of the present invention further provides a storage medium storing a computer program, and the computer program, when executed by a processor, can implement all the steps in the layout optimization method of the superconducting integrated circuit according to the embodiment.
The specific steps of the layout optimization method of the superconducting integrated circuit and the beneficial effects obtained by applying the readable storage medium provided by the embodiment of the invention are the same as those of the first embodiment, and are not described herein again.
It should be noted that: the storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Example four
In order to solve the technical problems in the prior art, the embodiment of the invention also provides a terminal.
Fig. 10 is a schematic structural diagram of a four-terminal according to an embodiment of the present invention, and referring to fig. 10, the terminal according to this embodiment includes a processor and a memory, which are connected to each other; the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the terminal can realize all the steps in the layout optimization method of the superconducting integrated circuit.
The specific steps of the layout optimization method of the superconducting integrated circuit and the beneficial effects obtained by applying the terminal provided by the embodiment of the invention are the same as those of the first embodiment, and are not described herein again.
It should be noted that the Memory may include a Random Access Memory (RAM), and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Similarly, the Processor may also be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A layout optimization method for a superconducting integrated circuit includes:
obtaining a circuit netlist of a circuit to be laid out, and preprocessing the circuit netlist to obtain the netlist to be laid out;
performing modular processing on the netlist to be laid out to obtain at least one segmentation module, and performing layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module comprises:
determining and storing the size of layout space required by each level of logic depth group in the segmentation module;
based on the size of the layout space required by each level of logic depth group in the partitioning module, performing position arrangement optimization on all logic gate units in the partitioning module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result to a layout plan, and adding unit information of all the logic gate units to the layout plan to obtain the layout of the partitioning module;
placing all the bus buffer units in the partitioning module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the interconnection line length mean and the interconnection line length variance is minimum, and the constraint condition is the movement in the random y-axis direction; the optimization goal of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation item is minimum, and the constraint conditions are in the x-axis direction and the y-axis direction, rotation is carried out according to a first probability, and unit layout type replacement is carried out according to a second probability.
2. The method of claim 1, wherein preprocessing the circuit netlist to obtain a netlist to be laid out comprises:
and removing all the interconnection line units except the bus buffer unit in the circuit netlist to obtain a netlist to be laid, and carrying out circuit statistics on the netlist to be laid.
3. The method of claim 1, wherein modularizing the netlist to be laid out to obtain at least one partitioning module comprises:
segmenting the netlist to be laid out based on preset segmentation conditions to obtain at least one segmentation module;
the preset segmentation condition is that segmentation is carried out horizontally by using a minimum segmentation algorithm, and segmentation is carried out longitudinally by using the principle that the logic depth keeps consistent.
4. The method of claim 1, further comprising, prior to performing layout optimization on all of the partitioning modules:
performing layout optimization on all the segmentation modules through a third global optimizer;
wherein the optimization goal of the third global optimizer is: the product of the difference between the abscissa and the ordinate of the minimum coordinate and the maximum coordinate of each partitioning module is minimum, and the linear combination of the total distance of the Manhattan distances of the interconnection lines among all the partitioning modules and the variance of the Manhattan distances of all the interconnection lines is minimum; the constraint conditions of the third global optimizer are as follows: the difference between the abscissa of the minimum coordinate and the abscissa of the maximum coordinate of each segmentation module is smaller than a first threshold, the difference between the ordinate of the minimum coordinate and the ordinate of the maximum coordinate of each segmentation module is smaller than a second threshold, the sum of the lengths of any two segmentation modules is smaller than a third threshold, and the sum of the widths of any two segmentation modules is smaller than a fourth threshold.
5. The method of claim 1, wherein determining a required layout space size for each level of logical depth group in the partitioning module comprises:
the height acquisition mode of all the level logic depth groups is as follows: acquiring the number of units in all the level logic depth groups, selecting the maximum number of the units as a height reference value, and setting the heights of all the level logic depth groups according to the height reference value;
the width of each level of logic depth group is calculated as follows: the linear combination of the number of units, the number of clock ends and the number of signal lines in the current stage logic depth group.
6. The method according to claim 1, wherein placing all the sink buffer units in the partitioning module into the layout by a preset placing manner comprises:
extracting all the confluence buffer units in the segmentation module to form a temporary queue;
acquiring a first confluence buffer unit of the temporary queue as a unit to be placed;
judging whether the previous stage unit of the unit to be placed is placed or not, if so, placing the unit to be placed, otherwise, placing the unit to be placed back to the tail end of the temporary queue, and acquiring the first confluence buffer unit of the current temporary queue as the unit to be placed again, and judging the unit to be placed again;
wherein placing the unit to be placed comprises:
and acquiring the position midpoints of all the preceding stage units of the unit to be placed as reference midpoints, placing the unit to be placed on the basis of the reference midpoints, and recording the placing positions of the unit to be placed in a database of the confluence buffer unit.
7. The method according to claim 1, wherein clock optimizing all clocked logic gate units in the layout comprises:
if the logic gate containing the clock is called a clock unit;
calculating all leaf nodes based on the coordinate positions of the clock units and a preset fan-out value;
optimizing the position of the clock unit through a fourth global optimizer;
wherein the optimization goal of the fourth global optimizer is: the total length of all the clock unit interconnecting wires is shortest; the constraint conditions of the fourth global optimizer are as follows: rotating the clock unit.
8. A layout optimization device for a superconducting integrated circuit is characterized by comprising a preprocessing mechanism and an optimization mechanism;
the preprocessing mechanism is used for acquiring a circuit netlist of the circuit to be laid out and preprocessing the circuit netlist to acquire the netlist to be laid out;
the optimization mechanism is used for performing modular processing on the netlist to be distributed to obtain at least one segmentation module and performing layout optimization on all the segmentation modules respectively to obtain an optimized circuit layout;
wherein performing layout optimization on the segmentation module comprises:
determining the size of layout space required by each level of logic depth group in the partitioning module;
based on the size of the layout space required by each level of logic depth group in the partitioning module, performing position arrangement optimization on all logic gate units in the partitioning module through a first global optimizer to obtain a preliminary optimization result;
mapping the preliminary optimization result to a layout plan, and adding unit information of all the logic gate units to the layout plan to obtain the layout of the partitioning module;
placing all the bus buffer units in the partitioning module into the layout by a preset placing mode, performing position optimization on all the units in the layout by a second global optimizer, and performing clock optimization on all the logic gate units containing clocks in the layout;
the optimization target of the first global optimizer is that the linear combination of the interconnection line length mean and the interconnection line length variance is minimum, and the constraint condition is the movement in the random y-axis direction; the optimization goal of the second global optimizer is that the linear combination of the length of the interconnection line, the time sequence constraint, the congestion condition and the compensation item is minimum, and the constraint conditions are in the x-axis direction and the y-axis direction, rotation is carried out according to a first probability, and unit layout type replacement is carried out according to a second probability.
9. A storage medium having stored thereon a computer program, wherein the program, when executed by a processor, implements the layout optimization method for a superconducting integrated circuit according to any one of claims 1 to 7.
10. A terminal, comprising: a processor and a memory;
the memory is used for storing a computer program, and the processor is used for executing the computer program stored by the memory to enable the terminal to execute the layout optimization method of the superconducting integrated circuit according to any one of claims 1 to 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116702301A (en) * | 2023-08-04 | 2023-09-05 | 中国电子工程设计院有限公司 | Method and device for generating multistage simulation layout of integrated circuit production line |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003045974A (en) * | 2001-07-31 | 2003-02-14 | National Institute Of Advanced Industrial & Technology | Pattern layout method of superconduction logical integrated circuit |
| JP2006252717A (en) * | 2005-03-14 | 2006-09-21 | Nec Corp | Method of constituting superconducting random access memory |
| CN107704649A (en) * | 2017-08-23 | 2018-02-16 | 中国科学院上海微系统与信息技术研究所 | Josephson junction circuit model and superconducting integrated circuit structure and method for building up |
| US20180253524A1 (en) * | 2017-03-01 | 2018-09-06 | Synopsys, Inc. | Computationally Efficient Nano-Scale Conductor Resistance Model |
| CN110121747A (en) * | 2016-10-28 | 2019-08-13 | 伊鲁米那股份有限公司 | For executing the bioinformatics system, apparatus and method of second level and/or tertiary treatment |
| CN111914500A (en) * | 2020-07-23 | 2020-11-10 | 清华大学 | Rapid single-flux quantum RSFQ circuit layout method and device |
| CN113095015A (en) * | 2021-05-08 | 2021-07-09 | 中国科学院上海微系统与信息技术研究所 | SFQ time sequence circuit comprehensive calculation method, system and terminal |
-
2021
- 2021-09-17 CN CN202111094793.4A patent/CN113627120B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003045974A (en) * | 2001-07-31 | 2003-02-14 | National Institute Of Advanced Industrial & Technology | Pattern layout method of superconduction logical integrated circuit |
| JP2006252717A (en) * | 2005-03-14 | 2006-09-21 | Nec Corp | Method of constituting superconducting random access memory |
| CN110121747A (en) * | 2016-10-28 | 2019-08-13 | 伊鲁米那股份有限公司 | For executing the bioinformatics system, apparatus and method of second level and/or tertiary treatment |
| US20180253524A1 (en) * | 2017-03-01 | 2018-09-06 | Synopsys, Inc. | Computationally Efficient Nano-Scale Conductor Resistance Model |
| CN107704649A (en) * | 2017-08-23 | 2018-02-16 | 中国科学院上海微系统与信息技术研究所 | Josephson junction circuit model and superconducting integrated circuit structure and method for building up |
| CN111914500A (en) * | 2020-07-23 | 2020-11-10 | 清华大学 | Rapid single-flux quantum RSFQ circuit layout method and device |
| CN113095015A (en) * | 2021-05-08 | 2021-07-09 | 中国科学院上海微系统与信息技术研究所 | SFQ time sequence circuit comprehensive calculation method, system and terminal |
Non-Patent Citations (3)
| Title |
|---|
| COENRAD J. FOURIE: "Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx", pages 1 - 9, XP011566370, Retrieved from the Internet <URL:《网页在线公开：https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6913533》> DOI: 10.1109/TASC.2014.2360870 * |
| 刘沁莹等: "基于转角样品杆的脉冲强磁场电输运测量系统", 《物理学报》, vol. 68, no. 23, pages 59 - 68 * |
| 李春光等: "中国超导电子学研究及应用进展", 《物理学报》, vol. 70, no. 1, pages 1 - 26 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116702301A (en) * | 2023-08-04 | 2023-09-05 | 中国电子工程设计院有限公司 | Method and device for generating multistage simulation layout of integrated circuit production line |
| CN116702301B (en) * | 2023-08-04 | 2023-10-10 | 中国电子工程设计院有限公司 | Method and device for generating multistage simulation layout of integrated circuit production line |
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