CN113807043A - Clock tree synthesis and layout hybrid optimization method and device, storage medium and terminal - Google Patents
Clock tree synthesis and layout hybrid optimization method and device, storage medium and terminal Download PDFInfo
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Abstract
The invention discloses a clock tree synthesis and layout hybrid optimization method and device, a storage medium and a terminal, wherein the method comprises the steps of obtaining coordinate positions of all clock ports and obtaining logic depths of all clock ports; grouping all the clock ports based on the logic depths of all the clock ports to obtain a plurality of logic depth groups, and obtaining the division point of each logic depth group; calculating a main node based on the division points of the logic depth group, and connecting to form a clock tree main track; calculating all leaf nodes in the logical depth group and connecting the leaf nodes to the main track of the clock tree; and converting all the main nodes and all the leaf nodes into virtual units, and taking all the virtual units and all logic gates in the circuit layout to be optimized as movable units to obtain an optimized circuit board diagram. The invention further improves the clock tree performance and the layout effect of the superconducting integrated circuit, particularly the Bit-Slice circuit structure in the SFQ logic, and provides more optimized layout for the wiring optimization of the subsequent circuit.
Description
Technical Field
The invention relates to the technical field of superconducting integrated circuit layout, in particular to a clock tree synthesis and layout hybrid optimization method and device, a storage medium and a terminal.
Background
Superconducting integrated circuits are integrated circuits based on josephson junctions and superconducting materials, including Single-Flux-Quantum (SFQ) circuits and the like.
The SFQ circuit is a relatively special superconducting integrated circuit, which is mainly composed of josephson junctions, and digital logic "0" and "1" are represented by the presence or absence of a magnetic flux quantum Φ 0. Compared with a traditional semiconductor CMOS (complementary Metal Oxide semiconductor) circuit, the micro and quantitative properties of the flux quanta obviously reduce the influence of crosstalk and power consumption, and narrow voltage pulses generated in the junctions when the flux quanta enter and exit the loop enable the flux quanta to obtain extremely high frequency. The circuit has the advantages of ultrahigh working speed and extremely low power consumption, so that the circuit has a remarkable prospect in the application of ultra-wide bandwidth Analog-to-Digital converters (ADC), superconducting computers and the like.
The large-scale design of SFQ circuits is largely limited by the performance of electronic design automation tools (EDAs), and the support of SFQ designs by current commercial and open-source EDA tools is insufficient to meet the requirements of SFQ circuits. Since current EDA tools are developed primarily around CMOS circuits, it is difficult to fully support automated design of SFQ circuits on some key attributes, such as the inability to support clock tree synthesis of current-flow and counter-flow structures commonly used in SFQ circuits; in addition, due to the particularity of the SFQ circuit, the degree of interaction between layout optimization and the clock tree is larger, and it is difficult for a single optimization step to exert the optimal performance of the circuit.
Disclosure of Invention
The invention aims to solve the technical problems that the conventional EDA tool cannot completely support the automatic design of the SFQ circuit, the mutual influence degree between the layout optimization of the SFQ circuit and a clock tree is large, and the conventional optimization mode cannot exert the optimal performance of the SFQ circuit.
In order to solve the technical problem, the invention provides a clock tree synthesis and layout hybrid optimization method, which comprises the following steps:
acquiring coordinate positions of all clock ports in the circuit to be optimized based on layout data of the circuit to be optimized, and acquiring logic depths of all clock ports in the circuit to be optimized based on a circuit netlist of the circuit to be optimized;
grouping all the clock ports based on the logic depths of all the clock ports to obtain a plurality of logic depth groups, and segmenting each logic depth group to obtain a segmentation point of each logic depth group;
respectively calculating the trunk nodes of each logic depth group by taking the division points of each logic depth group as reference nodes, and sequentially connecting all the trunk nodes to form a clock tree main track;
respectively calculating all leaf nodes corresponding to the logic depth groups based on the coordinate positions of all clock ports in each logic depth group, and connecting all the leaf nodes with the clock tree main track;
converting all the main nodes and all the leaf nodes into virtual units, taking all the virtual units and all the logic gates in the circuit layout to be optimized as movable units at the same level, and performing iterative optimization on all the movable units by using a layout optimizer based on a simulated annealing algorithm to obtain an optimized circuit.
Preferably, grouping all the clock ports based on their logic depths, and obtaining the plurality of logic depth groups includes:
grouping the same logic depth in all clock ports into one group, and sequentially arranging the logic depths from small to large to obtain a plurality of logic depth groups.
Preferably, the segmenting each of the logical depth groups to obtain a segmentation point of each of the logical depth groups includes:
and respectively taking the middle point of the position coordinate of the clock port at the top edge and the position coordinate of the clock port at the bottom edge in each logic depth group as a division point corresponding to the logic depth group.
Preferably, calculating the backbone node of each of the logical depth groups with the partition point of each of the logical depth groups as a reference node, respectively, includes:
respectively taking the division point of each logic depth group as a reference node of each logic depth group;
and searching the trunk nodes corresponding to the logic depth groups in the preset range of each reference node, so that the sum of the height differences between all adjacent trunk nodes is smaller than a preset threshold value.
Preferably, computing all leaf nodes corresponding to a single logical depth group based on all clock port coordinate positions in the logical depth group comprises:
a straight line extending from left to right of a backbone node in the logic depth group divides the logic depth group into an upper half plane and a lower half plane;
and calculating all leaf nodes in each half plane based on all clock port coordinate positions in each half plane and a preset fan-out value.
Preferably, connecting all of the leaf nodes with the clock tree main track comprises:
connecting all leaf nodes in each half plane into a sub-clock tree based on the preset fan-out value;
connecting root nodes of all the sub-clock trees with the clock tree main track so that each level node of two sub-clock trees in the same logic depth group has a clock track with the same length.
Preferably, the optimization target of the simulated annealing algorithm is the overall deviation value of the clock tree before and after movement, and the difference value between the mean value of all signal line lengths in the circuit to be optimized, the variance of all signal line lengths, the sum of the area occupied by the whole layout and the routing density is smaller than a preset threshold value
In order to solve the above technical problem, the present invention further provides a clock tree synthesis and layout hybrid optimization apparatus, including: the device comprises a data acquisition module, a segmentation module, a main track forming module, a leaf node acquisition module and an optimization module.
The data acquisition module is used for acquiring coordinate positions of all clock ports in the circuit to be optimized based on layout data of the circuit to be optimized and acquiring logic depths of all clock ports in the circuit to be optimized based on a circuit netlist of the circuit to be optimized;
the segmentation module is used for grouping all the clock ports based on the logic depths of all the clock ports to obtain a plurality of logic depth groups, and segmenting each logic depth group to obtain a segmentation point of each logic depth group;
the main track forming module is used for calculating the trunk nodes of each logic depth group by taking the division points of each logic depth group as reference nodes, and sequentially connecting all the trunk nodes to form a clock tree main track;
the leaf node acquisition module is used for respectively calculating all leaf nodes corresponding to the logical depth groups based on the coordinate positions of all clock ports in each logical depth group and connecting all the leaf nodes with the clock tree main track;
and the optimization module is used for converting all the trunk nodes and all the leaf nodes into virtual units, taking all the virtual units and all the logic gates in the circuit layout to be optimized as movable units, and optimizing all the movable units through a simulated annealing algorithm to obtain the optimized circuit.
In order to solve the above technical problem, the present invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the clock tree synthesis and layout blending optimization method.
In order to solve the above technical problem, the present invention further provides a terminal, including: a processor and a memory;
the memory is used for storing computer programs, and the processor is used for executing the computer programs stored by the memory so as to enable the terminal to execute the clock tree synthesis and layout mixing optimization method.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
by applying the clock tree synthesis and layout hybrid optimization method provided by the embodiment of the invention, the construction of a current-flow clock tree and a counter-flow clock tree in an SFQ circuit is supported mainly by converting all trunk nodes and all leaf nodes of the clock tree into virtual units, taking all the virtual units and all logic gates as movable units, and optimizing all the movable units through a simulated annealing algorithm, so that the clock tree synthesis and layout hybrid optimization method reduces the quantity of a clock tree network, meets the requirement of time sequence convergence, and is more suitable for the automatic design of the SFQ circuit. The clock tree performance and the layout effect of the superconducting integrated circuit, particularly the Bit-Slice circuit structure in the SFQ logic, are further improved, and more optimized layout is provided for the wiring optimization of subsequent circuits.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart illustrating a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an example of clock port grouping in a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an example of obtaining a backbone node and forming a clock tree main track in a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an example of obtaining leaf nodes and connecting them to main tracks in a clock tree synthesis and layout blending optimization method according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an example of converting all the trunk nodes and all the leaf nodes into virtual units in a clock tree synthesis and layout blending optimization method according to an embodiment of the present invention;
FIG. 6 is a schematic flow chart illustrating the utilization of simulated annealing algorithm in a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating an example of obtaining an optimized circuit board diagram by a clock tree synthesis and layout blending optimization method according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a second clock tree synthesis and layout hybrid optimization apparatus according to an embodiment of the present invention;
fig. 9 shows a schematic structural diagram of a four-terminal according to an embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
The SFQ circuit has the advantages of ultrahigh working speed and extremely low power consumption, so that the circuit has remarkable prospect in the application of ultra-wide bandwidth Analog-to-Digital Converter (ADC), superconducting computers and the like. However, the large-scale design of SFQ circuits is limited by the performance of electronic design automation tools (EDAs), and the support of SFQ designs by current commercial and open-source EDA tools is not sufficient to meet the requirements of SFQ circuits. Since current EDA tools are developed primarily around CMOS circuits, it is difficult to fully support automated design of SFQ circuits on some key attributes, such as the inability to support clock tree synthesis of current-flow and counter-flow structures commonly used in SFQ circuits; in addition, due to the particularity of the SFQ circuit, the degree of interaction between layout optimization and the clock tree is larger, and it is difficult for a single optimization step to exert the optimal performance of the circuit.
Example one
In order to solve the technical problems in the prior art, the embodiment of the invention provides a clock tree synthesis and layout hybrid optimization method.
FIG. 1 is a flow chart illustrating a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention; referring to fig. 1, a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention includes the following steps.
Step S101, obtaining coordinate positions of all clock ports in the circuit to be optimized based on layout data of the circuit to be optimized, and obtaining logic depths of all clock ports in the circuit to be optimized based on a circuit netlist of the circuit to be optimized.
Specifically, layout data and a circuit netlist of a circuit to be optimized are obtained, and coordinate positions of all clock ports in the circuit to be optimized can be calculated according to the layout data of the circuit to be optimized, wherein a logic gate port connected with a clock signal is called as a clock port. The connection relation of the circuit to be optimized can be obtained by analyzing the circuit netlist of the circuit to be optimized, and then the logic depths of all clock ports in the circuit to be optimized can be calculated and obtained based on the circuit connection relation.
And S102, grouping all the clock ports based on the logic depths of all the clock ports to obtain a plurality of logic depth groups, and segmenting all the logic depth groups to obtain segmentation points of each logic depth group.
Specifically, grouping clock ports with the same logic depth in all clock ports to obtain a plurality of clock port groups with the logic depth, and then sequentially arranging the clock port groups with the logic depth from small to large to obtain a plurality of logic depth groups; namely, the clock port groups arranged in the logic depth order are the logic depth groups. Fig. 2 is a diagram illustrating an example of clock port grouping in a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention. And then all the logic depth groups are segmented according to a certain mode, and segmentation points of the logic depth groups are obtained and used as reference nodes of the trunk of the subsequent calculation clock tree. Further, the acquisition mode of the logic depth group segmentation point is as follows: typically based on the midpoint of the uppermost clock port position coordinate and the lowermost clock port position coordinate within the logical depth group. It should be noted that, in the embodiment of the present application, a position where the midpoint moves left and right by a preset distance may also be used as a dividing point of the logical depth group, where the size of the preset distance may be set according to experience of a technician.
And step S103, calculating the backbone nodes of each logic depth group by taking the division points of each logic depth group as reference nodes, and sequentially connecting all the backbone nodes to form a clock tree main track.
Specifically, fig. 3 is a diagram illustrating an example of obtaining a trunk node and forming a clock tree main track in a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention; referring to fig. 3, when the clock tree main track is set, it is required to ensure that the jitter of the clock tree main track is minimum, so that when the method is applied to an SFQ circuit, the layout design of a long-distance josephson transmission line in an SFQ circuit process is convenient for timing sequence repair in subsequent wiring optimization. Further, after the segmentation points of each level of logic depth group are obtained in step S103, the segmentation points are used as reference nodes, and the most suitable backbone nodes are searched around the reference nodes according to the circuit layout conditions around the reference nodes and the coordinates of the front and rear level segmentation points, so that the deviation between the front and rear level nodes is minimized, and the deviation between the upper and lower half planes of the logic depth group is also ensured to be minimized. Furthermore, the selection method of the trunk node in the logic depth group may specifically be: and searching the trunk nodes corresponding to the logic depth groups in the preset range of each reference node, so that the sum of the height differences of the trunk nodes between all adjacent logic depth groups is smaller than a preset threshold value. The preset range is a range of the logical depth group to which the reference node belongs, and the preset threshold value can be set according to experience of a technician.
And after all the trunk nodes are searched, sequentially connecting all the trunk nodes to form a clock tree main track. It should be noted that the left and right extension lines of the trunk node of each logic depth group divide the corresponding logic depth group into an upper half plane and a lower half plane.
And step S104, respectively calculating all leaf nodes in the corresponding logic depth groups based on the coordinate positions of all clock ports in each logic depth group, and connecting all the leaf nodes with the clock tree main track.
Specifically, the corresponding logic depth groups are divided into upper and lower half planes according to the left and right extension lines of the trunk node of each logic depth group. And then calculating all leaf nodes in each half plane based on the coordinate positions of all clock ports in each half plane and a preset fan-out value. FIG. 4 is a diagram illustrating an example of obtaining leaf nodes and connecting them to main tracks in a clock tree synthesis and layout blending optimization method according to an embodiment of the present invention; referring to fig. 4, if the preset fan-out value is 2, grouping every two clock ports as a group for all the clock ports in the half-and-half plane to obtain a plurality of clock groups, wherein the grouping process is performed from far to near based on the clock tree main track; then, acquiring a leaf node of each clock group, namely acquiring the abscissa of the leaf node by taking the middle point of the ordinate of the two clock ports in the clock group as the ordinate and taking the smaller abscissa of the two clock ports as a reference point (specifically, acquiring the abscissa of the leaf node by subtracting an empirical value from the smaller abscissa of the two clock ports in the clock group); and then, with reference to the leaf node acquisition mode, performing grouping calculation on all the leaf nodes in the same level in the semi-plane to obtain upper-level leaf nodes, and repeating the process until the leaf node in the highest level in the semi-plane is acquired, so that all the leaf nodes in the semi-plane are acquired. At this time, all leaf nodes in the half plane are connected to obtain the sub clock tree in the form of a binary tree. When the fan-out value changes, other forms of sub-clock trees can be obtained. It is not exhaustive at this time and the way in which the leaf nodes are computed may also be modified empirically.
And then connecting all leaf nodes in the half-plane from left to right step by step based on a form of first up and down and then left and right to obtain the sub-clock trees of all the half-planes. The root nodes of all the sub-clock trees are then connected with the clock tree main track, so that the root nodes of the two sub-clock trees in the same logic depth group have clock tracks with the same length. It should be noted that, in the actual connection process, the clock tracks of the root nodes of the two sub-clock trees in the same logic depth group are inevitably different, and the lengths of the two sub-clock trees can be considered to be the same by taking similar values.
And S105, converting all the trunk nodes and all the leaf nodes into virtual units, taking all the virtual units and all logic gates in the circuit layout to be optimized as movable units at the same level, and performing iterative optimization on all the movable units by using a layout optimizer based on a simulated annealing algorithm to obtain an optimized circuit.
FIG. 5 is a diagram illustrating an example of converting all the trunk nodes and all the leaf nodes into virtual units in a clock tree synthesis and layout blending optimization method according to an embodiment of the present invention; referring to fig. 5, after the basic shape of the clock tree is established, all clock tree nodes (including the trunk node and the leaf nodes) need to be converted into virtual units. And simultaneously updating the connection relation of all the virtual units, and importing the connection relation into the circuit netlist to form a new circuit netlist. It should be noted that, for SFQ circuits of different processes, the dummy cells are all set to be square with a side length being a unit length or the same size as the minimum wiring unit.
And then taking all the virtual units and all logic gates in the circuit layout to be optimized as movable units in the same level, and performing iterative optimization on all the movable units by using a layout optimizer based on a simulated annealing algorithm to obtain the optimized circuit. FIG. 6 is a schematic flow chart illustrating the utilization of simulated annealing algorithm in a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention; referring to fig. 6, the optimization target of the annealing algorithm mainly includes the deviation value of the whole clock tree before and after movement, and the difference value between the mean value of all signal line lengths in the circuit to be optimized, the variance of all signal line lengths, and the sum of the area occupied by the whole layout and the routing density is smaller than a preset threshold, that is, the deviation value of the whole clock tree, the mean value of all signal line lengths in the circuit to be optimized, the variance of all signal line lengths, the sum of the area occupied by the whole layout and the routing density are used as the movement consumption in the simulated annealing algorithm. And initial parameters of the simulated annealing algorithm comprise temperature, annealing rate, particle number and moving space size; the simulated annealing algorithm selects the operation object with preset probability by single movement. Preferably, a single move operation can select the logic gate cell with the probability of 4/5 to perform a random move operation, select the clock tree node with the probability of 1/5 to perform a random move operation, and as the temperature decreases, the number of cells selected and the range of the move will gradually decrease until the upper running limit set by the program is reached or the optimization goal is reached. FIG. 7 is a diagram illustrating an example of obtaining an optimized circuit board diagram by a clock tree synthesis and layout hybrid optimization method according to an embodiment of the present invention.
The whole annealing process flow is as follows: setting initial parameters including setting initial values of temperature, annealing rate, particle number and moving space size; then generating an initial solution based on the initial parameters; then selecting a logic gate unit to perform random shift operation based on the probability of 4/5, and selecting a clock tree node to perform random shift operation with the probability of 1/5 to move an operation object once; calculating the mobile consumption, wherein the mobile consumption is equal to the sum of the mean value of all signal lines in the circuit to be optimized, the variance of all the signal lines, the whole occupied area of the layout and the routing density; judging whether the movement consumption change value is larger than zero, if so, receiving the movement result, otherwise, receiving the movement result according to the Metropolis criterion; and then judging whether a termination condition is reached, if so, outputting an optimal solution, otherwise, reducing the temperature, the number of particles and the size of a moving space, and reselecting the unit to perform random moving operation. Where all received move procedures (including accepting the move results and accepting the move results according to Metropolis criteria) need to be stored.
After the mixed optimization of the layout and the clock tree is completed, the program analyzes the optimization result, and outputs layout congestion data, clock tree offset, clock tree jitter and other data, information of the position of the logic gate unit, the position of a clock tree node and the like, and the information is used for subsequently guiding the routing optimization program to perform routing optimization.
The clock tree synthesis and layout hybrid optimization method provided by the embodiment of the invention mainly supports the construction of a current-flow clock tree and a counter-flow clock tree in an SFQ circuit by converting all trunk nodes and all leaf nodes of the clock tree into virtual units, using all the virtual units and all logic gates as movable units and optimizing all the movable units through a simulated annealing algorithm, reduces the volume of the clock tree network, meets the requirement of time sequence convergence simultaneously, and is more suitable for the automatic design of the SFQ circuit. The clock tree performance and the layout effect of the superconducting integrated circuit, particularly the Bit-Slice circuit structure in the SFQ logic, are further improved, and more optimized layout is provided for the wiring optimization of subsequent circuits.
Example two
In order to solve the above technical problems in the prior art, an embodiment of the present invention further provides a clock tree synthesis and layout hybrid optimization apparatus.
FIG. 8 is a schematic structural diagram of a second clock tree synthesis and layout hybrid optimization apparatus according to an embodiment of the present invention; referring to fig. 8, the clock tree synthesis and layout hybrid optimization apparatus according to the embodiment of the present invention includes a data acquisition module, a segmentation module, a main track formation module, a leaf node acquisition module, and an optimization module.
The data acquisition module is used for acquiring coordinate positions of all clock ports in the circuit to be optimized based on layout data of the circuit to be optimized and acquiring logic depths of all clock ports in the circuit to be optimized based on a circuit netlist of the circuit to be optimized;
the segmentation module is used for grouping all the clock ports based on the logic depths of all the clock ports to obtain a plurality of logic depth groups, and segmenting each logic depth group to obtain a segmentation point of each logic depth group;
the main track forming module is used for calculating the trunk nodes of each logic depth group by taking the division points of each logic depth group as reference nodes, and sequentially connecting all the trunk nodes to form a clock tree main track;
the leaf node acquisition module is used for respectively calculating all leaf nodes in the corresponding logic depth groups based on the coordinate positions of all clock ports in each logic depth group and connecting all the leaf nodes with the clock tree main track;
the optimization module is used for converting all the trunk nodes and all the leaf nodes into virtual units, taking all the virtual units and all the logic gates in the circuit layout to be optimized as movable units in the same level, and performing iterative optimization on all the movable units by using a layout optimizer based on a simulated annealing algorithm to obtain an optimized circuit.
The clock tree synthesis and layout hybrid optimization device provided by the embodiment of the invention mainly supports the construction of a current-flow clock tree and a counter-flow clock tree in an SFQ circuit by converting all trunk nodes and all leaf nodes of the clock tree into virtual units, using all the virtual units and all logic gates as movable units and optimizing all the movable units through a simulated annealing algorithm, reduces the volume of the clock tree network, meets the time sequence convergence requirement at the same time, and is more suitable for the automatic design of the SFQ circuit. The clock tree performance and the layout effect of the superconducting integrated circuit, particularly the Bit-Slice circuit structure in the SFQ logic, are further improved, and more optimized layout is provided for the wiring optimization of subsequent circuits.
EXAMPLE III
To solve the above technical problems in the prior art, an embodiment of the present invention further provides a storage medium storing a computer program, and the computer program, when executed by a processor, can implement all the steps in the clock tree synthesis and layout mixing optimization method according to the embodiment.
The specific steps of the clock tree synthesis and layout hybrid optimization method and the beneficial effects obtained by applying the readable storage medium provided by the embodiment of the present invention are the same as those of the first embodiment, and are not described herein again.
It should be noted that: the storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Example four
In order to solve the technical problems in the prior art, the embodiment of the invention also provides a terminal.
Fig. 9 is a schematic structural diagram of a fourth terminal according to an embodiment of the present invention, and referring to fig. 9, the terminal according to this embodiment includes a processor and a memory that are connected to each other; the memory is used for storing computer programs, and the processor is used for executing the computer programs stored in the memory, so that the terminal can realize all the steps in the clock tree synthesis and layout mixing optimization method of the embodiment when being executed.
The specific steps of the clock tree synthesis and layout hybrid optimization method and the beneficial effects obtained by applying the terminal provided by the embodiment of the invention are the same as those of the first embodiment, and are not described herein again.
It should be noted that the Memory may include a Random Access Memory (RAM), and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Similarly, the Processor may also be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A clock tree synthesis and layout hybrid optimization method comprises the following steps:
acquiring coordinate positions of all clock ports in the circuit to be optimized based on layout data of the circuit to be optimized, and acquiring logic depths of all clock ports in the circuit to be optimized based on a circuit netlist of the circuit to be optimized;
grouping all the clock ports based on the logic depths of all the clock ports to obtain a plurality of logic depth groups, and segmenting each logic depth group to obtain a segmentation point of each logic depth group;
respectively calculating the trunk nodes of each logic depth group by taking the division points of each logic depth group as reference nodes, and sequentially connecting all the trunk nodes to form a clock tree main track;
respectively calculating all leaf nodes corresponding to the logic depth groups based on the coordinate positions of all clock ports in each logic depth group, and connecting all the leaf nodes with the clock tree main track;
converting all the main nodes and all the leaf nodes into virtual units, taking all the virtual units and all the logic gates in the circuit layout to be optimized as movable units at the same level, and performing iterative optimization on all the movable units by using a layout optimizer based on a simulated annealing algorithm to obtain an optimized circuit.
2. The method of claim 1, wherein grouping all clock ports based on their logic depths to obtain a plurality of logic depth groups comprises:
grouping the same logic depth in all clock ports into one group, and sequentially arranging the logic depths from small to large to obtain a plurality of logic depth groups.
3. The method of claim 1, wherein segmenting each of the logical depth groups to obtain segmentation points for each of the logical depth groups comprises:
and respectively taking the middle point of the position coordinate of the clock port at the top edge and the position coordinate of the clock port at the bottom edge in each logic depth group as a division point corresponding to the logic depth group.
4. The method of claim 1, wherein computing the backbone node of each of the logical depth groups with the segmentation point of each of the logical depth groups as a reference node comprises:
respectively taking the division point of each logic depth group as a reference node of each logic depth group;
and searching the trunk nodes corresponding to the logic depth groups in the preset range of each reference node, so that the sum of the height differences between all adjacent trunk nodes is smaller than a preset threshold value.
5. The method of claim 1, wherein computing all leaf nodes in a corresponding logical depth group based on all clock port coordinate positions in a single logical depth group comprises:
a straight line extending from left to right of a backbone node in the logic depth group divides the logic depth group into an upper half plane and a lower half plane;
and calculating all leaf nodes in each half plane based on all clock port coordinate positions in each half plane and a preset fan-out value.
6. The method of claim 5, wherein connecting all of the leaf nodes with the clock tree main track comprises:
connecting all leaf nodes in each half plane into a sub-clock tree based on the preset fan-out value;
connecting root nodes of all the sub-clock trees with the clock tree main track so that each level node of two sub-clock trees in the same logic depth group has a clock track with the same length.
7. The method according to claim 1, wherein the optimization goal of the simulated annealing algorithm is that the overall deviation value of the clock tree before and after movement, and the difference value between the average value of all signal line lengths, the variance of all signal line lengths, the total area of the layout and the sum of the routing density in the circuit to be optimized is smaller than a preset threshold value.
8. A clock tree synthesis and layout hybrid optimization device, comprising: the system comprises a data acquisition module, a segmentation module, a main track forming module, a leaf node acquisition module and an optimization module;
the data acquisition module is used for acquiring coordinate positions of all clock ports in the circuit to be optimized based on layout data of the circuit to be optimized and acquiring logic depths of all clock ports in the circuit to be optimized based on a circuit netlist of the circuit to be optimized;
the segmentation module is used for grouping all the clock ports based on the logic depths of all the clock ports to obtain a plurality of logic depth groups, and segmenting each logic depth group to obtain a segmentation point of each logic depth group;
the main track forming module is used for calculating the trunk nodes of each logic depth group by taking the division points of each logic depth group as reference nodes, and sequentially connecting all the trunk nodes to form a clock tree main track;
the leaf node acquisition module is used for respectively calculating all leaf nodes corresponding to the logical depth groups based on the coordinate positions of all clock ports in each logical depth group and connecting all the leaf nodes with the clock tree main track;
and the optimization module is used for converting all the trunk nodes and all the leaf nodes into virtual units, taking all the virtual units and all the logic gates in the circuit layout to be optimized as movable units, and optimizing all the movable units through a simulated annealing algorithm to obtain the optimized circuit.
9. A storage medium on which a computer program is stored, which program, when being executed by a processor, is adapted to carry out the clock tree synthesis and layout blending optimization method of any one of claims 1 to 7.
10. A terminal, comprising: a processor and a memory;
the memory is configured to store a computer program, and the processor is configured to execute the computer program stored in the memory to cause the terminal to perform the clock tree synthesis and layout blending optimization method according to any one of claims 1 to 7.
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