CN106027032A - RM logic circuit delay optimization method in unit delay model - Google Patents

Abstract

A method for optimizing the time delay of an RM logic circuit under a unit time delay model, characterized in that: the specific steps of the method include: Step 1, reading in a Boolean logic circuit; Step 2, using the RM expression simplification method to obtain the number of items containing The least simplest RM logic expression; Step 3, based on the Huffman Huffman tree construction algorithm, decompose the time delay of each AND item in the simplest RM logic expression, so that the delay of each AND item is the smallest; Step 4 , based on the Huffman tree construction algorithm, decompose the delay of the simplest RM logic expression composed of all AND items, so that the delay of the simplest RM logic expression is the smallest; step 5, output the minimum delay of the simplest RM logic expression . The delay optimization method provided by the invention can quickly and effectively convert the Boolean logic circuit into the RM logic circuit with the minimum delay, thereby reducing the circuit delay and improving the working speed and performance of the circuit.

Description

A Delay Optimization Method for RM Logic Circuit under Unit Delay Model

【Technical field】

The invention relates to a Reed-Muller (RM) logic circuit optimization method, in particular to a Reed-Muller logic circuit delay optimization method under a unit delay model. The invention belongs to the technical field of logic circuit synthesis optimization.

【Background technique】

Digital circuits can be implemented by Boolean (Boolean) logic based on AND/OR/NOT (and/or/not) operations, or by AND/XOR (and/exclusive or) or OR/XNOR (or/same or) Reed-Muller (RM) logic implementation of the operation. For circuits such as arithmetic circuits, parity check circuits, and communication circuits with frequent XOR operations, compared with Boolean logic implementations, RM logic implementations have greater advantages in terms of power consumption, area, and speed. In addition, the change of a certain input of the XOR gate will directly cause the change of its output, so the RM logic circuit also has better testability. These properties of RM logic have attracted widespread attention and become a research hotspot in the field of logic circuit design.

With the rapid development of integrated circuits, the number of transistors integrated on a single chip and the number of layers of metal interconnection lines are constantly increasing, and these factors lead to continuous increase of circuit delay. Therefore, delay has become an important optimization goal in IC design. Especially for high-speed VLSI that requires a higher working speed, delay optimization has also become an important part of high-speed VLSI design. In addition, since the delay of combinational circuits determines the lower bound of the cycle period of sequential circuits, the delay optimization of combinational circuits has been widely concerned by circuit designers.

However, existing optimization methods for RM logic circuits mainly focus on power optimization, area optimization, and co-optimization of power consumption and area, while research on delay optimization of RM logic circuits is relatively scarce. In addition, the existing research on delay optimization of RM logic circuits has relatively large limitations and low optimization efficiency. Therefore, research on the delay optimization method of RM logic circuit is an important supplement to the optimization method system of RM logic circuit, and it is of great significance to the optimal design of integrated circuits. In circuit logic design, the delay caused by factors such as wires and capacitance is usually ignored, and only the basic gate delay is considered. Since the unit delay model is also widely used in delay estimation of integrated circuits, the present invention uses the unit delay model to optimize the delay of RM logic circuits. The RM logic circuit delay optimization method under the unit delay model provided by the invention can obtain the RM logic circuit with the minimum delay, so the invention can be used for comprehensive delay optimization of logic circuits. The RM logic circuit delay optimization method under a unit delay model provided by the present invention is an important supplement to the RM logic circuit optimization method system, and is an important contribution to the current logic-level automatic optimization design methodology of integrated circuits based on Boolean logic. Complete.

【Content of invention】

In order to solve the above problems, the present invention provides a delay optimization method for RM logic circuits under the unit delay model. This method first simplifies the RM logic expression to obtain the simplest RM logic expression with the least number of AND items; then based on the Huffman (Huffman) tree construction algorithm, each AND item in the simplest RM logic expression is obtained. Delayed decomposition minimizes the delay of each AND term; finally, the simplest RM logic expression is decomposed based on the Huffman tree construction algorithm to minimize the delay of the simplest RM logic expression.

Specifically, the present invention provides an RM logic circuit delay optimization method under a unit delay model, and the specific steps of the method include:

Step 1, read in the Boolean logic circuit;

Step 2, using the RM expression simplification method (such as algebraic simplification method, irrelevant item simplification method, etc.) to obtain the simplest RM logic expression containing the least number of terms;

Step 3, based on the Huffman tree construction algorithm, decompose the delay of each AND item in the simplest RM logic expression, so that the delay of each AND item is the smallest;

Step 4, based on the Huffman tree construction algorithm, perform delay decomposition on the simplest RM logic expression composed of all AND items, so that the delay of the simplest RM logic expression is the smallest;

Step 5, output the minimum delay of the simplest RM logic expression.

Among them, step 3 includes:

Step 31, calculating the number n of input variables contained in the AND item;

Step 32, if the number of input variables n is equal to 1, set the delay of the AND item as the delay of the input variable; if the number of input variables n is greater than 1, first create n leaf nodes for n input variables, Secondly, according to d ₁ ,d ₂ ,...,d _i ,...,d _n (1≤i≤n, d _i represents the delay of the i-th input variable, and d _n represents the delay of the n-th input variable When) to build a forest F={T ₁ , T ₂ ,...,T _i ,...T _n } with n binary trees, 1≤i≤n, where each binary tree T _i has only one delay d _i node, and finally repeat the following operations until there is only one binary tree (ie Huffman tree) in the forest F: select two trees l and r with the smallest root node delay from the forest F; create a tree with l A new tree with r as the left subtree and _r as the right subtree, where the delay of the root node of the new tree is equal to the greater of the delays of the two subtrees plus 1; delete the selected two trees l from the forest F and r; join the created new tree to forest F. Finally, the delay of the AND item is set as the delay of the root node of the Huffman tree.

Among them, step 4 includes:

Step 41, calculating the number m of AND terms contained in the simplest RM expression;

Step 42, create m leaf nodes for m AND items;

Step 43, construct a forest F with m binary trees according to the delay of m AND items;

Step 44, repeat the following operations until there is only one binary tree (i.e. Huffman tree) in the forest F: select the two trees l and r with the smallest root node delay from the forest F; create a tree with l as the left subtree And take r as the new tree of the right subtree, wherein, the delay of the root node of the new tree is equal to the larger of the delays of the two subtrees plus 1; delete the selected two trees l and r from the forest F; The newly created tree joins the forest F;

Step 45, setting the delay of the simplest RM expression as the delay of the root node of the Huffman tree.

The delay optimization method of RM logic circuit under the unit delay model provided by the present invention can lay the foundation for subsequent acquisition of RM logic circuits with minimum delay by simplifying the RM logic expression to minimize the number of terms; Making full use of the Huffman tree construction algorithm can quickly obtain the advantages of the minimum binary tree with weighted path length, and decompose each AND item in the simplest RM logic expression and the simplest RM logic expression separately, so that each AND item And the delay of the simplest RM logic expression is the smallest. The delay optimization method of RM logic circuit under a unit delay model provided by the present invention can quickly and effectively convert a Boolean logic circuit into an RM logic circuit with a minimum delay, thereby reducing circuit delay, improving circuit operating speed and performance.

【Description of drawings】

FIG. 1 is a flow chart of an RM logic circuit delay optimization method under a unit delay model of the present invention.

Fig. 2 is an AND term delay decomposition process diagram of an embodiment of an RM logic circuit delay optimization method under a unit delay model of the present invention, wherein the numbers on the nodes represent a binary tree with the node as the root node delay.

Fig. 2a shows that the embodiment of the present invention creates 5 leaf nodes for 5 input variables.

Fig. 2b shows the embodiment of the present invention to create a new tree with the two trees with the smallest root node delay as the left and right subtrees.

Fig. 2c shows the embodiment of the present invention to create a new tree with the two trees with the smallest root node delay as the left and right subtrees.

Fig. 2d is the embodiment of the present invention to create a new tree with the two trees with the smallest root node delay as the left and right subtrees.

Fig. 2e is a Huffman tree formed by the embodiment of the present invention.

FIG. 3 is a circuit form diagram of an AND term delay decomposition of an embodiment of an RM logic circuit delay optimization method under a unit delay model of the present invention.

FIG. 4 is a delay decomposition process diagram of the simplest FPRM logic expression in an embodiment of an RM logic circuit delay optimization method under a unit delay model of the present invention.

【detailed description】

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

FIG. 1 is a flow chart of an RM logic circuit delay optimization method under a unit delay model of the present invention. As shown in Figure 1, the method includes:

Step 1, read in the Boolean logic circuit;

Step 2, using the RM expression simplification method (such as algebraic simplification method, irrelevant item simplification method, etc.) to obtain the simplest RM logic expression containing the least number of terms;

Step 3, based on the Huffman tree construction algorithm, decompose the delay of each AND item in the simplest RM logic expression, so that the delay of each AND item is the smallest;

Step 4, based on the Huffman tree construction algorithm, perform delay decomposition on the simplest RM logic expression composed of all AND items, so that the delay of the simplest RM logic expression is the smallest;

Step 5, output the minimum delay of the simplest RM logic expression.

Among them, step 3 includes:

Step 31, calculating the number n of input variables contained in the AND item;

Step 32, if the number of input variables n is equal to 1, set the delay of the AND item as the delay of the input variable; if the number of input variables n is greater than 1, first create n leaf nodes for n input variables, _{Secondly ,} construct _a forest with _n binary trees F= _{ T ₁ ,T ₂ ,...,T _i ,...T _n }, 1≤i≤n, where each binary tree T _i has only one node with a delay of d _i , and finally repeat the following operations until There is only one binary tree (ie Huffman tree) in the forest F: select two trees l and r with the smallest root node delay from the forest F; create a tree with l as the left subtree and r as the right subtree Create a new tree, where the delay of the root node of the new tree is equal to the greater of the delays of the two subtrees plus 1; delete the selected two trees l and r from the forest F; add the created new tree to the forest F. Finally, the delay of the AND item is set as the delay of the root node of the Huffman tree.

Among them, step 4 includes:

Step 41, calculating the number m of AND terms contained in the simplest RM expression;

Step 42, create m leaf nodes for m AND items;

Step 43, construct a forest F with m binary trees according to the delay of m AND items;

Step 44, repeat the following operations until there is only one binary tree (i.e. Huffman tree) in the forest F: select the two trees l and r with the smallest root node delay from the forest F; create a tree with l as the left subtree And take r as the new tree of the right subtree, wherein, the delay of the root node of the new tree is equal to the larger of the delays of the two subtrees plus 1; delete the selected two trees l and r from the forest F; The newly created tree joins the forest F;

Step 45, setting the delay of the simplest RM expression as the delay of the root node of the Huffman tree. An embodiment of an RM logic circuit delay optimization method under a unit delay model of the present invention is listed below. Boolean logic function with a 5 input variable

For example, in order to obtain the FPRM logic circuit with the minimum delay, the second parameter X ₁ represents the first input variable, X ₂ represents the second input variable, X ₃ represents the third input variable, X ₄ represents the fourth input variable, X ₅ represents the fifth input variable. An RM logic circuit delay optimization method under a unit delay model of this embodiment includes:

Step 1, read in the 5-variable Boolean logic function f(x ₅ ,x ₄ ,x ₃ ,x ₂ ,x ₁ );

Step 2, use the irrelevant item simplification method to obtain the simplest FPRM (fixed polarity RM) logic expression with the least number of AND items

Step 3, based on the Huffman tree construction algorithm, decompose the delay of each AND term in the simplest FPRM logic expression, so that the delay of each AND term is the smallest. with the item For example, for the sake of simplicity, assume that the delays of the input signals x ₅ , x ₄ , x ₃ , x ₂ , and x ₁ are all zero, and the delay decomposition process is shown in Figure 2, and the circuit form after decomposition is shown in Figure 3 Shown:

Step 31, calculating the number of input variables n contained in the AND item, i.e. n=5;

Step 32, first create 5 leaf nodes for 5 input variables, secondly construct a forest F with 5 binary trees according to the delay of 5 input variables, and finally repeat the following operations until there is only one binary tree in the forest F (ie Huffman tree): Select two trees l and r with the smallest root node delay from the forest F; create a new tree with l as the left subtree and r as the right subtree, where the new tree root node The delay is equal to the greater of the delays of the two subtrees plus 1; delete the selected two trees l and r from the forest F; add the newly created tree to the forest F. Finally, set the delay of the AND item to the delay of the root node of the Huffman tree, which is 3.

Step 4: Based on the Huffman tree construction algorithm, the delay decomposition of the simplest FPRM logic expression composed of all AND items is carried out, so that the delay of the simplest FPRM logic expression is the smallest. The delay decomposition process is shown in Figure 4:

Step 41, calculate the number of AND terms m contained in the simplest FPRM expression, i.e. m=3;

Step 42, create 3 leaf nodes for 3 AND items;

Step 43, construct a forest F with 3 binary trees according to the delay of 3 AND items;

Step 44, repeat the following operations until there is only one binary tree (i.e. Huffman tree) in the forest F: select two trees l and r with the smallest root node delay from the forest F; create a tree with l as the left subtree And take r as the new tree of the right subtree, wherein, the delay of the root node of the new tree is equal to the larger of the delays of the two subtrees plus 1; delete the selected two trees l and r from the forest F; The newly created tree joins the forest F.

Step 45, set the delay of the simplest RM expression as the delay of the root node of the Huffman tree, which is 4.

Step 5, output the minimum delay of the simplest FPRM logic expression.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (6)

1. RM logic circuit delay optimization method under a unit delay model, it is characterized in that: the method concrete steps comprise: Step 1, read in Boolean logic circuit; Step 2, using the RM expression simplification method to obtain the simplest RM logic expression with the least number of AND items; Step 3, based on the Huffman Huffman tree construction algorithm, decompose the delay of each AND item in the simplest RM logic expression, so that the delay of each AND item is the smallest; Step 4, based on the Huffman tree construction algorithm, perform delay decomposition on the simplest RM logic expression composed of all AND items, so that the delay of the simplest RM logic expression is the smallest; Step 5, output the minimum delay of the simplest RM logic expression; Among them, RM means Reed-Muller. 2. The delay optimization method for RM logic circuits under a unit delay model according to claim 1, characterized in that: the simplification method in step 2 is an algebraic simplification method or an irrelevant item simplification method. 3. RM logic circuit delay optimization method under a kind of unit delay model according to claim 1, is characterized in that: step 3 comprises: Step 31, calculating the number n of input variables contained in the AND item; Step 32, if the number of input variables n is equal to 1, set the delay of the AND item as the delay of the input variable; if the number of input variables n is greater than 1, first create n leaf nodes for n input variables, Secondly, according to d ₁ ,d ₂ ,...,d _i ,...,d _n construct a forest F={T ₁ ,T ₂ ,...,T _i ,...T _n } with n binary trees , 1≤i≤n, where each binary tree T _i has only one node with a delay of d _i , and finally repeat the following operations until there is only one binary tree in the forest F: select the root node delay from the forest F The smallest two trees l and r; create a new tree with l as the left subtree and r as the right subtree, 1≤i≤n, d _i represents the delay of the i-th input variable, d _n represents Delay for the nth input variable. 4. the RM logic circuit delay optimization method under a kind of unit delay model according to claim 1, is characterized in that: step 4 comprises: Step 41, calculating the number m of AND terms contained in the simplest RM expression; Step 42, create m leaf nodes for m AND items; Step 43, construct a forest F with m binary trees according to the delay of m AND items; Step 44, repeat the following operations until there is only one binary tree in the forest F, select two trees l and r with the smallest root node delay from the forest F; create a tree with l as the left subtree and r as the right the new tree of the subtree; Step 45, setting the delay of the simplest RM expression as the delay of the root node of the Huffman tree. 5. RM logic circuit time delay optimization method under a kind of unit time delay model according to claim 3, is characterized in that: the time delay of new tree root node is equal to bigger plus 1 in the time delay of two subtrees; From Delete the two selected trees l and r in the forest F; add the new tree created to the forest F; finally set the delay of the AND item to the delay of the root node of the Huffman tree. 6. RM logic circuit time-delay optimization method under a kind of unit time-delay model according to claim 4, is characterized in that: the time delay of new tree root node is equal to bigger plus 1 in the time delay of two subtrees; From Delete the two selected trees l and r in forest F; add the newly created tree to forest F.