CN106027032A - RM logic circuit delay optimization method in unit delay model - Google Patents
RM logic circuit delay optimization method in unit delay model Download PDFInfo
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- CN106027032A CN106027032A CN201610341295.8A CN201610341295A CN106027032A CN 106027032 A CN106027032 A CN 106027032A CN 201610341295 A CN201610341295 A CN 201610341295A CN 106027032 A CN106027032 A CN 106027032A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention provides an RM logic circuit delay optimization method in a unit delay model. The method is characterized by specifically comprising the following steps: step 1, reading a Boolean logic circuit; step 2, acquiring the simplest RM logic expression containing the least terms by using an RM expression simplification method; step 3, performing delay decomposition on each term in the simplest RM logic expression based on the Huffman tree construction algorithm so as to enable the delay of each term to be minimum; step 4, performing delay decomposition on the simplest RM logic expression composed of the all terms based on the Huffman tree construction algorithm, so as to enable the delay of the simplest RM logic expression to be minimum; and step 5, outputting the minimum delay of the simplest RM logic expression. Through adoption of the delay optimization method provided by the invention, the Boolean logic circuit can be quickly and effectively converted to the RM logic circuit with the minimum delay, so that the circuit delay is reduced, a working speed of the circuit is accelerated, and the performance of the circuit is improved.
Description
[technical field]
The present invention relates to Reed Muller Reed-Muller (RM) logic circuit optimization method, particularly relate to a kind of unit and prolong
Time model under Reed-Muller logic circuit delay Optimization method.Belong to logic circuit synthesis optimisation technique field.
[background technology]
Digital circuit both can by Boolean (boolean) logic realization based on AND/OR/NOT (and/or/non-) computing,
Can also by based on AND/XOR (with/XOR) or OR/XNOR (or/with or) Reed-Muller (RM) logic realization of computing.
For the circuit such as XOR arithmetical circuit the most frequently, parity checker and telecommunication circuit, with Boolean logic
Way of realization is compared, and RM logic realization form has bigger advantage at aspects such as power consumption, area and speed.Additionally, XOR gate
The change of a certain input can directly cause its change exported, so RM logic circuit also has preferable testability.RM patrols
These characteristics collected have caused the extensive concern of people, and have become the study hotspot in Logic Circuit Design field.
Along with the fast development of integrated circuit, the quantity of transistor integrated on one single chip and the layer of metal interconnecting wires
Number is all constantly increasing, and these factors cause circuit delay constantly increasing.Therefore, time delay has become as IC design
One important optimization target.For operating rate is required higher high speed super large-scale integration, time delay is excellent
Change the important component part the most having become high speed VLSI designs.During additionally, due to combinational circuit time delay determines
The lower bound in sequence circuit cycles cycle, therefore, the delay Optimization of combinational circuit is by the common concern of circuit designer.
But, the existing optimization method for RM logic circuit is concentrated mainly on optimised power consumption, area-optimized and power consumption
Optimization collaborative with area, and the research to RM logic circuit delay Optimization is the deficientest.Prolong additionally, existing for RM logic circuit
The research of Shi Youhua has bigger limitation and optimizes inefficient.Therefore, carry out RM logic circuit delay Optimization method to grind
Studying carefully is the important supplement to RM logic circuit optimization method system, significant to IC optimal design.At circuit
During logical design, generally ignore the time delay caused by the factor such as wire and electric capacity, and only consider elementary gate time delay.Owing to unit is prolonged
Time model be also widely used in the Delay Estima-tion of integrated circuit, therefore the present invention uses unit delay model to optimize RM logic circuit
Time delay.Under a kind of unit delay model that the present invention provides, RM logic circuit delay Optimization method can obtain and have minimum time delay
RM logic circuit, therefore the present invention can be used for the comprehensive delay Optimization of logic circuit.A kind of unit time delay mould that the present invention provides
Under type, RM logic circuit delay Optimization method is the important supplement to RM logic circuit optimization method system, be to currently with
Boolean logic is the important perfect of main IC logic level automatic optimizing design method.
[summary of the invention]
For solving the problems referred to above, the invention provides a kind of RM logic circuit delay Optimization method under unit delay model.
First this method carries out abbreviation to RM logical expression, obtains containing the simplest RM logical expression minimum with item number；It is then based on
Huffman (Huffman) tree construction algorithm carries out time delay decomposition to each in the simplest RM logical expression with item so that Mei Geyu
The time delay of item is minimum；It is finally based on Huffman tree construction algorithm and the simplest RM logical expression is carried out time delay decomposition so that be the simplest
The time delay of RM logical expression is minimum.
Specifically, the invention provides a kind of RM logic circuit delay Optimization method under unit delay model, the method
Concrete steps include:
Step 1, reads in Boolean logic circuit；
Step 2, utilizes RM expression formula simplifying method (such as algebraical simplification, outlier abbreviation method etc.) to obtain containing with item number
The simplest few RM logical expression；
Step 3, carries out time delay based on Huffman tree construction algorithm to each and item in the simplest RM logical expression and divides
Solve so that each minimum with the time delay of item；
Step 4, carries out time delay based on Huffman tree construction algorithm to by all the simplest RM logical expressions formed with item
Decompose so that the time delay of the simplest RM logical expression is minimum；
Step 5, exports the minimum time delay of the simplest RM logical expression.
Wherein, step 3 includes:
Step 31, the input variable number n calculating and containing in item；
Step 32, if input variable number n is equal to 1, is then set to the time delay of this input variable by this time delay with item；If it is defeated
Enter variable number n and be more than 1, be first that n input variable creates n leafy node, secondly according to d1,d2,...,di,...,dn
(1≤i≤n,diRepresent the time delay of i-th input variable, dnRepresent the time delay of the n-th input variable) build there is n binary tree
Forest F={T1,T2,...,Ti,...Tn, 1≤i≤n, wherein every binary tree TiOnly having a time delay is diNode,
Finally repeat following operation until forest F only has a binary tree (i.e. Huffman tree): from forest F, select root
Two tree l and r that node time delay is minimum；Create one using l as left subtree and withrAs the new tree of right subtree, wherein, newly set
What the time delay of root node was bigger equal in two subtree time delays adds 1；Selected two tree l and r are deleted from forest F；To create
New tree add forest F.Finally this time delay with item is set to the time delay of Huffman tree root node.
Wherein, step 4 includes:
Step 41, calculate the simplest RM expression formula contains with item number m；
Step 42, creates m leafy node for m with item；
Step 43, according to the time delay of m with item, builds the forest F with m binary tree；
Step 44, repeats following operation until only having a binary tree (i.e. Huffman tree) in forest F: from gloomy
Woods F selects two tree l and r that root node time delay is minimum；Create one using l as left subtree new using r as right subtree
Tree, wherein, what the time delay of new tree root node was bigger equal in two subtree time delays adds 1；Selected two trees are deleted from forest F
L and r；Newly created tree is added forest F；
Step 45, is set to the time delay of Huffman tree root node by the time delay of this simplest RM expression formula.
RM logic circuit delay Optimization method under a kind of unit delay model that the present invention provides, by RM logical expression
Formula carries out abbreviation makes it minimum with item number, can be that follow-up acquisition has the RM logic circuit of minimum time delay and lays the foundation；Fully profit
The advantage that can quickly obtain cum rights path minimum binary tree with Huffman tree construction algorithm, respectively to the simplest RM logical table
Reach each and item in formula and the simplest RM logical expression carries out time delay decomposition, each and item and the simplest RM logical expression can be made
Time delay minimum.RM logic circuit delay Optimization method under a kind of unit delay model that the present invention provides, can be fast and effeciently
Boolean logic is converted to the RM logic circuit with minimum time delay, and then reduces circuit delay, the work of raising circuit
Speed and performance.
[accompanying drawing explanation]
Fig. 1 be the present invention a kind of unit delay model under the flow chart of RM logic circuit delay Optimization method.
Fig. 2 be the present invention a kind of unit delay model under RM logic circuit delay Optimization method one embodiment and Xiang Yan
Time catabolic process figure, wherein, the time delay of the binary tree with this node as root node of the digitized representation on node.
Fig. 2 a be the embodiment of the present invention be that 5 input variables create 5 leafy nodes.
Fig. 2 b is the embodiment of the present invention establishment one the new tree that tree is left and right subtree with two root node time delay minimums.
Fig. 2 c is the embodiment of the present invention establishment one the new tree that tree is left and right subtree with two root node time delay minimums.
Fig. 2 d is the embodiment of the present invention establishment one the new tree that tree is left and right subtree with two root node time delay minimums.
Fig. 2 e is that the embodiment of the present invention forms a Huffman tree.
Fig. 3 be under the present invention a kind of unit delay model RM logic circuit delay Optimization method one embodiment with item time delay
Circuit form figure after decomposition.
Fig. 4 is the simplest FPRM of RM logic circuit delay Optimization method one embodiment under the present invention a kind of unit delay model
The time delay catabolic process figure of logical expression.
[detailed description of the invention]
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Fig. 1 be the present invention a kind of unit delay model under the flow chart of RM logic circuit delay Optimization method.Such as Fig. 1 institute
Showing, the method includes:
Step 1, reads in Boolean logic circuit；
Step 2, utilizes RM expression formula simplifying method (such as algebraical simplification, outlier abbreviation method etc.) to obtain containing with item number
The simplest few RM logical expression；
Step 3, carries out time delay based on Huffman tree construction algorithm to each and item in the simplest RM logical expression and divides
Solve so that each minimum with the time delay of item；
Step 4, prolongs by all the simplest RM logical expressions formed with item based on Huffman tree construction algorithm
Time decompose so that the time delay of the simplest RM logical expression is minimum；
Step 5, exports the minimum time delay of the simplest RM logical expression.
Wherein, step 3 includes:
Step 31, the input variable number n calculating and containing in item；
Step 32, if input variable number n is equal to 1, is then set to the time delay of this input variable by this time delay with item；If it is defeated
Enter variable number n and be more than 1, be first that n input variable creates n leafy node, secondly according to d1,d2,...,di,...,dn
(1≤i≤n,diRepresent the time delay of i-th input variable) build the forest F={T with n binary tree1,T2,...,Ti,
...Tn, 1≤i≤n, wherein every binary tree TiOnly having a time delay is diNode, finally repeat following operation straight
Only there is in forest F a binary tree (i.e. Huffman tree): select from forest F minimum two the tree l of root node time delay and
r；Create one using l as left subtree and using r as the new tree of right subtree, wherein, the time delay of new tree root node is equal to two subtrees
Bigger in time delay add 1；Selected two tree l and r are deleted from forest F；The new tree created is added forest F.Finally will
It is somebody's turn to do the time delay with item and is set to the time delay of Huffman tree root node.
Wherein, step 4 includes:
Step 41, calculate the simplest RM expression formula contains with item number m；
Step 42, creates m leafy node for m with item；
Step 43, according to the time delay of m with item, builds the forest F with m binary tree；
Step 44, repeats following operation until only having a binary tree (i.e. Huffman tree) in forest F: from gloomy
Woods F selects two tree l and r that root node time delay is minimum；Create one using l as left subtree new using r as right subtree
Tree, wherein, what the time delay of new tree root node was bigger equal in two subtree time delays adds 1；Selected two trees are deleted from forest F
L and r；Newly created tree is added forest F；
Step 45, is set to the time delay of Huffman tree root node by the time delay of this simplest RM expression formula.It is exemplified below this
RM logic circuit delay Optimization method one embodiment under bright a kind of unit delay model.Patrol with the boolean of 5 input variables
Collect function
As a example by, for obtaining the FPRM with minimum time delay
Logic circuit, the second parameter X1Represent first input variable, X2Represent second input variable, X3Represent the 3rd input to become
Amount, X4Represent the 4th input variable, X5Represent the 5th input variable.Under a kind of unit delay model of this embodiment, RM patrols
Collect circuit delay optimization method to include:
Step 1, reads in 5 variable boolean logic function f (x5,x4,x3,x2,x1)；
Step 2, utilizes outlier abbreviation method to obtain containing the simplest FPRM (fixed polarity RM) logical expression minimum with item number
Formula
Step 3, carries out time delay based on Huffman tree construction algorithm to each and item in the simplest FPRM logical expression and divides
Solve so that each minimum with the time delay of item.With with itemAs a example by, for simplicity, it is assumed that input signal x5,x4,x3,
x2,x1Time delay be all zero, its time delay catabolic process as in figure 2 it is shown, the circuit form after Fen Xieing as shown in Figure 3:
Step 31, the input variable number n, i.e. n=5 calculating and containing in item；
Step 32, is first that 5 input variables create 5 leafy nodes, secondly builds according to the time delay of 5 input variables
There is the forest F of 5 binary trees, finally repeat following operation until forest F only has a binary tree (i.e.
Huffman tree): from forest F, select two tree l and r that root node time delay is minimum；Create one using l as left subtree and with r
As the new tree of right subtree, wherein, what the time delay of new tree root node was bigger equal in two subtree time delays adds 1；Delete from forest F
Selected two tree l and r；Newly created tree is added forest F.Finally this time delay with item is set to Huffman tree root
The time delay of node, is 3.
Step 4, prolongs by all the simplest FPRM logical expressions formed with item based on Huffman tree construction algorithm
Time decompose so that the time delay of the simplest FPRM logical expression is minimum, its time delay catabolic process as shown in Figure 4:
Step 41, calculate the simplest FPRM expression formula contains with item number m, i.e. m=3；
Step 42, is 3 and creates 3 leafy nodes with item；
Step 43, according to the time delay of 3 with item, builds the forest F with 3 binary trees；
Step 44, repeats following operation until only having a binary tree (i.e. Huffman tree) in forest F: from gloomy
Woods F selects two tree l and r that root node time delay is minimum；Create one using l as left subtree new using r as right subtree
Tree, wherein, what the time delay of new tree root node was bigger equal in two subtree time delays adds 1；Selected two trees are deleted from forest F
L and r；Newly created tree is added forest F.
Step 45, is set to the time delay of this simplest RM expression formula the time delay of Huffman tree root node, is 4.
Step 5, exports the minimum time delay of the simplest FPRM logical expression.
Certainly, the present invention also can have other various embodiments, in the case of without departing substantially from present invention spirit and essence thereof, ripe
Know those skilled in the art to work as and can make various corresponding change and deformation according to the present invention, but these change accordingly and become
Shape all should belong to the protection domain of appended claims of the invention.
Claims (6)
1. RM logic circuit delay Optimization method under a unit delay model, it is characterised in that: the method concrete steps include:
Step 1, reads in boolean's Boolean logic circuit；
Step 2, utilizes RM expression formula simplifying method to obtain containing the simplest RM logical expression minimum with item number；
Step 3, carries out time delay based on Huffman Huffman tree construction algorithm to each and item in the simplest RM logical expression and divides
Solve so that each minimum with the time delay of item；
Step 4, divides being carried out time delay by all the simplest RM logical expressions formed with item based on Huffman tree construction algorithm
Solve so that the time delay of the simplest RM logical expression is minimum；
Step 5, exports the minimum time delay of the simplest RM logical expression；
Wherein, RM implication is Reed Muller Reed-Muller.
RM logic circuit delay Optimization method under a kind of unit delay model the most according to claim 1, it is characterised in that:
Simplifying method in step 2 is algebraical simplification or outlier abbreviation method.
RM logic circuit delay Optimization method under a kind of unit delay model the most according to claim 1, it is characterised in that:
Step 3 includes:
Step 31, the input variable number n calculating and containing in item；
Step 32, if input variable number n is equal to 1, is then set to the time delay of this input variable by this time delay with item；If input becomes
Amount number n, more than 1, is first that n input variable creates n leafy node, secondly according to d1,d2,...,di,...,dnBuild
There is the forest F={T of n binary tree1,T2,...,Ti,...Tn, 1≤i≤n, wherein every binary tree TiOnly there is one prolong
Time be diNode, finally repeat following operation until forest F only has a binary tree: from forest F, select root
Two tree l and r that node time delay is minimum；Create one using l as left subtree and using r as the new tree of right subtree, 1≤i≤n,
diRepresent the time delay of i-th input variable, dnRepresent the time delay of the n-th input variable.
RM logic circuit delay Optimization method under a kind of unit delay model the most according to claim 1, it is characterised in that:
Step 4 includes:
Step 41, calculate the simplest RM expression formula contains with item number m；
Step 42, creates m leafy node for m with item；
Step 43, according to the time delay of m with item, builds the forest F with m binary tree；
Step 44, repeats following operation until only having a binary tree in forest F, selects root node to prolong from forest F
Time minimum two tree l and r；Create one using l as left subtree and using r as the new tree of right subtree；
Step 45, is set to the time delay of Huffman tree root node by the time delay of this simplest RM expression formula.
RM logic circuit delay Optimization method under a kind of unit delay model the most according to claim 3, it is characterised in that:
What the time delay of new tree root node was bigger equal in two subtree time delays adds 1；Selected two tree l and r are deleted from forest F；Will
The new tree created adds forest F；Finally this time delay with item is set to the time delay of Huffman tree root node.
RM logic circuit delay Optimization method under a kind of unit delay model the most according to claim 4, it is characterised in that:
What the time delay of new tree root node was bigger equal in two subtree time delays adds 1；Selected two tree l and r are deleted from forest F；Will
Newly created tree adds forest F.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107194023A (en) * | 2017-03-30 | 2017-09-22 | 宁波大学 | A kind of FPRM circuit areas and delay Optimization method |
| CN109710973A (en) * | 2018-11-22 | 2019-05-03 | 温州大学 | A kind of optimization method of three values fixed polarity RM circuit area, power consumption and delay |
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| CN107194023A (en) * | 2017-03-30 | 2017-09-22 | 宁波大学 | A kind of FPRM circuit areas and delay Optimization method |
| CN107194023B (en) * | 2017-03-30 | 2019-07-12 | 宁波大学 | A kind of FPRM circuit area and delay Optimization method |
| CN109710973A (en) * | 2018-11-22 | 2019-05-03 | 温州大学 | A kind of optimization method of three values fixed polarity RM circuit area, power consumption and delay |
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