JP2006252717A - Method of constituting superconducting random access memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve ultra-high speed and ultra-low power consumption in the constitution of a large scale RAM. <P>SOLUTION: In the constitution of the superconducting RAM, each of driving lines such as word lines and bit lines and each of sense lines which access a memory cell array are divided into a plurality of blocks. For signal propagation in the block, an in-block signal propagating circuit (DR)3 is used which has a driver circuit and a sense circuit each having a level logic with high load driving capability. Moreover, for the signal propagation between long distance blocks, a superconducting passive transmission line (PTL)2 is used which is constituted of single magnetic flux quantum (SFQ) elements that can conduct high speed operations. As a result, high speed operations are made possible as a whole. Splitters (S) or confluence buffers (C) and latch circuits (DL) can be added to the superconducting RAM. Moreover, a binary tree constitution can be adopted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a configuration of a random access memory (hereinafter abbreviated as RAM) used in an integrated circuit that operates at a cryogenic temperature and has superconductivity, and a configuration method thereof.

  The superconducting RAM is composed of a decoder circuit, a driver circuit, a sense circuit, and a memory cell array, like the semiconductor RAM. The memory cell array has memory cells arranged in a two-dimensional matrix array. In RAM, information is written to a memory cell designated by an address signal by selecting a row and a column of a matrix array by two decoder circuits in the horizontal direction and the vertical direction, and the driver circuit receives the signal and the memory circuit This is done by propagating a data signal (information) to the cell array. Similarly, the data signal (information) held in the memory cell selected by the row and column signals of the matrix array corresponding to the address is read by the sense circuit.

  In the conventional superconducting RAM configuration, as the RAM scale (storage capacity) increases, the matrix array of memory cells also increases, and the number of memory cells driven by one driver circuit or sense circuit (one row or one column of memory). There is a problem that the number of cells) increases and the operation time increases.

  In order to solve this problem, for example, Japanese Patent Laid-Open No. 2000-260187 (Patent Document 1) proposes a method of dividing a RAM into small blocks.

  This proposal will be described with reference to FIGS.

  FIG. 14 shows an example of a block diagram of a superconducting RAM (random access memory) according to this prior art. FIG. 15 shows an example of the 256 RAM block 51.

  The superconducting RAM shown in FIG. 14 is an example of a 16 kbit RAM configuration formed by 64 256 RAM blocks 51. The illustrated superconducting RAM includes a 256RAM block 51, a block decoder circuit 52, a block sense circuit 53, a voltage-type logic driver circuit (AC current bias) 54 that propagates signals between the blocks, and the circuits described above. And an LC resonance circuit 56 for supplying a high-frequency alternating current (AC).

  One 256 RAM block 51 includes a 16 × 16 storage cell array, a voltage-type logic driver circuit 61 and a sense circuit 62 each composed of a superconducting latching element biased by an alternating current, and a super bias biased by a direct current. The decoder circuit 63 is composed of a conductive single flux quantum (SFQ) element.

  In this circuit, in order to enable 10 GHz clock operation, the size of the memory cell array driven by one voltage-type logic driver circuit 61 is limited to 256 bits of 16 rows and 16 columns. For this reason, a multi-driver method for transmitting signals in parallel to a large number of RAM blocks is adopted. One 256 RAM block 51 includes a 16 × 16 storage cell array, a voltage-type logic driver circuit 61 and a sense circuit 62 each composed of a superconducting latching element biased by an alternating current, and a super bias biased by a direct current. The decoder circuit 63 is composed of a conductive single flux quantum (SFQ) element. Thus, in this conventional superconducting random access memory, the size of the memory cell array driven by one driver circuit is limited by dividing it into small RAM blocks of 256 RAM blocks, thereby enabling high-speed operation. Further, the use of a voltage logic type driver circuit operating with an AC power supply and an impedance matching line for signal propagation between the blocks enables high-speed operation of the entire RAM.

JP 2000-260187 A

  With the increase in scale of random access memories, in a normal configuration, the number of elements of the decoder circuit, driver circuit, and sense circuit only increases in proportion to the square root of the capacity of the memory cell.

  However, the prior art superconducting random access memory has been divided into small blocks of a complete RAM structure including a decoder circuit, a driver circuit, a sense circuit and a memory cell array. For this reason, as the capacity of the random access memory is increased, the number of divisions increases in direct proportion, so that the number of decoder circuits, driver circuits, and sense circuits also increases in direct proportion. Therefore, there is a problem that the layout area and power consumption increase in direct proportion to the increase in memory capacity.

  Furthermore, since the conventional superconducting random access memory is composed of voltage logic type elements that operate with an AC power supply other than the decoder circuit, a high-frequency AC power supply is required, and therefore power consumption is further increased. There was a big problem of becoming.

  The object of the present invention is to eliminate such problems of the prior art, enable super-high-speed operation even in a large-scale random access memory configuration, and operate with a DC power source with low power consumption. It is to provide a configuration of an access memory.

  In order to achieve the above object, the superconducting RAM according to the present invention has the following features.

  First, the structure of the word lines or bit lines that drive the memory cell array is divided into a plurality of blocks. Each block of this word line or bit line has a high level of driving capability, a superconducting driver circuit used for signal propagation in the block directly driving the memory cell, and a single flux quantum (SFQ). And a superconducting passive transmission line (hereinafter abbreviated as PTL) arranged to propagate signals between a plurality of blocks, which can be used for high-speed signal propagation.

The signal propagation between the plurality of blocks may be a configuration in which superconducting PTLs are connected in series via a splitter (S) composed of single flux quantum (SFQ) elements. Alternatively, the signal propagation between a plurality of blocks may have a configuration in which a superconducting PTL is arranged in a binary tree structure via a splitter (S) configured by a single magnetic flux quantum (SFQ) element. ,
Alternatively, signal propagation between a plurality of blocks includes at least one latch circuit (DL) in the middle of the superconducting PTL, and information is held in the latch circuit (DL), thereby the plurality of blocks. It may be configured to enable high-speed operation by operating signal propagation between them in a pipeline of at least two stages.

  Second, the sense line for detecting information from the memory cell array is also divided into a plurality of blocks. Each block of this sense line has a high-level driving capability and has a superconducting driver circuit used for signal propagation in the block that directly drives the memory cell, and a single flux quantum (SFQ). And a superconducting PTL arranged for propagating signals between a plurality of blocks capable of signal propagation.

  The signal propagation between the plurality of blocks may be a configuration in which superconducting PTLs are connected in series via a confluence buffer (C) composed of a single flux quantum (SFQ) element. Alternatively, the signal propagation between a plurality of blocks may be a configuration in which superconducting PTLs are arranged in a binary tree structure via a confluence buffer composed of single flux quantum (SFQ) elements.

  Alternatively, for signal propagation between a plurality of blocks, at least one latch circuit (DL) is provided in the middle of the superconducting PTL, and information is held in the plurality of blocks by holding the latch circuit (DL). It may be configured to enable high-speed operation by operating signal propagation between them in a pipeline of at least two stages.

  Thirdly, the RAM according to the present invention is composed of a memory cell array composed of word lines, bit lines and sense lines according to the present invention, and a decoder circuit composed of single flux quantum (SFQ) elements. Also good.

  In the configuration of the random access memory having superconductivity according to the present invention, each of the drive lines such as word lines and bit lines accessing the memory cell array and the sense lines are divided into a plurality of blocks. Therefore, the signal propagation within the block uses a driver circuit and a sense circuit having a high level of load driving capability, and a single flux quantum (high-speed operation is possible for signal propagation between long-distance blocks. Superconducting passive transmission line (PTL) composed of SFQ elements is used. As a result, there is an effect of enabling high-speed operation as a whole.

  This is because a superconductive passive transmission line (PTL) is composed of a strip or microstrip line having a desired characteristic impedance, and a driver circuit and a receiver circuit composed of SFQ elements. That is, the superconducting PTL is an ideal transmission line, and can transmit a signal with almost no attenuation at the speed of light corresponding to the dielectric constant of the insulating layer constituting the stripline.

  In addition, since these components are constituted by low power consumption SFQ circuits, there is an effect that they can be operated with a DC power supply and that power consumption can be greatly reduced. Furthermore, by pipelining the signal propagation between blocks, it is possible to achieve ultra-high-speed clock operation in any large-scale superconducting random access memory word line, bit line, and sense line configuration. is there.

  Furthermore, by forming a superconducting random access memory with the memory cell array composed of these word lines, bit lines and sense lines of the present invention and the decoder circuit composed of SFQ elements, it is possible to achieve ultra-high speed and ultra-low performance. There is an effect that a superconducting random access memory with large power consumption can be realized.

  A memory cell array composed of word lines, bit lines, and sense lines as described above is used for the purpose of forming a super-high-speed and ultra-low power consumption large-scale superconducting RAM that operates with a DC power supply as a whole. This is realized by configuring with a decoder circuit composed of magnetic flux quantum (SFQ) elements.

  The splitter, confluence buffer, and latch circuit composed of the single flux quantum (SFQ) element described above are described in detail in, for example, the literature (IEEE Transaction on applied superconductivity, vol. 1, no. 1, p. 7, 1991). Are listed. As the splitter, the circuit shown in FIG. 4 of this document can be used, and as the confluence buffer, the circuit shown in FIG. 6 or the OR circuit shown in FIG. 10 as a similar function can be used. it can. As the latch circuit, an RS flip-flop circuit described in FIG. 7 of this document can be used.

  The passive transmission line (PTL) is described in detail in, for example, a document (Extended Abstracts of ISEC'01, 175-176.) Or Japanese Patent Application Laid-Open No. 2004-72141. For signal propagation in the block, a driver circuit and a sense circuit having a high level of load driving capability are used. For example, documents (IBM J. RES. DEVELOP. Vol. 24, no. 2, pp. 143-154, 1980), a driver circuit and a sense circuit which can be operated with a DC power source can also be used.

  Further, dividing the word line, bit line, or sense line into the signal propagation circuit in the block and the signal propagation circuit between the blocks as described above complicates the structure of these lines. However, high-speed operation is possible even when the memory cell array becomes large. Such a somewhat complicated line structure can be realized without increasing the layout area of the memory cell by adopting a niobium (Nb) multilayer wiring structure in terms of the device structure.

  As the scale of the RAM increases and the memory cell array increases, the number of memory cells driven by one driver circuit increases and the operation speed inevitably decreases. Therefore, in the present invention, high-speed operation is possible by limiting the number of memory cells driven by one driver circuit and sense circuit by division. Then, with respect to a plurality of divided driver circuits or sense circuits, a circuit composed of a single magnetic flux quantum (SFQ) element having the characteristics of ultra-high speed and ultra-low power consumption and superconducting PTL can achieve super-high speed. Signal propagation takes place. In the present invention, a word line, a bit line, and a sense line composed of such signal propagation between blocks and signal propagation within the block are configured to enable high-speed operation as a whole RAM.

  Further, when the scale of the RAM is further increased, the number of blocks to be divided is increased and the time required for signal propagation between the blocks is increased. However, a desired high-speed operation is ensured by inserting a latch circuit to increase the number of pipeline stages required for signal propagation between blocks. In other words, in order to obtain a desired clock frequency of the RAM, the memory cell array is divided into a plurality of blocks so that the operation time of one driver circuit or sense circuit is completed within the clock cycle, and a plurality of divided plurality of blocks are divided. Signal propagation between blocks is also pipelined. As a result, a desired high-speed clock operation is possible in any large-scale RAM configuration.

  On the other hand, in a large-scale superconducting RAM, such an increase in the number of divisions leads to a problem of increased power consumption. However, the inter-block signal propagation circuit according to the present invention is composed of a single flux quantum (SFQ) element such as a superconducting PTL, a splitter, a confluence buffer, and a latch circuit. Taking advantage of a certain feature of ultra-low power consumption, it is possible to operate with ultra-low power consumption even in a large-scale RAM configuration.

  A first embodiment of the present invention will be described with reference to FIG.

  FIG. 1 is an equivalent circuit diagram showing a first embodiment in the configuration of a superconducting RAM according to the present invention. The first embodiment relates to a configuration of a word line or a bit line included in a superconducting RAM.

  First, the configuration and function of this circuit will be described.

Each block of the word lines or bit lines according to the first embodiment includes an in-block signal propagation circuit (DR) 3 including a superconducting driver circuit, a superconducting passive transmission line (PTL) 2 that performs signal propagation between the blocks, and A single flux quantum (SFQ) that distributes a signal received from the preceding superconductive passive transmission line (PTL) 2 to the superconductive passive transmission line (PTL) 2 and the intra-block signal propagation circuit (DR) 3 in the block. ) And a splitter (S) 1 composed of elements. In FIG. 1, the case where the said component is arrange | positioned to each of four blocks is shown. The in-block signal propagation circuit (DR) 3 _X is composed of 32 memory cells connected in series and one driver circuit for driving the memory cells, and outputs a level signal according to the SFQ pulse signal input. Generated and has a function of directly driving 32 memory cells.

Next, the circuit operation of the first embodiment will be described. In Figure 1, if the single-flux-quantum (SFQ) pulse from the left end is input to the splitter (S) _{1 1,} SFQ pulse four splitters _(S) 1 1 to 1 ₄ and four superconducting passive transmission line (PTL) Signal propagation between blocks is performed at an extremely high speed from the left to the right through 2 _{1 to} 2 ₄ alternately. At the same time, the SFQ pulses output from the other output terminals of the splitters (S) 1 ₁ to 1 ₄ are propagated to the _four intra-block signal propagation circuits (DR) 3 _{1 to} 3 _4, respectively. The driver circuits in the signal propagation circuits (DR) 3 _{1 to} 3 ₄ can be switched to propagate signals directly to the memory cells.

Signal propagation between the blocks is performed at an extremely high speed (the speed of light corresponding to the dielectric constant) by the splitter (S) 1 _X composed of SFQ elements and the superconducting passive transmission line (PTL) 2 _X. The SFQ pulse signal can be transmitted to the two intra-block signal propagation circuits (DR) with a slight time difference.

  With the above operation, a word line or a bit line of a superconducting RAM capable of an ultra-high speed operation can be configured.

In the circuit according to the first embodiment, the in-block signal propagation circuit (DR) 3 _X is composed of 32 memory cells connected in series and one driver circuit for driving the memory cells. The number of memory cells connected in series can be set to an arbitrary value depending on a desired operating frequency.

  A second embodiment of the present invention will be described with reference to FIG.

  FIG. 2 is an equivalent circuit diagram showing a second embodiment for the configuration of the superconducting RAM according to the present invention. The second embodiment relates to the configuration of the word lines or bit lines included in the superconducting RAM.

  First, the configuration and function of this circuit will be described.

In the second embodiment, in-block signal propagation circuits (DR) 3 _{1 to} 3 ₄ including superconducting driver circuits, superconducting passive transmission lines (PTL) 2 ₁ to 2 ₄ that perform signal propagation between blocks, information Latch circuits (DL) 4 ₁ to ₄ 4 composed of single flux quantum (SFQ) elements having a function of holding the superconducting passive transmission lines (PTL) 2 ₁ to 2 ₄ and latch circuits (DL) ) composed of the ₄₁ to ₄ single flux quantum (splitter comprised of SFQ) device _(S) 1 1 to 1 ₄ for distributing the signal to. In the present embodiment, the case where four of each of the above components are arranged is described. The in-block signal propagation circuit (DR) 3 _X is composed of 32 memory cells connected in series and one driver circuit for driving the memory cells, and outputs a level signal according to the SFQ pulse signal input. This circuit has a function of generating and directly driving 32 memory cells.

The circuit of the second embodiment operates with a two-stage pipeline. In the first clock cycle (T1), when the single-flux-quantum (SFQ) pulses from the left end of FIG. 2 is input to the splitter (S) ₁ 1, 4 single splitter SFQ pulses deployed alternately in series ( _S) performs signal propagation between blocks ultrafast from left to right through the 1 1 to 1 ₄ and four passive transmission line _(PTL) 2 1 ~2 _4. At the same time, SFQ pulses output from the splitter _(S) 1 1 ~1 ₄ of the other output end, the four latch circuits _(DL) 4 1 to 4 ₄ are inputted to the respective information is retained. When the clock signal is input to the four latch circuits (DL) 4 ₁ to 4 ₄ in the next clock cycle (T2), the information held in the latch circuits (DL) 4 ₁ to 4 ₄ is stored in the block. The signals are propagated to the signal propagation circuits (DR) 3 _{1 to} 3 ₄ almost simultaneously, and the driver circuits in the in-block signal propagation circuits (DR) 3 _{1 to} 3 ₄ can be switched to directly propagate the signals to the memory cells. .

  With the above operation, it is possible to configure a superconducting RAM word line or bit line capable of ultra-high speed operation with a two-stage pipeline.

As described above, in the second embodiment, the SFQ pulse signals propagated through the signal propagation path between the blocks are once held in the four latch circuits (DL) 4 ₁ to 4 ₄ , and the next clock cycle. Can be transmitted to the _four intra-block signal propagation circuits (DR) 3 _{1 to} 3 ₄ almost simultaneously. Therefore, there is an effect that a clock operation can be performed at a higher speed than in the first embodiment.

  A third embodiment of the present invention will be described with reference to FIG.

  FIG. 3 is an equivalent circuit diagram showing a third embodiment for the configuration of the superconducting RAM of the present invention. The third embodiment relates to the configuration of the word lines or bit lines included in the superconducting RAM.

  First, the configuration and function of this circuit will be described.

The third embodiment, in the first embodiment, further splitter _{(S) 5} 1 ~ between each of the four splitters _(S) 1 1 to 1 ₄ and the block signal propagation circuit (DR) 5 ₄ insert a has a structure of connecting the splitter _(S) 5 1 to 5 ₄ of the output block signal propagation circuit of each one by two (DR). Thereby, eight intra-block signal propagation circuits (DR) 3 _{1 to} 3 ₈ can be driven, which is twice as compared with the first embodiment. Here, for example, the splitter (S) block signal propagation circuit _{(DR) 3} 1, 3 ₂ is connected to the _{5 1,} respectively to form the blocks 1 and 2. Similarly, up to block 8 is formed.

  The operation of the circuit of Example 3 is the same as that of the first embodiment, and the same effect as that of the first embodiment can be obtained. Further, in the third embodiment, the number of splitters involved in inter-block signal propagation is relatively smaller than the number of intra-block signal propagation circuits. Therefore, since signal propagation between blocks can be performed at higher speed, there is an effect that signal propagation between blocks can be performed in a wider range for the same clock cycle.

  A fourth embodiment of the present invention will be described with reference to FIG.

  FIG. 4 is an equivalent circuit diagram showing a fourth embodiment for the configuration of the superconducting RAM of the present invention. The fourth embodiment also relates to the configuration of word lines or bit lines included in the superconducting RAM.

  First, the configuration and function of this circuit will be described.

In the fourth embodiment, splitters (S) 5 ₁ to 4 are further provided between the four latch circuits (DL) 4 ₁ to 4 ₄ and the intra-block signal propagation circuit (DR) in the second embodiment. 5 ₄ insert a has a structure of connecting the splitter _(S) 5 1 to 5 ₄ of the output block signal propagation circuit of each one by two (DR). As a result, it is possible to drive _eight in-block signal propagation circuits (DR) 3 _{1 to} 3 ₈ that are twice as large as those in the second embodiment. Here, for example, the splitter (S) block signal propagation circuit _{(DR) 3} 1, 3 ₂ is connected to the _{5 1,} respectively to form the blocks 1 and 2. Similarly, up to block 8 is formed.

The circuit of the fourth embodiment operates in a two-stage pipeline as in the second embodiment. In the first stage of the clock period (T1), 4 pieces are single-flux-quantum (SFQ) pulses from the left end in FIG. 4 is input to the splitter (S) 1 _1, SFQ pulses deployed alternately in series Signal transmission between the blocks from left to right via the splitters (S) 1 ₁ to 1 ₄ and four passive transmission lines (PTL) 2 ₁ to 2 ₄ . At the same time, the splitter _(S) 1 1 ~1 ₄ SFQ pulse outputted from each of the other output end, the four latch circuits _(DL) 4 1 to 4 ₄ are inputted to the respective information is retained.

Unlike clock period (T2) in the second embodiment of the second stage, when the clock signal is input to the four latch circuits _(DL) 4 1 to 4 _4, the latch circuit _(DL) 4 1 to 4 ₄ is transmitted to the eight intra-block signal propagation circuits (DR) 3 _{1 to} 3 ₈ via the _four splitters (S) 5 _{1 to} 5 ₄ almost simultaneously, and the intra-block signal propagation circuit (DR) The driver circuits in 3 _{1 to} 3 ₈ can switch and propagate signals directly to the memory cells.

  That is, the circuit operation of the fourth embodiment is the same as that of the second embodiment, and the same effect as that of the second embodiment can be obtained. Furthermore, in the fourth embodiment, the number of splitters involved in inter-block signal propagation is relatively smaller than the number of intra-block signal propagation circuits. Therefore, since signal propagation between blocks can be performed at higher speed, there is an effect that signal propagation between blocks can be performed in a wider range for the same clock cycle.

  A fifth embodiment of the present invention will be described with reference to FIG.

  FIG. 5 is an equivalent circuit diagram showing a fifth embodiment for the configuration of the superconducting RAM of the present invention, in which four blocks 1 to 4 out of eight blocks are shown. The blocks 5 to 8 have the same configuration as that of the illustrated blocks 1 to 4. The fifth embodiment also relates to the configuration of the word lines or bit lines included in the superconducting RAM.

  First, the configuration and function of this circuit will be described.

  In the fifth embodiment, in the fourth embodiment, a signal propagation circuit between blocks constituted by a superconductive passive transmission line (PTL) and a splitter (S) is arranged in a binary tree. . In addition, a latch circuit (DL) is inserted at an appropriate position of a signal propagation circuit arranged between the blocks of the binary tree structure, so that the circuit operates in a three-stage pipeline.

  Next, the configuration and operation of the fifth embodiment including parts omitted in FIG. 5 will be described.

That is, in the first stage of the clock period (T1), the splitter (S) 11 ₁ is receiving a SFQ pulse input via the latch circuit (DL) 14, two superconducting passive transmission line (PTL) 12 ₁ , 12 ₂ .

In the second-stage clock cycle (T2), the latch circuit (DL) 24 ₁ receives the SFQ pulse received from the superconducting passive transmission line (PTL) 12 ₁ via the splitter (S) 21 _1. Conductive passive transmission lines (PTL) 22 ₁ and 22 ₂ are sent. In the second stage, the SFQ pulse output from the superconducting passive transmission line (PTL) 22 ₁ is further transmitted via the direct splitter (S) 31 ₁ into two superconducting passive transmission lines (PTL) 32 ₁ , 32 is sent to _2. A splitter (S) 21 ₂ and a superconductive passive transmission line (PTL) 22 ₃ , 22 ₄ , 32 _{3 to} 32 ₈ (not shown) are also provided with the same configuration.

  The third stage clock cycle (T3) is the same as the second stage of the fourth embodiment and has a double circuit configuration.

  The circuit operation of the fifth embodiment is the same as that of the fourth embodiment, and the same effect as that of the fourth embodiment can be obtained. Furthermore, in the fifth embodiment, since the inter-block signal propagation circuit is configured by a binary tree, the wiring is equal in length to all the intra-block signal propagation circuits. Therefore, the SFQ pulse input from the upper end of the inter-block signal propagation circuit can be propagated to all the intra-block signal propagation circuits at the same time. Therefore, there is also an effect that a high-speed pipeline operation is possible even in a word line or a bit line having a larger block configuration.

  In this embodiment, a three-stage pipeline is configured by inserting a latch circuit at an appropriate position of a signal propagation circuit that forms a block between binary tree structures. It can also be configured as described above. Alternatively, when the circuit size is small, a normal operation without pipelining can be performed without inserting a latch circuit.

  A sixth embodiment of the present invention will be described with reference to FIG.

  FIG. 6 is an equivalent circuit diagram showing a sixth embodiment for the configuration of the superconducting RAM according to the present invention. The sixth embodiment is a first example relating to the configuration of the sense lines in the superconducting RAM.

  First, the configuration and function of this circuit will be described.

The sixth embodiment includes an intra-block signal propagation circuit (DR) 6 ₁ (˜6 ₄ ), a passive transmission line (PTL) 2 ₁ (˜2 ₄ ) that performs signal propagation between blocks, and a superconducting passive transmission line. Single flux quanta that receive signals from (PTL) 2 ₁ (˜2 ₄ ) and in-block signal propagation circuit (DR) 6 ₁ (˜6 ₄ ) and propagate to the next block superconducting passive transmission line (PTL) (SFQ) Confluence buffer (C) 7 ₁ (˜7 ₄ ) composed of elements. In the sixth embodiment, a case where four of the above-described components are arranged is described. The in-block signal propagation circuit (DR) 6 _X is composed of 32 memory cells connected in series and a sense circuit for detecting information from the memory cells, and the information held in the selected memory cell The circuit has a function of outputting SFQ pulses in response to the above.

  Next, the circuit operation of the sixth embodiment will be described.

First, a memory cell specified by an address of the memory cell array is selected, and information from the memory cell is read out. In Example 6, a block in the signal propagation circuit (DR) of 6 ₂ sense circuit block 2 is selected, the case where SFQ pulses from the block signal propagation circuit (DR) 6 ₂ is output. The output SFQ pulse is input to the confluence buffer (C) _{7 2,} superconducting passive transmission line as a block between the signal propagation circuit (PTL) _{2 3,} confluence buffer (C) _{7 3,} superconducting passive transmission line ( PTL) 2 ₄ and confluence buffer (C) 7 ₄ can be propagated to the right end of the figure at high speed.

  Also in the sixth embodiment, even if an SFQ pulse is output from an arbitrary intra-block signal propagation circuit (DR) in the four intra-block signal propagation circuits (DR), a confluence buffer (C ) And a superconducting passive transmission line (PTL), the inter-block signal propagation circuit propagates the signal at an ultra-high speed (the speed of light corresponding to the dielectric constant). (Right end of the figure).

  With the above operation, a superconducting RAM sense line capable of ultra-high speed operation can be configured.

  A seventh embodiment of the present invention will be described with reference to FIG.

  FIG. 7 is an equivalent circuit diagram showing a seventh embodiment for the configuration of the superconducting RAM according to the present invention. The seventh embodiment is a second example relating to the configuration of the sense line in the superconducting random access memory.

  First, the configuration and function of the circuit according to the seventh embodiment will be described.

The seventh embodiment holds information in the intra-block signal propagation circuit (DR) 6 ₁ (˜6 ₄ ), the superconductive passive transmission line (PTL) 2 ₁ (˜2 ₄ ) that performs signal propagation between the blocks, and information. Latch circuit (DL) 4 ₁ (˜4 ₄ ) composed of a single flux quantum (SFQ) device having a function to perform, superconducting passive transmission line (PTL) 2 ₁ (˜2 ₄ ), and intra-block signal propagation A confluence buffer (C) 7 ₁ composed of a single flux quantum (SFQ) element that receives a signal from the circuit (DR) 6 ₁ (˜6 ₄ ) and propagates it to the superconductive passive transmission line (PTL) of the next block. (˜7 ₄ ).

In the seventh embodiment, a case where four of each of the above-described components are arranged is described. The in-block signal propagation circuit (DR) 6 _X is composed of 32 memory cells connected in series and a sense circuit for detecting information from the memory cells, and the information held in the selected memory cell The circuit has a function of outputting SFQ pulses in response to the above.

The circuit of the seventh embodiment operates with a two-stage pipeline. In the first clock cycle (T1), the memory cell specified by the address of the memory cell array is selected, and information is read from the memory cell. In Embodiment 7, a block in the signal propagation circuit (DR) 3 ₂ sense circuit block 2 is selected, the case where SFQ pulses from the block signal propagation circuit (DR) 3 ₂ is outputted. SFQ pulses output from the block in the signal propagation circuit (DR) _{3 2} is input to the latch circuit (DL) _{4 2} is retained. In the next second stage clock cycle (T2), when the clock signal is input to the four latch circuits (DL) 4 ₁ to 4 ₄ , the information held in the latch circuit (DL) 4 ₂ is changed. confluence buffer (C) _{7 2} is input to the superconducting passive transmission line is a signal propagation circuit between the blocks (PTL) _{2 3,} confluence buffer (C) _{7 3,} superconducting passive transmission line (PTL) _{2 4,} and confluence buffer (C) 7 ₄ sequentially through the propagate quickly in the right end of the figure, the information of the memory cell can be taken out at high speed.

  A sense line of a superconducting random access memory having the above-described operation and capable of an ultrahigh-speed operation with a two-stage pipeline can be configured.

  As described above, in the seventh embodiment, even if an SFQ pulse is output from an arbitrary intra-block signal propagation circuit (DR) among the four intra-block signal propagation circuits (DR), Since it is held in the latch circuit (DL), the SFQ pulse signal can be propagated from the beginning of the next clock cycle to the inter-block signal propagation circuit composed of the confluence buffer (C) and the superconductive passive transmission line (PTL). As compared with the sixth embodiment, there is an effect that a higher-speed clock operation is possible.

  An eighth embodiment of the present invention will be described with reference to FIG.

  FIG. 8 is an equivalent circuit diagram showing an eighth embodiment for the configuration of the superconducting RAM according to the present invention. The eighth embodiment is a third example relating to the configuration of the sense line in the superconducting random access memory.

  First, the configuration and function of the circuit according to the eighth embodiment will be described.

  In the eighth embodiment, a signal propagation circuit between blocks constituted by a passive transmission line (PTL) and a confluence buffer (C) in the seventh embodiment is arranged in a binary tree. In addition, a latch circuit (DL) is inserted at an appropriate position of the signal propagation circuit between the blocks of the binary tree structure, so that the circuit operates in a three-stage pipeline.

  Next, the configuration of the eighth embodiment will be described including parts omitted in FIG.

That is, in the first stage of the clock period (T1), the block in the signal propagation circuit _(DR) 16 1 ~16 ₄ is shown for the block 1-4, respectively, it is omitted for the block 5-16. SFQ pulse outputted from the two blocks in the signal propagation circuit _(DR) 16 1, 16 ₂ is output to the confluence buffer (C) 18 ₁ receives a latch circuit (DL) 14 _1.

In the second-stage clock cycle (T1), the latch circuit (DL) 14 ₁ outputs an SFQ pulse to the confluence buffer (C) 17 ₁ via the passive transmission line (PTL) 12 ₁ . The confluence buffer (C) 17 ₁ receives the SFQ pulse in the blocks 3 and 4 from the latch circuit (DL) 14 ₂ via the passive transmission line (PTL) 122 ₂ , and therefore corresponds to the four blocks 1 to 4. Yes. Similarly, confluence buffer (C) 17 ₂ receives an SFQ pulse corresponding to a block 5-8. The same applies to the circuits corresponding to blocks 9-16.

Further, in the second stage, the confluence buffer (C) that receives SFQ pulses from the confluence buffers (C) 17 ₁ and 17 ₂ corresponding to the blocks 5 to 8 via the passive transmission lines (PTL) 22 ₂ and 22 _2, respectively. There is 27 _one . The confluence buffer (C) 27 ₁ outputs the received SFQ pulse to the latch circuit (DL) 24 ₁ . Circuit is also similar corresponding to the block 9 to 16 to output to the latch circuit (DL) 24 _2.

In the third stage of the clock period (T3), confluence buffer (C) 37 ₁ is the SFQ pulse, latch circuit _(DL) 24 1, 24 ₂ from the passive transmission line _(PTL) 32 1, 32 ₂ via respective Received and output to the latch circuit (DL) 34.

  The operation of the circuit of Example 8 is the same as that of the seventh embodiment, and the same effect as that of the seventh embodiment can be obtained. Furthermore, in this embodiment, since the inter-block signal propagation circuit is composed of a binary tree, it is an equal length wiring for all the intra-block signal propagation circuits. Therefore, an SFQ pulse output from an in-block signal wiring circuit at an arbitrary position can be propagated at substantially the same time. Therefore, there is also an effect that a pipeline operation can be performed at high speed even with a sense line having a larger block configuration.

  In the eighth embodiment, a latch circuit (DL) is inserted at an appropriate position of the signal propagation circuit between the blocks of the binary tree structure to configure a three-stage pipeline. It can also be composed of stages or four or more stages. Alternatively, when the circuit size is small, it is possible to perform a normal operation without performing the pipeline without inserting the latch circuit (DL).

  A ninth embodiment of the present invention will be described with reference to FIGS. 9 and 10 together.

  FIG. 9 is a block diagram showing a ninth embodiment for the structure of the superconducting RAM 40 according to the present invention. In the ninth embodiment, the storage capacity of 16 kbits is obtained by the configuration of the word line or the bit line according to the second embodiment and the configuration of the sense line according to the seventh embodiment in the superconducting RAM. This is an embodiment in the case where a superconducting RAM 40 having the above is configured.

  First, the circuit configuration and function according to the ninth embodiment will be described.

  The superconducting RAM 40 according to the ninth embodiment includes 32 rows and 32 columns of 1 k-bit memory cell array blocks 41 arranged in 4 rows and 4 columns, a driver circuit 42 and a sense circuit 43 that perform signal propagation in the blocks, and between the blocks. A line circuit 44 including a splitter, a confluence buffer, and a latch circuit for propagating signals, and two decoder circuits 45 and 46 in the row (X) direction and the column (Y) direction, which are configured by SFQ elements. Has been.

  Although not clearly shown in FIG. 9, the passive transmission lines (PTL) in the row (X) direction and the column (Y) direction are connected via the line circuit 44 including the splitter, the confluence buffer, the latch circuit, and the like. Thus, a word line and a sense line in the (X) direction, and a bit line in the column (Y) direction are configured. All the components are set to operate with a DC power supply.

  Next, the operation of the ninth embodiment will be briefly described with reference to FIG. FIG. 10 shows the signal propagation path and pipeline configuration of the superconducting RAM of the ninth embodiment.

  In the first clock cycle (T1), an input signal (SFQ pulse) such as an address, data, read / write (R / W), etc. is input to the SFQ decoder circuits 45 and 46, and a row designated by the address signal. The designated positions in the (X) direction and the column (Y) direction are selected (step S1).

  In the second-stage clock cycle (T2), as the inter-block signal propagation, the SFQ pulse output from the decoder circuits 45 and 46 is propagated to the word line or bit line associated with the selected row and column, and is transmitted within the block. It is held in the latch circuit arranged immediately before the signal propagation circuit (DR) (step S2).

  In the next third stage clock cycle (T3), the driver circuit of the intra-block signal propagation circuit (DR) operates, and the signal propagation (step S3) of data writing and reading to the selected memory cell is performed. The operation of the memory cell for that (step S4) is performed. In the case of the read operation, at the same time, the sense circuit of the intra-block signal propagation circuit (DR) propagates the data read from the selected memory cell and sends the data to the latch circuit connected to the sense circuit. Hold (step S5).

  In the next fourth-stage clock cycle (T4), the data signal held in the latch circuit is output and propagated to the output end by the inter-block signal propagation of the sense line (step S6).

  As described above, in the ninth embodiment, a 16 kbit superconducting random access memory is configured by a four-stage pipeline.

  In the ninth embodiment, dividing the memory cell array increases the number of driver circuits and sense circuits related to signal propagation in the block, but the decoder circuit is not divided, so the number of elements in the decoder circuit does not increase. For this reason, the number of elements can be reduced and the layout area or power consumption can be reduced as compared with the case of dividing the decoder circuit including the conventional technique.

  In the ninth embodiment, the size of one divided block is formed in a 1k-bit memory cell array of 32 rows and 32 columns for the purpose of clock operation of 10 GHz. However, the size of the divided blocks can be arbitrarily set. it can. For example, if the size of one block is 16 rows and 16 columns, the number of circuits involved in intra-block signal propagation associated with the division increases, but higher speed operation near 20 GHz becomes possible. On the other hand, if the size of one block is 64 rows and 64 columns, the number of circuits related to intra-block signal propagation associated with the division decreases, but the clock frequency remains at about 5 GHz.

  As described above, according to the ninth embodiment, it is possible to realize a 16 kbit superconducting random access memory that can operate with a DC power source that is ultra-high speed and consumes very low power.

  A tenth embodiment of the present invention will be described with reference to FIG.

  FIG. 11 is a block diagram showing the tenth embodiment for the structure of the superconducting RAM according to the present invention. In the tenth embodiment, four 16 kbit superconducting RAMs 40A shown in the ninth embodiment are arranged, and a decoder circuit is arranged in the center in the horizontal direction and the vertical method, respectively. 16k blocks are used in common. Therefore, a superconducting RAM having a storage capacity of 64 kbit is configured.

  Since the tenth embodiment is exactly the same in terms of circuit operation as the configuration of four 16 kbit superconducting RAMs 40 arranged in parallel in the ninth embodiment, even if the circuit scale is quadrupled, the ninth embodiment It is possible to operate with the same four-stage pipeline and the same clock frequency as in the embodiment. Therefore, the same effects as those of the ninth embodiment can be obtained, and a 64 Kbit superconducting RAM having a storage capacity of 4 times can be configured. In addition, by arranging the decoder circuit in the center of the horizontal direction and the vertical method so that the 16k blocks adjacent to each other can be used in common, four superconducting RAMs of 16 kbit are simply arranged in parallel. In comparison, the number of decoder circuits can be reduced.

  Embodiment 11 of the present invention will be described with reference to FIG.

  FIG. 12 is a block diagram showing an eleventh embodiment for the structure of the superconducting RAM according to the present invention. In the eleventh embodiment, the configuration of the word line or bit line according to the fifth embodiment and the configuration of the sense line according to the eighth embodiment are super-capacity having a storage capacity of 256 kbits. This is an embodiment when a conductive RAM is configured.

  First, the circuit configuration and function of Example 11 will be described.

  In the eleventh embodiment, first, a 1k-bit memory cell array block 41 of 32 rows and 32 columns is arranged in 8 rows and 8 columns based on the ninth embodiment, and a driver circuit for signal propagation between the blocks is provided. A 64 Kbit superconducting RAM 40 </ b> B including a sense circuit, a splitter, a confluence buffer, a latch circuit, and two decoder circuits in the row direction and the column direction configured by SFQ elements is formed. Next, based on the tenth embodiment, four 64 kbit superconducting RAMs 40B are arranged, and the decoder circuit is arranged in the center in the horizontal direction and the vertical method, respectively, and is commonly used in adjacent 64k blocks. To do. As a result, a superconducting RAM having a storage capacity of 256 kbits can be configured.

  The circuit operation in the eleventh embodiment is the same as in the ninth and tenth embodiments, and the size of the divided minimum block is also a 1k bit memory cell array 41 of 32 rows and 32 columns. It is possible to operate at the same clock frequency of 10 GHz, and the same effect can be obtained. However, since the circuit scale increases and the number of divided blocks increases, it takes time to propagate signals between blocks. Therefore, as shown in the pipeline configuration of FIG. 13, a two-stage pipeline cycle is set for signal propagation between blocks. Accordingly, the pipeline of the entire 256 kbit superconducting random access memory has six stages.

  FIG. 13 shows a signal propagation path and pipeline configuration of the superconducting RAM in the eleventh embodiment.

  In the first clock cycle (T1), an input signal (SFQ pulse) such as address, data, read / write (R / W), etc. is input to the SFQ decoder circuit, and the row (X) specified by the address signal The designated position in the direction and the column (Y) direction is selected (step S11).

  In the second-stage clock cycle (T2), the SFQ pulse output from the decoder circuit is propagated to the first half of the word line or bit line associated with the selected row and column as inter-block signal propagation. It is held in a latch circuit arranged in the middle of the line (step S12).

  In the third-stage clock cycle (T3), as the inter-block signal propagation, the SFQ pulse held in the latch circuit is propagated to the second half of the word line or the bit line, and immediately before the intra-block signal propagation circuit (DR). It is held in the arranged latch circuit (step S13).

  In the next fourth-stage clock cycle (T4), the driver circuit of the intra-block signal propagation circuit (DR) operates, and the signal propagation (step S14) of data writing and reading to the selected memory cell is performed. The operation of the memory cell for that (step S15) is performed. In the case of the read operation, at the same time, the sense circuit of the intra-block signal propagation circuit (DR) propagates the data read from the selected memory cell and sends the data to the latch circuit connected to the sense circuit. Hold (step S16).

  In the next fifth-stage clock cycle (T5), the data signal held in the latch circuit is output as the inter-block signal propagation, propagated to the first half of the sense line, and placed in the middle of the sense line. It is held in the circuit (procedure S17).

  In the sixth clock cycle (T6), as a signal propagation between blocks, the data signal held in the latch circuit arranged in the middle of the sense line is output and propagated to the output terminal via the latter half of the sense line (Procedure S18) is performed.

  Thus, even when a large-scale superconducting RAM is configured by the configuration of the word lines, bit lines, and sense lines of the superconducting RAM according to the present invention, the size of the memory cell array of the smallest unit to be divided is made constant. In this case, for example, there is an effect that a large-scale superconducting RAM can be configured while maintaining an extremely high clock frequency of 10 GHz. In this case, since the time required for signal propagation between blocks becomes longer depending on the number of divided blocks, an ultrahigh-speed clock operation of 10 GHz is guaranteed by increasing the number of pipeline stages required for signal propagation between blocks. .

  A drive line or sense line such as a word line or a bit line for accessing the memory cell array is divided into a plurality of blocks, and each of the signal propagation in the block has a driver circuit and a sense circuit having a high level drive capability and a load logic. It has a configuration that uses an intra-block signal propagation circuit (DR), and further, a superconducting passive device composed of a single flux quantum (SFQ) device capable of high-speed operation for signal propagation between long-distance blocks. A transmission line (PTL) is used. Therefore, the configuration using the superconducting element as described above can be applied to any memory that requires and is essential for ultra-high speed and low power consumption even in a large-scale configuration.

FIG. 2 is an equivalent circuit diagram for explaining a configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration related to a word line or a bit line. Example 1 FIG. 2 is an equivalent circuit diagram for explaining a configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration related to a word line or a bit line. (Example 2) FIG. 2 is an equivalent circuit diagram for explaining a configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration related to a word line or a bit line. Example 3 FIG. 2 is an equivalent circuit diagram for explaining a configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration related to a word line or a bit line. Example 4 FIG. 2 is an equivalent circuit diagram for explaining a configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration related to a word line or a bit line. (Example 5) FIG. 2 is an equivalent circuit diagram for explaining one configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration relating to a sense line configuration method. (Example 6) FIG. 2 is an equivalent circuit diagram for explaining one configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration related to a sense line configuration method. (Example 7) FIG. 2 is an equivalent circuit diagram for explaining one configuration of a superconducting RAM according to the present invention, and more specifically, an explanatory diagram showing a configuration relating to a sense line configuration method. (Example 8) It is a block diagram for explaining a configuration of a superconducting RAM according to the present invention, and is an explanatory diagram showing a configuration of a superconducting RAM having a storage capacity of 16 kbits. Example 9 It is explanatory drawing which shows the outline of the signal propagation path | route for demonstrating the circuit operation | movement in the structure of the superconducting RAM shown by FIG. 9, and a pipeline structure. Example 9 It is a block diagram for explaining a configuration of a superconducting RAM according to the present invention, and is an explanatory diagram showing a configuration of a superconducting RAM having a storage capacity of 64 kbits. (Example 10) 1 is a block diagram for explaining a configuration of a superconducting RAM according to the present invention, and is an explanatory diagram showing a configuration of a superconducting RAM having a storage capacity of 256 kbits. FIG. (Example 11) FIG. 13 is an explanatory diagram showing an outline of a signal propagation path and a pipeline configuration for explaining a circuit operation in the configuration of the superconducting RAM shown in FIG. 12. (Example 11) It is explanatory drawing which shows an example of the block configuration for demonstrating the conventional superconducting RAM. It is explanatory drawing which shows an example of the memory cell array part in FIG.

Explanation of symbols

1, 5, 11, 21, 31, 35 Splitter (S)
2, 12, 22, 32 Superconducting passive transmission line (PTL)
3, 6, 16 Intra-block signal propagation circuit (DR)
4, 14, 24, 34 Latch circuit (DL)
7, 17, 18, 27, 37 Confluence buffer (C)
40, 40A, 40B Superconducting RAM
41 Memory cell array block 42 Driver circuit 43 Sense circuit 44 Line circuit 45, 45A, 46, 46A Decoder circuit

Claims (9)

  In a method of configuring a word line or a bit line for driving a memory cell array, the word line or bit line is divided into a plurality of blocks, and a signal having a high driving capability is used for signal propagation in the block for directly driving a memory cell. A logic superconducting driver circuit is used, and a superconducting passive transmission line (PTL) capable of high-speed signal propagation using a single magnetic flux quantum (SFQ) is used for signal propagation between a plurality of blocks. A method of configuring a word line or a bit line.   2. The word line or bit line configuration method according to claim 1, wherein the word line or bit line further includes a splitter in which the superconducting passive transmission line (PTL) is configured by a single flux quantum (SFQ) element. A word line or a bit line.   2. The word line or bit line configuration method according to claim 1, wherein the word line or bit line further includes a splitter in which the superconducting passive transmission line (PTL) is configured by a single flux quantum (SFQ) element. A word line or a bit line, which is arranged in a binary tree structure.   4. The word line or bit line configuration method according to claim 2, wherein the word line or bit line further includes at least one latch circuit in the middle of connection of the superconducting passive transmission line (PTL). Providing a high-speed operation by operating signal propagation between the plurality of blocks in at least a two-stage pipeline by holding information in the latch circuit. Configuration method.   In a method for forming a sense line for detecting information from a memory cell array, the sense line for detecting information from the memory cell array is divided into a plurality of blocks, and signal propagation in the block for directly detecting information from the memory cell Is a superconducting passive transmission line that uses a high-level superconducting sense circuit with high driving capability and uses a single magnetic flux quantum (SFQ) for signal propagation between the blocks. (PTL) is used to form a sense line.   6. The sense line configuration method according to claim 5, wherein the sense line further connects the superconducting passive transmission line (PTL) in series via a confluence buffer composed of a single flux quantum (SFQ) element. A method for configuring a sense line in a random access memory.   6. The sense line configuration method according to claim 5, wherein the sense line further includes a binary tree structure through a confluence buffer in which the superconducting passive transmission line (PTL) is configured by a single flux quantum (SFQ) element. A method of constructing a sense line, characterized by comprising:   8. The sense line configuration method according to claim 6, wherein the sense line further includes at least one latch circuit in the middle of connection of the superconducting passive transmission line (PTL). A sense line construction method characterized in that, by holding information, signal propagation between the plurality of blocks is operated in at least two pipelines to enable high-speed operation. In the method of configuring a random access memory, the memory cell array includes one of the word lines and bit lines according to one of claims 1 to 4 and one of claims 5 to 8. And a decoder circuit comprising a single magnetic flux quantum (SFQ) element.

Images