CN113095015A - SFQ time sequence circuit comprehensive calculation method, system and terminal - Google Patents
SFQ time sequence circuit comprehensive calculation method, system and terminal Download PDFInfo
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Abstract
The comprehensive calculation method, the comprehensive calculation system and the comprehensive calculation terminal of the SFQ sequential circuit respectively explain and compile the state machine description of the SFQ logic gate state machine to obtain the state transition set information of the state machine, decompose the state transition set information into one or more sub-state machines, map each sub-state machine with each unit gate in an SFQ logic unit library, and recombine each sub-state machine based on the mapping result of each sub-state machine to obtain the SFQ sequential logic circuit structure. The invention utilizes the advantages of the SFQ logic gate, directly finishes the logic mapping from the SFQ logic gate state machine to the SFQ sequential circuit, reduces two steps of operation of simulating the CMOS logic gate in the middle and forming the CMOS sequential state machine, improves the logic comprehensive success rate of the SFQ sequential circuit and the utilization rate of the SFQ unit library, enables the large-scale automatic design of the SFQ sequential circuit to be more efficient, and solves the problems in the prior art.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a comprehensive calculation method, a comprehensive calculation system and a comprehensive calculation terminal for an SFQ sequential circuit.
Background
Superconducting integrated circuits are integrated circuits based on josephson junctions and superconducting materials, including Single-Flux-QuanTum (SFQ) circuits and the like. The SFQ circuit is a relatively special superconducting integrated circuit, which is mainly composed of josephson junctions, and digital logic "0" and "1" are represented by the presence or absence of a magnetic flux quantum Φ 0. Compared with a traditional semiconductor CMOS (complementary Metal Oxide semiconductor) circuit, the micro and quantitative properties of the flux quanta obviously reduce the influence of crosstalk and power consumption, and narrow voltage pulses generated in the junctions when the flux quanta enter and exit the loop enable the flux quanta to obtain extremely high frequency. The circuit has the advantages of ultrahigh working speed and extremely low power consumption, so that the circuit has a remarkable prospect in the application of ultra-wide bandwidth Analog-to-Digital converters (ADC), superconducting computers and the like.
Since the SFQ logic determines "0" and "1" by the presence or absence of a magnetic flux quantum, it is necessary to add a clock terminal to a basic cell gate, nor gate, or the like for timing. For SFQ and nor and other logic gates, the behavior of CMOS logic gates is generally simulated in the form of a state transition diagram, so that a CMOS logic synthesis algorithm can be directly applied to realize rapid automatic design of combinational logic. However, in the synthesis of the sequential logic, if the SFQ sequential logic is synthesized by adopting the traditional CMOS digital circuit synthesis algorithm, an algorithm flow of an SFQ logic gate state machine → behavior of an analog CMOS logic gate → formation of a CMOS sequential state machine → replacement with the SFQ sequential state machine is formed, wherein two links of the analog CMOS logic gate and the formation of the CMOS sequential state machine are redundant operations in the SFQ sequential circuit synthesis, and the problems that the SFQ cell library cannot be maximally utilized, the SFQ cells cannot be correctly matched to realize the design expected effect, and the like are found in the flow in practical application.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a comprehensive calculation method, system and terminal for SFQ sequential circuits, which are used to solve the problems of logic mismatch, unreasonable circuit overhead, low cell library utilization rate, etc. occurring when a traditional CMOS digital circuit comprehensive algorithm is used to synthesize SFQ sequential logic.
To achieve the above and other related objects, the present invention provides a comprehensive calculation method for an SFQ sequential circuit, including: respectively interpreting and compiling the state machine description of the SFQ logic gate state machine, and obtaining a compiling result; acquiring state transition set information corresponding to the SFQ logic gate state machine according to the compiling result; decomposing the state transition set information to obtain sub-state transition set information respectively corresponding to one or more sub-state machines; respectively mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library, and obtaining the mapping result corresponding to each sub-state machine; and recombining the sub-state machines based on the mapping result corresponding to each sub-state machine to obtain the SFQ sequential logic circuit structure.
In an embodiment of the present invention, the interpreting and compiling the state machine descriptions of the SFQ logic gate state machine respectively, and obtaining the compiling result includes: and respectively interpreting and compiling the state machine description of the SFQ logic gate state machine based on a preset customized algorithm of the SFQ logic, and obtaining a compiling result conforming to the SFQ logic.
In an embodiment of the present invention, the decomposing the state transition set information to obtain the sub-state transition set information respectively corresponding to one or more sub-state machines includes: and respectively carrying out one or more times of iterative decomposition on the state transition set information based on a decomposition rule related to the cell gate information of the SFQ logic cell library until one or more sub-state transition set information which can not be decomposed again is obtained.
In an embodiment of the present invention, the performing one or more iterative decompositions on the state transition set information respectively based on a decomposition rule related to a type of a unit gate in the SFQ logical unit library until one or more sub-state transition set information that cannot be decomposed again is obtained includes: grouping the states in the state transition set information to obtain one or more state groups with state continuity relation; based on the lowest state number obtained from the cell gate information of the SFQ logical cell library, each state in each state group is sequentially allocated to each sub-state machine, and one or more sub-state transition set information which can not be decomposed any more is obtained.
In an embodiment of the present invention, the mapping the sub-state transition set information of each sub-state machine based on the cell gate information of the SFQ logical cell library, and obtaining the mapping result corresponding to each sub-state machine includes: based on the unit gate information of the SFQ logic unit library, mapping the sub-state transition set information of each sub-state machine with each unit gate in the SFQ logic unit library respectively, and obtaining the mapping result corresponding to each sub-state machine; wherein the mapping result comprises: and the mapping result is successfully mapped corresponding to all the sub state machines and/or the mapping result is failed to be mapped corresponding to the sub state machines.
In an embodiment of the present invention, the reconstructing the sub-state machines based on the mapping result corresponding to each sub-state machine to obtain the SFQ sequential logic circuit structure includes: acquiring unit gates mapped by the state machines corresponding to the successful mapping results; and connecting the unit gates to obtain the SFQ sequential logic circuit structure.
In an embodiment of the present invention, the state transition set information includes: a state transition diagram and/or a state transition table.
In an embodiment of the present invention, the state machine description adopts Verilog language.
To achieve the above and other related objects, the present invention provides an SFQ sequential circuit synthesis calculation system, comprising: the compiling module is used for respectively interpreting and compiling the state machine description of the SFQ logic gate state machine and obtaining a compiling result; the state transition set information acquisition module is connected with the compiling module and is used for acquiring the state transition set information corresponding to the SFQ logic gate state machine according to the compiling result; the decomposition module is connected with the state transition set information acquisition module and is used for decomposing the state transition set information to acquire the sub-state transition set information respectively corresponding to one or more sub-state machines; the mapping module is connected with the decomposition module and used for mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library and obtaining the mapping result corresponding to each sub-state machine; and the recombination module is connected with the mapping module and used for recombining each sub-state machine based on the mapping result corresponding to each sub-state machine so as to obtain the SFQ sequential logic circuit structure.
To achieve the above and other related objects, the present invention provides an SFQ sequential circuit comprehensive computation terminal, comprising: a memory for storing a computer program; and the processor is used for executing the SFQ sequential circuit comprehensive calculation method.
As described above, the SFQ sequential circuit comprehensive calculation method, system and terminal of the present invention have the following advantages: the method respectively interprets and compiles the state machine description of the SFQ logic gate state machine to obtain the state transition set information of the state machine, decomposes the state transition set information into one or more sub-state machines, maps each sub-state machine and each unit gate in the SFQ logic unit library, and recombines each sub-state machine based on the mapping result of each sub-state machine to obtain the SFQ sequential logic circuit structure. The invention utilizes the advantages of the SFQ logic gate, directly finishes the logic mapping from the SFQ logic gate state machine to the SFQ time sequence circuit, reduces two steps of operation of simulating the CMOS logic gate in the middle and forming the CMOS time sequence state machine, improves the logic comprehensive success rate of the SFQ time sequence circuit and the utilization rate of the SFQ unit library, and leads the large-scale automatic design of the SFQ time sequence circuit to be more efficient.
Drawings
Fig. 1 is a schematic flow chart illustrating a comprehensive calculation method of an SFQ sequential circuit according to an embodiment of the present invention.
Fig. 2 is an exploded view of state transition set information according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of an SFQ sequential circuit comprehensive computation system according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating mapping of a sub-state machine according to an embodiment of the invention.
FIG. 5 is a diagram illustrating a reconfiguration of a sub-state machine according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of an integrated computation terminal of an SFQ sequential circuit according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It is noted that in the following description, reference is made to the accompanying drawings which illustrate several embodiments of the present invention. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "below," "lower," "over," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures.
Throughout the specification, when a part is referred to as being "connected" to another part, this includes not only a case of being "directly connected" but also a case of being "indirectly connected" with another element interposed therebetween. In addition, when a certain part is referred to as "including" a certain component, unless otherwise stated, other components are not excluded, but it means that other components may be included.
The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or sections, but are not limited thereto. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present invention.
Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," and/or "comprising," when used in this specification, specify the presence of stated features, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, operations, elements, components, items, species, and/or groups thereof. The terms "or" and/or "as used herein are to be construed as inclusive or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a; b; c; a and B; a and C; b and C; A. b and C ". An exception to this definition will occur only when a combination of elements, functions or operations are inherently mutually exclusive in some way.
The invention provides an SFQ sequential circuit comprehensive calculation method, which respectively interprets and compiles state machine description of an SFQ logic gate state machine to obtain state transition set information of the state machine, decomposes the state transition set information into one or more sub-state machines, maps each sub-state machine and each unit gate in an SFQ logic unit library, and recombines each sub-state machine based on the mapping result of each sub-state machine to obtain an SFQ sequential logic circuit structure. The invention utilizes the advantages of the SFQ logic gate, directly finishes the logic mapping from the SFQ logic gate state machine to the SFQ sequential circuit, reduces two steps of operation of simulating the CMOS logic gate in the middle and forming the CMOS sequential state machine, improves the logic comprehensive success rate of the SFQ sequential circuit and the utilization rate of the SFQ unit library, enables the large-scale automatic design of the SFQ sequential circuit to be more efficient, and solves the problems in the prior art.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement the embodiments of the present invention. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.
Fig. 1 is a schematic flow chart showing a comprehensive calculation method of an SFQ sequential circuit according to an embodiment of the present invention.
The method comprises the following steps:
step S11: and respectively interpreting and compiling the state machine description of the SFQ logic gate state machine, and obtaining a compiling result.
Optionally, based on a preset customized algorithm of the SFQ logic, the state machine descriptions of the SFQ logic gate state machine are interpreted and compiled respectively, and a compilation result conforming to the SFQ logic is obtained. Specifically, based on the comprehensive statement of the SFQ logic required by the preset SFQ sequential logic circuit, the state machine description of the SFQ logic gate state machine is respectively interpreted and compiled, and a compiling result is obtained; if the state machine description which is not in accordance with the SFQ logic appears, the exception is thrown in the semantic analysis stage, and the compiler is terminated. Preferably, a custom compiler is adopted to respectively interpret and compile the state machine description of the SFQ logic gate state machine, and obtain a compilation result. Wherein the custom compiler requires a synthesizable statement that specifies the SFQ sequential circuit.
Optionally, the state machine description of the SFQ logic gate state machine may be interpreted and compiled separately by MVEL or QLExpress, and a compiled result is obtained.
Optionally, the state machine description may adopt Verilog language to implement adaptation to other logic blocks in simulation function and call a part of IEEE standard.
Step S12: and acquiring state transition set information corresponding to the SFQ logic gate state machine according to the compiling result.
Alternatively, for SFQ circuits, because of the differences from CMOS circuits, it is necessary to output the compiled results as state transition set information after interpretation and compilation, rather than standard boolean logic and timing components. It should be noted that the state transition set information includes: and state transition information corresponding to each state.
Optionally, the state transition set information includes: a state transition diagram and/or a state transition table. Specifically, the compiling result is output as a state transition diagram and/or a state transition table after the interpretation and the compiling.
Step S13: and decomposing the state transition set information to obtain sub-state transition set information respectively corresponding to one or more sub-state machines.
Optionally, based on a decomposition rule related to cell gate information of the SFQ logical cell library, performing one or more iterative decompositions on the state transition set information respectively until one or more sub-state transition set information that cannot be decomposed again is obtained; specifically, since the same state machine may have a plurality of combination situations, it is necessary to introduce a random variable when decomposing the SFQ logic gate state machine, perform one or more iterative decompositions on the state transition set information based on a decomposition rule related to cell gate information of the SFQ logic cell library, and write the sub-state transition set information of each decomposed sub-state machine into a list for storage until all sub-state machines are irrevocable, thereby obtaining one or more sub-state transition set information corresponding to each sub-state machine.
Optionally, the state transition set information is subjected to one or more iterative decompositions respectively based on a decomposition rule related to the type of a unit gate in the SFQ logical unit library until one or more sub-state transition set information which cannot be decomposed again is obtained; grouping the states in the state transition set information according to the state continuity of the states to obtain one or more state groups with state continuity relation; based on the lowest state number obtained by the unit gate information of the SFQ logic unit library, each state in each state group is sequentially distributed to each sub-state machine, and one or more pieces of sub-state transition set information which can not be decomposed is obtained, so that the situation that the error state cannot jump out is avoided.
It should be noted that, based on the type (state minimum requirement) of each cell gate in the cell gate information of the SFQ logical unit library as the minimum state number, each state in each state group is sequentially allocated to each sub-state machine, and one or more sub-state machines which guarantee the minimum state number and are maximally decomposed are obtained; for example, the minimum requirement for satisfying the cell state machine in the SFQ cell library is that the number of states is equal to 2, i.e., the obtained sub-state machines at least include 2 states S0 and S1, as shown in FIG. 2.
Step S14: and respectively mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library, and obtaining the mapping result corresponding to each sub-state machine.
Optionally, based on the cell gate information of the SFQ logic cell library, mapping the sub-state transition set information of each sub-state machine with each cell gate in the SFQ logic cell library, and obtaining a mapping result corresponding to each sub-state machine; wherein the mapping result comprises: and the mapping result is successfully mapped corresponding to all the sub state machines and/or the mapping result is failed to be mapped corresponding to the sub state machines.
Specifically, based on the information of each unit gate in the unit gate information of the SFQ logic unit library, matching the sub-state transition set information of each sub-state machine with the information of each unit gate in the SFQ logic unit library, and when a sub-state machine which cannot be successfully matched occurs, obtaining a failure mapping result corresponding to the mapping failure of the sub-state machine, if a program is required to throw an exception, outputting the state machine transition information which cannot be matched, and continuing to perform matching; and if all the matching is completed, obtaining a successful mapping result corresponding to all the successfully mapped sub-state machines, namely, carrying out the next step. For the last incomplete matched unit gate, the user can design a new SFQ unit gate or modify the sequential circuit design according to the output failure mapping result.
Therefore, in the aspect of logic matching degree, compared with the traditional synthesis method, the method can solve the problems that the complete matching of the SFQ sequential logic to the unit gate cannot be realized by the traditional synthesis method, and the generated sequential circuit has a large number of loops and cannot meet the normal working requirement after being converted into the SFQ circuit.
The method has obvious advantages in the utilization rate of the SFQ logic unit library, the traditional method cannot call special logic gates of the SFQ such as ndro, rs1n, jandf and the like, but cannot realize the maximum utilization of the unit library, and the theoretical maximum utilization rate is 62.1 percent (29 unit gates in total, 11 logic gates cannot be called by the traditional comprehensive algorithm) according to the quantity analysis of the existing logic gates of the unit library; by adopting the comprehensive calculation method of the SFQ sequential circuit, the theoretical maximum utilization rate can be improved to 100%.
Optionally, for an existing SFQ unit gate, a designer needs to manually enter corresponding state transition information to form state transition set information, and the state transition set information is stored as a special library file for SFQ sequential logic circuit synthesis.
Step S15: and recombining the sub-state machines based on the mapping result corresponding to each sub-state machine to obtain the SFQ sequential logic circuit structure.
Optionally, the reconstructing the sub-state machines based on the mapping result corresponding to each sub-state machine to obtain the SFQ sequential logic circuit structure includes: acquiring unit gates mapped by the state machines corresponding to the successful mapping results; and connecting the unit gates to obtain the SFQ sequential logic circuit structure. Specifically, based on the successful mapping result corresponding to each sub-state machine, the cell gate mapped by each state machine corresponding to the successful mapping result is obtained; connecting all unit gates, recombining the unit gates into an SFQ sequential logic circuit, and obtaining a structure reflecting the SFQ sequential logic circuit; preferably, the structure is represented by a Verilog netlist.
Similar to the principle of the above embodiments, the present invention provides an SFQ sequential circuit comprehensive calculation system.
Specific embodiments are provided below in conjunction with the attached figures:
fig. 3 shows a schematic structural diagram of an SFQ sequential circuit comprehensive computing system according to an embodiment of the present invention.
The system comprises:
the compiling module 31 is configured to respectively interpret and compile the state machine descriptions of the SFQ logic gate state machine, and obtain a compiling result;
a state transition set information obtaining module 32, connected to the compiling module 31, configured to obtain, according to the compiling result, state transition set information corresponding to the SFQ logic gate state machine;
a decomposition module 33, connected to the state transition set information obtaining module 32, configured to decompose the state transition set information to obtain sub-state transition set information respectively corresponding to one or more sub-state machines;
the mapping module 34 is connected to the decomposition module 33, and configured to map the sub-state transition set information of each sub-state machine based on the cell gate information of the SFQ logical cell library, and obtain a mapping result corresponding to each sub-state machine;
and the restructuring module 35, connected to the mapping module 34, is configured to restructure each sub-state machine based on the mapping result corresponding to each sub-state machine, so as to obtain the SFQ sequential logic circuit structure.
It should be noted that the division of each module in the system embodiment of fig. 3 is only a division of a logical function, and all or part of the actual implementation may be integrated into one physical entity or may be physically separated. And these modules can be realized in the form of software called by processing element; or may be implemented entirely in hardware; part of the modules can be realized in a software calling mode through a processing element, and part of the modules can be realized in a hardware mode;
for example, the modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Optionally, the compiling module 31 respectively interprets and compiles the state machine description of the SFQ logic gate state machine based on a preset customized algorithm of the SFQ logic, and obtains a compiling result conforming to the SFQ logic. Specifically, the compiling module 31 respectively interprets and compiles the state machine description of the SFQ logic gate state machine based on the synthesizable statements of the SFQ logic required by the preset SFQ sequential logic circuit, and obtains a compiling result; if the state machine description conforming to the SFQ logic is not satisfied, the compiling module 31 throws an exception in the semantic analysis stage, and terminates the compiler. Preferably, the compiling module 31 includes: and the custom compiler is used for respectively interpreting and compiling the state machine description of the SFQ logic gate state machine and obtaining a compiling result. Wherein the custom compiler requires a synthesizable statement that specifies the SFQ sequential circuit.
Optionally, the compiling module 31 may use MVEL or QLExpress to respectively interpret and compile the state machine description of the SFQ logic gate state machine, and obtain a compiling result.
Optionally, the state transition set information obtaining module 32 needs to output the compiling result as the state transition set information after the interpreting and compiling. It should be noted that the state transition set information includes: and state transition information corresponding to each state.
Optionally, the state transition set information includes: a state transition diagram and/or a state transition table. Specifically, the state transition set information obtaining module 32 is configured to output the compiling result as a state transition diagram and/or a state transition table after the interpreting and compiling.
Optionally, the decomposition module 33 is configured to perform one or more iterative decompositions on the state transition set information respectively based on a decomposition rule related to cell gate information of the SFQ logical cell library until one or more sub-state transition set information that cannot be decomposed again is obtained. Preferably, the decomposition module 33 is configured to group the states in the state transition set information according to their state continuity, so as to obtain one or more state groups having a state continuity relationship; based on the lowest state number obtained by the unit gate information of the SFQ logic unit library, each state in each state group is sequentially distributed to each sub-state machine, and one or more pieces of sub-state transition set information which can not be decomposed is obtained, so that the situation that the error state cannot jump out is avoided. It should be noted that, the type (state minimum requirement) of each cell gate in the cell gate information of the SFQ logical unit library is used as the minimum state number, and the decomposition module 33 sequentially allocates each state in each state group to each sub-state machine, and obtains one or more sub-state machines which guarantee the minimum state number and are decomposed maximally.
Optionally, the mapping module 34 is configured to map the sub-state transition set information of each sub-state machine with each cell gate in the SFQ logic unit library respectively based on cell gate information of the SFQ logic unit library, and obtain a mapping result corresponding to each sub-state machine; wherein the mapping result comprises: and the mapping result is successfully mapped corresponding to all the sub state machines and/or the mapping result is failed to be mapped corresponding to the sub state machines. For example, as shown in fig. 4, the mapping module calls the logic cell gates DFFR and/or NDRO to implement matching of the information of each cell gate in the cell gate information based on the SFQ logic cell library, matches the sub-state transition set information (including the states S0 and S1) of each sub-state machine with the information of each cell gate in the SFQ logic cell library, and when the mismatch occurs successfully, needs the program to throw an exception, output the state machine transition table that fails to match, and continue the matching.
Optionally, the restructuring module 35 is configured to obtain the cell gates mapped by the state machines corresponding to the successful mapping results, and connect the cell gates to obtain the SFQ sequential logic circuit structure. Specifically, the restructuring module 35 is configured to obtain, based on the successful mapping result corresponding to each sub-state machine, a cell gate mapped by each state machine corresponding to the successful mapping result; connecting all unit gates, recombining the unit gates into an SFQ sequential logic circuit, and obtaining a structure reflecting the SFQ sequential logic circuit; preferably, the structure is represented by a Verilog netlist.
In the aspect of circuit overhead, because the traditional synthesis method cannot identify logic gates specific to the SFQ and cannot call the logic gates and map the logic gates into sequential logic, only basic AND-OR logic gates and triggers can be used for forming the sequential circuit, and therefore the area of a synthesis result can be increased; as shown in fig. 5, the present invention can call logic gates DFFR and NDRO specific to SFQ to optimize the circuit area.
Fig. 6 shows a schematic structural diagram of an SFQ sequential circuit comprehensive computation terminal 60 in the embodiment of the present invention.
The SFQ sequential circuit synthesis calculation terminal 60 includes: a memory 61 and a processor 62, the memory 61 being for storing computer programs; the processor 62 runs a computer program to implement the SFQ sequential circuit synthesis calculation method as described in fig. 1.
Optionally, the number of the memories 61 may be one or more, the number of the processors 62 may be one or more, and fig. 6 illustrates one example.
Optionally, the processor 62 in the SFQ sequential circuit comprehensive computation terminal 60 may load one or more instructions corresponding to the processes of the application program into the memory 61 according to the steps shown in fig. 1, and the processor 62 runs the application program stored in the first memory 61, so as to implement various functions in the SFQ sequential circuit comprehensive computation method shown in fig. 1.
Optionally, the memory 61 may include, but is not limited to, a high speed random access memory, a non-volatile memory. Such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid-state storage devices; the Processor 62 may include, but is not limited to, a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
Optionally, the Processor 62 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
The present invention also provides a computer-readable storage medium storing a computer program which, when running, implements the SFQ sequential circuit comprehensive calculation method shown in fig. 1. The computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disc-read only memories), magneto-optical disks, ROMs (read-only memories), RAMs (random access memories), EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions. The computer readable storage medium may be a product that is not accessed by the computer device or may be a component that is used by an accessed computer device.
In summary, the SFQ sequential circuit comprehensive calculation method, system and terminal of the present invention are used to respectively interpret and compile state machine descriptions of an SFQ logic gate state machine to obtain state transition set information of the state machine, decompose the state transition set information into one or more sub-state machines, map each sub-state machine with each unit gate in an SFQ logic unit library, and recombine each sub-state machine based on the mapping result of each sub-state machine to obtain an SFQ sequential logic circuit structure. The invention utilizes the advantages of the SFQ logic gate, directly finishes the logic mapping from the SFQ logic gate state machine to the SFQ sequential circuit, reduces two steps of operation of simulating the CMOS logic gate in the middle and forming the CMOS sequential state machine, improves the logic comprehensive success rate of the SFQ sequential circuit and the utilization rate of the SFQ unit library, enables the large-scale automatic design of the SFQ sequential circuit to be more efficient, and solves the problems in the prior art. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles of the present invention and its efficacy, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. An SFQ sequential circuit comprehensive calculation method is characterized by comprising the following steps:
respectively interpreting and compiling the state machine description of the SFQ logic gate state machine, and obtaining a compiling result;
acquiring state transition set information corresponding to the SFQ logic gate state machine according to the compiling result;
decomposing the state transition set information to obtain sub-state transition set information respectively corresponding to one or more sub-state machines;
respectively mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library, and obtaining the mapping result corresponding to each sub-state machine;
and recombining the sub-state machines based on the mapping result corresponding to each sub-state machine to obtain the SFQ sequential logic circuit structure.
2. The SFQ sequential circuit comprehensive computation method of claim 1, wherein the interpreting and compiling the state machine description of the SFQ logic gate state machine respectively and obtaining the compiled result comprises:
and respectively interpreting and compiling the state machine description of the SFQ logic gate state machine based on a preset customized algorithm of the SFQ logic, and obtaining a compiling result conforming to the SFQ logic.
3. The SFQ sequential circuit comprehensive computation method of claim 1, wherein the decomposing the state transition set information to obtain sub-state transition set information respectively corresponding to one or more sub-state machines comprises:
and respectively carrying out one or more times of iterative decomposition on the state transition set information based on a decomposition rule related to the cell gate information of the SFQ logic cell library until one or more sub-state transition set information which can not be decomposed again is obtained.
4. An SFQ sequential circuit synthesis computation method as claimed in claim 3, wherein said performing one or more iterative decompositions on said state transition set information respectively based on decomposition rules associated with types of cell gates in the SFQ logic cell library until one or more sub-state transition set information that are not resolvable are obtained comprises:
grouping the states in the state transition set information to obtain one or more state groups with state continuity relation;
based on the lowest state number obtained from the cell gate information of the SFQ logical cell library, each state in each state group is sequentially allocated to each sub-state machine, and one or more sub-state transition set information which can not be decomposed any more is obtained.
5. The SFQ sequential circuit comprehensive computation method of claim 1, wherein the mapping the sub-state transition set information of each sub-state machine based on the cell gate information of the SFQ logic cell library, respectively, and obtaining the mapping result corresponding to each sub-state machine comprises:
based on the unit gate information of the SFQ logic unit library, mapping the sub-state transition set information of each sub-state machine with each unit gate in the SFQ logic unit library respectively, and obtaining the mapping result corresponding to each sub-state machine; wherein the mapping result comprises: and the mapping result is successfully mapped corresponding to all the sub state machines and/or the mapping result is failed to be mapped corresponding to the sub state machines.
6. An SFQ sequential circuit comprehensive computation method as claimed in claim 5, wherein said reorganizing each sub-state machine based on the mapping result corresponding to each sub-state machine to obtain the SFQ sequential logic circuit structure comprises:
acquiring unit gates mapped by the state machines corresponding to the successful mapping results;
and connecting the unit gates to obtain the SFQ sequential logic circuit structure.
7. An SFQ sequential circuit synthesis calculation method as claimed in claim 1, wherein said state transition set information includes: a state transition diagram and/or a state transition table.
8. An SFQ sequential circuit synthesis calculation method as claimed in claim 1, characterised in that said state machine description uses Verilog language.
9. An SFQ sequential circuit synthesis computation system, the system comprising:
the compiling module is used for respectively interpreting and compiling the state machine description of the SFQ logic gate state machine and obtaining a compiling result;
the state transition set information acquisition module is connected with the compiling module and is used for acquiring the state transition set information corresponding to the SFQ logic gate state machine according to the compiling result;
the decomposition module is connected with the state transition set information acquisition module and is used for decomposing the state transition set information to acquire the sub-state transition set information respectively corresponding to one or more sub-state machines;
the mapping module is connected with the decomposition module and used for mapping the sub-state transition set information of each sub-state machine based on the unit gate information of the SFQ logic unit library and obtaining the mapping result corresponding to each sub-state machine;
and the recombination module is connected with the mapping module and used for recombining each sub-state machine based on the mapping result corresponding to each sub-state machine so as to obtain the SFQ sequential logic circuit structure.
10. An SFQ sequential circuit comprehensive computation terminal, comprising:
a memory for storing a computer program;
a processor for performing the SFQ sequential circuit synthesis calculation method of any one of claims 1 to 8.
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