CN1133534A - Detector for initial code - Google Patents

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Description

Detector for initial code

The invention belongs to the image processing technique field, relate to a kind of visual decompression technique that image transmits receiving terminal, particularly about a kind of initial code detection method and device

The present invention is intended to improve decompression method and device, and it is used for the input signal by multitude of different ways is decompressed and/or decodes. For illustrating that hereinafter selected embodiment relates to the decoding of Multi-encoding image standard, particularly this embodiment relate to be called JPEG, MPEG and H.261 in the decoding of the known standard of any people.

Serial flow waterline treatment system of the present invention comprises single two-wire (two-wire) bus, form with control token and data token, transmit exclusive and special-purpose interactive interface token to many adaptive de compressor circuits and similar circuit, the latter forms a reconfigurable pipeline processor.

U.S. Patent No. 5,216 has been described a kind of prior art systems in 724. This device comprises a plurality of computing modules, always has the computing module of 4 Parallel coupled in a preferred embodiment. In each such computing module processor is arranged, dual-port memory device, temporary transient (scratch-pad) memory and an arbitration organ. The first bus and computing module and primary processor coupling. Equipment comprises a shared memory, this memory and primary processor coupling, and pass through the second bus coupling to computing module.

U.S. Patent No. 4,785,349 disclose a kind of complete stream waterline that comprises a large amount of pipeline stages. Each pipeline stages comprises one group of input data latch, is thereafter a combinational logic circuit, the specific logical operation of this circuit execution pipeline level. Data latches and triggering signal are provided simultaneously, and triggering signal is to be produced by the data transfer control circuit that interrelates with that one-level. Data transfer control circuit is connected to each other to form a chain, and the handshaking type data that transmission and response signal link tester are crossed between this chain control Continuous Flow pipeline stage transmit. In addition, usually in every grade, provide a decoder, with the operation of selecting to finish in operand at the corresponding levels. Can also in previous stage, arrange a decoder, process with the decoding of pre decoding complexity, and the critical path problem in the mitigation logic circuit. The retractility of streamline has been eliminated any centralization control, because working in coordination, all between submodule determined by a decision that localizes fully, in addition, each submodule can independently be finished the data transfer control of data buffering and self-timing at one time. At last, be increasing the retractility of streamline, interted vacant level between the level of having used, is reliable to guarantee that data between the level transmit.

U.S. Patent No. 5,278,646 announced a kind of through improved decoding technique, wherein, the coefficient number that comprises in each sub-block is selectable, and the Bit String that is arranged in each encoded video sequence section start has all inserted a code, the number of coefficient in the every one deck of this yard indication. By being that each scale (scale) along the selected number of coefficients of continuous sweep forms a sub-block, this technology makes the original distance of swimming of the zero coefficient in the highest resolution layer keep complete. By in each scale, inserting the zero of right quantity and from each scale, abandoning unnecessary coefficient, obtain the sub-block of square ordering. Again these sub-blocks are used inverse discrete cosine transform, just can decode with standard mode. This technology has further been improved decoding efficiency, because it allows the hidden signal of block end to remove to distinguish explant, so that in most of the cases need not the video picture signal that decoding block finishes.

U.S. Patent No. 4,90 3,018 has announced a kind of processing method and data handling system for relevant a plurality of data sequences on compression and the expansion structure. Processing method is special to data set, has carried out structural analysis in data, to determine the common feature of continuous data element of a data sequence predetermined number. As substituting of data cell, a code is used, and this code is decoded in expansion process again. Common features is to obtain by analyzing the data cell have same sequence number in the mass data sequence. In expansion process, to be arranged with DS by the data cell that decoding gets, this arrangement is based on the sequence number of these data cells. Be used for carrying out the data handling system of processing and comprise a storage matrix (26) and a pointer memory (28), this pointer memory has the row address of storage matrix (26) in an arranged row sequence.

U.S. Patent No. 4,334,246 have announced a kind of circuit and method, it be used for for transmit or store and after the formerly compression to video decompression. The circuit hypothesis is surveyed the fallout predictor operation by the original video that the grating input scanner produces by a two-wire list, is encoded into 4,8 or 12 code word with the run length coding mode, and is packaged into 16 bit data word. Then, described this decompressor is by linking 16 bit data word and then connect respectively each code word to come data are unpacked, it is 4 zero nibble and the termination nibble of a position that includes one or more composition decoded datas entirely that these code conversions are become some, the last video bit that checks the real video of last scan line and one's own profession is separated the fallout predictor position to produce, and decoded data is conciliate the fallout predictor position compare, to produce last real video.

U.S. Patent No. 5,060,242 have announced a kind of image signal processing systems, DPCM is to Signal coding, then Huffman and run length are to Signal coding, to produce the code word of variable-length, then these code words by the closely packing of tight ground, do not lose any data in order to effectively transmit. Closely the device of packing has a barrel shifter, and its displacement modulus is by the accumulator control of a receiving code word length information. One or link to each other with shift unit, and a register is connected on the door. Closely pack and the device of the data signal of decorrelation has barrel shifter and an accumulator that unpacks usefulness Huffman and run length decoder and a reverse DCPM decoder for the treatment of a quilt.

United States Patent (USP) No.5,168,375 have announced a kind of method, for the treatment of a field pattern image data sample, so that one or more functions of extraction, interpolation to be provided, and sharpening is by using a formation transform processor to finish, and is employed the sort of such as the JPEG compressibility. In extraction and interpolation processing, all by discrete even cosine transform (DECT) distortion, through after this conversion, the item number of frequency is changed the data sampling piece. In situation about extracting, the frequency item number is reduced, and then carries out transformation by reciprocal direction, to produce the matrix that dwindles of the sampled point that represents original data block. In the situation of interpolation, the additional frequency composition of null value is inserted into frequency content and arranges, and then transformation by reciprocal direction produces a data sampling collection that has enlarged, and spectral bandwidth does not increase. In the sharpening situation, a kind of transformation by reciprocal direction is provided, produced the data sampling piece collection of processing; Sharpening is to be finished by convolution or filtering operation that frequency domain data conversion and frequency domain filtering nuclear phase are taken advantage of. These pieces are superimposed, keep subsequently the sample of appointment, and unnecessary sample is abandoned from the overlapping region. The space representation formula of nuclear is changed by reducing its component number, becoming linear-phase filter, and is loaded into zero in order to equate with the hits of data block; After this will form the discrete strange cosine transform (DOCT) to the nuclear matrix of having filled.

U.S. Patent No. 5,231,486 have announced a kind of HDVS High Definition Video System of processing bit stream, and the bit stream that it is processed comprises the data word of the variable length code of high and low priority. By minute other data packaged unit, coded data is divided into high priority packing data and low priority packing data. Coded data is offered this two kinds of packaged units continuously. The high priority of indication coded data and the high priority of low priority composition and low priority length word are supplied to high and low priority data packing device. Want packaged so that when being transmitted by the first outgoing route when high priority data, low preferential length word is zero; And want packaged when transmitting by the second outgoing route when low prioritized data, high preferential length word is zero.

U.S. Patent No. 5,287,178 have announced a kind of system for coding video signal. It comprises a signal processor, and being used for becomes the transmission block with a head part and packaged data part with the coding video frequency data segmentation. System also comprises repositioning control device, is used for after a total system resets, and resets with the predetermined order issue subsystem stage by stage of non-while, can begin with predefined procedure so that signal is processed. Found legal data when transmission data string, the distribution order that resets stage by stage namely begins.

U.S. Patent No. 5,124,790 have announced a kind of inverse quantization device that uses with image memory. This inverse quantization device is used with standard mode, with decoded differences predictive coding method (DPCM) coded data.

Authorize the patent No.136 of U.S. Savatier etc., 371 relate to a kind of quantizer that goes that can regulate quantization level that has, and level is variable and is determined by the full scale situation of buffer. The applicant claims that their the most novel characteristics of invention are to have realized farthest can obtain data transfer rate. Be used in the quantization level that is recalculated after each piece is encoded, to quantizer 152 with go the quantization step of quantizer 156 to make adaptive change, this has just been avoided overflow and the underflow of buffer. Compare with whole buffer sizes, quantization level be used as for frame the function of coded data amount calculate. Like this, quantization level can advantageously be recomputated and needn't be transmitted by decoder.

Grant the people's such as Sakagami U.S. Patent No. 5,142,380 and announced a kind of image compression device, it is applicable to still image, uses those images of solid-state image pickup formation such as the electronic still camera. Employed quantizer links to each other with a memory device, stores the threshold value of the quantization matrix of brightness signal Y here, and rom15 then stores the threshold value of the quantization matrix of carrier chrominance signal I and Q.

Grant the people's such as Guichard U.S. Patent No. 5,193,002 and announced a kind of device, this device is used for the real-time coding of H.261 being combined with ccitt standard/decoded picture signal. A digital signal processor is carried out forward and is quantized and inverse quantization.

Grant in the people's such as Chen the U.S. Patent No. 5,241,383 and described a kind of device, this device has the false constant bit rate Video coding of realizing by regulating quantization parameter. Quantizer 32 employed quantization parameters are by periodic adjustment, to increase or to reduce the code bit number that is produced by coding circuit. The quantization parameter that carries out in order to encode next group of picture changes to be measured by a difference to be determined, this difference measurements is to be to carry out between the actual code figure place of last group of picture generation and the estimated code figure place to last group of picture at coding circuit. The code bit number that coding circuit produces is controlled by the step-length of control quantizer. Usually, less quantiser step size produces more code bit, and larger quantiser step size produces less code bit.

Grant the people's such as Negata U.S. Patent No. 5,113,255; The people's such as Andrews No.5,126,842; The people's such as Gharavi No.5,253,058; The people's such as the people's such as Hui No. 5,260,782 and Nomile No.5,212,742 grades all are included as background, and as the general remark of one's own profession technology.

The present invention relates to an improved pipeline system, there is an input in this system, export and the many processing levels between input and output for one, this many processing level is with two line interface interior bonds, in order to transmit control token and/or the data token of token and general matching unit form along streamline, for with streamline in all level interfaces and with streamline in selected level mutual, for the control data in processing level and/or control one data function of combination, so that the processing level in the streamline is strengthening flexibility aspect configuration and the processing. According to the present invention, some are processed level and can be reconfigured when the identification of at least one token of response. These process one of level can be an initial code decoder, and it receives input and generation and/or some tokens of conversion.

The present invention also comprises some tokens, the token of PICTURE_START code form shows that an images begins the back with the DATA token, the token of PICTURE_END form indicates the end of an images, the token of FLUSH form is used for removing buffer and making system reset, and the token of a CODING_STANDARD form stipulates that system processes a kind of standard chosen in many image compression/decompression standard. The present invention also relates to one to the improved pipeline system of video data decoding, has a Huffman decoder, a data index level (ITOD), an ALU (ALU) and a data buffer device of closelying follow in the system back, utilize these, (time spread) can be controlled because the time that video image data amount difference causes distributes. Also according to the present invention, the processing level that receives input traffic comprises the bit stream pattern of identify appointment, becomes easy thereby process grade to make arbitrary access and right a wrong. The operation of (stop-after-picture) was used for obtaining the obvious end of pictorial data decoding after the present invention also can comprise a device and be used for to carry out an image and stop, and was used for indicating the end of an images and was used for removing streamline.

Improved pipeline system also can comprise a fixed size, and the device of the buffer of fixed width and filling buffer transmits any digit and passes through buffer. The present invention also relates to data flow and a reverse moulding device device that comprises run length coding, RLC, this device works to data flow according to token, be used for after the distance of swimming that run level code is expanded into a remainder certificate with a level, here each token represents with the number of the value of an appointment. The present invention also comprises a reverse moulding device level, a reverse discrete cosine transform level and a processing level that is placed between reverse moulding device level and the reverse discrete cosine variation level, the token table of a deal with data of its response.

In addition, the present invention relates to improved pipeline system. H.261 or the Huffman of MPEG or the mpeg standard coding regulation coded data word Huffman decoder of decoding this system has one to according to, and data word comprises the identifier that the data word past was identified in order to the Huffman coding standard of coding; The device that receives the huffman coded data word is arranged; Have and read identifier and once arranged the Huffman coding of the data word that receives to determine which kind of standard, and, if necessary, to identify the Huffman coded data word for H.261 or the identifier of MPEG Huffman coding read the device that responds; The device that is connected to Huffman coded data word receiving system is arranged practically, to produce the call number relevant with each JPEG Huffman coded data word of receiving from Huffman coded data word receiving system; There is operation to comprise the device of the look-up table of Huffman code table, the Huffman code table has under Joint Photographic Experts Group using form to transmit JPEG Huffman table information, this device comprises for the input from call number generation device reception hint number, also comprises the decoded data word output corresponding to this call number. The description of the drawings

Figure 1 shows that 6 cycles to 6 level production lines of the various combination of 2 kinds of internal control signals;

Fig. 2 a and 2b illustrate a streamline, and wherein each step comprises the auxiliary data memory. They give a kind of mode, and the level of streamline can " compression " and " expansion " with the delay in streamline in this mode;

Fig. 3 a (1), 3a (2), 3b (1), 3b (2) illustrate data transfer control between the pipeline stages of the preferred embodiment that uses two-wire interface and multi-phase clock;

Fig. 4 is a block diagram, and this figure demonstrates the basic embodiment of the pipeline stages of introducing two-wire transmission control, and shows 22 coherent pipeline processes levels with two wires transfer control;

Fig. 5 a and 5b describe the example of a sequential chart altogether, and this figure shown at timing signal, input and output data and be used for relation between the pipeline stages internal control signal shown in Figure 4;

Fig. 6 is the block diagram of the example of a pipeline stages, and it keeps its state under the control of extension bit;

Fig. 7 is the block diagram of pipeline stages, the activation data word of these pipeline stages decoder stage;

Fig. 8 a, 8b form block diagram jointly, are presented at the use of two-wire transfer control in " data Replica (data duplica-tion) " pipeline stages example;

Fig. 9 a, 9b describe an example of sequential chart jointly, and this figure shows diphasic clock, Double wire transmission control signal and be used in other internal data and control signal among Fig. 8 a, the 8b embodiment;

Figure 10 is a reconfigurable block diagram of processing level;

Figure 11 is the spatial decoder block diagram;

Figure 12 is the temporal decoder block diagram;

Figure 13 is video format device block diagram;

Figure 14 a～c shows with the in the present invention various arrangements of memory piece:

Figure 14 a is the memory Transformation Graphs, and it has shown the first arrangement of macro block;

Figure 14 b is the memory converter, and it has shown the second arrangement of macro block;

Figure 14 c is the memory Transformation Graphs, and it has shown another arrangement of macro block;

What Figure 15 had shown Venn diagram may show selective value;

Figure 16 has shown the in the present invention variable-length of pictorial data of usefulness;

Figure 17 is the block diagram that comprises the temporal decoder of predictive filter;

Figure 18 is the expression of predictive filtering process graphical;

Figure 19 is the general expression of macroblock structure;

Figure 20 has shown the general block diagram of detector for initial code;

The example of Figure 21 explanation numeric data code in data flow;

Figure 22 is the descriptive markup generator, the decoding pointer, and the leader generator adds the block diagram of word generator and output latch Relations Among;

Figure 23 is the block diagram of spatial decoder DRAM interface;

Figure 24 is the block diagram of writing the alternate buffering device;

Figure 25 is that explanation is from the schematic diagram of just processed prediction data skew;

Figure 26 is that the explanation prediction data has been offset the schematic diagram of (1,2);

Figure 27 is the block diagram of the routine analyzer state machine of explanation Dorothy Holman decoder and spatial decoder;

Figure 28 is explanation predictive filtering block diagram;

Figure 29 shows typical decode system;

Figure 30 has shown JPEG still image decoder;

Figure 31 has shown the JPEG Video Decoder;

Figure 32 has shown multi-standard video decoder;

Figure 33 has shown the starting and ending of token;

Figure 34 has shown token address and data field;

Figure 35 has shown the token that surpasses 8 bit wides at interface;

Figure 36 has shown macroblock structure;

Figure 37 has shown the two-wire interface agreement;

Figure 38 has shown the position of outside two-wire interface;

Figure 39 has shown clock analysis figure;

Figure 40 has shown the two-wire interface sequential;

Figure 41 has shown the access structure example;

Figure 42 has shown and has read the transmission cycle;

Figure 43 has shown the initial sequential of access;

Figure 44 has shown the access example of writing transmission with 2;

Figure 45 has shown and has read the transmission cycle;

Figure 46 has shown the transmission cycle of writing;

Figure 47 has shown the refresh cycle;

Figure 48 has shown 32 bit data bus and the dark DRAM (9 row addresses) in 256k position;

Figure 49 has shown the timing parameters of any gating signal;

Figure 50 has shown the timing parameters between any two gating signals;

Figure 51 has shown the timing parameters between bus and the gating;

Figure 52 has shown the timing parameters between bus and the gating;

Figure 53 has shown that MPI reads sequential;

Figure 54 has shown that MPI writes sequential;

Figure 55 has shown the tissue of a large amount of integers in the memory Transformation Graphs;

Figure 56 has shown typical decode clock mode;

Figure 57 has shown the input clock requirement;

Figure 58 has shown spatial decoder;

Figure 59 has shown the input and output of input circuit;

Figure 60 has shown the agreement of encoder port like those shown;

Figure 61 has shown detector for initial code;

Figure 62 has shown the detection of initial code and has converted token to;

Figure 63 has shown that initial code inspection device transmits token;

Figure 64 has shown overlapping MPEG initial code (byte location);

Figure 65 has shown overlapping MPEG initial code (non-byte location);

Figure 66 has shown the redirect between two video sequences;

Figure 67 has shown the sequence that additional token inserts;

Figure 68 has shown that decoder starts control;

Figure 69 allows traffic queuing before having shown output;

Figure 70 display space decoder buffer;

Figure 71 has shown buffer pointer;

Figure 72 has shown the video decomposer;

Figure 73 has shown the structure of an image;

Figure 74 has shown the structure of 4: 2: 2 macro block;

Figure 75 has shown from pel ones computing macro block size;

Figure 76 has shown the space decoding;

Figure 77 has shown the H.261 general survey of re-quantization;

Figure 78 has shown the general survey of JPEG re-quantization;

Figure 79 has shown the general survey of MPEG re-quantization;

Figure 80 has shown the memory conversion of quantization table;

Figure 81 has shown the general survey of JPEG baseline sequential structure;

Figure 82 has shown the jpeg picture of token;

Figure 83 has shown temporal decoder;

Figure 84 has shown the image buffer explanation;

Figure 85 has shown MPEG image sequence (m=3);

Figure 86 has shown how " I " image stores and export;

Figure 87 has shown how " P " image forms, storage and output;

Figure 88 has shown how " B " image forms and export;

Figure 89 has shown " P " pixel format;

Figure 90 has shown and has H.261 predicted form;

H.261 Figure 91 has shown " sequence ";

Figure 92 has shown H.261 syntactic level;

Figure 93 has shown H.261 image layer;

Figure 94 has shown the H.261 arrangement of piece group;

H.261 Figure 95 has shown " sheet " layer;

Figure 96 has shown the H.261 arrangement of macro block;

Figure 97 has shown the H.261 sequence of piece;

Figure 98 has shown H.261 macroblock layer;

Figure 99 has shown the H.261 arrangement of picture dot in piece;

Figure 100 has shown the level of MPEG syntax;

Figure 101 has shown the MPEG sequence layer;

Figure 102 shows the MPEG group of image layer;

Figure 103 has shown MPEG image layer;

Figure 104 has shown MPEG " sheet " layer;

Figure 105 has shown the sequence of mpeg block;

Figure 106 has shown the MPEG macroblock layer;

Figure 107 has shown " OPEN GOP ";

Figure 108 has shown the example of access structure;

Figure 109 has shown the initial sequential of access;

Figure 110 has shown one fast page of read cycle;

Figure 111 has shown one fast page of write cycle time;

Figure 112 has shown the refresh cycle;

Figure 113 has shown extraction row and column address from chip address;

Figure 114 has shown the timing parameters of any gating signal;

Figure 115 has shown the timing parameters between any two gating signals;

Figure 116 has shown the timing parameters between bus and gating;

Figure 117 has shown the timing parameters between a bus and the gating;

Figure 118 has shown Dorothy Holman decoder and analyzer;

H.261 Figure 119 has shown and MPEG AC coefficient decoding process figure;

Figure 120 has shown JPEG (AC and DC) coefficient decoding block diagram;

Figure 121 has shown JPEG (AC and DC) coefficient decoding process figure;

Figure 122 has shown Dorothy Holman token formatter;

Figure 123 has shown token formatter block diagram;

H.261 Figure 124 has shown and has decoded with MPEG AC coefficient;

Figure 125 has shown the interface of Dorothy Holman ALU;

Figure 126 has shown the basic structure of Dorothy Holman ALU;

Figure 127 has shown buffer-manager;

Figure 128 has shown the block diagram of imodel and hsppk;

Figure 129 has shown the imex state diagram;

Figure 130 illustrates the startup of buffer;

Figure 131 shows a DRAM interface;

Figure 132 has shown and has write the alternate buffering device;

Figure 133 has shown an arithmetic block;

Figure 134 has shown iq piece figure;

Figure 135 has shown the iqca state machine;

Figure 136 has shown IDCT one-dimensional transform algorithm;

Figure 137 has shown an IDCT one-dimensional transform structure;

Figure 138 has shown a token streams block diagram;

Figure 139 has shown the structure of a calibrated bolck;

Figure 140 is tests microprocessor access block diagram;

Figure 141 has shown the one-dimensional transform macrostructure;

Figure 142 has shown a time decoder block diagram;

Figure 143 has shown the structure of a two-wire interface level;

Figure 144 has shown the address generator block diagram;

Figure 145 has shown the pixel skew of piece;

Figure 146 has shown the multichannel predictive filter;

Figure 147 has shown single predictive filter;

Figure 148 has shown the one-dimensional prediction wave filter;

Figure 149 has shown the piece of pixel;

Figure 150 has shown the structure of read pointer;

Figure 151 has shown that piece and pixel depart from;

Figure 152 has shown the prediction example;

Figure 153 has shown the read cycle;

Figure 154 has shown write cycle time;

Figure 155 has shown the block diagram that uses the top layer register of timing base;

Figure 156 has shown the control that increases the number of presenting;

Figure 157 has shown buffer management state machine (fully);

Figure 158 has shown the major cycle of state machine;

Figure 159 has shown the buffer 0 (22 * 18 macro block) that comprises the SIF image;

Figure 160 has shown the SIF component 0 with display window;

Figure 161 has shown the pixel format of an example of storage block address;

Figure 162 has shown the buffer 0 (22 * 18 macro block) that comprises the SIF image;

Figure 163 has shown an address computation example;

Figure 164 has shown a writing address generator state machine;

Figure 165 has shown cutting apart of data path;

Figure 166 has shown the operation in two cycles of data path;

Figure 167 has shown that mode 1 carries out filtering;

Figure 168 has shown horizontal up-sampler data path;

Figure 169 has shown the structure of color space conversion device.

Description of the invention:

Use briefly general term, the invention provides an input, many processing between output and the input and output grade. This many processing level is with two line interface interior bonds, in order to transmit control token and the data token of token and general matching unit form along streamline, for with streamline in all grades interface and with streamline in selected level mutual, in order to process the middle control of level, control-the data function of data and/or combination, utilize these, the processing level in the streamline is strengthening flexibility aspect configuration and the processing.

Each processing level can comprise main and auxiliary memory in the streamline. Level in the streamline can reconfigure according to the identification to selected token. Some tokens in the streamline are dynamic self-adaptings, can be relevant with the processing level in order to finish POF, also can have nothing to do.

According to the present invention, in a streamline machine, some tokens can be changed by the interface of some grades, and some tokens can be mutual with all processing level in the streamline, and perhaps only to process level mutual rather than all with above-mentioned some. Token in the streamline can be mutual with adjacent processing level, and is perhaps mutual with non-conterminous processing level, and token can reconfigure the processing level. These tokens can be that the position is relevant to some function in streamline, can be location independents to other functions.

According to the present invention, in an improved pipeline machine, each token in these tokens can comprise an extension bits, and extension bits shows some additional words of existence in the token, and the last word of that token made mark, the address field variable-length also can be the Huffman coding.

Token can processed level produce in improved pipeline machine. Token can comprise the data that are sent to the processing level or not have data. Some token can be identified as data token and provide data to the processing level in the streamline, and other tokens are identified as controlling token, only make the processing level in the streamline reach desired regulation, and these regulations comprise processes reconfiguring of level. Some tokens can provide to the processing level in the streamline data and stipulate both in addition. Some above-mentioned token can be identified the coding standard of processing level in the streamline, and other tokens can irrespectively be worked with any coding standard in processing level. Token can be changed continuously by the processing level in the streamline.

According to the present invention, the mutual flexibility of token and the cooperation of processing level are processed a grade multi-purpose variation for inherent structure in the streamline makes and are become easy. The flexibility of token is expanded system and/or is become easy. Token can have the ability to make the many functions in any processing level in the streamline to become convenient. The streamline token can be based on hardware or software. Therefore token makes the easier effective utilization of system bandwidth in the streamline. Token can provide data and control simultaneously to the processing level in the streamline.

The present invention can comprise a pipeline processor, in order to process the bit stream of the many absolute codings that are arranged to the single serial bit stream of digit order number, the corresponding data of the control code that processor has some absolute codings to carrying with serial bit stream, and use many by two line interfaces do interior bonds the level, the further feature of processor represents that with detector for initial code the single serial bit stream of this detector response produces control token and the data token that is applied to two line interfaces. Identify some token as the control token that is suitable for that grade with a token decode circuit that is placed on some grade, and the token that is not identified is passed through along streamline, reconfigure an a specific order with the control token of an identification of a reconfigurable decoding and APU response and remove to process the data token of having identified.

According to the present invention, detector for initial code is that one of many levels are used for receiving input and are suitable for generation and/or conversion token. The detector for initial code response data generates token, searches and detects initial code and respond there the generation token, can detect overlapping initial code, thereby ignore the first initial code, generates the initial code token with the second initial code.

The detector for initial code level is suitable for the initial code that search is chosen in input traffic under search pattern. Detector is searched the intermittence in the data flow, and search can be made of the data of external data source. The detector for initial code level can generate the START_CODE token, PICTURE_START token, SLICE_START token, PICTURE_END token, SEQUENCE_START token, SEQUENCE_END token, and/or GROUP_START token. The detector for initial code level also can add to the word of token most end some positions and carry out the filling function.

One for the treatment of the many absolute coding bit streams that are arranged to the digit order number serial bit stream and initial code with absolute coding to and the machine of the data of in serial bit stream, carrying in, detector for initial code can provide an initial code detection subsystem. This subsystem has first, second, and third register of series connection, each register stores the position from the bit stream varying number, value of the first register, the associated initial code of value that the second register and the identification of the first decoding device and above-mentioned the first register comprise. Line unit is displaced to the predetermined end of the 3rd register to the latter's value, and the second decoding device is arranged from the 3rd register parallel receive data.

One or more control tokens that also can provide the memory of response second decoding device to be used for providing to have memory as with the decoded result of the associated value of initial code. Also can provide many flag shift registers for the treatment of the mark that shows from the legitimacy of register data. System comprises that also some devices are used for access and are used for format and organising data stream from the input traffic of MPI and some devices.

According to the present invention, detector for initial code can be identified the initial code with the associated variable-width of different coding bit stream. Detector for initial code can produce many data tokens from input traffic. And according to the present invention, system can be a pipeline system, and detector for initial code can be put and make streamline the first processing level.

The present invention also provides one many systems that process level are arranged, in system, a general matching unit of interactive interface token form is used at control and/or the data function of processing level, token be a PICTURE_START code token be used for indicating image begin to have subsequently data token and then.

Token also can be the end that a PICTURE_END token is used for indicating indivedual images.

Token also can be a removing (FLUSH) token, when token is removed some buffers and resetting system from being input to output when advancing from top to bottom system. According to the present invention, when token advances from top to bottom along streamline, remove mode that token can change some levels that reset.

Token also can stipulate that system processes according to a kind of going selected in many image compression/decompression standard by the CODING_STANDARD token.

It is JPEG that the CODING_STANDARD token can be specified image standard, and/any other suitable image standard. Have at least some processing level response CODING_STANDARD tokens to reconfigure.

One of processing level in the system can be Huffman decoder and analyzer, when receiving a CODING_STANDARD control token, analyzer is transformed into one and the corresponding address location of program unit, and program is for the treatment of the image standard with the identification of CODING_STANDARD control token. CODING_STANDARD control token also an optional reseting address to being applied to test the memory cell of Huffman decoder and analyzer.

The Huffman decoder can comprise a decoder stage and a data index level, and analyzer can send to the data directory unit instruction, selects specifically to be identified the more needed tables of coding standard, and whether the data that the analyzer level indicates arrival paraphase.

Some above-mentioned tokens also can adopt the form of mutual distortion interface token.

The present invention also provides one to the system of video data decoding, a Huffman decoder is arranged, a data index (ITOD) level, unit (ALU) and the data buffer device immediately following system are patrolled in a calculation, utilize these, can be controlled because the time that the video image that size of data changes causes distributes.

System can comprise a spatial decoder, has that two line interfaces are inner to be connected some and process level, and interface enable is with to the data serial process, to the control parallel processing.

As noted, system can further comprise wherein each the separately program of storage of promising many image standards of a ROM, and the program available tokens is selected, and makes the processing to many different image standards become easy.

The Space Solutions code system also comprises a token formatter and is used for the format token, and data token is generated.

System can also comprise a decoder stage and an AG and be used for sending an instruction to the data indexing units, is some tables that specific recognition coding Standard Selection needs, and whether the data that AG shows arrival paraphase. These tables are arranged at and enable in suitable place repeatedly use table in the memory.

The present invention also provides a pipeline system that an input traffic is arranged and for receiving the processing level of input traffic, this grade comprises the device of identification specific bit stream mode, utilizes above-mentioned level to make arbitrary access and right a wrong and becomes easy. According to the present invention, processing level can be an initial code detectors, and the bit stream pattern can comprise initial code. Therefore, invention provides a search-mode device to be used for searching the different coding data flow that is arranged to single serial data stream, is used for allowing arbitrary access and strengthens error correction.

The present invention also provides a streamline machine, device with (stop-after-picture) operation after carrying out image and stopping, being used for mentioning the pictorial data decoding significantly finishes, be used for indicating the image end and remove streamline, the combination that utilizes these devices to produce PICTURE_END token and FLUSH token.

The present invention also provides a fixed size in pipeline machine, the buffer of fixed width and device are used for filling buffer, transmits the position of arbitrary number and passes through buffer. Filling device can be an initial code detectors.

Fill and carry out at the last character of token only, fill and guarantee the consistent of word size. According to the present invention, can provide a treating stage capable of reconfigurating as spatial decoder, the pictorial data that filling device is processed spatial decoder is added enough images that adds the position so that every width of cloth of spatial decoder output decompresses to be had and take the position as the equal length of unit.

The present invention also has one provides a contrary moulding device device in the system of the data flow that comprises run-length code, this device acts on from the next data flow of token, in order to run level code is expanded into the run of remainder certificate, heel level, here each token is with the value representation that specifies number. Token can be a data token.

Reverse moulding device device stops the token of the value that specifies number not, can be 64 coefficients specifying number of preferential embodiment intermediate value of the present invention.

Practice of the present invention can comprise that one is expanded circuit and is used for receiving and the data token of run-length code arranged and run-length code is decoded. With tucker (padder) the channel check data token that expands line traffic whether predetermined length is arranged, if so that data token length less than predetermined length, the tucker circuit adds some data cells until reach pre-fixed length to the data token. Also provide one to be close to the route road for making data token any token in addition walk around the expansion circuit and filling circuit.

According to the present invention, the method that provides a kind of data effectively to fill buffer comprises providing the first kind of the first preset width token, is one of following form at least:

Form A-EXXXXXXLLLLLLLLLLL

Form B-ERRRRRRLLLLLLLLLLL

Form C-EOOOOOOLLLLLLLLLLL is the E=extension bits here; The F=specified format; R=distance of swimming position; L=length position or non-data token; X=" arbitrarily " (" don ' t Care ") position, form A token is divided into a form oa token that the ELLLLLLLLLLL form is arranged, form B token is divided into form 1 token has FRRRRRROOOOO form and a form oa data token, form C token is divided into form 0 token has the FLLLLLLLLLLL form, and form 0, form oa and form 1 token are put into the buffer that the second preset width is arranged.

The present invention also provides a device that one group of compressed image is provided time delay, image meets a kind of video compression/decompression standards, the data word that comprises there compressed image is counted with a counting circuit, one is suitable for receiving the actuate message consistent with video compression standard with microprocessor that counter is communicated by letter, actuate message counter of notifications circuit.

One is used for the receive data word and communicates by letter with the control circuit in the middle of the counter circuit with the reverse moulding device circuit of energy delayed data word, reverse moulding device circuit, control circuit is the sum counter line traffic also, and counter circuit relatively and to control circuit signals actuate message and data word counting. Control circuit is those Signal Queues consistent with the data phasing that satisfies the starting criterion and control reverse moulding device lag characteristic.

The present invention also provides improvement to a pipeline system with reverse moulding device level and reverse discrete cosine transform level, improved characteristics are between reverse moulding device and reverse discrete cosine transform level, and of the token table sensitivity of deal with data is processed level.

Token can be the QUANT_TABLE token according to the present invention, is used for making processing generating quantification table.

The present invention also provides a Huffman decoder, with to according to H.261, the Huffman coding clause coded data word decoding of JPEG or mpeg standard, this data word comprises a recognition data word past in order to the identifier of the Huffman code standard of coding. The Huffman decoder has the device that receives the Huffman coded data word; Be useful on and read the device that identifier is encoded with the Huffman that determines the data word which kind of standard domination is received; H.261 or after MPEG H Huffman encoded, this turning just carried out in case of necessity the handlebar data word converts the device of JPEG Huffman coded data word to, reads identifier in 1 device response, identifies the Huffman coded data word for; Have can the actual Huffman of receiving coded data word receiving system device, to produce the call number relevant with each JPEG Huff-man coded data word that receives from Huffman coded data word receiving system; There is operation to comprise the device of the look-up table of Huffman code table, this Huffman code table has the form that uses under Joint Photographic Experts Group, to transmit JPEG Huffman table information, this device comprises for the input from call number generation device reception hint number, also comprise output, this output is the decoded data word corresponding to call number.

The present invention also relates to a kind of method to data word decoding in different scope degree, and this data word is according to H.261, and the regulation clause of JPEG or mpeg standard coding comprises one to the identifier of data word past in order to the Huffman coding standard identification of coding; Some decoding step like this comprise reception Huffman coded data word, contain and read in case of necessity identifier to determine the Huffman coding of the data word that the in the past domination of which kind of standard receives, as to the response that H.261 the Huffman coded data word is identified as or the identifier of MPEG Huffman coded data word reads, comprise producing the call number relevant with each Huffman coded data that receives; Comprise that operation includes the look-up table of Huffman code table, this Huffman code table has the form that uses under Joint Photographic Experts Group, and transmitting JPEG Huffman table information, this step comprises reception hint number and produces decoded data word corresponding to the call number of receiving.

What the present invention was above-mentioned will set forth clearlyer from following more detailed description with other objects and advantages.

In the explanation of the back of enforcement of the present invention, following clauses and subclauses are frequent uses, so following vocabulary is made general definition:

Vocabulary

Piece: 8 row * 8 row PEL matrix or 64DCT coefficient (source quantizes or inverse quantization).

Colourity (component): relevant matrix, piece or the single pixel of primary colours in one of two kinds of colour difference signals of expression bit stream that coexists in institute's definition status, colour difference signal represents with symbol Cr and Cb.

The expression of coding: the expression of data element in its coding form.

The video bit stream of coding: the in the present note coded representation of defined serial one or more image.

The subsequence of coding: the order that image transmits and decodes. This order does not need with display order identical.

Component: matrix, piece or signal pixel, in its 3 matrixes that come the self-forming image (brightness and 2 colourities) one.

Compression: reduce figure place in order to represent data item.

Decoder: the entity that decoding is processed.

Decoding (processing): this illustrates that defined processing is to read the input coding bit stream and generate decoded picture or audio sample.

Display order: shown decoded picture order. Generally, the order that represents in this input with decoder is identical.

Coding (processing): a kind of processing does not describe in detail in the present note. Read the stream of input imagery or audio sample and generate one such as this defined efficient coding bit stream to be described.

Based encode: the used information of coding of macro block and image is only from macro block and image.

Brightness (component): the coexist matrix of the relation of the primary colours under institute's definition mode in the bit stream of the signal of expression monochromatic specification, piece or single pixel, brightness represents with symbol Y.

Macro block: 48 * 8 brightness data pieces and 2 (being 4: 2: 0 chroma formats) 4 (being 4: 2: 2 chroma formats) or 8 (being 4: 4: 4 chroma formats) are equivalent to 8 * 8 chroma data pieces from 16 * 16 parts of image brightness composition, macro block some the time refer to pixel data, some the time refer to resemble other data of halting in the macro block leader of syntax of numerical value and the definition of these declaratives, have the general skill person in this area for one, see that from context its usage is clearly.

Motion compensation: using motion vector is in order to improve the forecasting efficiency of pixel value, prediction be with motion vector in the past and/or in the future reference picture biasing is provided. Reference picture comprises the pels values of decoding that is used to form predicted error signal of front.

Motion vector: be used for the two-dimensional vector of motion compensation, a biasing of the coordinate of coordinate position in the reference picture from current image is provided for this reason.

Non-based encode: the coding of macro block or image was both also used macro block and the visual information that occurs in At All Other Times with the information of oneself.

Pixel: the element of image.

Image: original, the pictorial data of coding or reconstruct. Image original or reconstruct is comprised of 38 figure place rectangular matrix of showing brightness and 2 carrier chrominance signals, to progressive, an image is equal to a frame, and to interlaced video, image can represent or according to its context, is expressed as field, top or the field, the end of a frame with a frame.

Prediction: the estimation of the data element of pixel value or current decoding is provided with a fallout predictor.

Reconfigurable processing level (RPS): be a step level, in this grade in response to the token reconstruct self of identification to realize various operations.

A series of macro blocks

Token: a general suitable unit, it represents control and/or data function with the form of interactive interface packets of information.

Initial code (system and video): be embedded in unique 32 bit codes in the coding stream. They are included in the sign of some structure in the coding syntax as several purposes.

Variable length code; VLC: the process stated to coding is assigned to short coded word to the high event of frequency, and the low event of frequency number is assigned to long coded word.

Video order: a series of one or more images.

The detailed description of embodiment

As the explanation of the essential characteristic of pipeline system used in the preferred embodiment of the present invention, Fig. 1 is the instance graph in six cycles of six level production lines greatly simplified. (as described in following illustrating in greater detail, the preferred embodiment of this streamline comprises unshowned useful feature among some Fig. 1).

Referring now to accompanying drawing,, wherein same reference number in each figure of accompanying drawing TYP or corresponding element, particularly Fig. 1 the block diagram in six cycles in the example of the present invention is shown. Every row box example illustrates a cycle, and each different level is used respectively A～F mark. Each shade box shows corresponding grade of remain valid data, i.e. processed data in a pipeline stages. After processing (can comprise and only not carry out the simple transmission that data are calculated), valid data are transferred out as effective output data.

It should be noted that the actual flow waterline use can more than or less than six pipeline stages. Be interpreted as the present invention and can use the pipeline stages of any amount. Therefore, data can be processed in multistage, and the processing time not at the same level can be different.

Except clock and data-signal (below will illustrate), streamline comprises two transmission of control signals-" effectively " signal and " reception " signal. These signals are in order to control data transfer in the streamline. In the legend as the useful signal of the upstream in two row that connect adjacent level along forward or downward direction from each pipeline stages by and arrive immediate neighboring devices. This device can be other pipeline stages or some other system. For example, final pipeline stages can pass to its data following treatment circuit. In the legend as the reception signal that connects adjacent level two row middle and lower reaches, along other direction that makes progress by and reach a upper device.

The typical data pipeline system that the present invention is actual to be used has following one or more features in a preferred embodiment:

1, this streamline is " retractility is arranged ", so that delay on the specific stream pipeline stage may be disturbed minimum to other pipeline stages. Pipeline stages subsequently can continue to process, and this just means that interruption has been got through in the data flow delay-level after. Equally, above-mentioned pipeline stages also can work on may locating. In this case, any interruption can be removed from data flow in every possible place in the data flow.

2, the control signal of mediation streamline is to organize like this: they only propagate into immediate contiguous pipeline stages. For the flow direction signal identical with data flow, this is back to back next stage. For the signal opposite with the data flow flow direction, this is back to back upper level.

3, the data in the streamline are encoded in this wise, so that can process many dissimilar data in streamline. This coding is suitable for the packet of variable-size and needn't knows in advance the size of bag.

4, the auxiliary operation relevant with the explanation data type is as much as possible little.

5, concerning each pipeline stages, it is possible only identifying its data type that requires the needed minimal number of function. Yet it also should be able to pass to next stage with all data types, although it unidentified they. This just makes the communication between the non-conterminous pipeline stages become possibility.

Although not shown in Fig. 1, some data wires are arranged, i.e. single line or some parallel lines, their form the data bus of also introducing and drawing from each pipeline stages. As following illustrate in more detail, on these data wires, transfer of data is advanced, is transferred out pipeline stages and transmits between pipeline stages.

Should be pointed out that first-class pipeline stage can be by any type of said apparatus receive data and control signal. For example, the receiving circuit of digital image transmission system, other streamline or similar device. On the other hand, it self can be created in total data processed in the streamline or partial data. In fact as described below, " level " can comprise any treatment circuit, said treatment circuit comprises does not have system at all (being in order to pass through data) or whole system (for example, another streamline even a plurality of system or a plurality of streamline), and it can produce, changes and delete desired data.

When pipeline stages comprises along the downward valid data that transmit of streamline, show that VALID (effectively) signal of data validity only need to be transferred to immediate next pipeline stages again, and needn't pass fartherly. Therefore, two line interfaces are included in the system between every pair of pipeline stages. This comprises two line interfaces between preposition parts and the first order, and the interface, two wires of rearmounted parts and rear class, if such front and back parts are arranged, and data will transmit between they and streamline.

Each signal, i.e. " reception " and " effectively " has a high and low level value. These values are abbreviated as respectively " H " and " L ". In the invention of implementing, the prevailing application of streamline, most typical is digital. In such implemented in digital, high value is passable, for example is logical one, and low value can be logical zero. Yet, this system is not limited to implemented in digital, in analog realization, high value can be a voltage or be higher than other the similar quantity that (or being lower than) sets threshold value, and low value is with the corresponding signal indication that is lower than (or being higher than) this value or another threshold value. Concerning digital application, the present invention can utilize any known technology, finishes such as CMOS, ambipolar etc.

Needn't realize with each other storage device and cabling the storage of useful signal. Even also be like this in digital embodiment. The indication that whole requirements are data " validity " is stored with data. Only as an example, in the digital TV image that represents with digital value, as stipulating that in international standard CCIR601 some particular value is unallowed. In this system, use the sampled value of 8 bit representing images of binary number. Value of zero and 255 cannot be used.

If such image is processed in the streamline of setting up in the present invention's practice, one (for example zero) then may using in these numerical value points out that the data in a specific order in streamline are invalid. Therefore, any non-zero all should be thought effectively. In this example, do not have the special lock storage that can be identified and store relevant data " effectively ", however, data validity still is stored with data.

As shown in Figure 1, " H " or " L " that the state that enters every grade useful signal is used on the arrow that refers to the right on top points out. Therefore, the useful signal that enters the B level from the A level is low level, and is high level from the useful signal that the D level enters the E level. " H " or " L " that the state that enters every grade reception signal is used on the arrow that refers to left of bottom points out. Therefore, the reception signal that enters the D level from the E level is high level, and is low level from the reception signal that the device that connects the streamline downstream enters the F level.

Every when instantly connecing level and entering the reception signal that connects adjacent levels on it and be high level, during a cycle, (the following describes) data and be transferred to another level from one-level. If receiving signal between two-stage is low level, then not transmission between these levels of data.

Referring again to Fig. 1, if box is drawn hacures, as an example, the respective streams pipeline stage is believed to comprise effective output data. Equally, the useful signal that is sent to next stage from this grade is high level. Streamline when Fig. 1 example illustrates B, D and E level and comprises valid data. A, C and F level do not comprise valid data. When initial, the useful signal that enters pipeline stages A is high level, this means that in the enterprising data that enter streamline of transmission line be effective.

Also at this moment, the reception signal that enters pipeline stages F is low level, therefore, does not have data, no matter is effective or invalid, exports from the F level. It should be noted that effectively and invalid data both transmits between pipeline stages. Be unworthy the invalid data that stores to rewrite, thereby it is removed from streamline. Yet valid data needn't be rewritten because it be process or in lower connection device, use must storage data, said lower connection device is streamline, install or be connected to streamline and from the system of streamline receive data.

In the streamline that Fig. 1 exemplifies, the E level comprises valid data D₁, the D level comprises valid data D₂, the B level comprises valid data D₃, and the device (not drawing) that is connected with the upstream flow waterline comprises transmission influent stream waterline and the data D that processes therein₄ Except on the device that connects, B, D and E level comprise valid data, therefore, the useful signal that enters respectively their next stage devices from these grades or device is high level. Yet, because these levels do not comprise valid data, so be low level from the useful signal of A, C and F level.

The device that now supposition connects downwards from streamline does not prepare to receive the data of streamline. This device is put corresponding low level reception signal into the F level and is done bulletin. Yet self does not comprise valid data the F level, therefore can be from above-mentioned E level receive data. Become high level so entered the reception signal setting of E level by the F level.

Equally, the E level comprises that valid data and the preparation of F level receive these data. Therefore, as long as valid data D₁At first be transferred to the F level, the E level just can receive new data. In other words, although the downward the transmission of data of F level, all other levels can both be transmitted, and are rewritten or lose without any valid data. At cycle 1 end, data can be arrived the right by " displacement " step. This situation was shown in the cycle 2.

In the example that has exemplified, in the cycle 2, lower connection device does not also prepare to receive new data, and therefore, the reception signal that enters the F level is still low level. Owing to do like this and can cause valid data D₁Rewrite and loss, so the F level can not receive new data. Become low level so entered the reception signal of E level by the F level; Equally, because the E level also comprises valid data D₂, make the reception signal also enter the D level from the E level. Yet, all A～D level can both receive new data (because they do not comprise valid data, perhaps because they can make their valid data to following transfer and reception new data), they are high level by the corresponding reception signal setting with them, and transmit this conditioned signal to their preposition adjacent levels.

Pipeline stages after cycle 2 is illustrated in that delegation in mark cycle 3 among Fig. 1. As an example, suppose that the lower device that connects also do not prepare to receive new data (the reception signal that enters the F level is low level) from the F level. Thus, E and F level still are " blocked ", but in the cycle 3, the D level has received valid data D₃, its originally the invalid data in this grade rewritten. Because the D level can not the transmission of data D in the cycle 3₃, it just can not receive new data, is low level so will enter the reception signal setting of C level. Yet A～C level prepares to receive new data, by placing high level to do bulletin their corresponding signals that receives. Should be understood that data D₄Be displaced to the B level from the A level.

The lower device that connects of now supposition becomes to be prepared to receive new data in the cycle 4. Place high level that this information is delivered to streamline by the reception signal that will enter the F level. Although C～F level comprises valid data, they can make data be shifted downwards now, thereby can receive new data. Because therefore every one-level can both make data to following one step of displacement, they are exported separately the reception signal with it and place high level.

As long as entering the reception signal of last pipeline stages (being the F level in this example) is high level, then streamline shown in Figure 1 just serves as the streamline that is fixedly connected with, and just in each cycle data displacement is downwards gone on foot. Therefore, in the cycle 5, included data D in the F level in cycle 4₁Shift out streamline to next device, one step of other all data displacement downwards.

The reception signal that now supposition enters in the cycle 5 in the F level becomes low level. Repeat again once, this means that D～F level can not receive new data. The reception signal of exporting and enter the most contiguous higher level from these grades becomes low level. Therefore, data D₂、D ₃And D₄Can not be shifted downwards, however data D₅Can. The corresponding state of streamline is shown in the cycle among Fig. 16 after the cycle 5.

According to the preferred embodiments of the present invention, the mutually isolation because the processing level in the streamline becomes, the unappropriated ability of processing level of " filling " of streamline is very useful. In other words, although pipeline stages receive data immediately not, whole streamline also needn't stop and the latency delays level. On the contrary, when one-level can not receive valid data, it formed one interim " wall " simply in streamline. However, the lower of " wall " connects continuation secured transmission of payload data at different levels, even to the circuit that is connected with streamline, " wall " left side is at different levels still to be received and downward secured transmission of payload data. Even when some pipeline stages temporarily can not receive new data, other level still can continue normal operation. Especially as long as the A level not yet comprises the valid data that can not advance owing to next stage does not receive new data immediately, streamline just can continue receive data and enter its initial A level. So example is described, even when one or more processing grade obstruction, data still can be conveyed into streamline and at different levels between.

In the embodiment shown in fig. 1, suppose the reception signal that the every flow pipeline stage is not stored them and received from its most contiguous next stage. Generation be that when the reception signal that enters next stage became low level, the upstream propagation at different levels of this low level signal were not until comprise the most contiguous pipeline stages of valid data. For example, referring to Fig. 1, suppose that the reception signal that enters the F level in the cycle 1 becomes low level. In the cycle 2, this low level signal transfers back to the D level from the F level.

In the cycle 3, as data D₃When being locked into the D level, receiving signal and upstream transmit level Four to the C level. When the reception signal that enters the F level in the cycle 4 became high level, it must upstream transmit until the C level. In other words, the variation that receives in the signal must back pass be returned level Four. Yet, if the intergrade that exists some can receive new data in the illustrative embodiment of Fig. 1, receives the starting point that signal just needn't be delivered to passback streamline.

In the embodiment that Fig. 1 exemplifies, each pipeline stages will still need independently to input, output data latch, so that data transmit and unconsciously do not rewrite at inter-stage. Although the streamline that instantly connects gets clogged, be that they are can not transmit contained data the time, the streamline that exemplifies among Fig. 1 can " compression ", but this streamline not for comprise provide between valid data at different levels do not comprise valid data grade and " expansion ". Say that precisely compressed capability depends on some cycles of existence, does not occur valid data during these cycles before the first-class pipeline stage.

For example, in the cycle 4, keep low electricity to produce if enter the reception signal of F level, and valid data filling pipeline stages A and B, as long as valid data continue to appear at A level input, streamline can not be done any further compression, effectively input data and may lose. However, illustrated streamline among Fig. 1 is because as long as there is the pipeline stages that does not comprise valid data, it just can compress, so reduced the risk of loss of data.

Fig. 2 example illustrates another embodiment of streamline, and it can logically compress and stretch, and comprises that restriction receives the circuit that signal transmits to the most contiguous prime. The below will be at length illustrating and illustrate in order to the circuit of implementing this enforcement, and Fig. 2 is only in order to illustrate its operation principle.

Just for the ease of relatively, identical in entering input data and the reception signal among the streamline embodiment shown in Figure 2 and entering streamline embodiment shown in Figure 1. Therefore, E, D and B level include respectively effect data D₁、D ₂And D₃ Entering F level reception signal is low level, data D₄Appear at before the initial pipeline stages A. Each contiguous three right line of pipeline stages of connection shown in Figure 2. The line that can be the top of a bus is data wire. Middle that line is the line of transmission useful signal, and beneath that line is the line that transmission receives signal. And as mentioned above, the reception signal that enters the F level all keeps low level except in the cycle 4. Therefore, other data D in the cycle 4₅Before appearing at streamline.

In Fig. 2, the box indicating in two of each pipeline stages all comprises the primary and secondary data storage cell to illustrate every grade in this streamline embodiment. Every grade right half part represents the primary data memory cell in Fig. 2. Know this description just in order to illustrate, and not as limiting.

As shown in Figure 2, be high level as long as enter certain grade reception signal, data just are transferred to the secondary storage unit of next stage from the primary memory cell of this grade during any given cycle. Therefore, be low level although enter the reception signal of F level, entering all other reception signals at different levels is high level, thus in the cycle 2 data D₁、D ₂And D₃Shift forward a step, and data D₄Displacement is advanced among the first order A.

By this, streamline embodiment shown in Figure 2 works in the mode of similar streamline embodiment shown in Figure 1. Yet, be low level although enter the reception signal of F level, the reception signal that enters the E level from the F level is high level. As following illustrated, because the secondary storage unit is arranged, except the F level, low level reception signal does not just need to more prime transmission. And by allowing the reception signal that enters the E level continue as high level, it can receive new data immediately the bulletin of F level. Because the F level can not be transmitted the data D in its primary memory cell downwards in the cycle 3₁(the reception signal that enters the F level is low level) is so the E level must be with data D₂The secondary storage unit of F level is entered in transmission. Because the primary and secondary memory cell of F level both comprises the valid data that can not transmit, so the reception signal that enters the E level from the F level places low level. Therefore, this expression low level receives signal and send one-level with respect to reverse passback of cycles 2, and this reception signal must send until the C level to passback in the embodiment shown in fig. 1.

Because A～E level can transmit its data, the reception signal that enters its most contiguous prime from these grades places high level. Thereby data D₃And D₄The right shift one-level is so that in the cycle 4, they are loaded respectively the primary data memory cell of E level and C level. Although the E level comprises valid data D in its primary memory cell now₃, but its secondary memory cell still can not have in order to store other data the danger of rewriting any valid data.

As mentioned above, suppose that now the reception signal that enters the F level in the cycle 4 becomes high level. This expression streamline can be immediately from the streamline receive data to its lower connection device that transmits data. Yet the F level receives signal with it and places low level, thereby represents that to the E level F level do not prepare to receive new data. The reception signal that it is also noted that each cycle point out in next cycle with " generation " what, that is to say and point out whether data can transmit (the reception signal is high level), and perhaps whether data must remain on origin-location (the reception signal is low level). Therefore, from the cycle 4 to the cycle 5, data D₁Device below the F level is sent to, data D₂In the F level from the secondary primary memory that is displaced to, but the data D in the E level₃Be not sent to the F level. Because stage further has high level to receive signal, so data D₄And D₅Can as usually, transmit into next pipeline stages.

Compare cycle 4 and the state of streamline in the cycle 5, arranging of visible secondary storage unit can make streamline embodiment expansion shown in Figure 2, that is to say can advance wherein data storage cell of random increase valid data. For example in the cycle 4, because before the reception signal that enters the F level became high level, their data can not transmit, data block D₁、D ₂And D₃Form one " caching ". In case yet this signal becomes high level, data D₁Shift out streamline, data D₂The primary memory cell of F level is advanced in displacement, and if following device can not receive data D₂, the secondary storage unit of F level just becomes idle to receive new data. Streamline is " compression " again. This showed in the cycle 6, data D₃Be displaced to the secondary storage unit of F level, data 4 are transferred to the E level from the D level as usually.

Fig. 3 a (1),, 3a (1), 3b (1) and 3b (2) (their stack ups represent with Fig. 3) exemplify out the preferred embodiment of streamline. This preferred embodiment uses the not overlapping clock pulses of the two phase with φ 0 and φ 1 phase place to realize the structure shown in Fig. 2. Although recommended the two phase clock pulse, it will be appreciated that to drive each embodiment of the present invention also be possible with having clock pulses more than two-phase.

As shown in Figure 3, each pipeline stages represents with the box of the representative primary and secondary memory cell that two separation are arranged. And, although being connected with data wire, useful signal connects different pipeline stages, for convenience of explanation, the reception signal only is shown in Fig. 3. During some received the clock pulses phase place of signal, the variation of state used the arrow that makes progress to represent variation from the electronegative potential to the high potential in Fig. 3. Equally, downward arrow represents the variation from the high potential to the electronegative potential. The transmission of data from a memory cell to another memory cell represents with the arrow of the hollow of t. Suppose that the useful signal of exporting from these memory cells is in high potential when any elementary or secondary storage unit to deciding grade and level includes valid data.

In Fig. 3, each cycle represents with during nonoverlapping clock pulses phase 0 and φ 1 whole. As more detailed description below, (box with the left side every grade represents) is sent to primary memory cell (box with the right in every grade represents) to data from the secondary storage unit during clock cycle φ 1, and during clock cycle φ 0, data are sent to the secondary storage unit of next stage from the primary memory cell of one-level. Primary and secondary memory cell during Fig. 3 also shows every grade further connects via an internal interface take-up, so that with receiving signal passes to one-level from one-level the same manner by this internal interface collection of letters number. Like this, the secondary storage unit will know when its data can pass to primary memory cell.

Fig. 3 illustrates φ 1 phase place in cycle 1, the data D of the secondary storage unit of wherein formerly be shifted respectively E, D and b level₁、D ₂And D₃Be shifted the primary memory cell into each corresponding stage. Therefore, during the φ in cycle 11 phase place, streamline presents as the same structure the cycle 1 of Fig. 2. As mentioned above, the reception signal that enters the F level supposes it is electronegative potential. Yet as shown in Figure 3, the reception signal that enters the primary memory cell of F level is electronegative potential, but because this memory cell does not comprise valid data, places high potential so will enter the reception signal of its secondary memory cell.

Because the secondary storage unit of F level does not comprise valid data, the reception signal that enters the primary memory cell of E level from the secondary storage unit of F level also places high potential. As mentioned above, because the primary memory cell of F level energy receive data, the data in the primary and secondary memory cell of all upstreams can both be shifted downwards and be rewritten without any valid data. Data displacement from the one-level to the next stage occurs during next φ 0 phase place in the cycle 2. For example, the valid data D that in the primary memory cell of E level, comprises₁Displacement enters the secondary storage unit of F level, data D₄Displacement enters pipelining-stage, i.e. displacement enters secondary storage unit of A level etc.

Still do not comprise valid data during φ 0 phase place of the primary memory cell of F level in the cycle 2, therefore from primary memory cell enter the F level the secondary storage unit the reception signal keep high potential. Therefore during φ 1 phase place in the cycle 2, data are one step of right shift again, i.e. secondary to primary memory cell from every one-level.

Yet, if the reception signal that enters the F level from the device that connects down remains low level, in case valid data load into the primary memory cell of F level the secondary storage unit of the F level that data will be shifted out and don't rewriting and destruction valid data D₁Impossible. Enter the reception signal of secondary storage unit thereby become low level from F level primary memory cell. Yet because it does not comprise that the reception signal of valid data and its output is high level, data D₂Still can be shifted the second-level storage into the F level.

During the φ in cycle 31 phase place, although data can above-mentionedly be shifted at different levels at all, be with data D₂The primary memory cell that displacement enters the F level is impossible. In case valid data load the secondary storage unit into the F level, the F level just can not transmit these data. It receives signal setting in low level with its output, thus the generation of this event of bulletin.

Suppose that the reception signal that enters the F level keeps low level, the data of F level top can continue during each clock pulses phase place at inter-stage and level internal shift, until next valid data piece D₃Reach the primary memory cell of E level. Such as described, during the φ in cycle 41 phase place, reach this situation.

During the φ in cycle 50 phase place, data D₃Loaded into the primary memory cell of E level. Because these data can not be shifted again, the output of the primary memory cell of E level receives signal and places low electricity to produce. The data of upstream can be shifted as usually.

As in the cycle 5 of Fig. 2, suppose that the device that connects the streamline below can receive pipeline data now. It will enter pipeline stages F during the φ in cycle 41 phase place reception signal places high level, thereby sends the information of this situation. The primary memory cell of F level present energy right shift data and they also can receive new data. After this, data D during the φ in cycle 50 phase place₁Be shifted away, so the primary memory cell of F level no longer comprises the data that must preserve. During the φ in cycle 51 phase place, data D in the F level₂Be displaced to primary memory cell from the secondary storage unit. The secondary storage unit of F level also can receive new data, and the reception signal that will enter the primary memory cell of E level places high level, thereby spreads out of this information. During data transmit in level, namely secondary to its primary memory cell from it, two groups of memory cell will comprise same data, but because these data also will remain in the primary memory cell, the data in the secondary storage unit can be rewritten according to loss ground by countless. This situation is applicable to data are conveyed into next stage from the primary memory cell of one-level secondary storage unit.

The reception signal that enters now the primary memory cell of F level during φ 1 phase place of supposition in the cycle 5 becomes low level. This means that the F level can not make data D₂Send out streamline. Therefore, the F level with the reception signal setting from its primary memory cell to its secondary memory cell in low level, to prevent from rewriting valid data D₂ Yet be stored in the data D of the secondary storage unit of F level₂Can be rewritten by harmless lost territory, and so data D₃During the φ in cycle 60 phase place, be transmitted the secondary storage unit into the F level. Data D₄And D₅Can downward displacement as usually. As long as entering the reception signal of F level primary memory cell is low level, in case valid data D₃With data D₂Be stored in together the F level, then neither one secondary storage unit can receive new data, and places low level to come this information of bulletin by the reception signal that will enter the E level.

When the reception signal that enters streamline from the device that connects down from the low level to the high level or when changing on the contrary, this variation needn't transmit in streamline upward except to a most contiguous upper memory cell (in one-level or in a upper pipeline stages). On the contrary, this variation each clock pulses phase place in streamline transmits a memory cell part upward.

So example is described, and the concept of " level " is the understanding problem to a certain extent in the pipeline organization that Fig. 3 exemplifies. Because data are (from the secondary storage unit to primary memory cell) transmission in level, as it interpolar (entering the secondary storage unit of adjacent next stage from the primary memory cell of the upper level) transmission, people can think that equally level is to comprise " elementary " memory cell, are thereafter " secondary storage unit " rather than as said in Fig. 3. Therefore the concept of " elementary " and " secondary " memory cell mainly is the appellation problem. In Fig. 3, " elementary " memory cell also can be called " output " memory cell, because they are to make data spread out of the memory cell that enters next stage or next device from one-level, and " secondary " memory cell should be with one-level " input " memory cell.

In explanation above-described embodiment, shown in Fig. 1～3, only narrated data transfer under reception and useful signal control. Should be further understood that as each pipeline stages and also can before transmission between the internal storage unit of random data at streamline that its receives, perhaps before being sent to next pipeline stages, process these data. Therefore, again referring to Fig. 3, pipeline stages can be defined as and contain the input and output memory cell and optionally process the part streamline that is stored in the data in its memory cell.

In addition, need not be the hardware configuration of some other type from streamline F level downward " device ", on the contrary, it can be the part of another part or another streamline of same flow waterline. As following, pipeline stages not only can be set to reception (ACCEPT) signal of the corresponding levels low level when all the lower memory cell that connects all is equipped with the effect data, and when processing pipeline stages need to be greater than a clock pulses phase place time for finishing data, also it can be set low. When pipeline stages was set up valid data in one or two memory cell, this situation also can exist. In other words, certain grade does not need only whether to comprise that according to the most contiguous memory cell that connects down the valid data that can not transmit transmit the reception signal. On the contrary, transmit between adjacent memory cell in order to control data, also can in level or by the circuit outside the outer corresponding levels, make to receive signal change itself. Effectively (VALID) signal also can be processed with similar approach.

The very large advantage of two line interfaces (effectively with each line of reception signal) is that it just can control streamline without control signal, and said control signal must transmit against the direction of streamline until its initial level. Again referring to Fig. 1, for example in its cycle 3, F level " notice " E level it can not receive data, E level notice D level, the D level is notified again the C level. Really, as truly the more multistage valid data that comprise being arranged, then this signal can send fartherly along streamline to passback. In the embodiment shown in Fig. 3, in the cycle 3, this low level receives signal and transfers back to till the E level, and then only passes to its primary memory cell.

As mentioned above, this embodiment need not greatly increase the needed silicon area of complete design and just can reach this flexibility. That each latch that is used for data storage in the streamline only needs an independent extra transistor (it is arranged on silicon chip very effectively) representatively. In addition, preferably increase again two added latch and a small amount of gate circuit, in order to process reception and the useful signal relevant with data latches in per half grade.

Fig. 4 example illustrates the hardware configuration of finishing level shown in Fig. 3.

Only as an example, suppose that 8 Bit datas are by pipeline parallel method transmission (having or not further processing in the combinational logic circuit arbitrarily). Yet it will be appreciated that also can use in the embodiment of this invention more than or less than the data of 8 bits. In addition, be applicable to any data bus width according to these embodiment two line interfaces, and if special applications need this data bus width even can change to next stage from one-level. According to this embodiment, this interface also can be used for the signal for the treatment of of simulated.

As previously mentioned, when using other conventional timing means, the not overlapping clock control interface of the most handy two-phase. In Fig. 4～9, these clock phase signals are designated as PH0 and PH1. In Fig. 4, each the time phase place clap signal and represent with line.

The input data enter pipeline stages through long numeric data line bus IN-DATA, and are transferred to following pipeline stages through output data bus OUT-DATA, perhaps are transferred to receiving circuit subsequently. These input data at first load the input latch (one of each input data signal) that is referred to as LDIN into a group with following method, and they consist of above-mentioned secondary storage unit.

In the example that present embodiment exemplifies, suppose their the D input of Q output tracking of whole latch, that is to say that working as the clock pulses input is high level, namely they are " loaded " when the logical one level. In addition, Q output keeps its end value. Change speech this it, this Q output " being latched " is on the trailing edge of their clock pulse signals separately. Each latch has any (as shown in Figure 5) among two not overlapping clock pulse signal PH0 and the PH1, or the combination of the logical “and” of these clock pulse signals PH0, PH1 and a logical signal. By being provided at latch or any other the known latch means that latchs on the clock pulse signal rising edge, as long as conventional method is used to guarantee the correct timing of the work of latching, the present invention can work equally.

From the output data of input data latch LDIN via suitable and combinational logic circuit B arbitrarily₁Transmission, this circuit B₁To become intermediate data from the output data transaction of input register LDIN, then this intermediate data is loaded into later among the output data latch LDOUT that is comprised of above-mentioned primary memory cell. This from the output of output data latch LDOUT before being transferred to forward the next stage in downstream as OUT_DATA, equally can be by suitable and combinational logic circuit B arbitrarily₂ This can be other pipeline stages or any other device that is connected to this streamline.

In practice of the present invention, every grade of streamline also comprises effective input latch LVIN, effective output latch LVOUT, receives input latch LAIN and receives output latch LAOUT. In these four registers each preferably is simple single-stage latch. Output by latch LVIN, LVOUT, LAIN and LAOUT is respectively QVIN, QVOUT, QAIN, QAOUT. Can be used as input by the output signal QVIN of effective input register output and be directly connected to effective output register LVOUT, perhaps via intermediate logic device or the circuit that can change signal.

Equally, input that can be directly connected to effective input latch QVIN of next stage for the output useful signal QVOUT that defines the level is perhaps via the middle device that can change useful signal or logic circuit. This input QVIN also is connected to logic gates (will illustrate below), and its output is connected to the input that receives input latch LAIN. Selectively be connected to same logic gates (the following describes) via another logic gates by the output QAOUT that receives output latch LAOUT.

As shown in Figure 4, output useful signal QVOUT forms an OUT_VALIND signal that can be received by rear one-level as the IN_VALID signal, and perhaps indication is connected to the valid data of the subsequent conditioning circuit of streamline simply. To every grade of state of pointing out in order to the preparation of the lower connection circuit of receive data or level, said signal OUT_ACCEPT preferably is connected to through following logic circuit and receives output latch LAOUT as input with signal OUT_ACCEPT. Equally, receive the output QAOUT of output latch LAOUT as input, preferably be connected to through following logic circuit and receive input register LAIN.

Implementing in the middle of the present invention, from output signal QVIN, the QVOUT of effective register LVIN, LVOUT respectively with receive signal QAOUT, OUT_ACCEPT combination, to form respectively receiving the input of latch LAIN, LAOUT. In the embodiment that Fig. 4 exemplifies, these input signals make up and form as each useful signal QVIN, QVOUT and each logic NAND that receives the logic negate of output signal QAOUT, OUT_ACCEPT. Conventional gate NAND1 and NAND2 carry out NAND work, and phase inverter INV1, INV2 form each logic negate that receives signal.

As known in digital design techniques, when its input signal is the logical zero state when any or all, be logical one from the output of NOT-AND gate. So, only when it all is input as the logical one state, be logical zero from the output of NOT-AND gate. What business of this trade was known is, when its input signal was " 0 ", the digital phase inverter for example output of INV1 was logical one, and when its input signal was " 1 ", its output was " 0 ".

Input to NOT-AND gate NAND1 is QVIN and NOT (QAOUT), and its " NOT " refers to the binary system paraphase. Use known technology, can press following formula to the input that receives latch LAIN and solve:

NAND(QVIN，NOT(QAOUT))＝NOT(QVIN) OR QAOUT

In other words, when signal QVIN be " 0 " or when signal QAOUT be " 1 ", when perhaps both occurred simultaneously, the combination of phase inverter INV1 and NOT-AND gate NAND1 was logical one. Gate circuit NAND1 and phase inverter INV1 can finish with single OR-gate, and one of its input directly relies on the QAOUT output that receives latch LAOUT, and another is inputted, and relies on the anti-value of the output signal QVIN of effective input latch LAIN.

As known in digital design techniques, the many latch that are suitable for use as effectively and receive latch can have two output Q and NOT (Q), i.e. Q and its logical inverse value. If select such latch, then can directly rely on NOT (Q) output of effective latch LVIN to an input of OR-gate. Gate circuit NAND1 and phase inverter INV1 can finish with conventional known technology. Yet rely on used latch structure, using can be more effective without the latch of anti-phase output, replacement provide gate circuit NAND1 and phase inverter INV1, the two also can be finished in silicon device effectively. Therefore, any known device can be used for producing Q signal and/or its logical inverse value.

When the clock pulses signal (is PH0 at input side, PH1 at outlet side) with from the output of the reception latch of the same side both during logical one, data and effectively latch LDIN, LDOUT, LVIN and LVOUT load their data inputs separately. Like this, clock pulse signal (PH0 of input latch LDIN and LVIN) and each receive the output of latch (being LAIN in this case) and use in the logical “and” mode, when they both during logical one, only load data.

In special applications, the CMOS device of latch for example, the control latch loads the logical “and” operation of (CK through having illustrated or enable " input "), can be connected to the usual manner that the MOS transistor gate circuit that is connected in series uses finish at an easy rate in the input line of latch by making each enable input signal (for example PH0 and be the QAIN of latch LVIN and LDIN). Therefore, must provide actual logical “and” door, it may produce timing problems owing to postpone transmission in high-speed applications. So the AND gate shown in the figure only shows the logic function of finishing in the enable signal that produces various latch.

Thereby only as PH0 and QAIN both during logical one, data latches LDIN loads the input data. When in two signals any one becomes " 0 ", it will latch these data.

Although only among clock pulses phase signal PH0 or the PH1 is used as the data latches of the input that clock is added to pipeline stages (and output) side and effective latch, another clock pulses phase signal directly is used as the reception latch that clock is added to the same side. In other words, be preferably in the data latches of the clock of reception latch of streamline either side (input and output) and the same side and effective latch " not homophase ". For example, although use PH0 in for data latches LDIN and effective latch LVIN clocking CK, PH1 is used as receiving the clock of input latch.

As by two-wire effectively and the work embodiment of the streamline expanded of receiving circuit, suppose at first input at circuit do not exist from before pipeline stages, perhaps valid data from transmitting device. In other words, suppose reset recently from system after, do not become " 1 " to effective input signal IN_VALID of the level that exemplifies. Also suppose after system's last reset and spent several clock cycles, correspondingly, circuit has reached the condition of stable state. During the next positive period of clock pulses PH0, be used as " 0 " from effective input signal QVIN of effective latch LVIN and load. During the next positive period of clock pulse signal PH1, be used as " 1 " to the input that receives input latch LAIN (through gate circuit NAND1 or another gate equivalent circuit) and load. In other words, because the data in data input latch device LDIN are not effectively, so this grade sends the information (because it does not keep the data of any worth preservation) that it prepares to receive the input data.

Should point out that in this example signal IN_ACCEPT is used to enable data and effective latch LDIN and LVIN. Because at this moment IN ACCEPT is " 1 ", these latch are worked as conventional transparent latch effectively, so that regardless of being what data in the IN_DATA bus, first-class becomes " 1 " to clock pulses signal PH0, just all put into data latches LDIN. Certainly, needing only from its output QAOUT that receives latch is " 1 ", and these valid data also will be put into the next data latches LDOUT of next pipeline stages.

Therefore, as long as data latches does not comprise valid data, during the next positive period of its each clock signal, it receives or " loading " any data that offer it. On the other hand, such invalid data do not pack into any reception signal from its corresponding reception latch be low level (i.e. " 0 ") those the level. In addition, needing only corresponding IN_ VALID (or QUIN) signal from the output signal of effective latch (it forms effective input signal to next effective latch) is low level to effective latch, just keeps " 0 ".

When the input data that arrive data latches were effective, useful signal IN_VALID pointed out this state by bringing up to " 1 ". Then the output of corresponding effectively latch its separately the next rising edge of clock pulses phase signal constantly bring up to " 1 ". For example, when when the constantly corresponding signal IN_VALID of the next rising edge of clock pulses phase signal PH0 becomes high level (namely bringing up to " 1 "), effective input signal QVIN of latch LVIN just brings up to " 1 ".

Now supposition replaces data input latch device LDIN and comprises valid data. If data output latch LDOUT prepares to receive new data, it receives signal QAOUT will be " 1 ". In this case, during the next positive period of clock pulse signal PH1, data latches LDOUT and effective latch LVOUT will be enabled, and data latches LDOUT will be loaded in the data that its input exists. Because clock pulse signal is nonoverlapping, this will occur in the next rising edge front of another clock pulse signal PH0. Therefore, at the next rising edge of PH0, above-mentioned data latches (LDIN) latchs the new input data that will not latch before the data that transmit from latch LDIN from prime safely at data output latch LDOUT.

Therefore, the data latches of the energy receive data that each is adjacent adopts same operation to (in one-level or between the adjacent level), because they will be according to the phase place work that replaces of clock pulses. Any data latches of not preparing to receive new data, because it comprises the valid data that can not transmit, to there be a low level output to receive signal (receiving the QA output of latch LA from it), and will not load its data latches LDIN or LDOUT, after this, as long as it is low level giving the reception signal (from the output that receives latch) of every side (inputing or outputing) of deciding grade and level or level, will not load its corresponding data latch.

Fig. 4 also illustrates included in a preferred embodiment reset feature. In the example that exemplifies, reset signal NOTRESET0 is connected to paraphase the RESET input R (anti-phase represent with small circle) of effective output latch LVOUT as routine. As everyone knows, this means whenever reset signal NOTRESET0 becomes " 0 " that effectively register LVOUT will be forced to output " 0 ". A benefit that (becomes " 0 ") when reset signal becomes low level latch is resetted is the intermittence in the transmission this latch will be resetted. Then whenever effective transmission beginning and reset signal become high level, they will be in their " zero-bit " or reset mode. Therefore, on-off action that reset signal NOTRESET0 rises digital " ON/OFF ", in order to drive streamline, it must be in the high potential value.

Should point out that the latch that needn't make in the streamline all hold valid data resets. As describing among Fig. 4, effectively input latch LVIN directly resets with reset signal NOTRESET0, and would rather say Indirect reduction. Suppose that reset signal NOTRESET0 drops into " 0 ". Effectively output signal QVOUT also drops to " 0 ", and is irrelevant with the state before it, becomes high level to the input that receives output latch LAOUT (through gate circuit NAND1) subsequently. Receive output signal QAOUT and also bring up to " 1 ". Then, this QAOUT value " 1 " conduct " 1 " is sent to the input that receives input latch LAIN and irrelevant with the state of effective input signal QVIN. Then at the next rising edge of clock pulse signal PH1, receive input QAIN and bring up to " 1 ". Suppose that useful signal IN_VALID resets to " 0 " exactly, then at the next rising edge of clock pulse signal PH0, will become " 0 " from the output of effective latch LVIN, just as its direct reduction.

So example is described, must be only at the side of every grade (comprise rear class) effective latch that resets, in order to reset whole effective latch. In fact, each other effective register needn't reset in many application: if two phase place PH0, PH1 of clock pulses greater than a complete cycle during can guarantee that reset signal NOTRESET0 is low level, then in front the pipeline stages effectively latch " automatically reseting " (sending reset signal to passback) will occur. In fact, if reset signal keeps low level in the clock pulses two phase place has the so much whole periodicity of pipeline series at least, just need only in last pipeline stages, directly effective output latch be resetted.

Fig. 5 a and 5b (being referred to as Fig. 5) example illustrates sequential chart, it illustrates the relation between nonoverlapping clock pulse signal PH0, the PH1, the effect of reset signal, with different arrange effectively and receive maintenance and the transmission of the data of signals, said maintenance and transmission be the pipeline stages both sides that dispose in the embodiment shown in fig. 4 and between them. In the illustrative example, supposing need not be by inserting logic block B from the output of data latches LDIN, LDOUT in the time diagram of Fig. 5₁、B ₂Further processing transmit. This is as an example and unrestricted. It will be appreciated that between the data latches of continuous pipeline stages, perhaps between the input and output side of independent pipeline stages, can comprise any combined logical structure. The value of the actual input data that exemplify (for example hexadecimal data word " aa " or " 04 ") also only is illustrative. As mentioned above, as long as other memory device of data latches can be admitted and latch, perhaps store the value of every bit or input word, then input data bus can have any width (and even can simulate).

Preferred data structure-" token "

In application example shown in Figure 4, because not comprising, any level do not avoid making the input data communication device to cross its combined logic block B₁、B ₂Etc. control circuit, so every one-level is processed all input data. For larger adaptability is provided, the present invention includes a data structure, wherein " token " is in order to distribute data in whole system and control information. Each token is comprised of a series of binary bits that separately enter one or more token blocks. In addition, bit is a kind of in the three types: address bit (A), data bit (D), extended bit (E). As an example rather than as limiting, tentation data is transmitting as word with the equal 8 bit buses of 1 bit expanded bit line. The example of four word tokens is to arrange by transmission:

The first word E A A A D D D D D

The second word E D D D D D D D D

The 3rd word E D D D D D D D D

The 4th word E D D D D D D D D

Should point out that extended bit E (best) is used as replenishing each data word. In addition, the length of address field is variable, preferably just transmits after the extended bit of the first word.

Therefore, token is comprised of one or more words of (binary system) digital data in the present invention. Each this word transmits in turn and preferably concurrently, although this transfer approach not necessarily: some uses the serial data of known technology to transmit also is possible. For example, in video analyzer, parallel transmission control information, and serially-transmitted data.

Illustrated such as this example, each token preferably has a address field (string that the A bit is initial) in order to identify data type included in the token at initiating terminal. In great majority are used, for the part that transmits whole address field, single character or a word is enough, but this is dispensable according to the present invention, as long as corresponding pipeline stages comprises logic circuit, this logic circuit just can be stored the expression of some sufficiently long part address field, so that these levels receive the decode whole address field.

Should point out that the transfer address field does not need industrial siding or register. The transmission of usage data position. As described below, if do not want to drive with specific address field, streamline just can not slow down, and that is to say that pipeline stages can transmit token without delay.

The data redundancy part of following address field in token is not used the constraint of token. These D-data bit can adopt arbitrary value, and these represented meanings here are unessential. That is to say that the meaning of data can change, for example, depend on a certain particular moment position of in system, being placed of data. The quantity of additional data D can be long or short as required after address field, and the number of data word can greatly change in different tokens. Address field and extension bits are used to control signal is sent to pipeline stages. Because the number of words in the data wire (D Bit String) can be arbitrarily, the information of transmitting in data field also can correspondingly change. Therefore, following explanation is the use for address bit and extension bits.

In the present invention, when some circuit block diagrams connected together in fairly simple structure, token was useful especially. The simplest structure is the streamline for the treatment of step. Structure shown in Figure 1 for example. Yet token is not limited to only be used on the pipeline organization.

Suppose that again each box represents a complete pipeline stages. In the streamline of Fig. 1, data flow in the drawings from left to right. Data enter machine and transmit and advance to process level A. These data can be revised or do not revised to this level, then these data is sent to the B level. This modification can be complicated at random if any, and usually sends the different of data item number at different levels and output to. The B level has again changed data and has delivered to the C level, and so on. In such as this scheme, data can not transmit round about, so that the C level can not be sent to data the A level. This restriction usually allows fully.

On the other hand, although directly do not connect between the two-stage, wish very much A level energy and the communication of C level. A level and the communication of C level can only be passed through the B level. One of advantage of token is that they have the ability to realize this class communication. Because any processing level just allows it not be sent to subordinate to its unacquainted token simply with not changing.

According to this example, in each token, extension bits and address and data field transmit together so that one process level can fully needn't be to its address decoder by a token (it can be random length). According to this example, any one extension bits is the token of HIGH (one " 1 "), and the back and then is a word subsequently of the part of same token. This word also has an extension bits, and it shows whether an other word is arranged in token. When one-level runs into the token that an extension bits is LOW (one " 0 "), just know that this is the last character of token. So next word is counted as the first character of a new token.

Note, although it is particularly useful to process the simple stream waterline of level, should understand the more complicated structure that token can be used for processing unit. The example of a more complicated processing unit is described in down.

According to the present invention, unnecessary state with extension bits namely the extension bits reset, is used as the signal of the last word of a given token. The other method that replaces this priority scheme is to change the expansion bit position, and it is shown is the first character of token rather than last word. In decoding hardware, make corresponding changes and just can realize this point.

With extension bits of the present invention as the advantage of the signal of the last character in the token rather than first character be, usually useful for the characteristic of revising a circuit. This modification depends on whether token has extension bits. One of this example is that a token works that one-level of processing the video quantizing value. The video quantizing value is stored in (typically storage component part) in the quantization table. For example, table that comprises 64 8 any bigits.

In order to fill a new quantization table to the quantizer level of streamline, " QUANT_ TABLE " token is sent to quantizer. In this case, suppose that token comprises 65 token words. First character comprises " QUANT_TABLE " code, namely sets up a quantization table. This back is 64 words and then, and they are the integers in the quantization table.

When being video data encoding, must transmit such quantization table once in a while. In order to realize this function, can not deliver to the quantizer level with the QUANT_TABLE token of expansion word for one. See this token and notice that the extension bits of its first character is low, the quantizer level can be read its quantization table, and builds a QUANT_TABLE token. This token comprises 64 and quantizes tabular value. The extension bits of first character (it is originally LOW) becomes HIGH, and token continues with some HIGH extension bits, until the new end of token. Extension bits with the 64th quantification tabular value is the new end that LOW shows token. In whole system, carry out in this typical mode and be encoded into bit stream.

Continue to see this example, whether quantizer puts 1 according to the extension bits of the first character of QUANT_TABLE token, fills a new quantization table to its memory device, perhaps reads its table from memory device. So, whether select in a token with the signal of extension bits as first or last token word, depending on will be with the system of streamline. According to the present invention, two kinds of alternative methods all are possible.

Another alternative method to the extension bits scheme of preferential use is to begin to comprise length counting at token. This token that is arranged in can be beneficial to when very long, such as, efficient is high. For example, in a known applications, suppose that a typical token is 1000 word lengths. With extension bits scheme described above (with the position that invests each token word), in order to comprise all extension bits, token must need 1000 extra positions. Yet, token length is only needed 10 with the binary form coding.

So although long token has some use, experience shows that short token also has many use. Here, this preferential extension bits scheme of using is favourable. If a token only has a word length, then only need one and make this sign. Yet counting scheme typically must require same 10 as before.

The shortcoming of length counting scheme comprises following aspect: 1) not high to short token efficient; 2) token has been added maximum length restriction (only with 10, can not to greater than 1023 word counts); 3) producing necessary known token length before the counting (this chances are token the zero hour); 4) every circuit of processing token may need to have the hardware of pair word count; With 5) if whether counting is just in case destroyed (because a data transmission error), just unclear can being restored.

According to the present invention, the advantage of extension bits scheme comprises: 1) pipeline stages does not need to comprise the circuit piece to each token decode, because unrecognized token is only considered extension bits and can be allowed it correctly pass through; 2) to all tokens, the coding of extension bits is same; 3) to token length without limits; 4) to short this scheme efficient of token high (aspect the overhead of expression token length); 5) can naturally finish error correction. If an extension bits is destroyed, then will produce a token (when the destruction of an extension bits is when becoming " 0 " from " 1 ") or lose a token (destruction of extension bits is to become " 1 " from " 0 ") at random. In addition, problem is confined to some related tokens. After that token, automatically restart true(-)running.

In addition, the length of address field can change. This is very favorable, because it allows the most frequently used token to be compressed to minimum number of words. This is very important equally in the video data pipeline system, because it guarantees that all process level and can move continuously at full bandwidth.

According to the present invention, for the length that allows address field is variable, the address is chosen such that so that the back follows the short address of random data to obscure mutually with long address never. By the famous technology of first discovery of Huffman, therefore, namespace uri is " Huffman Code " to the preferential technology of using of address code field. (address field also is used as " code " of the pipeline stages that activates an expection). Yet there is the people of the general technical ability of one's own profession can know that other encoding schemes also can successfully be used.

Although encoding at Digital Design field Huffman is that everybody is very familiar, following example provides the background of a summary:

The Huffman code comprises the word (in the situation of digital display circuit, just as among the present invention, symbol is binary digit normally) that is comprised of a symbol string. The variable-length of code word. The special characteristics of Huffman code word is that code word is chosen such that so that neither one long code word is with forming sign-on of short code word. According to the present invention, the token address field is preferentially selected famous Huffman coding techniques (although dispensable).

In this invention, address field is also preferential from the highest significant position (MSB) of first character token. (notice that the appointment of MSB is arbitrarily, the difference that this programme can be revised to adapt to MSB is specified). Address field extends to contiguous some than low order. In a known applications, require more than a token word such as a token address, namely exceeded the least significant bit in arbitrary given word, this address field will be extended to the highest significant position of next word. The minimum length of address field is one.

In the present invention, any in some known hardware configurations can be used to produce token. One of this class formation is little programming state machine. Yet known microprocessor or miscellaneous equipment are also available.

According to the present invention, the major advantage of token scheme is that it is to the adaptive capacity of unexpected needs. For example, if introduce a new token, maximum possibility is that this will only affect a small amount of pipeline stages. Most probable situation is, only affects two-stage or two circuits, namely at first produce token that and newly designed or revised to process that or that one-level of new token. Note, unnecessaryly go to revise any other pipeline stages. Or rather, these grades do not need their design made an amendment and just can process new token, because the new token of their nonrecognition just correspondingly allows that token not pass through with being modified.

The present invention have the ability to keep a large amount of device already present, that designed unaffected. This ability has obvious advantage. The impact that keeps some semiconductor chip in the core assembly sheet not to be subjected to other chip in this group to improve design fully is possible. See it all is favourable from the viewpoint of user and chip maker. Mean because the design change has influence on (because the increase of integrated level of all chips even revise, an intrasystem core number reduces, the more and more possibility so this situation becomes), same design still having considerable advantage than otherwise aspect the time of putting on market, because can be reused.

Pay special attention to when expanding to situation about occuring when comprising two word address to the token group. Even in this situation, still already present design of unnecessary modification. Token decode device in pipeline stages can be attempted to the decoding of the first character of such token, and can make a decision it and can not identify this token. Then it can be pass by unaltered token passing, utilizes extension bits correctly to carry out this operation. It can not attempted to second word decoding (even this is comprising address bit) of token, because the part of the token data field that second word of its meeting " supposition " is it can not be identified.

In many cases, a pipeline stages or an associated circuit piece can be revised token. This but is not necessarily normally, takes to revise the mode of the data field of a token. In addition, common situation is to revise the number of data word in the token, perhaps removes some data word or adds some new words. In some situation, some tokens are left out from token streams fully.

In great majority were used, pipeline stages can be typically only to minority token decode (only being started by the minority token); Other token of this grade nonrecognition and do not allow them pass through with not changing. In many cases, only have a token decoded, i.e. data token word itself.

In many application, the result that it operates is in the past usually depended in the operation of an a specific order. Therefore, " state " of this one-level depends on its state in the past. In other words, this one-level depends on the status information of storage. Another saying is that it must keep the one or more cycles in the past about its own some historical information. The present invention is not only applicable to that latch is the application of simple pipeline latch in data path, is applicable to well comprise the streamline of such " state machine " level yet.

According to the present invention, two line interfaces are very large advantages of the present invention to the applicability of above-mentioned state machine circuit. In the place of controlling data path with state machine especially like this. In this situation, " current state " that two above-mentioned line interface technology can be used to the Guarantee Status machine keep and streamline in the data controlled synchronous.

Fig. 6 represents the simplified block diagram of an example of circuit. This circuit is included in one in the pipeline stages of token address field decoding. It represents the pipeline stages with " state machine " characteristic. Each word of token comprises one " extension bits ", and when in token more word being arranged, extension bits is high (HIGH), as for the last character of token then extension bits be low (LOW). If this is the last character of token, next valid data word is the beginning of new token, so its address must be decoded. In any given word, whether to the decision of token address decoding, depend on the value of the extension bits of knowing the front.

The reason in order to simplify just, two line interfaces (and accept and make useful signal and latch) are undeclared in the drawings, and the details that all process circuit reset also is omitted. With in the past the same, be assumed to 8 words just for for example, not in order to limit.

The streamline of this demonstration makes data bit and extension bits postpone a pipeline stages. It is also to the data token decode. When the first character of data token appeared at the output of circuit, signal " DATA_ADDR " was produced and is set to " HIGH ". Data bit is by LDIN and LDOUT latch delay. For 8 data bit that are used for this example, each in two latch repeats (corresponding 8-input, 8-output latch) 8 times. Similarly, extension bits is expanded a latch LEIN and LEOUT delay.

In this example, latch LEPREV is provided the nearest state of being used as the Memory Extension position. The value of the extension bits LEIN that packs into, LEOUT then packs into when the next rising edge of not overlapping (non_overlapping) clock phase signal PH1 arrives. So only at second of non-overlapped two phase clock during half, latch LEOUT comprises the value of current extension bits. Yet, when the next rising edge of clock signal PH0 is come, pack into the value of this extension bits of latch LEPREV. The enable signal of this clock signal and extension bits input latch LEIN is same signal. So during a upper PH0 clock phase, the output QEPREV of latch LEPREV can keep the value of extension bits. From the data word of anti-phase (inverting) Q output 5 add the not anti-phase MD[2 of latch LDIN], the expansion place value QEPREV with the front is combined in a series of gate NAND1, NAND2 and NOR1. Operating in the digital design techniques of these gates is that everybody knows. Symbolic representation " N-MD[m] " shows intermediate data word MD[7:0] the logical inverse of m position. Technology with known Boolean algebra, can show only have when last extension bits be the structure of data word (input word originally) of output place of " 0 " (QRPEV=" 0 ") and noninverting Q latch LDIN when being " 000001xx ", be HIGH (one " 1 ") from the output signal SA (from the output of NOR1) of this logical block. " 000001xx " this representation MD[7]-MD[3] these 5 high order tagmemes all are " 0 ", MD[2] position is " 1 ", is any arbitrary value in the position of 0～1 position. Therefore, there are 4 possible data words (" xx " has four kinds of arrangements) can make SA become HIGH. SA is connected to the input of address signal latch LADDR, so the output of LADDR latch is uprised. In other words, only when four may be suitable one of tokens occur and only when the extension bits of front when being zero, this one-level just provides an initiating signal (DATA_ADDR=" 1 "). Last time, extension bits was zero, and the data word of last time is the last character in token word string last time in other words, this means that current token word is the first character of current token.

When the signal QPREV that comes from latch LEPREV is LOW, be the first character of a new token in the value of latch LDIN output place. Gate NAND1, NAND2 and NOR1 decode to data token (000001xx). Yet this address decoding signal SA is delayed in latch LADDR, so that signal DATA_ADDR has same timing with output data OUT_DATA and OUT_ EXTN.

According to the present invention, Fig. 7 is the example of the relevant pipeline stages of another state, and it produces the LAST_OUT_EXTN signal to show the value of previous output extension bits OUT_EXTN. Add till now with a upper extension bits latch (they are respectively LEOUT and LEPREV) on two enable one of number of making (in the CK input) and obtain from gate AND1 so that these latch only data effectively and data just be they new values (export Q that effective latch LVOUT and output accepts latch LAOUT export all be height) of oneself packing into when just received. Like this, they are only remained valid extension bits and are not packed into and the associated value that does not meet logic of invalid data. In concrete device shown in Figure 7, two lines effectively/RL comprises OR1 door and OR2 door, their input signal is that the paraphase of the reception signal in downstream and the effective latch that is respectively LVIN and LVOUT is exported. This has enumerated a kind of method: if latch has anti-phase output, NAND1/2 door and INV1/2 door among Fig. 4 can be substituted.

Although this is the extremely simple example of the pipeline stages of " state is relevant ", that is, it only depends on the state of a single position, and only when data really transmitted between streamline, the state that keeps in all latch just can be updated. This point is general correct. In other words, only when data be when not only effectively but also having been received by next stage, the state in the latch just can be updated. Correspondingly, must guarantee that carefully these latch reset suitably.

According to the present invention, the generation of token has been compared several advantages with the coding techniques that use is crossed the streamline transmission with known data communication device.

The first, as mentioned above, token makes the address field (and for example, it is next to utilize Huffman to encode) of different length that the representation of the high token commonly used of efficient is provided.

The second, the consistent compilation of token length is so that the end of token (thereby beginning of next token) the correct processing of quilt (comprise and simply do not process transmission). Even the token that token decode device circuit can not be identified in given pipeline stages also can correctly be processed.

The 3rd, the rule that the token that is not identified (namely not transmitting them) is processed with changing and hardware configuration be not so that the one-level in the streamline can and be communication between its next-door neighbour's the downstream stage. This has also increased extendible ability and the high adaptive capacity of efficient of streamline, does not need existing pipeline stages is reseted meter on a large scale because it makes when changing the token group in the future. Token of the present invention with top and below two line interfaces that all mentioned particularly useful especially when using together.

As an above-mentioned example, Fig. 8 a and 8b are taken at together (the following Fig. 8 that collectively is referred to as), describe the block diagram of a pipeline stages. Its function is as follows. If this grade processed a predetermined token (being known as data token in this example), then each word in its meeting duplicate tokens is removed beyond the first character. The address field that comprises data token in the first character. On the other hand, if this grade processed the token of any other type, it can delete each word. Final effect at output is that each word that only occurs in data token and these tokens repeats twice.

Many parts in this example system may be the same with those parts that are shown in the structure simply too much among Fig. 4,6 and 7 of having described. This has illustrated a very large advantage. More complicated pipeline stages can still be enjoyed same flexibility and the benefit of retractility, because two same line interfaces can not need be changed a social system or seldom change a social system and be used. Data Replica level shown in Fig. 8 only is an example of the dissimilar operation of pipeline stages can be finished in any known applications countless versions. Yet this " replication order " is the level that can form " bottleneck ", so that according to this specific implementation, the streamline meeting " is crowded together ".

" bottleneck " can be any level, perhaps its time complete operation that will relatively grow, and the data that perhaps its generates in streamline are more than its reception. This example illustrates that also according to this specific implementation, two line reception/valid interfaces can adapt to different application at an easy rate.

Replication order shown in Figure 8 also has two latch LEIN and LEOUT, example as shown in Figure 6, and they pin the state in the extension bits of the input of this one-level and output respectively. Shown in Fig. 8 a, input expanding position latch LEIN and input data latch LDIN and to make useful signal IN_VALID be clock synchronous.

In order to be easy to consult, the various latch and their the output signal pairings separately that are included in replication order are as follows:

At replication order, from the output of data latches LDIN, form the intermediate data that is known as MID_DATA. This intermediate data word is only when indirect trusted number (being designated as " MID_ACCEPT " in Fig. 8 a) when being set to HIGH, the data of just packing into output latch LDOUT.

The line system shown in below receiving latch LAIN and LAOUT is the circuit that is added to the basic pipeline structure among Fig. 8, to produce various internal control signals. These signals are used for copy data, comprise " DATA_TOKEN " signal, and it shows that current what processing is a valid data token to circuit, also comprises the NOT_DUPLICATE signal, and it is used for controlling copying of data. When circuit during just at the deal with data token, the NOT_DUPLICATE signal changes between a HIGH and a LOW state, and this makes each word in the token be replicated once (but not being repeatedly). When circuit is not to process a valid data token, then NOT_ DUPLICATE signal remains on the HIGH state. Correspondingly, this means that the token word of processing is not replicated.

Such as Fig. 8 a explanation, higher 6 and form the input of gate group NOR1, NOR2, NAND18 from the output signal that latch LI1 comes in 8 of the intermediate data words. The output signal of coming from gate NAND18 is marked as S1. Can find out with well-known Boolean algebra, only when output signal QI1 be that " 1 " and NID_DATA word have following structure: when " 000001xx ", signal S1 is only " 0 ". Structure " 000001xx " shows that higher five all is " 0 ", MID_DATA[2] be " 1 ", at MID_DATA[1] and MID_DATA[0] there is any arbitrary value the position. So signal S1 serves as " token identification signal ", only S1 is only low when MID_ DATA has a structure of being scheduled to and the output from latch LT1 to be " 1 ". The characteristic of latch LI1 and its output QI1 further specifies as follows.

The function that the last value of extension bits to the centre (be designated as " MID_EXTN " and as signal S4) of finishing latch LO1 latchs is come then its latch LI1 that this value is packed at the accompany next rising edge of PH0 of clock. The output of LI1 is a QI1, and it also is one of the input that forms the token decode logical groups of signal S1. As described above, signal S1 only when signal QI1 is " 1 " (and the MID_DATA signal has predetermined structure), just can be reduced to " 0 ". So, whenever a upper extension bits is " 0 ", show that when a token had finished, signal S1 just can be reduced to " 0 ". So the MID_DATA word is first data word of a new token.

Latch LO2 and LI2 and NAND gate NAND20, NAND22 are DATA_TOKEN signal formation memory together. In normal condition, the signal QI1 of NAND20 input and the signal S1 of NAND22 input both can be at the logical one state. Can find out with the Boolean algebra technology that again the working method of these NAND gates is the same with phase inverter in this case, i.e. the output signal QI2 of latch LI2 paraphase in NAND20, then this signal forms signal S2 again by NAND 22 paraphase. In this case, because twice logic paraphase arranged in the path, signal S2 has the value identical with QI2.

Can find out that also the DATA_TOKEN signal forms input to latch LI2 at the output of latch LO2. As a result of, if QI1 and S1 both the situation of HIGH remain unchanged, signal DATA_TOKEN will keep its state (no matter being " 0 " or " 1 "). Even clock signal PH0 and PH1 are to latch (being respectively LI2 and LO2) when latching, this also is correct. Only have as signal QI1 and S1 when both " 0 " or one of them are " 0 ", the value of DATA_TOKEN could change.

Such as earlier time explanation, when the extension bits when the front was " 0 ", signal QI1 is " 0 " always. So when the MID_DATA value is the first character of token (so also comprising the address field of token), signal QI1 is " 0 " always. In this situation, signal S1 can be " 0 " or " 1 ". Such as earlier time explanation, if the MID_DATA word has in this example the predetermined structure that is indicated as being " data " token, signal S1 will be " 0 ". If MID_ DATA word has other any structure (indicating token is certain other token, is not a data token), S1 will be " 1 ".

If QI1 is " 0 " and S1 is " 1 ", this shows the token that certain different pieces of information token is arranged. In the digital electronics field, well-known, the output of NAND20 must be " 1 ". NAND gate NAND22 can anti-phase it (illustrating such as the front), so signal S2 will be " 0 " as a result of, when next PH1 clock phase begins, this " 0 " value can be loaded into latch LO2, the DATA_TOKEN signal can become " 0 ", and what show that circuit processing is not data token. Signal S2 if QI1 is that " 0 " and SO are " 0 ", thereby shows it is a data token, so will be " 1 " (no matter what other input of NAN22 that comes from NAND20 output is). As a result, when next PH1 clock phase began, this " 1 " value can be loaded into latch LO2, and the DATA_TOKEN signal can become " 1 ", showed that circuit processing a data token.

NOT_DUPLICATE signal (output signal QO3) is loaded into latch LI3 similarly when the next rising edge of clock PH0 arrives. The output signal QI3 of latch LI3 and output signal QI2 are combined into signal S3 in gate NAND24. With in the past the same, Boolean algebra can be used to show, only when two signal QI2 and QI3 had value " 1 ", signal S3 just can be " 0 ". If signal QI2 becomes " 0 ", namely the data token signal is " 0 ", and then signal S3 becomes " 1 ". In other words, if neither one valid data token (QI2=0) or data word are not a duplicate (QI3=0), then signal S3 uprises.

Now supposition, during more than a clock signal, the data token signal remains height. Because NOT_DUPLICATE signal (QO3) " feedback " arrives latch LI3, and can be by gate NAND24 paraphase (because its another input QI2 keeps HIGH), output signal QO3 will saltus step between " 0 " and " 1 ". If yet there is not the valid data token, signal QI2 can be " 0 ", and signal S3 and output QO3 can be forced to HIGH, until DATA_ TOKEN signal becomes " 1 " again.

Output QO3 (NOT_DUPLICATE signal) also is fed and combines with the output QA1 that accepts latch LAIN in a series of gates (NAND16 and INV16, their common formation and doors). When only the value as QA1 and Q03 all was " 1 ", the output of gate was only " 1 ". Shown in Fig. 8 a, also form with the output of door (gate NAND16 follows the back gate INV16) and to receive signal IN_ACCEPT. Cross as described above, this signal is used for two line interface structures.

Receive signal IN_ACCEPT also with making to latch LDIN the enable signal of LEIN and LVIN. As a result, if the NOT_DUPLICATE signal is low, it also can be low receiving signal IN_ACCEPT, and all these three latch can be under an embargo, and can keep the value of storage at their output. Before the NOT_DUPLICATE signal uprises, the corresponding levels will not receive new data. In order to force reception latch LAIN to be output as height, except aforesaid ask for something, also replenish with this.

As long as a valid data token (DATA_TOKEN signal QO2 is " 1 ") is arranged, signal QO3 will saltus step between HIGH and LOW state, so that input latch can and may be accepted data at the most in two clock phase PH0 and PH1 every other week complete cycle separately. The next stage that shows with " HIGH " OUT_ACCEPT signal has been ready to receive data, and these additional conditions must still be satisfied certainly. So output latch LDOUT will be put into same data word on the output bus OUT_DATA, this continues two complete clock cycle at least. Only as data token effective (QO2 HIGH), when making useful signal QVOUT be HIGH again, OUT_ VALID signal just can be " 1 ".

Signal QEIN is the extension bits of corresponding MID_DATA. It and signal S3 are combined in a series of gates (INV10 and NAND10) and form signal S4. Between a data token apparition, each data word MID_DATA is repeated. Method is its pack into twice of output latch. During the first time of doing like this, because the effect of NAND10, S4 can be forced " 1 " and be loaded into LDOUT formation OUT_DATA[7:0 at MID_DATA] in, signal S4 is loaded into latch LEOUT, forms OUTEXIN.

So when given MID_DATA was loaded into LEOUT for the first time, relevant OUTEXTN can be forced to uprise, and at twice, OUTEXTN can be the same with signal QEIN. Consider now this situation, known QEIN is low during the last word of a token. During the first time, the MID_DATA LDOUT that packs into, OUTEXTN can be " 1 "; And OUTEXTN can be " 0 " during the second time, shows the real end of token.

Output signal QVIN and the signal QI3 of effective latch LVIN similarly are being combined in the door combination (INV12 and NAND12) together, form signal S5. Can find out that with known boolean's technology no matter make useful signal QVIN for high, or when signal QI3 was low (showing that data are duplicate), signal S5 was high. Signal S5 packs into and makes effective output latch LVOUT, simultaneously, the MID_DATA LDOUT that packs into, middle extension bits (signal S4) is packed into LEOUT. Signal S5 and signal QO2 (data token signal) also make up in gate NAND30 and INV30, form output and make useful signal OUT_VALID. Said as earlier the time, only when effective token with when to make useful signal QVOUT be high, OUT_VALID just be height.

In the present invention, MID_ACCEPT signal and signal S5 make up in a series of gates (NAND26 and INV26), form signal S6. These gates realize known and function. Signal S5 is with making to latch LO1 one of two enable signals of LO2 and LO3. No matter when the MID_ACCEPT signal was high and makes useful signal QVIN be a duplicate (QI3 is " 0 ") for high or token, signal S6 rose to " 1 ". So if signal MID_ACCEPT is high, when clock signal PH1 be height, maybe when the data that are latched were duplicate, latch LO1～LO3 can be enabled in the input that installs to this one-level whenever effective input data.

Can find out from above discussion, can under the control that makes useful signal and reception signal, receive and the transmission data in this level shown in Fig. 8 a and the 8b, as in the concrete device in front. But an exception is arranged, and is exactly in the output signal of the reception latch LAIN of input side and the reproducing signals combination of saltus step, so that before new word will be received, a data word can be output twice.

Certainly, various logic gates such as NAND16 and INV16, can be replaced with the logic circuit of equivalence (in this situation, single and a door). Similarly, for example, if latch LEIN and LVIN have paraphase output, phase inverter INV10 and INV12 are exactly unnecessary. Or rather, the paraphase output of these latch can be directly received in the corresponding input of door NAND10 and NAND12. As long as finish suitable logical operation, this grade just can be worked under same state. Data word and extension bits still can be replicated.

Must be noted that the copy function that the example level is finished can not be done, unless first data word of token is " 1 " in the 3rd position of word, and all is " 0 " on 5 high order tagmemes. (certainly, select other gate and interconnection rather than NOR1 as shown in FIG., NOR2, the NAND18 gate can change and arrange required pattern at an easy rate).

In addition, as shown in Figure 8, during whole token, the OUT_VALID signal can be forced low, unless first data word has above-mentioned structure. Its effect is, except that token that produces reproduction process, all tokens all can be deleted from token streams, can not identify these token words as valid data because be connected to a device of output (OUTDATA, OUTEXIN and OUTAVLID).

Ditto, at the corresponding levels make effective latch LVIN, LVOUT both can make to reset with a single wire NOT_RESETO with single on the latch LVOUT of downstream and input R and reset. Simultaneously, the reset signal backpropagation makes the effective latch of making of upstream be forced to step-down in the next clock cycle.

Should be noted that in example shown in Figure 8, be included in the example as a method of only copying of data in the data token. In this method, circuit can be processed ACCEPT and VALID signal, makes the data of constantly leaving pipeline stages more than the data that constantly arrive input. Similarly, the example among Fig. 8 is got rid of all non-data tokens, is an explanation of doing such as method purely, and circuit can be handled the VALID signal and remove data from stream in this method. Yet, to use in that great majority are typical, pipeline stages can allow its Unidentified any token not pass through simply with changing, so that can work to them when needed at streamline other grade below again.

Fig. 9 a and 9b are taken at a graphic example of timing are described together. This diagram is to do for the data Replica circuit shown in Fig. 8 a and the 8b. Ditto, the timing diagram solution shows the relation between the two phase clock signal, various inside and outside control signals, the mode that the mode that data are latched between corresponding levels input side and output side and data are replicated.

In more detail with reference to Figure 10, the restructural that expression provides according to an aspect of the present invention among the figure is processed level now.

Input latch 34 is received input in first bus 31. First output of input latch is delivered to token decode subsystem 33 by line 32. Second output of input latch is delivered to processing unit 36 as its first input by line 35. First output of token decode subsystem 33 is delivered to processing unit 36 as its second input by line 37. Second output of token decode subsystem 33 is delivered to action recognition unit 39 by line 40. Action recognition unit 39 also receives input by line 46 from register 43 and 44. The state of machine is preserved in register 43 and 44 stack ups. This state is determined by the history of the token of former reception. The output of action recognition unit 39 is delivered to processing unit 36 as its 3rd input by line 38. Output latch 41 is delivered in the output of processing unit 36. The second bus 42 is delivered in the output of output latch 41.

Referring now to Figure 11,, initial code decoder (SCD) 51 receives input by two line interfaces 52. This input can or data token form or data flow in data bit. First output of initial code decoder 51 is delivered to first first in first out buffer (FIFO) 54 by line 53. The output of first FIFO54 is delivered to Huffman decoder 56 as its first input by line 55 logically. Second output of initial code decoder 51 is delivered to DRAM interface 58 as its first input by line 57. DRAM interface 58 also receives from the input of buffer manager 59 by line 60. Pass through line 61 to outside DRAM (not shown in FIG.) transmitted signal or receive signal with DRAM interface 58. First output of DRAM interface 58 is delivered to Huffman decoder 56 as its first physics input by line 62.

The output of Huffman decoder 56 is delivered to data directory unit (ITOD) 64 by line 63 as an input. Huffman decoder and ITOD64 work together as a single logical block. The output of ITOD64 is delivered to calculate by line 65 and is patrolled unit (ALU) 66. First output of ALU66 is delivered to read-only storage (ROM) state machine 68 by line 67. The output of rom state machine 68 is delivered to Huffman decoder 56 as its second physics input by line 69. Second output of ALU 66 is delivered to token formatter (T/F) 71 by line 70.

First output 72 of T/F71 of the present invention is delivered to second FIFO73 by line 72. The output of second FIFO73 is delivered to reverse moulding device 75 as its first input by line 74. Second output of T/F71 is delivered to DRAM interface 58 as its 3rd input by line 76. The 3rd output of DRAM interface 58 is delivered to reverse moulding device 75 as its second input by line 77. The output of reverse moulding device 75 is delivered to inverse quantization device 79 by line 78 as an input. The output of inverse quantization device 79 is delivered to reverse zig_zag (IZZ) 81 by line 80 as input. The output of IZZ81 is delivered to reverse discrete cosine transform device (IDCT) 83 by line 82 as input. The output of IDCT83 is by 84 time of delivery (TOD) of line decoder (not shown).

In more detail referring to Figure 12, be demonstrated according to a temporal decoder of the present invention now. Fork 91 receives the output of IDCT83 (being shown in Figure 11) as its input by line 92. As the first control token of exporting at fork 91, for example mobile vector etc. is delivered to address generator 94 by line 93. For the purpose of counting, data token is also delivered to address generator 94. As second output at fork 91, data communication device is crossed line 95 and is delivered to FIFO96. Then the output of FIFO96 is delivered to adder 98 by line 97 as first input. Deliver to DRAM interface 100 by line 99 as first input from the output of address generator 94. Pass through the DRAM (not shown) transmitted signal of 101 pairs of outsides of line or receive signal with DRAM interface 100. First output of DRAM interface 100 is delivered to predictive filter 103 by line 102. The output of predictive filter 103 is delivered to adder 98 by line 104 as second input. First output of adder 98 is delivered to outlet selector 106 by line 105. Second output of adder 98 is delivered to DRAM interface 100 by line 107 as second input. Second output of DRAM interface is delivered to outlet selector 106 by line 108 as second input. The output of outlet selector 106 is delivered to video formatter (not shown in Figure 12) by line 109.

Referring now to Figure 13,, fork 111 receives input by line 112 from outlet selector 106 (being shown in Figure 12). As first output at fork 111, the control token is delivered to address generator 114 by line 113. The output of address generator 114 is delivered to DRAM interface 116 by line 115 as the first input. As second output at fork 111, data communication device is crossed line 117 and is delivered to DRAM interface 116 as second input. Send or receive data with the DRAM (not shown) of DRAM interface 116 by 118 pairs of outsides of line. The output of DRAM interface 116 is delivered to a display pipes 120 by line 119.

Obvious from the above description in case of necessity every line can comprise many lines.

Referring now to Figure 14 a,, in mpeg standard, an images 131 is encoded as a slice (slic) or multi-disc 132. Comprise again many 133 for every 132, and line by line the coding, in every row from left to right. As shown in the figure, every 132 a lucky full line of topped 133, or be less than B or the D of delegation such as piece 133 or the C of multirow such as piece 133.

Referring to Figure 14 b, at JPEG with H.261 in the standard, taked intermediate form commonly used (CIF), an images 141 is encoded as 6 row there, and every row comprises two piece groups (GOBS) 142. Each piece group is comprised of uncertain 143 interior 3 row or 6 row of number again. Each GOB142 presses the tortuous direction encoding of arrow 144 indications. Each piece group 142 is processed successively line by line, and every row from left to right.

Referring now to Figure 14 c,, can find out that to MPEG and CIF, the output of encoder all is that the form with data flow 151 represents. Decoder receives this data flow 151. So decoder can be according to the form image reconstruction of coding. In order to make starting point and the end point of every kind of standard of decoder identification, it is some sections of 33 that data flow 151 is divided into length.

Referring to the Venn figure of Figure 15, it shows the possible range of table choosing (table selection) value of making according to Huffman decoder 56 of the present invention (being shown in Figure 11). The mpeg decoder possible values and H.261 the decoder possible values be overlapping a bit, show a single table select can to some mpeg format and some H.261 form both decode. Equally, possible some values of possible some of mpeg decoder values and jpeg decoder are overlapping, and this shows that a single table selection meeting both decodes to some jpeg format and some mpeg format. In addition, show among the figure that H.261 value and the value of JPEG are not overlapping, this shows and does not exist the single table that can both decode to two kinds of forms to select.

In more detail referring to Figure 16, it is the graphic representation of the variable length pictorial data of practice according to the present invention now. The first images 161 to be processed comprises first PICTURE_START token 162, first random length pictorial information 163, and first PICTURE_END token 164. The second images 165 to be processed comprises 166, the second random length pictorial information 167 of second PICTURE_START token, and second PICTURE_END token 168. PICTURE_START token 162 and 166 pairs of processors show visual 161 and 165 beginning. Equally, PICTURE_END token 164 and 168 pairs of processors indicate visual 161 and 165 end. Like this so that processor can be processed the pictorial information 163 and 167 of variable length.

Referring to Figure 17, dispenser (split) 171 receives input by line 172. First output of dispenser 171 is delivered to address generator 174 by line 173. DRAM interface 176 is arrived by line 175 in the address that address generator 174 produces. Pass through 177 pairs of outside DRAM (not shown) transmitted signals of line or receive signal with DRAM interface 176. First output of DRAM interface 176 is delivered to predictive filter 179 by line 178. The output of predictive filter 179 is delivered to adder 181 by line 180 as the first input. Second output of dispenser 171 is delivered to first in first out (FIFO) 183 by line 182 as input. Deliver to adder 181 by line 184 as the second input from the output of FIFO183. The output of adder 181 is delivered to write signal generator 186 by line 185. First output of write signal generator 186 is delivered to DRAM interface 176 by line 187. Second output of write signal generator is delivered to read signal generator 189 by line 188 as first input. Second output of DRAM interface 176 is delivered to read signal generator 189 by line 190 as second input. The output of read signal generator 189 is delivered to video formatter (not drawing) by line 191 in Figure 17.

Referring now to Figure 18, the predictive filtering process is described. A forward direction image 201 is delivered to adder 203 by line 202 as the first input. Deliver to adder 203 by line 205 as the second input for one backward visual 204. Adder 203 is by line 206 outputs.

Referring to Figure 19, a sheet 211 comprises one or more macro blocks 212. Successively, each macro block 212 comprises four luminance block 213 and two colour signal pieces 214, and comprises the information of 16 * 16 original pixel blocks. The size of each of four luminance block 213 and two colour signal pieces 214 is 8 * 8 pixels. Four luminance block 213 comprise brightness (Y) information that a pixel ground mapping is got from original pixel of 16 * 16 pixel blocks. A colour signal piece 214 comprises the information of the chrominance levels of blue color signal (CU/b), and another colour signal piece 214 comprises the information of the chrominance levels of blusher chrominance signal (CV/r). Each chrominance levels by double sampling (subsampled) so that each 8 * 8 colour signal piece 214 comprises the chrominance levels of whole original 16 * 16 pixel block colour signals.

Referring now to Figure 20,, the 26S Proteasome Structure and Function of initial code decoder will become apparent. Value register 221 receives pictorial data by line 222. Line 222 is 8 bit wides, and it allows 8 of each parallel conveys. The output of value register 221 is delivered to codec register 224 with serial mode by line 223. The first output of codec register 224 is delivered to detector 225 by line 226. Line 226 is 24 bit wides, and it allows 24 of each parallel conveys. Whether detector 225 detects map and exists. Reflection is followed single " a 1 " value representation corresponding to an initial code that has nothing to do with standard with 23 " 0 " value. The map of 8 bit data value is followed in effective initial code map back. When detecting the initial code map, detector 225 transmits an initial map to value decoder 228 by line 227.

The second output of codec register 224 is passed through line 229 to value decode shift register 230 with serial mode. Value decode shift register 230 can be preserved 15 long data value maps. Follow on the right of the data value value of being displaced to decode shift register 230 of 8 of initial code map back, such as regional 231 indications. Overlapping initial code map is eliminated in this processing, and discussion sees below. The first output of value decode shift register 230 is delivered to value decoder 228 by line 232. Line 232 is 15 bit wides, and it allows 15 of each parallel conveys. Value decoder 228 usefulness the first look-up table (not shown) is to the decoding of value map. The second output of value decode shift register 230 is sent to value decoder 228, and it transmits one by line 235 and is identified to token index converter 234. Value decoder 228 also arrives token index converter 234 by line 236 transmission information. Information or data value map or initial code index mapping, it obtains from the first look-up table. What sign showed transmission is any message form. Line 236 is 15 bit wides, and it allows 15 of each parallel conveys. Although the width of selecting among the present invention is 15, can see that the figure place of other length is also available. Token index converter 234 usefulness second look-up table (not shown) become the token map to information conversion. The table 12-3 that the similar user's manual of second look-up table has provided. Then, the token map that is produced by token index converter 234 is exported by line 237. Line 237 is 15 bit wides, and it allows 15 of each parallel conveys.

Referring to Figure 21, the data flow 241 that comprises some respective bits 242 is input to detector for initial code (not shown in Figure 21). Detector for initial code detects first initial code map. Then detector for initial code receives first data value map 244. Before first data value 244 of processing, detector for initial code may detect second initial code map 245, and it is overlapping on a segment length 246 with the first data value map 244. If this thing happens, detector for initial code is not processed the first data value map 244, and receives and process the second data value map 247.

Referring now to Figure 22,, identifier generator 251 is inputted receive data by line 252 as first. Line 252 is 15 bit wides, and it allows 15 of parallel conveys. Identifier generator 251 also receives sign as the second input by line 253, and receives the effective map of input by first two line interface 254. The first output of identifier generator 251 is delivered to the effective register (not shown) of input by line 255. The second output of identifier generator 251 is delivered to decoding pointer 257 by line 256. Decoding pointer 257 produces four outputs; The initial map of image transmits by line 258, and an image numbers map transmits by line 259, and an insertion map transmits by line 260, and an alternative map transmits by line 261. Leader generator 263 usefulness look-up tables produce and substitute map, and it transmits by line 262b. Extra word generator 264 usefulness MPU produce and insert map, and it transmits by line 262c. Line 262a and line 262c are merged into line 262, and it is the first input of output latch 265. Output latch 265 transmits data by line 266. Line 266 is 15 bit wides, and it allows 15 of parallel conveys.

Inputting effective register (not shown) transmits a map by line 268 and delivers to first or door 267 as the first output. Insert map and deliver to first or door 267 by line 269 as the second input. First or door 267 output by line 271 as the first input deliver to first with door 270. The logical inverse of cancellation map (remove image) by line 272 as the second input deliver to first with door 270, deliver to output latch 265 by line 273 as the second input again. Output latch 265 transmits the effective map of output by second two line interface 274. Receive latch 275 with output and receive signal by the 274 reception outputs of second liang of line interface. Output receives the output of latch 275 and delivers to output receiving register (not shown) by line 276.

Output receiving register (not shown) transmits a map by line 278 and delivers to second or door 277 as the first input. The logical inverse of inputting the output of effective register delivers to second or door 277 by line 279 as the second input. The cancellation map by line 280 as the 3rd the input deliver to second or the door 277. Second or door 277 output by line 282 as the first input deliver to second with door 281. The logical inverse of inserting map by line 283 as the second input deliver to second with door 281. Second delivers to input with the output of door 281 by line 284 receives latch 285. The output that input receives latch 285 transmits by first liang of line interface 254.

Table 600

The token 1. that the map that form receives produces is SEQUENCE START SEQUENCE START H.261

  MPEG     PICTURE START      GROUP START

  JPEG     (None)             PICTURE START

                              PICTURE DATA 2.    H.261    (None)             PICTURE END

  MPEG     (None)             PADDING

  JPEG     (None)             FLUSH

                              STOP AFTER PICTURE

Table 600 is illustrated in some machine-independent control token, does not have standard signal and relation between the standard signal is arranged. As the table shows, the detection of detector for initial code 51 map overs produces the irrelevant control of a series of machines token. Be listed in each map on " map of reception " hurdle, start the generation of the irrelevant control of the machine token that is listed in " token of generation " hurdle. So, shown in table 600 the first row, during H.261 processing whenever receive " sequence is an initial " map or during MPEG processes when receiving " image is an initial " map, just produce whole group four control tokens, its a corresponding data value or some data values followed in each token back. In addition, such as the second line display of table 600, four control tokens of second group produced in the suitable time, no matter what the map that detector for initial code 51 is received is.

Table 601

Display order: I1 B2 B3 P4 B5 B6 P7 B8 B9 I10

Transmit order: I1 P4 B2 B3 P7 B5 B6 I10 B8 B9

Shown in table 601 capable 1, it show the image of transmission and the image that shows between timing relationship, picture frame press the numerical order demonstration. Yet it must exist in the memory for the number that reduces frame, and some frames transmit with different order. It is useful beginning to analyze from basic frame (I frame). The I1 frame is to transmit according to order to be shown. Then next predictive frame (P frame) P4 is transmitted. Then, any two-way interpolation frame that transmission will show between I1 frame and P4 frame (some B frames) represents with frame B2 and B3. This just makes the B frame that is transmitted take past frame (forward prediction) as benchmark, perhaps come frame (back forecast) to be benchmark take the end. All to after the B frame that shows between I1 frame and the P4 frame, transmit next P frame P7 having transmitted. Below, the B frame that all will be shown between P4 frame and P7 frame corresponds to B5 and B6, is transmitted. Then, next I frame, I10 is transmitted. At last, the B frame that all will show between P7 frame and I10 frame should be frame B8 and B9 mutually, is transmitted. This order that transmits frame only requires at any one time and keep two frames in memory, and the transmission that does not require the next P frame of decoder waits or I frame is to show an adjacent B frame.

More about structure of the present invention and operation, also have the information of the aspects such as characteristic, purpose and advantage, in the more detailed description of subsequently invention being specialized intuitively, have the people of general technology can become more apparent to one's own profession. In order to make the clear and purpose easily of explanation, its sorted out and be expressed as follows:

1, many standard configurations

2, JPEG still image decoding

3, active images go compression

4, RAM memory diagram

5, bit stream characteristic

6, restructural is processed level

7, many standard codes

8, the second mode of many standards process circuit-operation

9, initial code decoder

10, token

11, DRAM interface

12, predictive filter

13, the access of register

14, MPI (MPI)

15, MPI reads sequential

16, MPI writes sequential

17, keyhole address location

18, image finishes

19, clear operation

20, remove function

21, stop behind the image

22, many standard search mode

23, reverse moulding device

24, inverse quantization device

25, Huffman decoder and program analyzer

26, various discrete cosine transformers

27, buffer manager 1, many standard configurations

Because various compression standards, i.e. JPEG, MPEG and H.261 be well-known, such as the United States Patent (USP) NO.5 that narrated in front as an example, 212,742,, the detailed description of those standards no longer repeats here.

Said such as the front, the present invention can be to the data bit diffluence compression of many kinds of different codings. In each different coding standard, need the output format device of some form to reach data. These data appear at independent operating space decoder output, perhaps appear at the series winding output of a spatial decoder and temporal decoder combination operation operation, (as more being described in detail subsequently) herein. Two decoders are also to this output reformatting, in order to use and in computer or other display system (comprising video display system) demonstration. The realization of this format alters a great deal because of coding standard and/or selected display type.

According to the present invention, in first specific implementation, as described previously with reference to Figure 10～12, address generator is used for storing a formatted data block. The array output of the output of this data block or the first decoder (spatial decoder) or the first decoder (spatial decoder) and the second decoder (temporal decoder). Address generator also is used for will depositing and/or getting to memory through the information of decoding with the order of grating. Video formatter described below provides the combination of a large amount of output signal.

In the preferential multi-standard video decoder implementation of the present invention, spatial decoder and temporal decoder require not only to realize the mpeg encoded signal but also realize H.261 video decoding system. DRAM interface on two equipment is configurable, so that required DRAM amount can reduce when being operated in some little pixel formats and low coded data rate. The reconstruct of these DRAM will further describe in the DRAM interface hereinafter. In typical case, each temporal decoder and spatial decoder circuit require 4 single Mbytes DRAM.

Spatial decoder of the present invention is finished all essential processing in a single width image. This just reduces the redundancy in the images.

Redundancy between one images of temporal decoder minimizing theme image (subject picture) and arrival before the theme image arrives also reduces the redundancy between theme one images visual and that arrive after its arrives. An aspect of temporal decoder is that an address decoder network will be provided, and it processes complicated addressing needs, and with minimum circuit number, high-speed and improved accuracy is read the data relevant with all these images.

As previously mentioned, with reference to Figure 11, before data arrive, by the initial code decoder, be positioned at Huffman decoder and analyzer (parser) fifo register before again by the second fifo register, reverse moulding device first, the inverse quantization device, reverse zigzag and inverse-DCT. These two FIFO do not need to be placed on the chip. In a kind of implementation, data do not flow through the FIFO on chip. Data are added to the DRAM interface, FIFO-IN storage register and FIFO-OUT register. Both outside the chip. These operations register complete and that standard is irrelevant can be narrated in this article subsequently in more detail.

The most of subsystems and the most of level that are shown in Figure 11 are real irrelevant with used specific criteria, and they comprise DRAM interface 58, produce the buffer manager 59 of DRAM interface IP address, reverse moulding device 75, reverse zig-zag81, and inverse-DCT 83. Within Huffman decoder and analyzer, comprise ALU66 and token formatter 71 with the irrelevant unit of standard.

With reference now to Figure 12,, the unit irrelevant with standard comprises DRAM interface 100, fork 91, fifo register 96, adder 98 and outlet selector 106. The unit relevant with standard is address generator 94, it H.261 be different among the MPEG, also have predictive filter 103, it is reconfigurable, has the ability H.261 all working with two kinds of standards of MPEG. Jpeg data can not flow through whole machine fully with changing.

Figure 13 describes a high level block diagram of video formatter chip. The very most of and standard of chip is irrelevant. The only projects that affected by standard are modes that data write DRAM in situation H.261, and this mode is from different when MPEG or the JPEG; And unnecessary to each single picture coding in H.261. Have some timing information to be called time standard (temp-oral reference), it provides some for information about when image will be shown. This part thing is also processed with the address occurrence type of logic in the video formatter.

The circuit remainder of realizing in video formatter and used specific compression standard are fully irrelevant, and these parts are: all color space transformations, over-sampling (up-sampl-ing) wave filter and all γ proofread and correct PAM. Initial code decoder of the present invention is relevant with compression standard, and it must be identified every kind of different initial code pattern of standard in the bit stream. For example, H.261 16 initial codes are arranged, MPEG has 24 initial codes and the JPEG flag code, and it is fully different from other initial code. In case the initial code decoder has identified those different initial codes, its operation is in fact just irrelevant with compression standard. For example, at searching period, except the circuit of identifying dissimilar marks, most of operation is very similar between three kinds of different compression standards.

Next unit is that state machine 68 (Figure 11) is positioned within Huffman decoder and the analyzer. Here, each the actual track that is used for three compression standards be similar complete with. In fact, the unique element that affected by standard is the reseting address of machine. If just analyzer is reset, then its corresponding each standard jumps to different addresses. What in fact, be identified has four standards. H.261 these standards are, JPEG, MPEG and another. In this 4th standard, analyzer is introduced one section code that is used for test. This explanation circuit similar aspect each be complete with, but difference is the micro code program to every kind of standard. So when the program that H.261 operates when a usefulness is being moved, and when the program of a various criterion is being moved, do not have overlapping between them. Correct to this same maintenance of JPEG, JPEG is the 3rd fully independently program.

Next unit is Huffman decoder 56, works together in it and data directory unit 64. Work in coordination and finish the Huffman decoding in those two unit. Here no matter which kind of compression standard is, be the same to the algorithm of Huffman decoding usefulness. Difference is to enter the whether paraphase of Huffman encoder with any table and data. Itself also comprises state machine the Huffman decoder, and it understands some aspect of coding standard. The selection of these different operatings is corresponding to an instruction that comes from the analyzer state machine. The analyzer state machine with different program works, and is sending correct order with the consistent different time of operation standard to Huff-man decoder to each of three kinds of compression standards.

A last unit is the inverse quantization device 79 relevant with compression standard on chip, and here, the inverse quantization device is that the computing that every kind of different standard is finished is different. In this, a CODING_STANDARD token is decoded, and what inverse quantization device 79 was remembered to move is any standard. Then, after that event but before another CODING _ STANDARD may occur, data token is subsequently processed with regard to the mode of using the CODING_STANDARD that remembered by inverse quantization device inside to indicate. In more detailed description, different parameters and corresponding those different parameters of which kind of circuit or the calculating in the table explanation various criterion is arranged.

In H.261, to the every sub-systems shown in Figure 12 and Figure 13, the generation of address is different. In Figure 11, the address generate at two forward and backward FIFO of Huffman decoder does not change because of coding standard. Even in H.261, the generation in the address that chip occurs also is immovable. In fact, the difference between these standards is the difference with MPEG and JPEG, and the tissue of some macro blocks is arranged, one side these macro blocks are flatly from the another side that is stretched over of image in the linear rows mode. Can observe best in Figure 14 a, first macro block A covers a full line. Macro block B covers and is less than delegation. Macro block C covers multirow. Be to be divided into some 132 cutting apart in MPEG, and a slice can be a horizontal line A, perhaps can be a part of B of horizontal line, and perhaps it also can expand to next line from delegation, C. Each of these sheets 132 forms the delegation of macro block.

In H.261, organize considerably difference, because image is divided into some piece groups (GOB). A piece group is that three row macro block height take advantage of 11 macro blocks wide. If a width of cloth CIF is visual, 12 such piece groups are arranged. Yet they are not one and are placed on such tissue above another. But have two piece groups mutually against, and have 6 high, namely vertical direction has 6 piece groups, horizontal direction has 2 piece groups.

In all other standards, when carrying out addressing, macro block addresses by above-mentioned order. More specifically, addressing is carried out along row, begins next line behind the arrival end of line. In H.261, in a piece group, the order of piece and description the same, but when shifting to next piece group, order almost is in a zigzag (zig-zag).

The invention provides circuit and process the latter's impact. H.261, the generation of address is like that because changing in spatial decoder and video formatter. When writing DRAM, information just finishes such variation. It is to write with the knowledge that sequence occurs said address, front, thus sequence physical set bit position in RAM, if when being an onesize MPEG image with this should the position be just the same. Therefore, from all address generate circuits of DRAM read data, for example, when forming prediction, unnecessary to understand that be standard H.261, if because the physical location of information in memory be in the MPEG sequence it should the position be the same. So in all cases, only have writing of data to be affected.

In temporal decoder, identify oneself some thing and in fact occurent different to H.261 abstract, Circuits System are arranged. That is exactly, and each piece group is extended away conceptive, so that it is not the rectangle of 11 * 3 macro blocks, but macro block is extended away the piece group that becomes 33 block lengths (seeing Figure 14 c), and its height is a macro block. Since done like that, the counting mechanism used with the piece group of in temporal decoder, passing through for calculating, and identical ground also is used for MPEG.

H.261 the method for piece group line design is corresponding with MPEG sheet line design method. Processed after the initial code decoder when data H.261, there is a slice_start_code each piece group front. There is next slice_start_code next piece group front. The counting that is carrying out in temporal decoder inside for this structure is counted from the beginning to the end, identifying oneself this is a macro block height, 33 piece groups that macro block is long. This is just enough, although circuit is also counted every 11 macro blocks. Count to the 11st macro block or the 22nd macro block when it, it resets some counter. This simple circuit with another counter realizes that this counter is to each count of macroblocks, and when it obtained 11, it was reset to zero. The microcode inquiry is also done that work. All circuits in the temporal decoder of the present invention are irrelevant with compression standard in fact with regard to the physical layout of macro block.

Aspect many standard adaptations property, many different tables and circuit are arranged, be the suitable suitable table of Standard Selection in suitable. Every kind of standard has many tables; Circuits System elects from showing to concentrate at any given time. In any standard, circuit is once selected a table, and another table is then selected constantly at another. In different standards, circuit is selected different table collection. Between those tables, there is some to intersect, pointed when in front Figure 15 being discussed. For example, a table that is used among the MPEG also is used for JPEG. These tables are not the collection that isolates fully. Figure 15 illustrates a H.261 collection, a MPEG collection and a JPPEG collection. Note, H.261 have between collection and the MPEG collection one much bigger overlapping. With regard to their used table, two collection are quite common. H.261 and fully not overlapping between the JPEG have overlappingly on a small quantity between MPEG and JPEG,, thereby these standards have diverse table collection.

As noted, the largest portion of system unit and compression standard are irrelevant. If unit and standard are irrelevant, that then such unit does not need to remember to process is any CODING_STANDARD. Compression standard is remembered in all unit relevant with standard when CODING_STANDARD flows through them. When the information of coding/decoding in first coding standard is distributed to whole machine, and certain machine is being when changing standard, and the machine in front under microprocessor control will normally be selected according to H.261 compression standard work. MPU in these machines in front just produces signal, represents that in different place, the many places of machine intimate compression standard changes. MPU makes change in different, in addition, it can remove whole streamline.

According to the present invention, be arranged in the change that the initial code decoder of first unit of streamline sends the CODING_STANDARD token, this makes the change of compression standard be easy to process. Token declares that certain coding standard is about to begin, so that control information is past dirty along machine, and disposes all other registers in the suitable time. MPU need not plan each register.

How prediction token notice forms prediction with some positions in the bit stream. Circuits System is the information that finds in standard, and the information that namely finds from bit stream changes into a prediction mode token. This depends on move which compression standard. This processing is finished with Huffman decoder and analyzer state machine, processes easily some positions based on some condition here. The initial code decoder produces this prediction mode token. So token down flows to the temporal decoder circuit along machine, it is responsible for forming prediction. What the spatial decoder circuit needn't know that it is moving is that what standard just can be explained token, because in three various criterions, in the token everybody is constant. Spatial decoder is just by doing that token is informed. These tokens have been arranged and suitably utilized them, the design of other unit just has been simplified in the machine. Although in program some complex situations may be arranged, some hard wire logic that originally is difficult to be designed to many standards can use at this, so obtained benefit. 2, to the decoding of JPEG still image

As noted, the present invention is related to the compression of going of signal, especially is related to no matter use what compression standard to the compression of going of encoded video signal.

One aspect of the present invention is to provide one first decoding circuit (spatial decoder) to go the first code signal (JPEG encoded video signal) decoding in the pipeline processes system, also provides one second decoding circuit (temporal decoder) to go the first code signal (MPEG or H.261 encoded video signal) decoding. For decoder between JPEG decoding when not required.

In this, the present invention makes the compression of going of numerous different coding signals become easy by with a simple stream waterline decoder and remove compressibility. Decoding and remove to compress pipeline processor and form with the structure of uniqueness, this structure is so that can process the multi-standard video signal by the technology with all and single streamline decoder and treatment system compatibility. Spatial decoder and temporal decoder combination, video formatter are used for driving video display.

Another aspect of the present invention is the combination of having used spatial decoder and video formatter, and it only is used for still image. Finish the processing of all data in the single visual scope with the irrelevant spatial decoder of compression standard. Such decoder processes the space of interior view image data go compression, those data communication devices are crossed streamline and are distributed in the relevant RAM. Process storage and retrieval at the memory internal information with the irrelevant address generator circuit of standard. The still image data are decoded in the output of spatial decoder, and this output is used as many standards, the input of reconfigurable video formatter, and then formatter provides output to display terminal. In first sequence of similar image, each when image arrives spatial decoder output, all is the same in the length of the position of removing the image that compresses of spatial decoder output. Second sequence of some images may have diverse image size, therefore, with first Length Ratio different length arranged. Also have, the length of the position of all these of similar image the second sequence when these images reach the output of spatial decoder, also all is the same.

What invent is the sequence that the bit stream tissue relevant with standard that enters is become control token and data token in inside on the other hand. Combination also has numerous orders to lay therewith, and is reconfigurable, and through selecting and the processing level of tissue, group has nothing to do with standard as one, reconfigurable pipeline processor.

With regard to JPEG decoding, one single does not have the spatial decoder of the outer DRAM of chip can be very fast to basic jpeg picture decoding. All characteristics of the basic JPEG coding standard of spatial decoder support. Yet the size of the buffer output that can provide may be provided the image size that can decode. The spatial decoder circuit also comprises a RAM circuit, also have relevant with machine, but with the irrelevant address generator circuit of standard. This circuit for the treatment of with information storage in memory.

As noted, temporal decoder does not require the JPEG encoded video signal is decoded. Correspondingly, when setup time, decoder was the JPEG operation, the entrained signal of data token did not directly further process by temporal decoder.

Another aspect of the present invention is that a pair of memory circuitry is provided in spatial decoder, and such as the buffer memory circuit, this is for the Huffman decoder/vision signal separator circuit (HD and VDM) combines work. First buffer memory is placed on HD and VDM front, and second buffer memory is placed on HD and VDM back. HD and VDM be to the bitstream decoding of the binary one in the standard code bit stream and 0, and these circulations are changed into numeral for the downstream. The Double Register system is in order to realize the compressibility that goes of standard more than. The combination of this two buffers and the Huffman decoder that has confirmed to realize will be described hereinafter in more detail.

It is the combination of initial code decoder and Huffman decoder that these many standards are gone to another aspect of compressor circuit. The initial code decoder is positioned at the upstream of the first forward direction buffer. An advantage of this combination is to process incoming bit stream, increased flexibility during the filling that particularly must add in processing bit stream. These confirmed parts, the initial code decoder, the arrangement of store buffer and Huffman decoder has strengthened the processing to some sequence in the incoming bit stream.

In addition, the outer DRAM of chip is used for the video image of real-time decoding JPEG coding. The size of some buffers of reinstating with DRAM one and the speed that speed depends on video data encoder.

Coding standard identifies the information of all types relevant with standard, has among the DRAM that links in order to be stored in spatial decoder, and those information are necessary. What spatial decoder was used is the circuit irrelevant with standard. 3, active images go compression

In the present invention, if active images will go compression by decoding step order, just a temporal decoder must be arranged again. Temporal decoder will combine by the more decoded images of decoded data and front in spatial decoder. These images are predetermined or before current image of decoding or later on demonstration. Temporal decoder is reception information in image coded data stream, goes to identify the information that this time staggers. Temporal decoder is organized the information addressing of being staggered in time and space, retrieve these information and these information of combination, the combination carry out in such a way, going to decode with current image of decoding is arranged in the information of an images, and with a width of cloth composite image as end. This images is complete, and is applicable to be sent to video formatter to drive display screen. In other words, synthetic image can store away as using when making time decoder with image afterwards later on.

In general, temporal decoder carries out the processing between image and the image. These images than current image of decoding earlier and/or a little later in time. Temporal decoder is introduced those information that is provided with coding in the coded representation of image again, because it is redundant, and can obtain at decoder. More particularly, following situation is possible, namely any given image can comprise with other in time or the information of front or rear image similarity. If added movement compensation, it is larger that this similitude can become. Temporal decoder and go compressor circuit also to reduce redundancy between relevant image.

In another aspect of this invention, temporal decoder is for the treatment of the output information relevant with standard of coming from spatial decoder. The information relevant with standard of this single width image is distributed in the middle of several zones of DRAM. This says in the sense, goes to compress output information with what spatial decoder was processed, is that to be stored in other some DRAM registers with other RAM interior. These RAM also have other relevant with machine and with the irrelevant address generator circuit of standard. The address generator circuit is used for the space images of decoded information bag of decoded picture information of interblock space. This images staggers with the time location of the first images in time.

In many standard circuit of having the ability to the mpeg encoded signal decoding, some pixel formats that may be larger in the time of may requiring larger logic DRAM buffer to use MPEG with support.

Pictorial information flows through the serial flow waterline take 8 pixels * 8 pixel blocks as unit. In a kind of form of the present invention, address decoding circuitry is along these pixel blocks of BORDER PROCESSING (storage and retrieval) of these pieces. The address decoder circuit is also from storage and the retrieval of processing these 8 * 8 pixel blocks to the other end on these borders. This many-sided adaptive hereinafter more completely description.

Second temporal decoder also can be provided, and it directly is sent to video formatter to the output of first decoder circuit (spatial decoder), in order there not to be the signal processing delay when processing.

Temporal decoder is also reset the order of image data block in order to show with display circuit. The processing that the address decoding circuitry of hereinafter describing provides this to reorder.

As previously mentioned, temporal decoder key property is that the pictorial information of selecting from some images is added together. These images earlier or a little later arrive than the image of processing. When describing image in this sense, any point below may always distinguishing the flavor of:

1, the coded data of image represents;

2, result, i.e. the formed last decoded picture of result of the treatment step addition finished of decoder.

The image of the former decoding of 3, reading from DRAM;

4, the result of space decoding, i.e. a sheet of data between a PICTURE_START token and PICTURE_END token subsequently.

With after the time decoder processes image data information, data or shown or write back to the video memory unit. Then this information is saved in order to do further reference when the different coded data of another width of cloth of processing is visual.

For visible demonstration reordering of mpeg encoded image contained useful change temporal decoder and the method for the characteristic that reorders, obtain the possibility of the coding image of a width of cloth requirement. 4, RAM memory diagram

Spatial decoder, temporal decoder and video formatter are all used outside DRAM. Best, all three devices are all used same DRAM. Although all three devices are all used DRAM, and all three devices all use the DRAM interface that links with address generator, and what is finished is different to each device in DRAM. In other words, each chip, for example spatial decoder and temporal decoder, even they are with the outside DRAM of similar physics, their DRAM interface is different with the address generator circuit.

In brief, spatial decoder two FIFO that in public DRAM, pack into. Referring again to Figure 11, a FIFO54 is placed on Huffman decoder 56 and analyzer front, and another is placed on Huffman decoder and analyzer back. FIFO realizes in a relatively simple manner. Be each FIFO, the specific part lie by of DRAM is as physical storage. FIFO will be mounted in it.

Keep tracking to fifo address with spatial decoder DRAM interface 58 associated address generators with two pointers. There is the first character among the FIFO in pointed, and there is the last character among the FIFO in another pointed, so can carry out read/write operation at suitable word. Reach the terminal of physical storage in the process that is reading or writing, address generator is with regard to " lap wound " top to physical storage.

In brief, temporal decoder of the present invention must be able to be deposited two view picture image or frames, and no matter that appointment is what coding standard (MPEG or H.261). For the sake of simplicity, in DRAM, store the physical storage of two frames in two, a width of cloth of whenever half special use (with suitable pointer) appointment in two images.

MPEG is with three kinds of different visual types: base (I), (P) of prediction and (B) of two-way interpolation. As previously mentioned, the B image is based on the prediction of making according to two images. One width of cloth is following, and a width of cloth is gone over. The I image does not need further to encode with the time decoder, but must have one of two picture buffer, uses for later on to P and B image decoding the time. The decoding request of P image forms prediction from the decoded P in a width of cloth front or I image. Decoded P image exists in the picture buffer, and this is in order to be used for the decoding of P and B image. The B image can require two picture buffer that prediction all is provided. Yet the B image does not exist among the outside DRAM.

Note, do not export from temporal decoder behind I and the P image decoding. But I and P image write one of picture buffer, and and if only if the I that will decode subsequently or P image just be read out when arriving. In other words, temporal decoder relies on subsequently P or I image that the clear picture of front in two picture buffer is removed, and further discusses as hereinafter removing part. In brief, spatial decoder can provide the I of forgery or P image to be used for the P of last time or I image are cleared out in video sequence end. When the video sequence subsequently began, the false image of this width of cloth was eliminated again.

When to the B image decoding, the maximum memory bandwidth load occurs. The worst situation is possible form the B frame according to the prediction from two picture buffer, and the precision of all predictions will reach pixel half.

As previously mentioned, temporal decoder can be configured to provide the MPEG image to reorder. Because this image reorders, the output of P and I image is delayed, until the next P in the data flow or the beginning of I image are decoded by temporal decoder.

Because P or I image are rearranged order, when image was write picture buffer, some token temporarily existed on the chip. When image was read out in order to show, the token of these storages was retracted. In the output of temporal decoder, the data token of the P of new decoding or I image is replaced by the data token of the image of old P or I.

, H.261 only make a prediction from the image of firm decoding. Because every images is decoded, it is written into one of two picture buffer, so it can be used to the decoding of next images. Storage operation is only required and is write 8 * 8 and form prediction with the mobile vector of integer accuracy to DRAM.

In brief, video formatter is deposited three frame formulas, three images. Need to deposit three width of cloth figure adapts to such as multiimage or jumps over figure characteristic like this. 5, bit stream characteristic

When being particularly related to spatial decoder of the present invention now, bit stream (bit stream) characteristic of looking back encoded data stream is helpful, because the Circuits System of spatial decoder and time decoder must be discussed these characteristics. For example, under one or more of standards, the compression ratio of this standard is respectively schemed usefulness by changing certain images coding figure place realizes. Figure place can change on a large scale. Specifically, this means that the bit stream length to the reference map of images coding usefulness can be defined as a unit head, and should another figure of image can be several unit head that the 3rd figure then can be less than a unit head.

Existing each standard (MPEG 1.2, JPEG, H.261) all not regulation finish the method for a figure, its implication is, during next figure beginning, current that finishes. In addition, each standard (especially H.261) allows encoder to produce imperfect image.

According to the present invention, a method that image finishes is provided, Here it is uses one of its token: PICTURE_END. From detector for initial code out still begin the figure that finishes to the PICTURE_END token for the pictorial data of coding comprises each by the PICTURE_START token, their length variations is still very large. May be also (between first and second figure) send other information, but first figure knows and given.

Data flow in spatial decoder output represents the image that some still keep image beginning and visual end mark, but for given sequence, their length (figure place) is identical. Once image beginning and the time length between once image finishes are variable.

Video formatter is got these times image different in size, and they is shown at screen visual display speed is fixed, and concrete numeral depends on driven type of display. Different display speeds has been used in the whole world, such as the television standards such as PAL, NTSC are arranged. Taken into account this species diversity with unique way: leave out selectively or repeat some images. Common " frame speed converter ", as 3 frames being kept to 2 frames (2-3pulldown), with fixing input imagery speed work, but video formatter but can be processed variable input imagery speed.

6, reconfigurable processing level (RECONFIGURABNLE PROCESSING STAGE)

Again consult Figure 10, reconfigurable processing level (RPS) is comprised of token decode circuit 33, and it is used for receiving the token from two-wire interface 37 and input latch 34. The output of token decode circuit 33 is added to processing unit 36 by two-wire interface 37, and output also is added to action recognition (action identification) circuit. After processing finished, the signal that processing unit 36 will so be finished through output register 41 was delivered to output two-wire interface bus 42.

Two-wire interface bus 40 is passed through in the input of action recognition decoding circuit 39, from token decode circuit 33, with/or pass through two-wire interface bus 46 from memory circuit 43 and 44. Token from token decode circuit 33 is added to action recognition circuit 39 and processing unit 36 simultaneously. The function of RPS and action recognition will further be set forth with chart in the aft section of this explanation.

Functional block diagram among Figure 10 has illustrated that those are not the work at different levels of standard independent circuits among Figure 11,12,13. Data successively flow through token decode circuit 33, processing unit 36, output latch 41, arrive two-wire interface circuit 42. If control token (Control Token) is identified by RPS, it is just interior decoded at token decode circuit 33, after this suitable action will occur. If unrecognized, it just delivers to output two-wire interface 42 through output circuit 41 without change. The present invention plays the effect of pipeline processes, and it is furnished with two-wire interface with the movement of control control token in streamline. In EUROPEAN PATENT OFFICE (EPO) number of patent application 92306038.8 of the former application of these characteristics of invention more detailed narration is arranged.

In the present invention, actually or token decode circuit 33 is used for the token data token control token that identification enters two-wire interface 42 at present. If recognized by the token that token decode circuit is being investigated, it just is withdrawn into action recognition circuit 39, suitable designator (index) signal or marking signal occur simultaneously to indicate this action to be used. Meanwhile, token decode circuit 33 also provides suitable sign or indicator signal to arrive processing unit 36, notes having token just to process in action recognition circuit 39 to remind the latter. The control token also can be accepted corresponding processing.

With hereinafter to the present invention can with various token type be described in more detail. With regard to the purpose of this part explanation, only it is also noted that controlling the entrained address of token decodes in decoder 33, and be used for the register of access in action recognition circuit 39 that this is just enough. When control token that the token of just being investigated is recognized, its reconfiguration status circuit of action recognition circuit 39 usefulness (reconfiguration state circuit) distributes each control signal in whole state machine. As previously mentioned, this starts with regard to the state machine that makes action recognition decoder 39, so 39 pairs of itselfs of decoder are reshuffled. For example, it can change coding standard. This shows that action recognition circuit 39 has solved the required action of specific criteria of just passing through at present state machine for processing, referring to Figure 10.

Similarly, the processing unit 36 under action recognition circuit 39 control now at any time can pack processing be contained in the information in the data token data field, as long as opportune words. Under many occasions, the control token is at first come, and action recognition circuit 39 is reshuffled; Then data token accepts processing immediately following thereafter in processing unit 36. The control token just withdrawed from output latch circuit 41 and arrives the opposite side of output two-wire interface 42 before the data token that processing unit 36 is disposed.

In the present invention, action recognition circuit 39 is state machines that keep historic state (history state). Register 43 and 43 is keeping solving and to be stored in information in this register from the token decode device. Such register can be located at as required in the chip or chip outside. These numerous status registers contain the action message relevant with the current action recognition of just identifying in action recognition circuit 39. Connect 40 and directly arrive action recognition parts 39 from token decode device 33. Its objective is that expression action also can be subjected to the impact of the current token of just being processed by token decode circuit 33.

So far pointed out substantially that the token decode that carries out according to the present invention and data process. Data are processed the mode that consists of according to action recognition circuit 39 and are carried out. Action is subject to the impact of many conditions, it is also affected by following factor: the information that obtains from the token that solved in the past in general, the information in register 43 and 44 of being stored in that more particularly from the token that solved in the past, obtains, the current token of present, and action recognition unit 39 acquired state own and historical informations. We point out to control the difference between token and the data token whereby.

In arbitrary RPS (reconfigurable processing level), some tokens are regarded as the control token by this RPS unit, and this is because they probably can affect the work of RPS in certain follow-up moment. Other tokens are then regarded as data token by this RPS, such data token contains certain information of being processed by this RPS, processing mode depends on: the design of indivedual (particular) Circuits System, former decoded token and the state of action recognition circuit 39. Although certain other RPS recognizes some token as the control of these indivedual RPS, recognizing other tokens is data tokens, and this is the opinion of these indivedual RPS. Another RPS can have different views to same token. As data token may be regarded certain token in a RPS unit, and another RPS unit then may decide it and be actually the control token. For example, with regard to Huffman decoder and state machine, quantization table information is data, and it is formatted into a series of 8 words, and these words form again the token that is called quantization table token (QUANT_TABLE); Under pass to the processing streamline. With regard to this machine, these all are data; Deal with data becomes another kind of with a class data transaction, and this is undoubted to be this part a kind of function of processing of machine. Yet when this information arrived the inverse quantization device, the inverse quantization device deposited the information in this token in numerous register. In fact, because 64 8 figure places are arranged, so many registers are arranged, in general, numerous registers can be arranged. This information is counted as control information. Then, this control information meeting impact is to the processing of subsequent data token, because its impact is to the multiplier of each data word. More than be exactly that one-level may be regarded token as data and another grade may be regarded it as the example of control.

According to the present invention, token data almost is counted as data without exception in whole machine. One of importance is, in general, every one-level Circuits System with token decode device must be sought some token, any token that it can not identified must in statu quo hand down from streamline by the corresponding levels, so that have the right to see these tokens in each subsequent stages when the prime downstream, and may respond to it. This is a very important feature, that is, use token skill can realize the communication between each parts not adjacent to each other.

Another important feature of the present invention is, every one-level of Circuits System has the inter-process ability, carrying out each substandard necessary operation, and carries out the control of coming with the token form, goes to determine should finish which operation at certain given time. For aforementioned capabilities is provided, a treatment element is arranged, but it is not at the same level all variant. In the state machine ROM of Parser, three kinds of diverse programs of separating are arranged, each program adapts to a related standard. Carry out which kind of program and depend on the CODING_STANDRAD token. In other words, each section's dual capability of having the decoding processed and processing the CODING_STANDARD standard token within it all of three kinds of programs. When which each coding standard of seeing that the next one will be decoded of three kinds of programs was, they just jumped to the initial address in the microcode ROM that arranges into this specific program faithfully. More than be many standards of how treating at different levels.

There are two things to be subject to the impact of various criterion. The firstth, be considered to everybody style of initial code or identity code in the bit stream, in order to shift register is reshuffled, go to detect the length of beginning flag code. The secondth, the first information of this initial code of expression or identity code meaning in microcode. Please remember every coding difference under three kinds of standards. Therefore, microcode is being searched the whatsit irrelevant with standard for this compression standard in the specific table, namely represents a kind of token of the code that arrives. Because in most of the cases, each different standard all provides certain code to remove to produce this token, and it is general and standard is irrelevant.

Inverse quantization device 79 has mathematical operational ability. Quantizer is done multiplication and addition, and has the ability to adapt to all three kinds of compression standards that formed by some parameters. For example, a flag bit in controlled ROM can inform whether the inverse quantization device adds a certain constant K. Another sign informs whether it adds another constant. When the CODING_STANDARD token streams was crossed the inverse quantization device, there was it in the register in quantizer. When data token after this by the time, the inverse quantization device is that any standard stores to get off with this, and search it be added on the treatment element, for carrying out the required parameters of proper handling. For example, the inverse quantization device will be searched the K that is fit to a certain specific compression standard and be zero setting or put 1, and this is added to treatment circuit.

Similarly, many tables are arranged in the Huffman decoder, some is JPEG, and some is MPEG, and H.261 some for arranging. In fact, these form majorities can be more than one these compression standard services. Use which table to depend on the grammer (synt-ax) of this standard. After the order of receiving from state machine, the Huffman decoder is work just, and which table is the state machine decoder will use. Therefore, be not to have a state directly to enter Huffman decoder itself, store there, and inform it to be processed be which type of coding. On the contrary, be that Parser state machine and Huffman decoder combine and information be included in their inside.

As for spatial decoder of the present invention, the generation of address has change, and this is to shown in Figure 10 similar, and many information of namely decoding from token are such as coding standard. Coding standard and additional information are by the typing register, and this has just affected advancing of address generator state machine, because it passes by length by length, and one by one to the count of macroblocks in the system. H.261 or MPEG afterbody may be predictive filter 179 (Figure 17), and it is operated in one of dual mode, or, and this is easily identification. 7, many standard codes

System of the present invention also provides the combination of some designators (indices) generation circuit that has nothing to do with standard, and these circuit and token decode circuit combine and spread all over total system tactfully. For example, native system is used to specifically video standard H.261, or the MPEG video standard, or the decoding of JPEG video standard. These three kinds of compression and coding standards have been stipulated the step that should process the arrival data similarly, but data flow architecture is not identical. As previously mentioned, one of function of detector for initial code is exactly to detect MPEG initial code, H.261 initial code and jpeg marker code, and all converts them to a kind of form, i.e. a kind of control token that contains the token streams that embodies the present encoding standard. The control token is by pipeline processor, and is used (namely decoded) in relevant with it state machine. The control token is other state machine by having no truck with also. Thus, also treat data token with the same manner, accept processing because they only can be consisted of in the state machine of processing them by the control token at those. In remaining state machine, their former states are passed through unchangeably.

More specifically say, according to the present invention, can comprise more than one word in the control token. If so, that is called as extension bits is set to 1, uses additional word to carry additional information in the token thereby be defined in. Some position of these additional control bits is equivalent to designator (indices), is used to refer to the information that will use in corresponding state machine, to produce one group of indicator signal that has nothing to do with standard. The remainder of token is used to refer to and identifies inter-process control function (internal processing control function), and the latter is standard to all data flow by pipeline processes. In a kind of form of the present invention, the token expansion is used for transmitting (carry) coding standard, and this standard is solved by the relevant token decode circuit that spreads all over complete machine. Every place being suitable for new coding standard operation, the token expansion also is used for the action recognition circuit 39 at different levels that spreads all over complete machine is reshuffled. Token decode circuit can point out whether certain control token is relevant with one of selected standard, and these standards are that circuit design is good treatable in addition.

More specifically, the back of MPEG initial code and jpeg marker is 8 bit value. H.261 the back of initial code is 4 bit value. For this reason, the detector for initial code 51 usefulness way that detects MPEG initial code or jpeg marker (marker) indicates follow-up 8 to be exactly and the related value of initial code. Irrelevant with top this part thing, it then produces a signal and goes to point out that this is not H.261 initial code but MPEG initial code or jpeg marker. At first, 8 place values enter decoding circuit, and a part of 8 produces the signal of expression designator and sign (flag), this signal in current circuit for the treatment of the token by this circuit. Some segments that this also is used to insert the control token will check these segments later on, are which standards with what determine processing. In this sense, a part points out should do the data of following the operation of which kind of type in the control token, and also some points out that it is relevant with mpeg standard. As previously mentioned, this operation information is used for reshuffling processing level in system, is used for finishing the desired difference in functionality of various criterion and process level, and various standards are exactly to set up for this purpose.

For example, be as the criterion with initial code H.261, it is with relevant immediately following 4 place values thereafter. Detector for initial code is sent this value into token generator state machine. Numerical value is added to 8 decoders, and the latter just produces 3 starting symbol. Starting symbol is used for identifying the beginning of an images, and figure number is indicated with the numerical value of starting symbol.

Native system also comprises multistage parallel processing streamline, and this streamline is according to the principle work of aforesaid two-wire interface. Every grade of machine by common employing form shown in Figure 10 forms. Token decode circuit 33 is used for guiding the token of the current machine that gets the hang of to arrive action recognition circuit 39, or to processing unit 36, is as the criterion with suitable. Processing unit is former to be set to the required form of present encoding standard of processing by the control token reprovision of front more, and the present encoding standard is just entering now processes level, and is that next data token is entrained. In addition, according to this situation of invention, each the follow-up state machine in processing streamline can worked with a kind of coding standard (namely H.261), and its prime can worked with other standard (such as MPEG). Same two-wire interface is used for transfer control token and data token.

System of the present invention has also utilized the control token, and these control tokens are required with the reconfigurable processing level of fixed number some coding standards to be decoded. More specifically say, used PICTURE_END control token, because there is the indication of the visual real finish time extremely important. Corresponding therewith, in the design of many Standard Machines, must at some extra control tokens of the inner generation of the pipeline processor of many standards, make the indication of processing function will use which kind of standard decoding technique. A control token like this is exactly the PICTURE_END token. It is complete that this PICTURE _ the END token is used to refer to current image, is used for forcing buffer to rinse well and be used for current image is pushed to display from decoder. 8, many standards treatment circuit-the second working method

With the form of aforesaid detector for initial code compressor circuit that form, relevant with coding standard, through certain suitable bus, be interconnected to suitably the compressor circuit irrelevant with standard. The circuit relevant with standard is connected to the combinational circuit irrelevant with standard, and links additional busses also by same bus. The circuit irrelevant with standard is added to the circuit relevant with standard with the input that adds, and the circuit that the latter has nothing to do information back and standard. Be added to output from crossing another suitable bus with the irrelevant circuit information exchange out of standard. Table 600 has illustrated that the multiple standards as the detector for initial code relevant with standard 51 inputs is comprising some bit stream, and the latter has the meaning relevant with standard in each coding stream. 9, detector for initial code

As front pointing out, according to the present invention, detector for initial code can extract MPEG, JPEG and bit stream H.261, and can produce thus proprietary (proprietary) sequence of tokens, and these proprietary tokens are meaningful for the remainder of decoder. The example that how decoding is finished as multiple standards, MPEG (1 and 2) picture_start_code, H.261 picture_start_cide and JPEG start_of_scan (SOS) mark are used as signal of equal value by detector for initial code, and they all produce an inner PICTURE_ START token. Similarly, MPEG sequence_start_code and JPEG SOI (start_of_image) mark also all produce a machine sequence_start token. Yet H.261 standard does not have initial code of equal value. Therefore, as to first H.261 response of picture_start_code, detector for initial code will produce a sequence_ start token.

Above-mentioned various visual neither one is directly used, except the use in detector for initial code (SCD). On the contrary, machine PICTURE_START token for example, has been considered to be equal to each the PICTURE_START map (inages) that is included in the bit stream. In addition, must remember that machine PICTURE_START itself is not the direct map (direct image) of the PICTURE_START in standard. On the contrary, it is a control token, and being used for providing the decoding irrelevant with standard with after other control token combination, and this has simulated under each compression and coding standard the operation to image. The cooperation that each controls token adds that the designator and/or the further of sign that partly produce with state machine token decode circuit out of the ordinary cooperate, and is unique in itself. The cooperation that each controls token adds that with the entrained information of control token to the reshuffling of circuit, this is unique in itself equally. A typical reconfigurable state machine will be narrated afterwards.

Again referring to table 600, the table left hurdle shown in be the title of one group of standard picture, shown in the right hurdle is more machine dependent control tokens, and they are used to the standard code signal simulation, and this standard code signal does not exist in standard picture or is not used.

Reference table 600 can find out that as previously mentioned, it just produces machine sequence_start signal No. one time when detector for initial code is decoded to the arbitrary standard signal shown in this table. Detector for initial code produces sequence_start, group_start, and sequence_end, slice_start, user_data, the tokens such as extra_data and PICTURE_START, they are applied to spreading all over system-wide two-wire interface. Decided by the token content with these structures of controlling every one-level of token cooperatings, or determined by the designator that the token content produces. At different levelsly all be ready to process the data that expection will be received when the pictorial data token is come this grade.

As previously mentioned, for example H.261 one of compression standard, does not have the map of sequence_start at it in data flow, do not have the map of PICTURE_END yet. Detector for initial code indicates the place of PICTURE_END in the bit stream that enters, and produces the PICTURE_END token. In this respect, being intended that of system of the present invention transmits the fully data word of combination, so that each register-bit of selecting in the invention process has been set up an information. For this reason, 15 figure places that conduct transmits have been selected between two initial codes. Certainly, the people with the general technical ability of one's own profession also can recognize the selection that can make greater or less than 15. In other words, just from detector for initial code send into the DRAM interface data word whole 15 for the normal operation all be essential. Therefore, detector for initial code will produce the more extra positions that are called filling, in the last word with the data inserting token. For the purpose of example, 15 have been selected.

In order to realize the filling operation, according to the present invention, the follow-up some binary ones of Binary Zero are inserted automatically, to fill up 15 bit data word. Then these data by the coded data buffer, deliver to the Huffman decoder, and this decoder is removed filling again. So, any digit just can be by the buffer of fixed size and width.

In a kind of specific implementation, slice_start control token is used to identify a slice (slice) image. Use slice_start control token, in order to image is cut into less zone. The size in zone is selected by encoder. Detector for initial code identifies the slice_start code of this unique form, cuts into some less zones in order to be positioned at the image detector for initial code downstream, that machine dependent each state levels will received. The size in zone is selected by encoder, is identified by detector for initial code, by reformulating (recombinat-ion) Circuits System and controlling token and use, to coding image decompression (decompre-ss). Recovery after the slice_start code is mainly used in makeing mistakes.

Initial code provides a kind of peculiar methods of starting decoder, and this will be described in a more detailed discussion afterwards. Detector for initial code is placed on before the coded data buffer, rather than is placed on thereafter and is placed on Huffman decoder and vision signal separator (video demultiplexor) before, this has many benefits. Detector for initial code is positioned at the first buffer can makes it: 1) collect (assemble) token, 2) the standard control signal is decoded, as initial code is decoded, 3) before entering buffer, data load bit stream, 4) produce suitable control sequence of tokens, with the clearancen buffer, simultaneously available data is pushed the Huffman decoder from buffer.

The syntactic element (syntactic elements) and the video encoding standard that have directly been reflected different images by the major part of the control token of initial detector output. Detector for initial code is transformed into the control token with syntactic element. Except these natural token parts, some uniquenesses and/or machine dependent token have also been produced. These unique tokens comprise some specially for use the token that designs in system of the present invention, and the latter is unique in itself, helps to embody the character of the many standards of adaptation of the present invention. The example of these unique token has PICTURE_END and CODING_STANDARD.

Also introduce some tokens, removing some the grammer difference between each coding standard, and possessed the function that cooperates with the condition of makeing mistakes. The automatic generation of token is that the data relevant with standard are being done just to finish after a series of analyses. Therefore spatial decoder is identical to the response of two class tokens. One class is that those directly have been provided to the token that spatial decoder is the SCD input, and a class is that those detect the token that has produced after the initial code in coded data. A succession of extra token is inserted into two-wire interface, in order to control many standard feature of the present invention.

MPEG has relevant with standard, non-data, discernible bit models with encoded video streams H.261, and one of them will be known as initial map (start image) and/or relevant code with standard from now on. The code that plays similar effect in JPEG is flag code (marker codes). These initial/flag codes are used for the pith of recognition coding data flow grammer. By detector for initial code finish initial/analysis of flag code is the first step of coded data being made syntactic analysis (parsing).

The modelling of initial/flag code must make them can be needn't be just identified to whole bitstream decoding. So according to the present invention, they can be used for assisting to do makeing mistakes restores and work that encoder starts. Detector for initial code is provided at and detects wrong facility in the encoded data structure, and helps the decoder starting. Decoder starting process and detector for initial code detect wrong ability and all will be described in a more detailed discussion afterwards.

Above explanation be mainly concerned with machine dependent bit stream characteristic and with the relation of addressing characteristic of the present invention. Bit stream characteristic hereinafter with reference to the detector for initial code explanation coded data relevant with standard.

The compressing and coding system of each standard has used a kind of initial code configuration (configuration) or its map of uniqueness, and it is in order to identify the specific standard of this system for selected use. Every kind of initial code is also all with oneself with the initial code value. Initial code value is used for the identification action type relevant with this initial code in the speech range of this standard. In many standard decoders of the present invention, as previously mentioned, compatible configuration based on control token and data token. Indicator signal comprises marking signal, is produced by circuit in each state machine inside, and they will be illustrated when suiting from now on.

The initial code that in each standard, comprises and/or flag code, and with opposed other standard word of data word, sometimes be considered to map, obscure mutually with the code and/or the machine dependent code that use avoiding, the latter refers to the control token that uses and/or the content of data token in machine. Moreover this word of initial code uses as generic word (generic term) often, refers to MPEG and initial code H.261, also refers to the jpeg marker code. The purposes of flag code and initial code is identical. Have, " flushing " word both had been used to refer to the FLUSH token again, also used as verb, for example (comprised " flushed " of signal in " being rinsed ") when mentioning the shift register of flushing detector for initial code. For avoiding confusion, the flushing (English words) in the flushing token is always write with upper case. Other usage of this word (verb or noun) is used lower case.

The coding input picture input stream relevant with standard is comprised of data and the initial map of different length. Initial map is with oneself with numerical value, and this numerical value informs which kind of operation the user will carry out according to this standard to the data that are right after thereafter. Yet in many normal stream waterline treatment system of the present invention, requiring has compatibility to multiple standards, and system through optimizing, can carry out all operations with all standards. Therefore, under many occasions, must set up unique initial control token, not only they are compatible with the numerical value in the numerical value that is included in the code signal Standard Mapping, they can also control operations of going to simulate this standard at different levels, and the parameter that every kind of standard has the one's own profession of appointment to know represents its operation. All such standards all embody in this manual according to reference.

Importantly understand the relation between the token, these tokens individually or with other control token in combination simulation package be contained in non-data message in the standard bit streams. Each state machine produces a cover indicator signal separately, comprises marking signal, to do certain processing in this state machine inside. Numerical value subsidiary in each standard can be with visiting machine dependent each control signal, so that simulation is to the operation of normal data and non-data-signal. For example, the slice_start token is the double word token, and then it enters aforesaid two-wire interface.

The data that are input to system of the present invention can be from any suitable data source, for example disk, tape etc., the data of coming. Data source offers first functional level of spatial decoder with 8 bit data, detector for initial code (Figure 11). Detector for initial code comprises three shift registers; First shift register 8 bit wides, next 24 bit wides, more next 15 bit wides. Each shift register is the part of two-wire interface. The data of coming from data source in a timing cycle with single 8 byte first register of packing into. After this, ground of content of the first shift register moves into decoding (second) shift register. At 24 all after dates, 24 bit registers are just full.

First shift register of once packing into of per 8 cycles of octet. Each the byte value of being loaded into shift register 221 (Figure 20) then uses 8 additional cycle with its clearancen, and shift register 224 is packed into. It has used 8 cycles clearancen, so three such operations or after 24 weeks, still have the content of three bytes in 24 bit registers. Value decode shift register 230 still is empty.

Supposing has a PICTURE_START word now in 24 bit shift register, sense cycle has been recognized the form of this PICTURE_START code, and provides initial signal to export as it. In case it is initial that detector detects once, the byte after this signal is the value relevant with this initial code, and this byte is current just to be accounted in value register 221.

Be identified as initial code owing to detect the content of shift register, its content must be removed from two-wire interface, no longer is further processed with these three bytes guaranteeing. Codec register is by clearancen, and the value decode shift register is being waited for and will all moved past next value through such register.

A value relevant with PICTURE_START is arranged on the low order position of value decode shift register now. The signal corresponding with the PICTURE_START signal of standard is called SD PICTURE_START in the spatial decoder. SD PICTURE_START signal itself is about to be included in the token head now, and value also is about to be included in the expansion word of token head. 10, token

In practice of the present invention, token is a kind of broad-spectrum adaptation unit (adapta-tion unit), its form is an interactive interface packets of information (an interactive interfacing messenger package), is used for control and/or data. It is adapted to the reconfigurable use of processing level. The latter (RPS) is when a certain token of having identified of response, to oneself reshuffling to carry out various operations.

In order to realize different functions, token can or relevant with the position of processing level, perhaps with location independent. Token also can be out of shape, and they can be revised by a certain processing level, then pass to down streamline to carry out more function. Token is can be with all at different levels or be less than all at different levels working in coordination, and in this sense, token can be worked in coordination with adjacent level and/or non-conterminous level. Token can be relevant with the position to some function, and to other functions and location independent; The concrete interaction of token and certain one-level can be take the processing history in past certain grade of as condition.

The PICTURE_END token is a kind of method that the sign image finishes in many standard decoders.

Many standard tokens be with MPEG, JPEG and H.261 data flow be mapped to a kind of method of single decoder. This decoder uses relevant with standard and with the irrelevant hardware of standard and control the mixture of token.

The SEARCH_MODE token is a kind of MPEG of search, JPEG and the skill of data flow H.261, and its allows the error recovery of random access and enhancing.

The STOP_AFTER_PICTURE token is clearly to finish a kind of method of decoding, and it indicates the end of an images and removes decoder stream waterline, i.e. passage conversion (channel change).

In addition, filling is with a kind of method of any digit by fixed size, fixed width buffer to token.

Target of the present invention is a kind of token and two wire device, variable pipeline processes system of configuration of using. Adopt control token and data token and combine with two wire device, make multi-standard system become easy. Compare with the system that does not use the control token, it has the operational capacity of expansion.

The control token is produced by the Circuits System of decoder processor inside, and they simulate the work of many dissimilar signals relevant with standard, and these signals are sent into the pipeline processor of serial and accepted processing. Employed method is to study all parameters of those many standards of being selected by serial processor, attention 1) similitude of these standards, 2) their difference, 3) their needs and requirement, 4) select correct token function, the standard signal of sending into serial processor effectively to process all. The effect of token is that standard is simulated. The agency part ground of control token partly is used as the key element of communicating control information in pipeline processor as the emulation between the signal relevant with standard/conversion.

In the system of prior art, be the special machine that can recognize standard according to the well-known process design, then establish special-purpose line system by MPI. The signal that comes from microprocessor is used to control data flowing special-purpose downstream components. The selection of this decompressing function, timing and organize under the control that all is in fixing logic circuit have the signal of microprocessor to participate in control.

With above-mentioned contrast, system of the present invention then under the control of control token to each functional level configuration in downstream. Obtain control essential and/or its replacement from MPU (microprocessor unit), this provides as option.

Token provides and has formulated the form that gears to actual circumstances for transmission information in the decompression circuit pipeline processor. In the design that embodiment that select hereinafter, preferential uses, each token word at least 8 bit wide, a token can continue one or more words. The variable-length of address field, and may continue a plurality of words. In a preferred embodiment, the address is no longer than 8. Yet this is not the restriction to the scope of application of the present invention, and this has just limited and has utilized these tokens and treatment step number that must finish, selected. Attention is under extension bits Identifiaction plates item, and the extension bits in word 1 and word 2 is 1, and its meaning is after this some add-word will occur. Extension bits in the word 3 is 0, therefore indicates the end of this token.

Token also can be that variable bit is long. For example, the token word is 9, adds extension bits, is exactly 10 altogether. In design of the present invention, the width of each output bus also is variable. The output of spatial decoder is 9 bit wides, perhaps, when comprising extension bits, is 10. In preferential embodiment, utilizing unique token of these extension bits is data tokens; All other tokens are all ignored this extension bits. Should be understood that this is not restriction, this is a kind of realization.

Profiling characteristic by application data token and control token just just may change the length by the data of these data tokens transmission, and this is that the meaning of figure place is said in the word. For example, once discussed, some data bit in the data token word can with another word of same data token in some data bit combine, forming 11 or 10 bit address, be used for each random memory that access spreads over this serial decompression processor. This has just increased variable degree, also just makes greatly to expand multifunctionality and become easily.

As previously mentioned, data token is processed level with data from one and is sent to the next one. Therefore, the characteristic of this token has changed during by decoder at it. For example, in the input of spatial decoder, what data token carried is bit sequence (bit serial) coding video frequency data that 8 words form. Herein, to the length of each token without limits. Yet, in this respect multifunctionality (in the output of spatial decoder circuit) in order to demonstrate the invention, each data token has 64 words just, and every word is 9 bit wides. More particularly, the standard code signal allows the message of different length to the different densities and different details codings of image. First width of cloth during one picture group resembles has the longest data bits usually, because it need to provide maximum information to processing unit, so that it can go to begin to decompress with information as much as possible. In a typical case, the length of follow-up word is shorter, is the difference signal that the second place on the first word and the scanning information field is drawn more afterwards because they comprise.

System is desired as standard code, and these words are mingled with mutually, so that the data of varying number can be provided for the spatial decoder input. Yet after spatial decoder was finished effect, its output information but was to suit to provide in the pixel format speed that screen shows. For different demonstration standards from the whole world integrate with (such as NTSC, PAL and SECAM), can change with the output speed of spatial decoder time representation. The static image speed that video formatter becomes to be suitable for showing with this variable visual rate transition. But pictorial data is still transmitted by the data token of 64 words. 11, DRAM interface

In three decoder chips each has all been used the configurable DRAM interface of independent high-performance. In general, the DRAM interface on each chip is the same basically, but these interfaces are different aspect the treatment channel order of priority how. It is spatial decoder, temporal decoder and the used DRAM of video formatter that this interface is designed to directly drive. In typical case, in those systems, the DRAM interface does not always need external logic, buffer or other assembly to the connection between the DRAM.

According to the present invention, interface can dispose from two aspects:

1, the detailed timing relationship of interface is configurable, to be fit to various dissimilar DRAM.

2, data-interface is configurable to the width of DRAM, in order to reach the compromise of price/performance in different application.

In general, the DRAM interface is the every part upper and standard is irrelevant that is contained in three kinds of chips of native system. Again repeat, they are spatial decoder, temporal decoder and video formatter. Again referring to Figure 11,12 and 13, these figure have showed respectively the block diagram that concerns of DRAM interface and spatial decoder, temporal decoder, video formatter remainder. On every kind of chip, the DRAM interface is connected to certain outside DRAM with chip. Use DRAM also not conform to reality because in sheet, making up to now the required relatively huge DRAM of quantity. Attention: each chip has its outside DRAM and its DRAM interface.

H.261, JPEG and MPEG in addition, although DRAM interface and compression standard are irrelevant, it still must be configured to realize each standard in many standards. As for how the DRAM interface being reshuffled to realize many standard operations, this will be described further in this specification back.

Understand the work of DRAM interface, correspondingly need to understand the relation of DRAM interface and address generator, and understand the two and how to communicate by letter with two-wire interface.

In general, as its name suggests, address generator produces the DRAM interface to the required address of DRAM addressing (namely reading or write the particular address of DRAM). Two-wire interface has been arranged, only had read and write just occurs when the DRAM interface has data (from each prime of streamline) and effective address (from address generator) simultaneously. As discussed further below, use address generator separately both to simplify the structure of address generator, also simplified the structure of DRAM interface.

In the present invention, the DRAM interface can move under a kind of clock, and this clock and address generator are asynchronous, and it is also asynchronous with the clock at different levels that data communication device is crossed. Adopted special skill to treat this asynchronous behavior of operation.

Data typically transmit (sole exception is the prediction data in the temporal decoder) take the piece of 64 bytes as unit between DRAM interface and chip remainder. Transmit by the device of a kind of being called " alternately buffer " and realize. This mainly is a pair of RAM with the work of two buffer memory form, the DRAM interface fill or RAM of clearancen in, chip another part clearancen or fill another RAM. Each replaces buffer and is furnished with minute other bus, to transmit from the next address of address generator.

In the present invention, every kind of chip has four alternately buffers, but these effects that replace buffer are not identical in every kind of situation. In spatial decoder, one alternately buffer be used for coded data is sent to DRAM, another is used for reading coded data from DRAM, the 3rd is used for the token data are sent to DRAM, the 4th is used for reading the token data from DRAM. In temporal decoder, then be one alternately buffer be used for the pictorial data of base (intra) or prediction is write DRAM, read the pictorial data of base or prediction from DRAM for second, read forward direction or back forecast data for all the other two. In video formatter, one alternately buffer be used for data are sent to DRAM, its excess-three is used for from the DRAM read data, each respectively reads in brightness (Y) and red, the blue chromatism data (being respectively Cr and Cb) one.

Below explanation is had one write alternately buffer and one and read the alternately work of the imaginary DRAM interface of buffer. It is basically identical with the work of the DRAM interface of spatial decoder. Working condition illustrates in Figure 23.

Other control interface between at different levels of chip that Figure 23 shows address generator 301, DRAM interface 302 and transmits data all is two-wire interface. Address generator 301 can produce as the address that receives control token result, also can only produce fixing address sequence (the FIFO buffer that for example, is used for spatial decoder). The DRAM interface is treated the two-wire interface relevant with address generator 301 with particular form. When being ready to accept the address, it does not make acceptance (accept) line remain height, but waits for that address generator provides effective address, processes this address, then puts acceptance line for high during a clock cycle. So, it has realized request/response (REQ/ACK) agreement.

Exclusive characteristics of DRAM interface 302 are that it can reach and provide or accept the at different levels of data and communicate by letter with address generator 301 independently. For example, address generator can produce with write buffer alternately in the relevant address (Figure 24) of data, occur but do not have action, signal and show that an existing blocks of data is ready to outside DRAM to be written until write alternately buffer. Say similarly, write alternately that buffer can contain data that have been ready to outside DRAM to be written, but action occurs, until there is the address to be added on the suitable bus from address generator 301. In addition, in case a RAM who writes in the buffer alternately has been full of data, another RAM is clearancen fully, and is stopped (letter of acceptance of two-wire interface is set to low) in the data input and just " replace " before and arrive DRAM interface side.

In the process of understanding DRAM interface 302 work of the present invention, importantly in a suitable system of configuration, the DRAM interface must can make alternately transmit data between the buffer and outside DRAM 303 speed at least and to replace all the average speed sums of transmission data between buffer and the chip remainder the same fast.

Each DRAM interface 302 determines which will use replace buffer its next time. In general, this will be once " circulation " (round robin) (namely, the alternately buffer that uses next time be recently minimum taking turns to and next time available that), or a preferred order encoder (namely, therein, some replaces buffer and has higher priority than other). In both cases, refresh requests generator (refresh request generator) all can be sent additional request one time, and this request is all higher than the priority of all other requests. Refresh requests is produced by refresh counter, and the latter can programme by MPI.

Referring now to Figure 24,, be to write the alternately block diagram of buffer there. Writing alternately, the buffer interface contains two RAM, RAM1 311 and RMA2 312. Further will discuss as this paper, under the control of write address 313 and control 314, the data of coming from prime are written into RAM1 311 and RAM2 312. Data are from RAM1 311 and RAM2 312. Data write DRAM 315 from RAM1 311 and RAM2 312. When data were write DRAM 315, the row address of DRAM was provided by address generator, and column address is then provided by write address and control signal, and this also will narrate from now on. During operation, valid data (data input) occur at input 316 places. In typical case, from the prime receive data. Along with each data is received from prime, it is written into RAM1 311, and then write address control makes the address increment of RAM1, writes RAM1 to allow next data. Data continue to be written into RAM1 311, until or no longer include data, or RAM1 is full. When RAM1 was full, input side abandoned controlling subsequent signal to the side of reading, and RAM1 has been ready to be read out now with indication. This signal passes through between two kinds of asynchronous clock systems, therefore passes through the trigger of three synchronous usefulness.

If RAM2 312 is empty, next data of coming in input side just are written into RAM2. Otherwise, behind RAM2 312 clearancens, just write. Point out to take turns to now when reading this and replacing buffer when circulation or priority encoder (which using decide on individual chip), the DRAM interface just reads the content of RAM1 311 and they is write outside DRAM 315. Then, cross asynchronous interface and send a signal back to, RAM1 311 is ready to now and can again be filled with expression.

If DRAM interface clearancen RAM1 311 also " replaced " before input side is full of RAM2 312 to RAM1, then data can constantly be accepted by replacing buffer. Otherwise when RAM2 was full, alternately buffer can set low its acknowledge(ment) signal, is used for input side until RAM1 " has replaced " to return.

According to the present invention, read the work of buffer alternately similarly, but want the mountain peak bus of falling input and output.

The design of DRAM interface of the present invention makes it have maximum available memory bandwidth. Each data block of 8 * 8 exists in the same DRAM page or leaf. Therefore, can use fully the variety of way of the quick access to web page of DRAM, this mode provides first a row address, and many column address then are provided. Particularly, row address is supplied with by address generator, and column address is supplied with by the DRAM interface. This also will further discuss afterwards.

In addition, this interface also has such device, and the width that it allows to receive the data/address bus of outside DRAM is 8,16 or 32. Therefore, employed DRAM quantity can match with application-specific required size and bandwidth.

In this example (it is identical with the DRAM interfaces principle in the spatial decoder), address generator provides each read and write to replace the address of devices of buffer to the DRAM interface. This address is as the row address of DRAM. Six column address itself is provided by the DRAM interface, and these six also as the address that replaces buffer RAM. Extremely alternately the data/address bus of buffer is 32 bit wides. Therefore, if extremely the highway width of outside DRAM is less than 32, then next word from write alternately buffer and read or next word write study in alternately buffer before (read and write refers to the direction of transfer with respect to outside DRAM), must carry out the access of twice or four times outside DRAM.

If temporal decoder and video formatter, situation is just more complicated. The addressing of temporal decoder is more complicated to be because its prediction aspect, and this further discusses in this section. The addressing of video formatter is more complicated to be many standards aspect of exporting owing to video, and this further discusses in each joint relevant with video formatter.

As previously mentioned, temporal decoder has four alternately buffers: wherein two are used for the base (I) of read and write decoding and the pictorial data of prediction (P). This work is as aforementioned. Two are used for receiving prediction data in addition. These two buffers are comparatively interesting.

In general, prediction data will be according to x and the y value of moving dynamic vector regulation, from this piece position skew of processing. Therefore there is the general border of getting along well the data block when originally encoding (and writing DRAM) of that blocks of data of (to be retrieved) to be retrieved to conform to. This point represents in Figure 25, the piece that is forming with the area representative of shade, and the piece that the dotted outline representative is being calculated. The address transition that address generator will move the dynamic vector defined becomes piece skew (the monoblock number represents with large arrow) and pixel skew (representing with little arrow).

In address generator, frame point, matrix address and vector shift three addition remain from the address of the piece of DRAM retrieval with formation. If the pixel skew is zero, just only produce once request. If the skew of x direction or y direction is arranged, just produce Twice requests, i.e. original block address and be right after below address. If existing x skew has again the y skew, then produce four requests. For each piece that will retrieve, address generator calculates the initial sum halt address, and this preferably exemplifies.

Imagination has the pixel skew of (1,1), represents with the shaded area of Figure 26. Address generator is made four requests, and label in the drawings is A to D. The problem that solves is how Quick is for the row address sequence. Answer is to use " initial/as to stop " technology, is described as follows.

Investigate the piece A among Figure 26. Reading must (1,1) beginning and (7,7) end in the position in the position. The tentative byte (that is, 8 DRAM interface) of once reading. Three least significant bits in the x value calculated address of coordinate (co_ordinate pair) centering, the y value forms three highest significant positions. The initial value of x and y all is 1, so the address is 9. Data are read from this address, then x increment. This process repeats, and stops value until the x value arrives. At this moment the y value initial value that increases 1, x reloads, and provides address 17. After each data byte was read, the x value increased again until arrive its value that stops. This process repeats, and stops value until x and y value all arrive. So produced address sequence 9,10,11,12,13,14,15,17 ..., 23,25 ..., 31,33 ... ... 57 ..., 63.

Similarly, it is (1,0) and (7,0) that the initial sum of piece B stops coordinate, and piece C is (0,1) and (0,7), and piece D is (0,0) and (0,0).

Next problem is where these data should write. Clearly, see piece A, the data of reading from address 9 write the address 0 that replaces the buffer, and should write the address 1 that replaces the buffer from address 10 sense datas, etc. Similarly, the data that read address 8 in the piece B should write the address 15 in the buffer alternately, and the data of reading from address 16 should be at writing address 15 in the buffer alternately. This function proof can have very simply realization, is summarized as follows.

Investigating piece A exists. When reading to begin, replace the anti-value (inverse) that the buffer address register is packed into and stopped to be worth. Y is counter, and the value that stops to form 3 highest significant positions, and x is counter, and the value that stops to form 3 least significant bits. In this case, when DRAM interface when externally DRAM reads address 9, alternately the buffer address is zero. Then, when the increment of outside DRAM address register, alternately buffer address register increment, this is consistent with appropriate prediction addressing.

So far, discussion concentrates on 8 DRAM interfaces. If 16 or 32 interfaces must be done a small amount of local modification. At first, must to pixel offset vector " pruning " (clip), make it point to 16 or 32 border. In the example that we use always, for piece A, first DRAM reads sensing address 0, and the data in address 0 to 3 will be read. Secondly, must abandon unwanted data. This reads after all data being write register alternately (aequum when its physical capacity must be than 8 is large) and adding skew. When carrying out MPEG half pixel interpolation, must read from the DRAM interface with 9 bytes that x and/or y represent. In the case, address generator provides suitable initial sum halt address. In the DRAM interface, used some extra logics, but the working method of DRAM interface there is not basic change.

A bit be to provide additional information with indication which kind of processing to be data done to predictive filter to what temporal decoder DRAM interface of the present invention will be noted at last. This information is comprised of following:

" last byte " signal is to indicate last byte that once transmits (64,72 or 81 byte);

H.261 indicate;

Bi-directional predicted sign;

Two binary digits are with the size of expression piece (8 or 9 bytes representing with x and y); And

The number that is formed by two binary digits is to indicate each piece order.

The sign of last byte can produce when alternately buffer is read in data. All the other letter address generators obtain, and transmit by the DRAM interface, so that when the predicted filter of data was read from replacing buffer, these signals and correct data block were associated. In video formatter, data write outside DRAM one by one, but read by the light order. Write with the method for the front spatial decoder that has illustrated identical. But slightly more complex. Data in the outside DRAM of video formatter are done so to arrange, so that at a list 8 blocks of data of packing at least. These 8 is 8 continuous horizontal block. When raster scanning, from each piece of these 8 continuous blocks, read 8 bytes, and it is write alternately buffer memory namely, every same delegation in eight). Investigate highest line (the supposition interface is a byte wide), x address (three minimum positions) are set to zero, too zero setting of y address (3 the highest significance bits). Then, when inferior 8 bytes are read out, the increment of x address. At this moment, the address high-order portion position 6 and above position because least significant bit is position 0) rise in value, and x address (3 significance bits) is reset to zero. This process constantly repeats, until 64 bytes are whole. If to the interface width of outside DRAM be 16 or 32, need only be respectively with the x address or increase four, rather than increase one. In the present invention, address generator can signal to the DRAM interface requirement and read to be less than 64 (these needs may be arranged at a capable head or tail place of grating), although it always reads 8 multiple. This can and stop value with initial value and reach. Initial value is used for address bit (position 6 and above position), stops value and initial value relatively, stop to read when signal refers to produce. DRAM interface timing part has in the present invention used timing chain, so that the DRAM signal is along 1/4th cycles that are accurate to system clock. With the clock of 90 ° in the phase place come by phaselocked loop. They are combined into nominal twice clock. Then each chain forms with two parallel shift registers, with anti-phase each other twice clock work.

At first, there is a chain to produce the start of Page cycle, another generation read/write/refresh each cycle. The length in each cycle can be programmed by microprocessor. Through after such programming, the start of Page chain has fixing length; And the length of another periodic chain is variable during a start of Page, is as the criterion with suitable.

When resetting, each chain is eliminated, and produces a pulse. Pulse is advanced along each chain, and is subjected to from the control of the next status information of DRAM interface. This pulse produces the clock of DRAM interface. The clock cycle of each DRAM interface, therefore, because there is different length in the DRAM cycle, the speed of DRAM interface clock was not constant corresponding to the week of DRAM.

In addition, other has some timing chains will be combined with the information of coming from the DRAM interface from the pulse that above-mentioned each chain comes, and produces output gating and enable signal, such as notcas, notras, notwe, notbe. 12, predictive filter

Again consult Figure 12,17,18, particularly Figure 12, show there the block diagram of temporal decoder. It comprises predictive filter. The relation of predictive filter and termporal filter remainder illustrates in greater detail in Figure 17. The structural element of predictive filter is seen Figure 18 and Figure 28. The detailed description of predictive filter work can be found in " more detailed description of the present invention " joint.

In general, according to the present invention, predictive filter is in MPEG and mode and not using under the JPEG mode H.261. Please remember that in the JPEG mode, temporal decoder just is sent to video formatter with data, it does not do the decoding of any essence, except the sort of decoding that spatial decoder is done. Again consult Figure 18, in the MPEG mode, the forward and backward predictive filter is equal to, and they carry out filtering to MPEG forward and backward prediction piece respectively. Yet, in mode H.261, only use the forward prediction wave filter, because H.261 without back forecast. Two predictive filters of the present invention are in fact identical. Again consulting Figure 18 and 28, particularly Figure 28, is the block diagram of predictive filter structure there. Each predictive filter is comprised of the level Four of series connection. Data enter form level 331, are placed among the form that carries out easily filtering. In next stage 332, the X-coordinate is carried out I-D calculate. After dimension buffer (dimension buffer) level 333 is finished necessary transposition, the prediction of carrying out the Y-coordinate in level 334. How to predict and to illustrate in greater detail afterwards. Need which filtering operation, this is defined by compression standard. If H.261, the filtering of carrying out and low pass filter similar.

Consult again Figure 17, many standard operations requirement forecast wave filter can be reconfigured so that or carry out MPEG or H.261 filtering, or do not carry out filtering in the JPEG mode. As other many reconfigurable aspects of three chip systems, predictive filter also is that the method with token is reconfigured. Token also is used for informing this particular job of address generator mode. Use this way, address generator just can provide to predictive filter the address of desired data, and these addresses difference between MPEG and JPEG is very large. 13, to the access of register

Most of registers in MPI (micro processor interface, MPI) can only work as they with it relevant level stop Shi Caineng and be modified content. Therefore, each is organized register and always typically links together with access register. Value in access register zero indicates that group register relevant with this access register and should not be modified. In access register, write 1, just ask certain level to quit work. Yet this level does not stop immediately, so the level access register is with retention value zero, until this level stops.

Any user software relevant with MPI and that finish the work by MPI all must " writing after 1 to certain request access register " wait for, until read 1 from this access register. If during its access register zero setting, the user writes certain configuration register (configuration register) with value, and is consequently uncertain. 14, MPI

On all circuit in spatial decoder and temporal decoder, all used the MPI (MPI) of a byte wide of standard. The various clocks of the work of MPI and spatial decoder and temporal decoder are all asynchronous. Table A .6.1 in being described in more detail referring to the back, it shows the various MPI signal that is used on this interface. The character of signal illustrates in the I/O hurdle, and signal name illustrates in the signal name hurdle, and the explanation of semiotic function illustrates in the explanation hurdle. A.6.2 the power technology condition of MPI sees Table. All technical conditions are all classified according to type, and these types illustrate in title is the hurdle of symbol. Explanation illustrates in the parameter hurdle to these symbologies and so on. Actual technical conditions illustrate in corresponding minimum, maximum and each hurdle of unit.

Each DC (direct current) condition of work can be referring to Table A .6.3. The title on each hurdle and Table A .6.2's is identical in the table. The Dc electrical characteristics illustrate with Table A .6.4, other each column headings and Table A .6.2 and A.6.3 describe identical. 15, MPI's reads regularly

AC (interchange) characteristic that MPI reads timing diagram illustrates with Figure 54. Each provisional capital among the figure marks with corresponding signal name, regularly provides take nanosecond as unit. The Timing characteristics of reading that MPI is detailed represents with Table A .6.5. Title is that the column of number (Number) is used for representing that signal corresponding to the signal name shown in the characteristic hurdle. Column take MIN and MAX as mark provides respectively the maximum duration that shortest time that signal exists and signal can be used. Unit one hurdle provides to describe the measuring unit of signal. 16, the write timing of MPI

The general description of MPI write timing figure is seen Figure 54. The figure shows the title of each respective signals relevant with the MPI write timing. The title of signal, feature and other all physical characteristics are shown in the table 6.6. 17, keyhole address location (KEYHOLE ADDRESS LOCATIONS)

In the present invention, after the keyhole register, placed some Mapping memory unit of asking without frequentation. The keyhole register has two registers relevant with it. First register is the keyhole address register. Second register is the keyhole data register. Certain memory cell (location) in expanded address space inside has been stipulated in the keyhole address. A read operation of keyhole data register or write operation these unit by the appointment of lockhole address register have just been accessed. After access lockhole data register, with it relevant lockhole address register increment. Each access only has new value is write the keyhole address register, just may carry out random access in the address space inside of expanding. Circuit in the present invention can have a more than keyhole Mapping memory. But, do not exist between the different keyholes and influence each other. 18, PICTURE_END

Refer again to Figure 11, the general diagram of the spatial decoder that diagram is used in the present invention. Will be by the effect of PICTURE_END be described with this block diagram. The PICTURE_END function has the advantage that adapts to many standards, and it can process H.261 enciphering image information, mpeg signal and JPEG signal.

As previously mentioned, the system of Figure 11 interconnects with aforesaid two-wire interface. Each functional part arranges to such an extent that they are worked like that according to state machine configuration shown in Figure 10.

In general, according to the present invention, the function of PICTURE_END begins at the detector for initial code place, and the latter produces PICTURE_END control token. PICTURE_END control token arrives the DRAM interface by start control circuit without change. Here it is used to writing in the DRAM interface replaced the buffer removing totally. Please remember to only have when alternately buffer is full, its content just is written to RAM and goes. Yet an images may everywhere not finish at buffer, thereby causes the obstruction of pictorial data. The PICTURE_END token forces these data from alternately buffer output.

Because the present invention is many Standard Machines, for each compression standard, the operation of machine is different. More detailed say that machine has been done so sufficient narration: it is according to machine dependent each action cycle work. For each compression standard, can by the combination of control token and/or the output signal from MPU, from total available action cycle, select the cycle of certain number; Perhaps, can they be selected by the design of these tokens itself. From then on say on the meaning that the present invention organizes like this, information is postponed enter follow-up parts, until all information have been collected complete in upstream components. Native system is in wait state, until data have been ready to reach subordinate. The PICTURE_END signal is added to the coded data buffer by this way, and the control section of PICTURE_END signal is read out the content of data buffer and is added to the Huffman decoder and separates (Video demultiple-xor) circuit with vision signal.

Another benefit of PICTURE_END control token is, for the reason in Huffman decoder and the demultiplexer use, the end of image is identified, even image does not typically reach the full journey of expection and/or do not have the desired so much signal of typical case to be added to Huuf-man decoder and vision signal split circuit. In this occasion, the information in the coded data buffer as a width of cloth completely image be added to Hufman decoder and vision signal separator. Therefore, Huffman decoder and vision signal separator still can be processed these data according to the design of system.

Another benefit of PICTURE_END control token is its fully clearancen coded data buffer, is not retained in by accident among the outer DRAM of sheet or replaces in the buffer so that do not have fragmentary information.

Another benefit of PICTURE_END function is that it is used for error recovery. For example, suppose in the just maintained data volume of coded data buffer to be less than the amount of typically using that the latter is used for describing the spatial information that is as the criterion with a single image. Therefore, that last images can be retained in data buffer until alternately buffer is full; Yet according to definition, this buffer can not reinject. Sometime, machine can determine certain condition of makeing mistakes of existence. Therefore, as long as the PICTURE_END token is decoded, and it forces the data in the coded data buffer to be added to Huffman decoder and vision signal separator, and last image is with regard to decodable code, and information also can be from the buffer clearancen. Consequently, machine can not enter the error recovery mode, and can successfully continue to process coded data.

Use another benefit of PICTURE_END token to be, the serial pipeline processor can continue to process not interrupted data. Can process the data of lacking than anticipated number owing to used PICTURE_END token, serial pipeline processor to be configured to, can continue so process. Owing to possess the condition of makeing mistakes, use the machine of prior art itself to stop, this is typical case. As previously mentioned, when macro block entered the storage areas of coded data buffer, this buffer was just to count of macroblocks. In addition, Huffman decoder and vision signal separator know that usually namely, the state machine of Huffman decoder and vision signal separator is partly known its to be processed number within the restore cycle of every images to the information content of every images decoding expection. When the piece number that arrives from the coded data buffer not to the time, originally can bear the wrong process of recovering by typical real estate. Yet, because PICTURE_END control token has reconfigured Huffman decoder and vision signal separator, state machine can work on, and this is because reconfigure and informed Huffman decoder and vision signal separator, state machine processing an amount of information really.

Consult Figure 10, the token decode of cache manager partly detects the PICTURE_END control token that is produced by detector for initial code again. Under normal operation, as the alternately normal operation of buffer of addressing in the past, cache register was filled then clearancen before this. Say once again, part is packed the alternately buffer of data into can clearancen, until it is filled fully and/or it is known clearancen time is up. PICTURE_END control token is decoded in the token decode part of cache manager, and the alternately buffer that it forces to only have part to pack into is sent content into the coded data buffer with own clearancen. This content directly or by the DRAM interface is delivered to Huffman decoder and vision signal separator. 19, clear operation

Another advantage of PICTURE_END control token is the associated working of it and FLUSH token. The FLUSH instruction is both irrelevant with reconfiguring of state of a control machine, also with to system provides data independence. But it uses former partial information completion for machine dependent state machine. Each such state machine is controlled token with FLUSH and is regarded the information of disregarding as. Therefore, the FLUSH token is used to the vacant part that the coded data buffer stays is filled, and allows one group of complete information to send to Huffman decoder and vision signal separator. Therefore, the FLUSH token is similar to the filling (padding) of buffer.

Token decode device in the Huffman circuit is recognized the FLUSH token, forces the pseudo-data that enter it but ignore by the FLUSH token. Before so the Huffman decoder only arrives to PICTURE_ END token and FLUSH token just those data contents of the final image buffer of existence operate. Use separately the PICTURE_END token or with another benefit that the FLUSH token is united use be the reconfiguring and/or recombinating of Huffman decoder circuit (reorgan-ization). Because the arrival of PICTURE_END token, the Huffman decoder circuit knows that it will have the information that is less than normal, expected to come final image is decoded. The Huffman decoding circuit finishes being included in the processing of the information in the final image, and this information is exported in the countercurrent fashion device through DRAM. In the end after the identification of image, the Huffman decoder enters immediately its reset mode and readjusts for the arriving of next pictorial information. 20, scavenging action

According to the present invention, the FLUSH token is in order to by whole pipeline processor, and guarantees that each buffer is reconfigured to wait for the arrival of new data by clearancen, other circuit. More particularly, the present invention comprises the combination of PICTURE_END token, filling word and FLUSH token, and it points out the image processing of current graphic form complete to the serial pipeline processor. After this, each state machine need to reconfigure to wait for new processing of new data arrival acceptance. Be also noted that the FLUSH token serves as resetting especially of native system. The FLUSH token resets it during by every one-level at it, but allows the continuation operations at different levels of back. This has just prevented loss of data. In other words, the FLUSH token is a kind ofly variablely to reset rather than definitely reset. 21, STOP_AFTER_PICTURE

The STOP_AFTER_PICTURE function is used for going the operating a certain logical point of compressor circuit to stop its work at the serial flow waterline. At this moment, produce the PICTURE_END token, designation data has finished to enter from Data In-Line, and the filling operation is also finished. The data token of part vacancy is filled in the filling operation. Then, produce the FLUSH token, it is released all information by the serial flow line system from register, force these registers to get back to the stand-by state of their neutrality. In other words, the PICTURE_END token sends the signal that image finishes, and STOP_AFTER_PICTURE then sends the signal that all current operations finish. 22, many standard search mode

Another characteristic of the present invention is to have used SEARCH_MODE control token, and it is used for reconfiguring the input of serial pipeline processor, the bit stream that enters with inspection. When the setting search mode, detector for initial code is only searched for for the specified start code of arbitrary compression standard or mark. Yet, it must be understood that, for realizing this purpose, also can be used to other image from other data bit stream. Therefore, these images can use in whole the present invention, and becoming another kind of the realization, the latter can also mix except reconfigurable circuit is arranged and uses control token and data token similarly to be operated.

In the present invention, the use of way of search suits under many occasions, wherein has: 1) if the interruption of data bit stream occurs; 2) when the user is interrupted data bit stream with the way of having a mind to change passage (for example, sending data here with the cable that transmits compressed digital video signals); Or 3) when the user when controlled data source (such as CD or optic disk) starts F.F. or fall soon. In general, when the user does not expect that at machine the place of interrupt interrupts the serial flow waterline when normally moving, way of search suits.

When any way of search was set up, detector for initial code was just sought the initial map of input that is suitable for producing machine-independent token. All data that entered detector for initial code before the identification initial map relevant with standard all are considered to meaningless and abandon, and machine is in idle condition when this information of wait.

Detector for initial code can be taked any in many configurations. For example, one of these configurations allow search one picture group to resemble or allow the initial code of higher degree. This pattern makes detector for initial code abandon its all inputs, and removes to seek the group_start Standard Mapping. When recognizing such map, detector for initial code just produces the GROUP_START token, and then way of search automatically resets.

Be important to note that Huffman decoder and vision signal separator are the single circuits according to multiple input signal work. These input signals have: the CODING_STANDATD signal also has each setting (set-up) signal irrelevant with standard. CODING_STANDA-RD signal will directly send from incoming bit stream, be Huffman decoder and the required information of vision signal separator. Yet, Huffman decoder and vision signal split circuit be with the operation of the irrelevant burst of standard under work.

Select this working method to be because it is the most effective, and according to its original design, can be used in the occasion of special control token. Use these special tokens, the signal relevant with standard can be sent into Huffman decoder and vision signal separator rather than transmit these actual signals itself.

23, the countercurrent fashion countercurrent fashion is a common feature of all three kinds of standards, and it is identical for all three kinds of standards. In general, the data token in the token-caching device contains the information of the value that is quantized coefficient (quantized coefficients), also contains the information (this is a kind of form of run length coding, RLC) of the zero number that shows between coefficient. Countercurrent fashion device of the present invention has adapted to token and has used, and it has just expanded the information of relevant zero the distance of swimming, makes data token contain 64 essential values. After this, the value in data token is exactly the coefficient that can be quantized by the process that the inverse quantization device uses. 24, inverse quantization device

Inverse quantization device of the present invention is the essential parts to sequential decoding, but it has been embodied as the whole integrated circuit group processing of permission multi-standard certificate. In addition, the inverse quantization device has been fit to use with token. The inverse quantization device is positioned between countercurrent fashion device and the anti-DCT (IDCT).

For example, in the present invention, the adder in the inverse quantization device is used for adding certain and counts to pixel decoder number before data are delivered on the IDCT.

IDCT has used pixel decoder number, and this number changes along with employed each standard of information coding. For information is correctly decoded, before data continue to be sent to IDCT, by the inverse quantization device 1024 value is added in the decoding number.

Adder is in the inverse quantization device. Standardization when using these adders to make data before the quantizer arrive IDCT. This has just saved Circuits System or software extra in the integrated circuit when processing the data of being compressed by various criterion. Other allow the operation of many standards operate in " operation after quantizing " during finish, discussion sees below.

Control token with data is decoded, and the standardized program of various realizations that needs the inverse quantization device to finish is identified, and identification as detailed below. The repetition of circuit has all been avoided in the realization of these " after quantizing " operations, also all allows this integrated circuit to process many standard codes data. 25, Huffman decoder and Parser machine

Consult Figure 11 and 27, spatial decoder comprises the Huffman decoder again, and the latter is used for decoding to being made the Huffman coded data by different compression standards.

JPEG, MPEG and H.261 each of standard all need some data is made Huffma-n coding, but every kind of desired Huffman decoding of standard is but different in some importances. In spatial decoder of the present invention, be not design and make three each other Huffman decoders, one of every kind of standard; The present invention identifies the common aspect of every kind of Huffman decoder, only makes these aspects once, saves valuable label space with such method. In addition, use cleverly many parts (multi-part) algorithm, made the many-sided of Huffman decoder of every kind of standard also can be common with other standard, otherwise just do not accomplished this point.

Briefly, Huffman decoder 321 is worked with other unit, sees Figure 27. These other unit are Parser state machines 322, input shift unit 323, data directory unit 324, ALU 325, and token formatter 326. As previously mentioned, the connection between these parts is controlled by two-wire interface. Working condition about these unit will be done more detailed introduction afterwards, stress the certain situation of Huffman decoder aspect the many standard operations of support according to the present invention here.

Parser state machine of the present invention is programmable state machine, and its effect is the remainder of coordinating video Parser (Video Parser). As the response to data, the Parser state machine produces therewith data control word side by side, and control word is transferred to other parts of system, these other parts is worked, thereby reach the purpose of control. Because these parts connect by two-wire interface, transfer control word and relevant data are not only useful but also essential abreast. Like this, data and control just arrive simultaneously. In Figure 27, the transmission of control word represents that with control line 327 it is positioned under the data wire 328 of connecting components. Except other task, this code word identification is just at that decoded specific criteria.

Huffman decoder 321 also has some control function. Particularly, Huffman decoder 321 contains and can control data directory unit 324 and calculate the state machine of patrolling unit 325 some function. It is necessary controlling these unit by the Huffman decoder, in order to component-level information is made appropriate decoding. Determine if allow Parser state machine 322 make these, will spend the too many time.

An importance of Huffman decoder of the present invention is can be to reading in each coded data bit negate of Huffman decoder. This is necessary to the Huffman code decoding of type H.261 the time, because the sort of special type and the employed code of JPEG of the employed Huffman code that H.261 (in fact also has MPEG) have opposite polarity. Therefore, use phase inverter in fact just to allow the Huffman decoder that three kinds of standards are used same table. How the Huffman decoder realizes that the other side of all three kinds of standards discusses in more detail in " to more detailed description of the present invention ".

Second one in multi-section (muti-part) algorithm finished in data directory unit 324. There is a look-up table that actual Huffman decoding (decoded) data are provided this unit. The call number that the tissue of each list item is produced take the Huffman decoder is as the basis.

Each remainder that the multi-section algorithm is realized in unit (ALU) 325 is patrolled in calculation. Particularly, ALU processing signals expansion. ALU also comprises the register group (register file) that keeps vector prediction and DC prediction, and their use is discussed in each joint relevant with predictive filter. In addition, ALU also has some counters, and they align by the structure of the image of spatial decoder decoding and count through and through, especially, the size of image is programmed, and sends in the register relevant with counter, and this has just made things convenient for the initial of the detection of " image is initial " and each macro block code.

According to the present invention, token formatter 326 (Token formatter, TF) will be assembled in the data token through the data of decoding and go, and then token is sent to other level or other parts of spatial decoder.

In the present invention, 323 receptions of input shift unit are from the data of FIFO (first in first out). The FIFO buffer memory is by the data of detector for initial code. The data that received by the input shift unit generally belong to two types: data token and initial code. Detector for initial code has been used these initial codes token replacement separately, and this further discusses in token one joint. Attention: occur at most in the data, the chances are needs the data token of decoding.

Input shift unit 323 with data serial deliver to Huffman decoder 321. On the other hand, its transfer control token concurrently. In the Huffman decoder, the Huffman coded data is decoded according to the first of multi-section algorithm. Especially, specific Huffman code is identified, and then index of reference number is replaced it.

Huffman decoder 321 is also identified some data that need to be done by other parts among Figure 27 specially treated. This data comprise block end and withdraw from. In the present invention, the 321 interior detections of Huffman decoder they, rather than detect them in the data directory unit 324, this has just saved the time.

Then this call number is sent to data directory unit 324. The data directory unit is look-up table in essence. According to an aspect of algorithm, the Huffm-an code table of look-up table and JPEG regulation is very nearly the same. In general, look-up table uses compression (condensed) data format, and this form is JPEG defined when transmitting the JPEG table that substitutes.

The call number of process decoding or other data are delivered to ALU325 with the control word of following from data directory unit 324, and the latter carries out aforesaid operations.

From ALU325 out, data and control word are sent to token formatter 326 (TF). In the token formatter, data basedly need to make up to form token with control word, then token is sent to the following at different levels of spatial decoder. Note, at this moment herein, system will with token had. 26, reverse discrete cosine transform (Inverse Discretc Cosine Tramform)

According to the present invention, reverse discrete cosine transform (IDCT) goes compression to the data relevant with the frequency of visual DC composition. When the specific image of a width of cloth was just compressed, the frequency of light was quantized in the image, thereby had reduced the information content that needs storage. IDCT gets this data through quantizing, and it is gone compression, is reduced into frequency information.

IDCT is to the part operation of image. The size of this part is 8 * 8 pixels. Mathematical operation to these data is mainly decided by used specific criteria that data are encoded. Yet, in the present invention, effectively utilized the common mathematical operations of each standard avoiding the unnecessary repetition of Circuits System.

Owing to used specific calibration order (scaling order), algorithm up and down two-part symmetry has improved, so common mathematical operations can reuse, has eliminated extra Circuits System.

IDCT responds many many standard tokens. The data that the first of IDCT checks into, correct with the size of guaranteeing data token, be fit to process. In fact, in certain this occasion, if error is not too large, token streams can be corrected. 27, cache manager

In the video information of cache manager acceptance input of the present invention, it returns the timing information that address generator provides data arriving, demonstration and frame frequency. Used a plurality of buffers to allow to occur the variation of (presentation) rate and demonstration (display) rate. In a typical case, always occurrence rate and display rate with coded data and showing that the monitor of information changes before this. The speed that data arrive changes with the mistake in coding, the decoding or with the source material that produces data usually. When information was come cache manager, it was gone compression. Yet data are according to going the useful order of compressor circuit to arrange, rather than the useful order of specific display unit is arranged. When a blocks of data entered cache manager, cache manager provided information to address generator, and this data block can be placed according to the order that display unit can be used. Buffer manager for use will be adjusted the conversion of the needed frame of input block speed and take into account, so that data block can show in employed particular display device.

In the present invention, the main task of cache manager is to provide information to address generator. However, yet want it to connect with other parts of native system. For example, have an interface to link to each other with input FIFO, FIFO is sent to cache manager with token, and cache manager passes to the write address generator with these tokens again.

Cache manager also connects with the address generator of display, whether is ready to show the information of new data to receive this display unit. Cache manager confirms that also the address generator of display removed the demonstration information in the buffer.

Cache manager of the present invention is monitoring all the time whether specific buffer is empty, full, is preparing to use or using. It is also monitoring the appearance relevant with particular data in each buffer number (presentation number) all the time. Therefore, cache manager partly determines the state of these buffers with the method that once only makes a buffer be ready to show. In case a certain buffer is shown, this buffer just is in " free time " state. When cache manager receives PICTURE_START, FLUSH, effectively or during access token, it just determines the state of each buffer and accepts the preparation of new data. For example, PICTURE_STA-RT token makes cache manager make an inspection tour each buffer, can accept new data so which to be found.

Cache manager also can be configured to process the desired multiple standards of token that it is received. For example, in standard H.261, during showing, data may be skipped. If such token is to cache manager, the data that skip will be eliminated from the buffer of storing it.

Therefore, by the management to buffer, can according in order to the compression standard of data codings, according to the speed of data decode with according to the display unit of use particular type, data be shown effectively.

Believe that above-mentioned explanation realizes general conception of the present invention, system and enough detailed suitable narration has been done in various work so that have the general technical ability of one's own profession the people can by its all characteristic, target and advantage be made and the actual the present invention of use. Yet, for the ease of the present invention there being further more intensive understanding, for the ease of obtain with various embodiments of the present invention more specifically, the relevant subsidiary details of more commercial realization, further specifying and explaining below suggestion is read.

This is the more detailed description to a multi-standard video decoder chipset. It is divided into three major part: A, B and C. For the ease of the convenience of tissue, succinct and explanation, being disclosed in the following part that this is additional is established.

The public characteristic of chipset chips is described:

Token (TOKEN)

Two-wire interface

The DRAM interface

MPI

Clock

The explanation of space decoding chip

The explanation of time decoder chip A.1

The first declaratives have comprised the overwhelming majority circuit design problem relevant with using chipset. A.1.1 typesetting and printing is arranged

For the information of emphasizing some type has been used the little collection of printing typesetting and printing agreement: the effective Wire_name signal of NAMES_OF_TOKENS token name Wire_name signal high level Low level effective register_name register name is Video Decoder series 30MHz operation decodes MPEG A.2, JPEG and H.261 the coded data rate reach 704 * 480 to the 25Mb/S video data rate to 21MB/S MPEG resolution ratio, 30Hz, the PQFP type encapsulation absolute coding data of sticking 208 lead legs of (Glue-less) page mode DRAM interface of the few subsides of the full JPEG baseline of the variable chroma of 4:2:0 (baseline) decoding and decoder clocks are reset (Re=orders) MPEG image sequence Video Decoder series provides a low chip-count scheme to realize the high resolution digital video decoder. For supporting three kinds of different videos and image encoding system: JPEG, MPEG and H. 261, chipset is normally configurable.

Full JPEG baseline image decoding is supported. 720 * 480,30Hz, the video of the JPEG coding of 4:2:2 can be by real-time decoding.

CIF (common interchange format) and QCIF H.261 video can be decoded. Have up to 740 * 480,30Hz, full feature (featrue) the MPEG video of 4:2:0 form can be decoded.

Attention: above-mentioned value just needn't be limited to this to illustrating of one embodiment of the invention. Correspondingly, the use of other value and/or scope will be appreciated. A.2.1 System Construction output format A.2.1.1

In the middle of the example that provides below, each example all needs the output format device of certain form, with the data that occur in the output that obtains spatial decoder or temporal decoder, and is that computer or display system are to its reformatting. The details of this format is different to different application. Under certain simple scenario, whole required just address generators obtaining the block format data by decoder chip output, and write memory with a raster order with it.

The pixel format device is a single-chip VLSI equipment, and it provides large-scale output format function. A.2.1.2 JPEG still image decoding

A single spatial decoder that does not have an outer DRAM of chip baseline jpeg image of can decoding rapidly. Spatial decoder will be supported all features of baseline jpeg. Yet dimension of picture that can be decoded will be subject to the restriction of the output buffer size that the user provides. The characteristic of output format device may limit chroma sampling form and the color space that can be supported. A.2.1.3 JPEG video decode

Add the video image that the outer DRAM of chip can real-time decoding JPEG mode encodes to spatial decoder. The size of needed buffer and speed will be according to video and coded data rates and are decided. The temporal decoder video that the JPEG mode is encoded that do not need to decode. Yet if temporal decoder comes across in the chipset of standard decoder more than, when system is jpeg operation when disposing, it only makes data communication device cross the time decoder and does not do any change or modification. A.2.1.4 H.261 decoding

Realize a H.261 Video Decoder, spatial decoder and temporal decoder all need. This DRAM is configurable to the interface of above-mentioned two kinds of devices, can reduce in order to finish the required DRAM quantity of proper handling when using the work of little pixel format and low coded data rate. Say that typically each spatial decoder and temporal decoder need a single 4Mb (namely 512K * 8) DRAM. A.2.1.5 mpeg decode

Finish the required configuration of MPEG operation with H.261 required identical. Yet the larger pixel format that will support MPEG to occur may need larger DRAM buffer, and the people of technical ability knows together as having this area. A.3 token token form A.3.1

Corresponding to the present invention, token provides widely form for the communication information by the decoder chip collection. Although in the present invention, each word of token has 8 bit widths at least, has in this area that the people of general technical ability knows together, and token can be any width. A single token can be striden one or several word in addition; This can realize by use an extension bits in each word. The form of token is summarised among the Table A .3.1.

Whether token of extension bits indication proceeds to another word. Extension bits all is set to 1 except the last character in all words of token. If it is 0 extension bits that the first character of token has, just illustrate that this token only has a word length.

Each token is identified by an address field, and it is from the 7th bit of token first character. This address field length is variable, and can reach a plurality of words (not having length to surpass the address of 8 bits in current chip, can be any length yet the people of this general technical ability in field of tool will recognize the address again).

Some interface transmits the data that surpass 8 bits. For example, the output of spatial decoder has 9 bit widths (comprising that extension bits then is ten bits). Unique token of obtaining benefit from these additional bit is data token. Carry out processing for certain ad-hoc location in system, data token can have many arbitrarily bits as required. Other all tokens are all ignored extra bit. A.3.2 data token

Data token is processed level with data from one and is taken the next one to. Therefore, the characteristic of this token changes during by decoder at it. And the data implication that data token carries changes according to the position of data token in system, that is to say, data are fixed according to the position. In this, according to the position of data token in spatial decoder, data both can be that frequency domain also can be the pixel domain data. For example, in the input of spatial decoder, data token carries the Bit String coding video frequency data that is assembled in 8 bit words. Here, the length of every token without limits. Yet by comparison, in the output of spatial decoder, each data token just carries 64 words and each word is 9 bit widths. A.3.3 use the data of token format

In the middle of some was used, circuit need to directly link to each other with input or the output of decoder or chipset. As a rule, collect data token and that several tokens of synchronizing information (such as PICTURE_START) that provide are provided is enough. In this, see also the A.16 part of back, " output of connection space decoder " and A.19 the part " output of connect hours decoder ".

As discussed above, the activity of observing extension bits is enough to identify when a new token begins. Moreover, the extension bits sign the last word of current token. In addition, address field can be tested with the identification token. Do not need the token that maybe can not identify to be eliminated (and abandoning) and need not know their content. Yet the token that is identified can cause the appearance of an appropriate action.

In addition, the data that input to spatial decoder can be used as the data byte that is encoded or are provided with the form of data token (seeing A.10 part, " coded data input "). Provide token that many characteristics of decoder chip collection are set up from data flow by the coded data port or by MPI. This provides the another kind of approach of finishing configuration by MPI.

Table A .3.1 token list

7 6 5 4 3 2 1 0	The token title	Reference
				0 0 1	QUANT_SCALE
0 1 0	PREDICTION_MODE
			0 1 1	(reservation)
1 0 0	MVD_FORWARDS
			1 0 1	MVD_BACKWARDS
0 0 0 0 1	QUANT_TABLE
			0 0 0 0 0 1	DATA
1 1 0 0 0 0	COMPONENT_NAME
			1 1 0 0 0 1	DEFINE_SAMPLING
1 1 0 0 1 0	JPEG_TABLE_SELECT
			1 1 0 0 1 1	MPEG_TABLE_SELECT
1 1 0 1 0 0	TEMPORAL_REFERENCE
			1 1 0 1 0 1	MPEG_DCH_TABLE
1 1 0 1 1 0	(reservation)
			1 1 0 1 1 1	(reservation)
1 1 1 0 0 0 0	(reservation) SAVE_STATE

Table A .3.1 token list (continuing)

7 6 5 4 3 2 1 0	The token title	Reference
				1 1 1 0 0 0 1	(reservation) RESTORE_STATE
1 1 1 0 0 1 0	TIME_CODE
			1 1 1 0 0 1 1	(reservation)
0 0 0 0 0 0 0 0	NULL
			0 0 0 0 0 0 0 1	(reservation)
0 0 0 0 0 0 1 0	(reservation)
			0 0 0 0 0 0 1 1	(reservation)
0 0 0 1 0 0 0 0	SEQUENCE_START
			0 0 0 1 0 0 0 1	GROUP_START
0 0 0 1 0 0 1 0	PICTURE_START
			0 0 0 1 0 0 1 1	SLICE_START
0 0 0 1 0 1 0 0	SEQUENCE_END
			0 0 0 1 0 1 0 1	CODING_STANDARD
0 0 0 1 0 1 1 0	PICTURE_END
			0 0 0 1 0 1 1 1	FLUSH
0 0 0 1 1 0 0 0	FIELD_INFO

Table A .3.1 token list (continuing)

7 6 5 4 3 2 1 0	The token title	Reference
				0 0 0 1 1 0 0 1	MAX_COMP_ID
0 0 0 1 1 0 1 0	EXTENSION_DATA
			0 0 0 1 1 0 1 1	USER_DATA
0 0 0 1 1 1 0 0	DHT_MARKER
			0 0 0 1 1 1 0 1	DQT_MARKER
0 0 0 1 1 1 1 0	(reservation) DNL_MARKER
			0 0 0 1 1 1 1 1	(reservation) DRI_MARKER
1 1 1 0 1 0 0 0	(reservation)
			1 1 1 0 1 0 0 1	(reservation)
1 1 1 0 1 0 1 0	(reservation)
			1 1 1 0 1 0 1 1	(reservation)
1 1 1 0 1 1 0 0	BIT_RATE
			1 1 1 0 1 1 0 1	VBV_BUFFER_SIZE
1 1 1 0 1 1 1 0	VBV_DELAY
			1 1 1 0 1 1 1 1	PICTURE_TYPE
1 1 1 1 0 0 0 0	PICTURE_RATE
			1 1 1 1 0 0 0 1	PEL_ASPECT

Table A .3.1 token list (continuing)

7 6 5 4 3 2 1 0	The token title	Reference
				1 1 1 1 0 0 1 0	HORIZONTAL_SIZE
1 1 1 1 0 0 1 1	VERTICAL_SIZE
			1 1 1 1 0 1 0 0	BROKEN_CLOSED
1 1 1 1 0 1 0 1	CONSTRAINED
			1 1 1 1 0 1 1 0	(reservation) SPECTRAL_LIMIT
1 1 1 1 0 1 1 1	DEFINE_MAX_SAMPLING
			1 1 1 1 1 0 0 0	(reservation)
1 1 1 1 1 0 0 1	(reservation)
			1 1 1 1 1 0 1 0	(reservation)
1 1 1 1 1 0 1 1	(reservation)
			1 1 1 1 1 1 0 0	HORIZONTAL_MBS
1 1 1 1 1 1 0 1	VERTICAL_MBS
			1 1 1 1 1 1 1 0	(reservation)
1 1 1 1 1 1 1 1	(reservation)

A.3.4 token explanation

This part has provided the token that is provided according to the present invention as data in spatial decoder and temporal decoder. See Table A.3.2 and to note: " r " represents those current are retained and value is 0 bit. All integers all are unsigned numbers, unless specialize.

The token that Table A .3.2 provides in spatial decoder and temporal decoder

E

7 6 5 4 3 2 1 0	Explanation
		1 1 1 1 0 1 1 0 0	BIT_RATE test into only
1 r r r r r r b b	Carry MPEG bit-rate parameters R. Produce 18 bit integer by the MPEG definition of b-when the decoding-MPEG Bit String by Huffman (Huffman) decoder
		1 b b b b b b b b
0 b b b b b b b b
		1 1 1 1 1 0 1 0 0	BROKEN_CLOSED carries two MPEG flag bit C-closed_gap b-broken_link
0 r r r r r r c b
	1 0 0 0 1 0 1 0 1	8 bit integer of an indication of CODING_STANDARD S-present encoding standard. It is worthwhile frontly by tax to be: 0-H.261 1-JPEG 2-MPEG
0 s s s s s s s s
	1 1 1 0 0 0 0 c c		COMPONENT_NAME contacts the relation between a component ID and the component name. Referring to ... C-2 bit component ID n-8 bit component " title "
0 n n n n n n n n

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		1 1 1 1 1 0 1 0 1	CONSTRAINED C-carries by the next constraint parameter sign of MPEG Bit String decoding
0 r r r r r r r c
	1 0 0 0 0 0 1 c c	Data are carried data communication device and are crossed 2 bit integer component ID (seeing A.3.5.1) of decoder chip collection C-. This field is not (not being picture dot information) that defines for the token that carries coding
1 d d d d d d d d
	0 d d d d d d d d
1 1 1 1 1 0 1 1 1			DEFINE_MAX_SAMPLING maximum horizontal and vertical sampling number. They have illustrated the largest block number of horizontal/vertical in any macro block component. See A.3.5.2 h-2 bit level number of samples v-2 bit vertical sampling number
	1 r r r r r r h h
0 r r r r r r v v
	1 1 1 0 0 0 1 c c	The horizontal and vertical sampling of a certain particular color component of DEFINE_SAMPLING. See A.3.5.2 C-2 bit component ID h-2 bit level hits v-2 bit Vertical Sampling number
1 r r r r r r h h
	0 r r r r r r v v

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		0 0 0 0 1 1 1 0 0	This token notice video distributor of DHT_MARKER, the data token of its back includes the explanation of Huffman table, provides the syntax of using JPEG " definition Huffman table section ". This token only is that this legal token is produced in the JPEG decode procedure by detector for initial code when a DHT mark occurring in the serial data when coding standard is JPEG
0 0 0 0 1 1 1 1 0	This token notice video distributor of DNL_MARKER data token thereafter includes JPEG Parameter N L, and this parameter has been specified the line number in the frame. This token is produced in the JPEG decode procedure by detector for initial code when a DNL mark occurring in the serial data.
		0 0 0 0 1 1 1 0 1	The data token of this its back of token notice video distributor of DQT_MARKER includes the quantization table explanation, provides the syntax of using JPEG " definition quantization table section ". It is legal that this token only is only when coding standard is JPEG. Video distributor produces an OUANT_TABLE token, and it comprises new quantization table information. This token is produced in the JPEG decode procedure by detector for initial code when a DQT mark occurring in the serial data.
0 0 0 0 1 1 1 1 1	The data token of this its back of token notice video distributor of DRI_MARKER includes the JPEG parameters R; This parameter indicates the number of the minimum code unit that restarts between the mark. This token is when a DRI mark occurring in the serial data, is produced in the JPEG decode procedure by detector for initial code.

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		1 0 0 0 1 1 0 1 0	The data token of this its back of token notice video distributor of EXTENSION_DATA JPEG includes growth data. Referring to A.11.3 " initial code is to the conversion of token ", and A.14.6 " reception of user and growth data ". Eight bit fields in jpeg operation carry JPEG mark value. This so that the classification of growth data can be identified.
0 v v v v v v v v
	0 0 0 0 1 1 0 1 0	The data token of this its back of token notice video distributor of EXTENSION_DATA MPEG includes growth data. Referring to A.11.3 " initial code is to the conversion of token ", and A.14.6, " reception of user and growth data ".
1 0 0 0 1 1 0 0 0			FIELD_INFO
	0 r r r t p f f f	Carry about the demonstration of visual thereafter information with auxiliary this image. This function be can't help any existing coding standard and is sent. If the t-image is an interlaced frame, the field above the indication of this bit is first (t=0) or second whether. If the p-image is field, it indicates next image is upper field (p=0) or lower field in the frame. 3 bit numbers of f-indicate the position of field in 8 field PAL sequences.
0 0 0 0 1 0 1 1 1			FLUSH is used to indicate the ending of present encoding data and decoder is passed through in the ending of promotion serial data.
	0 0 0 0 1 0 0 0 1	When GROUP_START finds visual initial code group in decoding MPEG process, or be produced when finding the frame mark in the decoding JPEG process.

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		1 1 1 1 1 1 1 0 0	13 bit integer of HORIZONTAL_MBS h-, the horizontal width of the image that indication represents with macro block.
1 r r r h h h h h
	0 h h h h h h h h
1 1 1 1 1 0 0 1 0		HORIZONTAL_SIZE h-16 bit integer is indicated the horizontal width with the image of pixel expression. It can get any integer value.
	1 h h h h h h h h
0 h h h h h h h h
	1 1 1 0 0 1 0 c c		Which quantization table JPEG_TABLE_SELECT notice inverse quantizer selects in particular color component. C-2 bit component ID (seeing 1.3.5.1) t-2 bit integer table.
0 r r r r r r t t
	1 0 0 0 1 1 0 0 1	MAX_COMP_ID m-2 bit integer, the maximum (seeing A.3.5.1) of the component ID that indication will be used in next image.
0 r r r r r r m m
	0 1 1 0 1 0 1 c c		Which DC coefficient Huffman table the MPEG_DCH_TABLE configuration should use for color component CC. C-2 bit component ID (seeing A.3.5.1) t-2 bit integer table number code.
0 r r r r r r t t

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		0 1 1 0 0 1 1 d n	Whether MPEG_TABLE_SELECT notice inverse quantizer uses default for inner or non-internal information or the user defines quantization table. N-0 indicates internal information, and the non-inner d-0 of 1 indication indicates default table, 1 user definition
1 1 0 1 d v v v v	MVD_BACKWARDS carries backward that the one-component of motion vector (horizontal or vertical) d-0 refers to the x component, and the complement code number of 1 finger y component v-12 bit 2, least significant bit provide the resolution ratio of 1/2 pixel
		0 v v v v v v v v
1 1 0 0 d v v v v			MVD_FORWARDS carries the one-component (horizontal or vertical) of the vector that travels forward. D-0 refers to the X component, 1 finger Y component. The complement code number of v-12 bit 2, least significant bit provides the resolution ratio of 1/2 pixel
	0 v v v v v v v v
0 0 0 0 0 0 0 0 0		NULL does not do anything.
	1 1 1 1 1 0 0 0 1		4 bit integer by the MPEG definition of PEL_ASPECT p-.
0 r r r r p p p p
	0 0 0 0 1 0 1 1 0	PICTURE_END is added by detector for initial code, indicates the end of current image.

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		1 1 1 1 1 0 0 0 0	4 bit integer of PICTURE_RATE p-are defined by MPEG.
0 r r r r p p p p
	1 0 0 0 1 0 0 1 0	PICTURE_START indicates the beginning of the new image of a width of cloth. 4 binary image index of being distributed to image by detector for initial code of n-
0 r r r r n n n n
	1 1 1 1 0 1 1 1 1		The bi-directional predicted 3-DC of 2 bit integer 0-inner 1-prediction 2-of the picture coding type of an indication of PICTURE_TYPE MPEG p-back image is inner
0 r r r r r r p p
	1 1 1 1 0 1 1 1 1	H.261, PICTURE_TYPE indicates different H.261 options to be out (1) or closes (0), and these options always close for MPEG and JPEG. S-division screen indicator. D-data video camera f-removes image and freezes the source image form: q=0QCIF q=1CIF
1 r r r r r r 0 1
	0 r r s d f q 1 1

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		0 0 1 0 h y x b f	Flag bit collection of PREDICTION_MODE, the prediction mode of indication back macro block. F-predicts that forward b-predicts that backward the x-vector forecasting y-posteriorly directed force prediction h-that resets that resets forward enables H.261 ring wave filter
0 0 0 1 s s s s	5 bit integer of QUANT_SCALE notice inverse quantizer one new scalar factor s-from 1 to 31 scope. The 0th, retention.
		1 0 0 0 0 1 r t t	QUANT_TABLE loads the inverse quantizer table of appointment with 64 8 bit unsigned integer. Value is arranged 2 bit integer that t-indicates the inverse quantizer table of intending loading by the z font.
1 q q q q q q q q
	0 q q q q q q q q
0 0 0 0 1 0 1 0 0		SEQUENCE_END MPEG seguence_end_code and JPEG EOI mark are produced this token.
0 0 0 0 1 0 0 0 0			SEQUENCE_START is produced by MPEG sequence initial code.

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		1 0 0 0 1 0 0 1 1	SLICE_START is corresponding to MPEG slice_start, H.261 GOB and JPEG sync interval again. The meaning of 8 bit integer " S " is different with the different coding standard. MPEG sheet upright position-1 is piece group number-1 JPEG sync interval sign (only 4 lowest orders) more H.261
0 s s s s s s s s
	1 1 1 0 1 0 0 t t	TEMPORAL_REFERENCE t-carries the time reference. For MPEG, this is 10 bit integer. To H.261, only have 5 lowest orders to be used, a high position will always be 0.
0 t t t t t t t t
	1 1 1 1 0 0 1 0 d		The freeze frame 6 visual bit integer of 6 bit integer p-indication of 6 bit integer-indication second of 5 bit integer m-indication minute of sign-indication hour of TIME_CODE MPEG time_code:-
1 r r r h h h h h
	1 r r m m m m m m
1 r r s s s s s s
	0 r r p p p p p p
1 0 0 0 1 1 0 1 1		The data token of USER_DATA JPEG token notice video distributor back includes user data. See A.11.3,, " initial code is to the conversion of token " and A.14.6, " reception of user and growth data ". In jpeg operation, 8 bit fields " V " carry JPEG mark value. This so that the classification of user data can be identified.
	0 v v v v v v v v

The token that Table A .3.2 provides in spatial decoder and temporal decoder (continuing)

E 7 6 5 4 3 2 1 0	Explanation
		0 0 0 0 1 1 0 1 1	The data token of this token notice video distributor back of USER_DATA MPEG includes user data. See A.11.3 " initial code is to the conversion of token " and A.14.6 " reception of user and growth data ".
1 1 1 1 0 1 1 0 1	10 bit integer such as the MPEG definition of VBV_BUFFER_SIZE s-.
		1 r r r r r r s s
0 s s s s s s s s
		1 1 1 1 0 1 1 1 0	16 bit integer such as the MPEG definition of VBV_DELAY b-.
1 b b b b b b b b
	0 b b b b b b b b
1 1 1 1 1 1 1 0 1		One of VERTICAL_MBS v-shows 13 bit integer of the vertical size of the image take macro block as unit.
	1 r r r v v v v v
0 v v v v v v v v
	1 1 1 1 1 0 0 1 1		One of VERTICAL_SIZE v-shows 16 bit integer of the visual vertical size take pixel as unit, and it can be any integer value.
1 v v v v v v v v
	0 v v v v v v v v

A.3.5 the component identification number A.3.5.1 of the figure denote in the token

Corresponding to the present invention, the component id number is that 2 bit integer that indicate a color component say that typically the part that this 2 bit field is used as leader places data token. For MPMG and H.261, its relation is very simple: see Table A.3.3

Table A .3.3 is to MPEG and component ID H.261

Component ID	MPEG or color component H.261
		0	Brightness (Y)
1	Blue difference signal (Cb/u)
		2	Red color difference signal (Cr/v)
3	Do not use

For JPEG, situation is more complicated, because JPEG does not limit operable color component. Decoder chip allows up to four kinds of different colours in every one scan. ID when the explanation of color component arrives decoder by continuous dispensing. A.3.5.2 horizontal and vertical hits

For in four color components each, level or the piece number that is vertically arranged in the macro block there are a detailed description, this explanation comprises one than the dibit integer of piece number little 1.

For example, in MPEG (or H.261), be assigned with at tool 4:2:0 chroma samples (figure A.15.4) and component ID such as Table A .3.3.

Table A .3.4 was to 4: 2: the hits of 0/MPEG

Component ID	Horizontal hits	Width take piece as unit	The Vertical Sampling number	Height take piece as unit
					0	1	2	1	2
1	0	1	0	1
					2	0	1	0	1
3	Need not	Need not	Need not	Need not

See A.3.5.1 and note: JPEG requires 1 to its macro block when processing 4: 2: 2 data: 1: 1 structure.

Table A .3.5 is for the hits of 4: 2: 2 JPEG

Component ID	Horizontal hits	Width with the metering of piece number	The Vertical Sampling number	Height with the piece metering
					Y
	1	2	0	1
					U	0	1	0	1
V	0	1	0	1

A.3.6. special token form

Corresponding to the present invention, concentrate at decoder chip such as the token of data token and quantization table token to be used with its " extend type ". In extend type, token comprises some data. In the situation of data token, they can comprise coded data or pixel data. In the situation of quantization table token, they comprise quantization table information.

In addition, " the non-extend type " of these tokens is defined as " sky " in the present invention. This token form provides the place that can be filled subsequently by the extended version of same token in the token string. This form is mainly used in encoder, thereby no longer is further used as data at this and provides.

Table A .3.6 is to the token of various criterion

The token title	MPEG	JPEG	H261
				BIT_RATE	/
BROKEN_CLOSED	/
				CODING_STANDARD	/	/	/
COMPONENT_NAME		/
				CONSTRAINED	/
DATA	/	/	/
				DEFINE_MAX_SAMPLING	/	/	/
DEFINE_SAMPLING	/	/	/
				DHT MARKER		/
DNL_MARKER		/
				DQT_MARKER		/
DRI_MARKER		/

Table A .3.6 is to the token (continuing) of various criterion

The token title	MPEG	JPEG	H261
				EXTENSION_DATA	/	/
FIELD_INFO
				FLUSH	/	/	/
GROUP_START	/	/
				HORIZONTAL_MBS	/	/	/
HORIZONTAL_SIZE	/	/	/
				JPEG_TABLE_SELECT		/
MAX_COMP_ID	/	/	/
				MPEG_DCH_TA8LE	/
MPEG_TABLE_SELECT	/
				MVD_BACKWARDS	/
MVD_FORWARDS	/		/
				NULL	/	/	/
PEL_ASPECT	/
				PICTURE_END	/	/	/
PICTURE_RATE	/
				PICTURE_START	/	/	/
PICTURE_TYPE	/	/	/
				PREDICTION_MODE	/	/	/
QUANT_SCALE	/		/
				QUANT_TABLE	/	/
SEQUENCE_END	/	/
				SEQUENCE_START	/	/	/
SLICE_START	/	/	/
				TEMPORAL_REFERENCE	/		/
TIME_CODE	/
				USER_DATA	/	/
VBV_BUFFER_SIZE	/
				VBV_DELAY	/
VERTICAL_M8S	/	/	/
				VERTICAL_SIZE	/	/	/

A.3.7 the token of various criterion uses

Corresponding to the present invention, every kind of standard is used a different subset that is defined token. See Table A.3.6. A.4 A.4.1 two-wire interface and token port of two-wire interface

Simple two-wire effectively/accept all rank of agreement in chipset to be used flowing with control information. Data just are sent out between piece when only observing transmit leg and recipient all being ready to when the clock rising edge time.

1) data transmit

2) recipient is unripe

3) transmit leg is unripe

If transmit leg unripe (transmit leg such as top 3 is unripe), recipient's input must be waited for. If recipient's unripe (unripe such as the recipient in top 2), transmit leg will continue same data are placed on its output, until its received side reception.

When token information was transmitted between device, the two-wire interface between the device was referred to as a token port. A.4.2 use field institute

Corresponding to the present invention, the decoder chip collection connects three chips with two-wire interface. In addition, the coded data that is input to spatial decoder also is a two-wire interface. A.4.3 bus signals

The data word width that is transmitted by two-wire interface changes (seeing Figure 35, " being wider than the token on the interface of 8 bits ") according to the needs of relevant interface. For example, 12 bit coefficients are input to inverse discrete cosine transform (IDCT), but only have 9 bits to be output.

Table A .4.1 two-wire interface data width

Interface	Data width (bit)
		Input to the coded data of spatial decoder	8
The output port of spatial decoder	9
		The input port of temporal decoder	9
The output port of temporal decoder	8
		The input port of pixel format device	8

Except data-signal also has other three signals that transmit by two-wire interface:

Effectively

Receive

Expand A.4.3.1 spread signal

Spread signal is corresponding with the token extended bit that illustrates previously. A.4.4 design is considered

The purpose of two-wire interface is the short distance point to point link between the chip.

Decoder chip should adjacently be placed, so that the PCB wire length between the chip is the shortest. In possible place, wire length should keep less than 25mm. The PCB wire capacitances should remain on minimum of a value.

The distribution of clock should be designed to make that not occur clock between the chip uneven. If there is any clock uneven, should arrange to make " receiving chip " to see before clock at " transmission chip ".

All should be by same digital power operation by the chip communication of two-wire interface. A.4.5 interface regularly

Table A .4.2 two-wire interface regularly

Number	Characteristic	The 30NHz minimax	Unit	Annotate a b
						1	Input signal setting time	5	ns
2	The input signal retention time	0	ns
					3	The output signal driving time	23	ns
4	The output signal retention time	2	ns

A, figure can be different and different with design in Table A .4.2

It is 2095 (20 picofarad) note 1 that b, peak signal load, and A.16.3: figure has shown system assignment device chip and from the two-wire interface between the spatial decoder coded data passage of main decoder clock operation. This is optional, because this two-wire interface can be from coded data clock work that can be synchronous with decoder clocks. Referring to part A.10.5, " coded data clock ". Similarly, the display interface of pixel format device can be operated from a clock with the main decoder clock synchronous. A.4.6 signal level

Two-wire interface is used the CMOS input and output. V_1HminApproximately be V _DD70% and V_1LMaxApproximately be V _DD30%. Numerical value shown in the Table A .4.3 is V_1HAnd V_1LAt its poorest V separately_DDIn the situation. V_DD＝5.0±0.25V。

Table A .4.3 direct current characteristic

Symbol	Parameter	Minimum	Maximum	Unit
					V 1H	Input logic " 1 " volt	3.68	V DD＋0.5	V
V IL	Input logic " 0 " volt	GND-0.5	1.43	V
					V OH	Output logic " 1 " volt	VDD-0.1		V a
V DD-0.4		V b
			V OL	Output logic " 0 " volt				0.1	V c
					0.4	V d
			l IN	The input leakage current				±10	μA

a.I _OH≤ 1 milliampere of b.I_OH≤ 4 milliamperes of c.I_OL≤ 1 milliampere of d.I_OLA.4.7 control clock for≤4 milliamperes

Usually in fact, control is the decoder clocks (decoder_clock) of chip by the clock that two-wire interface transmits. Coded data port input to spatial decoder is an exception. It is controlled by encoded clock (coded_clock). Will be further described below clock signal. A.5 DRAM interface DRAM interface A.5.1

The configurable DRAM interface of one single high-performance is used in each video decoder chip. Usually, the DRAM interface on each chip is in fact identical; Yet, be different between the interface how on the treatment channel priority. Interface is designed to directly drive the used DRAM of each decoder chip. In typical case, in most systems, do not need external logic, buffer or element to connect the DRAM interface in DRAM. A.5.2 interface signal

Table A .5.1 DRAM interface signal

Signal name	I/O	Explanation
			DRAM_data(31：0)	I/O	The DRAM data/address bus of 32 bit widths. This bus selectively is configured to 16 or 8 bit widths, sees A.5.8 part
DRAM_addr(10：0)	O	The DRAM interface IP address of 22 bit widths is to make the timesharing multichannel in the bus of 11 bit widths
			RAS	O	The DRAM row address messenger that changes
CAS(3：0)	O	The DRAM column address messenger that changes. Each byte of the data/address bus of interface is provided a signal. All CAS signals are driven simultaneously.
			WE	O	DRAM allows write signal
OE	O	DRAM allows output signal
			DRAM_enable	I	When this input signal makes all output signals on the interface become high-impedance state when low. Annotate: the data processing is non-stop on the high-impedance state sheet when the DRAM interface is in, thereby when the DRAM_enable enable signal was low level, mistake will produce when planning access DRAM such as slice, thin piece.

Corresponding to the present invention, interface can dispose in two ways:

" width " that the details sequential of interface can be configured to adapt to multiple different DRAM type DRAM interface can be configured to provide the compromise of price/performance in different application.

A.5.3 the configuration of DRAM interface

Usually, there are three groups of registers and DRAM interface to interrelate: interface timing configured register, interface bus configuration register and refresh configuration register. Refresh configuration register (register among the Table A .5.4) should be disposed at last. A.5.3.1 the situation after resetting

After resetting, according to the present invention, DRAM interface start-up operation is with a series of default timing parameters (corresponding with the slowest mode of operation). Beginning, the DRAM interface will be carried out the refresh cycle (comprising other all transmission) continuously. This will proceed to a value and be written into the refresh interval register. Then the DRAM interface can be carried out the transmission of other type between the refresh cycle. A.5.3.2 bus configuration

Bus configuration (register among the Table A .5.3) should only not carry out finishing when data transmit at interface. Be right after after resetting and before a value was written into the refresh interval register, interface was placed in this state. If necessary, only in that interface can reconfigure afterwards when being attempted without transmitting. See temporal decoder chip access function resister (A.18.3.1) and spatial decoder buffer management access function resister (A.13.1.1). A.5.3.3 interface timing configured

According to the present invention, interface timing configured information is by regularly access (interface_ timing_access) register control of interface. For this reason register write 1 so that interface timing register (among the Table A .5.2) can be modified. Work as interface_timing_access=1, the DRAM interface continues the configuration operation with its front. After writing 1, the user should wait for before writing any interface timing register until 1 can be read back from interface_timing_access. After configuration finished, 0 should be written into interface_timing_access. Then new configuration will be transmitted to the DRAM interface. A.5.3.4 refresh configuration

The refresh interval of DRAM interface of the present invention can only dispose once after resetting. Interface continues to carry out refresh cycle, until refresh_interval is configured. This has prevented that any other data from transmitting. Data transmit and can begin after a value is written into refresh_interval.

So be known in the field, the DRAM typical case needs 100 μ s to " time-out " between the 500 μ s after powering up first, then is possible a large amount of refresh cycles before the normal operation. Correspondingly, these DRAM start requests should be satisfied before giving value of refresh_interval. A.5.3.5 to the read operation of configuration register

All DRAM interface registers of the present invention all can be read at any time. A.5.4 interface timing (ticks pulse)

The DRAM interface is regularly obtained by a clock, and this clock is with the speed running (decoder clocks) of the input clock that is four times in equipment. This clock is produced by phaselocked loop in the chip.

For easy, the cycle of this high-frequency clock is represented as " ticks pulse ". A.5.5 interface register

Table A .5.2 interface timing configured register

The register title	Size/direction	Reset mode	Explanation
				intertace_ timing_ access	1    bit    rw	0	This function makes the register can access DRAM interface sequence configuration register. When this register kept 0 value, configuration register should not be modified. Be written into after this register the DRAM interface 0 and will begin in the sequential configuration register, to use new value.
page_start- length	5    bit     rw	0	Indicate the initial length of access with ticks. Spendable minimum of a value was 4 (referring to 4 tick). 0 selects the maximum length of 32ticks.
				transfer_ cycle_ length	4    bit     rw	0	Indicate the fastest page or leaf read or write cycle of expressing with ticks. Spendable minimum of a value was 4 (referring to 4 tick). 0 selects the maximum length of 16ticks.
refresh_ cycle- length	4    bit     rw	0	Indicate the length of refresh cycle with ticks. Spendable minimum of a value was 4 (referring to 4 tick). 0 selects the maximum length of 16ticks.
				RAS_falling	4    bit     rw	0	Startup RAS transfers low level tick number to after specifying in the startup access. Spendable minimum of a value was 4 (referring to 4 tick). 0 selects the maximum length of 16ticks.
CAS_falling	4    bit     rw	8	After specifying in startup read cycle, write cycle time or access, start CAS and transfer low level tick number to. Spendable minimum of a value was 1 (referring to 1tick). 0 selects the maximum length of 16ticks.

Table A .5.3 interface bus configuration register

The register title	Size/direction	Reset mode	Explanation
				DRAM_data -width	2    bit     rw	0	Indicate and be used in DRAM interface data bus DRAM_data[31:0] on bit number. See A.5.8
row_ address -bits	2    bit     rw	0	Be indicated as being the bit number that the row address of DRAM interface IP address bus partly uses. See A.5.10
				DRAM_ enable	1    bit     rw	1	For writing 0 value, register force the DRAM interface to enter a high impedance status. Be written into register if DRAM_ enable signal is in low level or 0, from then on 0 incite somebody to action, and register is read out.
CAS_strength	3    bit     rw	6	The output of these three bit register configurations DRAM interface signal drives intensity. This so that interface can be multiple different loads and be configured. See A.5.13
				RAS_strength
addr_strength
				DRAM data- strength
OEWE_strength

A.5.6 interface operation

The DRAM interface uses fast page mode. Have three kinds of dissimilar accesses to be supported:

Read

Write

Refresh

Each reads or writes access transmits train of pulse from 1 to 64 byte to a single DRAM page address. Read and write transmits and does not mix mutually in a single access, and each continuous access is all processed as the arbitrary access to a new DRAM page.

Table A .5.4 refresh configuration register

The register title	Size/direction	Reset mode	Explanation
				refresh_ interval
	8    bit     rw	0	This value indicated take 16 decoder_ clock cycles as the interval between the refresh cycle of unit. Value in from 1 to 255 scope can be configured. 0 value is by automatic loading and force the DRAM interface continue to carry out the refresh cycle, until an effective refresh interval is configured after resetting. Refresh_interval preferably only is configured once at every turn after resetting.
				no_refresh	1    bit     rw	0	Prevented the execution of any refresh cycle for this register value of writing 1.

A.5.7 access structure

Each access comprises two parts

Access is initial

Data transmit

Among the present invention, each access is followed thereafter one or more data transfer cycles by an initial beginning of access. In addition, access initial sum data transfer cycles there are reading and writing and refresh variant.

When a particular access having been finished final data and transmit, interface enters its default setting (seeing A.5.7.3) and keeps this state, until the preparation of beginning is carried out in new access. Prepare beginning if one new when being accessed in an access and having finished, this new access will begin immediately so. A.5.7.1 access is initial

Access is initiated with to read or write to transmit and the page address is provided and sets up some initialize signal condition. Corresponding to the present invention, have three kinds of different accesses initial:

Read initial

Write initial

Refresh initial

Table A .5.5 DRAM interface timing parameters

Number	Characteristic	Minimum	Maximum	Unit	Note
							5	By the RAS prestrain cycle of register RA S_falling setting	4	16	tick
6	Initial lasting by the access that register page_start_length arranges	4	32
						7	CAS prestrain length by register CAS_falling setting	1	16		a
8	Quick page read or write cycle length by register transfer_cycle_ length setting	4	16
						9	By the refresh cycle length of depositing the refresh_cycle setting	4	16

A. this value can be less than RAS_falling, to guarantee that CAS occurred before RAS refreshes.

In each case, the sequential of RAS and row address are all by register RA S_falling and Page_start_length control. OE and DRAM_data[31:0] state is held from the end that last data transmits, to becoming low level to RAS. When RAS became low level, how three kinds of initial types of different accesses only drove OE and DRAM_data[31:0 at them] on difference to some extent. See Figure 43. A.5.7.2 data transmit

In the present invention, data transfer cycles has dissimilar:

The quick page read cycle

Write cycle time behind the quick page

Refresh cycle

One is refreshed and initially can only follow a single refresh cycle. Read that (or writing) is initial can follow one or more quick pages and read (or writing) cycle for one. The initial CAS of read cycle be driven to high level and new column address driven.

Further, one early write cycle time be used. Be driven to low level and keep to the last end of writing transmission of low level at the initial WE that writes for the first time transmission. The output data are driven according to the address.

Owing to be by the initial initiation of refresh cycle at the CAS of RAS before the refresh cycle, within the refresh cycle, there is not interface signal movable. The purpose of refresh cycle is to satisfy the required minimum RAS low period of DRAM. A.5.7.3 interface default setting

Interface signal enters a default setting in the ending of primary access among the present invention:

RAS, CAS and WE high level

* data and OE remain on their former state

The address keeps stable A.5.8 data-bus width

Two bit register DRAM_data_width allow the wide data path of DRAM interface to be configured. This so that when the work of little pixel format the DRAM cost can be down to minimum.

Table A .5.6 disposes DRAM_data_width (DRAM data width register)

DRAM_data_with
		0 a	DRAM_data[31：24] bOn 8 bit width data/address bus
1	DRAM_data[31：16] [b]On 16 bit width data/address bus
		2	DRAM_data[31:0] on 32 bit width data/address bus

A, default after resetting

B, untapped signal are maintained at A.5.9 row address width of high impedance

For providing row address to be disposed by register row_address_bits from the bit number of the mid portion taking-up of 24 bit internal addresses.

Table A .5.7 disposes row_address_bits (row address bits)

row_address_bits	The row address width
		1	DRAM_addr[9:0] upper 10 bits
2	DRAM addr[10:0] upper 11 bits

A.5.10 address bit

24 bit address are produced at chip. How this address is used for producing the figure place that will select according to the width of data/address bus with for row address the row and column address is decided. Some configuration does not allow all internal address bit all to be used, and therefore produces " hidden bit ".

Similarly, row address is extracted by the mid portion from the address. Correspondingly, this makes DRAM naturally be refreshed with maximum rate.

Mapping between the inside and outside address of Table A .5.8

The row address width	Inside → outer row address transition	Data-bus width	Column address conversion inside → outside
				9	[14：6]→[8：0]	8	[19：15]→[10：6][5：0]→[5：0]
16	[20：15]→[10：5][5：1]→[4：0]
		32	[21：15]→[10：4][5：2]→[3：0]
10	[15：6]→[9：0]					8	[19：16]→[10：6][5：0]→[5：0]
		16	[20：16]→[10：5][5：1]→[4：0]
				32	[21：16]→[10：4][5：2]→[3：0]
		11	[16：6]→[10：0]			8	[19：17]→[10：6][5：0]→[5：0]
16	[20：17]→[10：5][5：1]→[4：0]
				32	[21：17]→[10：4][5：2]→[3：0]

A.5.10.1 low level column address bit

4 of least significant bit to 6 are used to provide the address for the fast page-mode that reaches 64 bytes transmits in the column address. Control the required address size of these transmission and will decide according to the width of data/address bus (seeing A.5.8). A.5.10.2 the decoded row address is with the more DRAM body of access

In the place of a monolithic entity that only uses DRAM, employed row address will depend on the DRAM type of use. For those need to more than a single DRAM body can typical case's storage capability that provide application, can dispose a wider row address, and some row address bit of then decoding is to select a single DRAM body.

Attention: row address is that the centre of internally address extracts. If some of row address decoded bodies with selection DRAM, all probable values of these " body is selected the position " must be selected a DRAM body so. Otherwise address space just may stay the cavity. A.5.11 DRAM interface enable

In the present invention, there are two methods can make all output signals on the DRAM interface become high impedance, namely, by DRAM_enable register and DRAM_enable signal are set. For making the driver operation on the DRAM interface, register and signal all must be in logical one. If any one is low, interface is set to high impedance so.

Attention: when the DRAM interface during at high impedance on the chip data process and finish. Thereby, attempt such as fruit chip that access DRAM just may make a mistake when interface is in high impedance.

Corresponding to the present invention, the ability that the DRAM interface is set to high impedance is provided so that spatial decoder (or temporal decoder) when not being used miscellaneous equipment can test or use DRAM by spatial decoder (or temporal decoder) control. This is not in order to share memory at the normal miscellaneous equipment that allows in service. A.5.12 refresh

Unless register no_refresh is write to forbid refreshing, the DRAM interface will use a CAS automatically DRAM to be refreshed at RAS in an interval that is determined by register refresh_interval before the refresh cycle.

Value among the refresh_interval indicates interval between the refresh cycle with 16 decoder_clock cycles. Value in 1 to 255 scope can be configured. 0 value is by automatic loading and force the DRAM interface continue to carry out the refresh cycle (in case permission), until an effective refresh interval is configured after resetting. We advise that refresh_interval should only be configured once at every turn after resetting.

When the reset signal occurred, the DRAM interface can not refresh DRAM. Yet decoder chip is enough lacked required resetting time, thereby should reset them, and reconfigures the DRAM interface before the content consumption of DRAM is lost. A.5.13 signal strength signal intensity

The driving intensity of the output of DRAM interface can be used by the user 3 register CAS_ strength, RAS_strength, and addr_strength, DRAM_data_strength and OEWE_strength dispose. The highest order of this 3 bit value is selected the fast or slow of edge rate. Two low orders are different load capacity configuration output.

Default intensity after resetting is 6, if its configuration output load capacitance is 24 pf, approximately drives one between GND and V with 10 ns_DDBetween signal.

The configuration of Table A .5.9 output intensity

Intensity level	Drive characteristic
		0	About 4 nanoseconds/volt on the capacitive load of 6pf
1	About 4 nanoseconds/volt on the capacitive load of 12pf
		2	About 4 nanoseconds/volt on the capacitive load of 24pf
3	About 4 nanoseconds/volt on the capacitive load of 48pf
		4	About 2 nanoseconds/volt on the capacitive load of 6pf
5	About 2 nanoseconds/volt on the capacitive load of 12pf
		6a	About 2 nanoseconds/volt on the capacitive load of 24pf
7	About 2 nanoseconds/volt on the capacitive load of 48pf

A, reset rear default

The load that drives for it when an output and suitably being disposed, it will meet Table A .5.13 to the alternating current characteristics of indicating A.5.16. When configuration is suitable, therefore the overshoot of minimum degree will appear in each output and its load approximate match after a signal saltus step. A.5.14 electrical characteristics

All information that this part provides only are the explanations of one embodiment of the present invention, are to be included within the example and needn't be as restriction.

Table A .5.10 maximum rating

Symbol	Parameter	Minimum	Maximum	Unit
					V DD	Supply voltage with the GND reference	-0.5	6.5	V
V IN	Input voltage on any pin	GND-0.5	V DD＋0.5	V
					T A	Running temperature	-40	+85	℃
T S	Storage temperature	-55	+150	℃

Table A .5.10 only is provided with maximum rating for the explanation embodiment. To this particular implementation of emphasizing below, that lists in the table should be used, to guarantee reliability of operation.

Table A .5.11 dc operation condition

Symbol	Parameter	Minimum	Maximum	Unit
					V DD	Supply voltage with the GND reference	4.75	5.25	V
GND	Ground
			0	0	V
V IH	Input logic " 1 " voltage					2.0	V DD＋0.5	V
		V IL	Input logic " 0 " voltage	GND-0.5	0.8				V
T A	Running temperature					0	70	℃ a

A, with TBA wire feet per minute clock crossflow

Table A .5.12 direct current characteristic

Symbol	Parameter	Minimum	Maximum	Unit
					V OL	Output logic " 0 " voltage		0.4	V a
V OH	Output logic " 1 " voltage	2.8		V
					I O	Output current	±100		μA b
I OZ	Output off-state leakage current	±20		μA
					IIZ	The input leakage current	±10		μA
I DD	The RMS source current		500	mA
					C IN	Input capacitance		5	pF
C OUT	Output I/O electric capacity		5	pF

A, AC parameter are by with V_OLmaxRank is pointed out b to=0.8V, this is the stable state driving force of interface in order to measure. Immediate current may be much bigger. A.5.14.1 AC characteristic

The deviation of the relative nominal value of Table A .5.13 gate pulse

Number	Parameter	Minimum	Maximum	Unit	Note	a
							10	Cycle time	-2	+2	ns
11	Cycle time	-2	+2	ns
						12	High level pulse	-5	+2	ns
13	Low level pulse	-11	+2	ns
						14	Cycle time	-8	+2	ns

The driving intensity of a, signal must corresponding its load and is configured, as the people of technical ability can recognize having in this area.

Between twice gating of Table A .5.14 to the deviation of nominal value

Number	Parameter	Minimum	Maximum	Unit	Note	a
							15	Be strobed into the time-delay of gating	-3	+3	ns
16	The low level retention time	-13	+3	ns
						17	Be strobed into giving the load time of gating, such as tCRP, tRCS, tRCH, tRRH, tRPC	-9	+3	ns
Give the CAS signal of load pulses on wide a plurality of DRAM between any two CAS, as tCP or RAS rise with CAS decline between CAS signal such as tRPC	-5	+2	ns

Between twice gating of Table A .5.14 to the deviation (continuing) of nominal value

Number	Parameter	Minimum	Maximum	Unit	Note	a
							18	Giving before forbidding filled	-12	+3	ns

The driver intensity of a, two signals must adapt to their load and be configured

Between Table A .5.15 bus and the gating with respect to the deviation of nominal value

Number	Parameter	Minimum	Maximum	Unit	Note	a
							19	Setup times	-12	+3	ns
20	Retention time	-12	+3	ns
						21	Address access time	-12	+3	ns
22	Next time effectively behind the gating	-12	+3	ns

The driver intensity of a, bus and gating must adapt to its load and be configured

Between Table A .5.16 bus and the gating with respect to the deviation of nominal value

Number	Parameter	Minimum	Maximum	Unit	Note
							23	Read data setup times before the CAS signal begins to be upgraded to high level	0		ns
24	The read data duration after the CAS signal begins to be upgraded to high level	0		ns

When reading DRAM, the DRAM interface DRAM_data [31:0] that when the CAS signal is upgraded to high level, samples.

Cross-reference between Table A .5.17 " standard " DRAM parameter name and the timing parameters value

Parameter		Parameter		Parameter
						Title	Numerical value	Title	Numerical value	Title	Numerical value
tPC
		10	tRSH	16	tRHCP  tCPRH	18
tRC							11	tCSH	tASR		19
	tRP	12	tRWL		tASC
tCP						tCWL		tDS
	tCPN		tRAC		tRAH					20
tRAS						13	tOACnOE				tCAH
	tCAS	tCHR		tDH
tCAC					tCRP
		17	tAR
tWP				tRCS			tAA		21
	tRASP	tRCH								tRAL
tRASC				tRRH			tRAD				22
	tACPnCPA	14	tRPC
tRCD
		15	tCP
tCSR							tRPC

A.6 MPI (MPI)

The MPI of one standard byte wide (MPI) is used on all chips in the video decoder chip collection, yet the people of general technical ability will recognize that the MPI of other width also can be used in tool this area. MPI and the operation of multiple decoder chip clock synchronous. A.6.1 MPI signal

Table A .6.1 MPI interface signal

Signal name	I/O	Explanation
			enable[1：0]	Input	The sheet of two Low level effectives enables, and the two must be low level can carry out access by MPI
rw	Input	The high level indicating equipment is wanted from the video chip value of reading. This signal should be stable when chip is allowed to.
			addr[n：o]	Input	In the memory Transformation Graphs of address indication chip in 2n place one. This signal should be stable when chip is allowed to.
data[n：o]	Output	The data I of 8 bit widths/O port. These pins are exactly high impedance if arbitrary enable signal is high level.
			irq	Output	A Low level effective open collector interrupt request singal.

A.6.2 MPI electrology characteristic

Table A .6.2 absolute maximum rating

Symbol	Parameter	Minimum	Maximum	Unit
					V DD	Supply voltage with the GND reference	-0.5	6.5	V
V IN	Input voltage on any pin	GND-0.5	V DD+0.5	V
					T A	Operating temperature	-40	+85	℃
T S	Storage temperature	-55	+150	℃

Table A .6.3 DC operating condition

Symbol	Parameter	Minimum	Maximum	Unit
					V DD	Supply voltage with the GND reference	4.75	5.25	V
GND	Ground
			0	0	V
V IH	Input logic " 1 " voltage					2.0	V DD+0.5	V a
		V IL	Input logic " 0 " voltage	GNO-0.5	0.8				V (a)
T A	Operating temperature					0	70	℃ b

A, AC input parameter are measured rank at 1.4V and are measured. B, with TBA wire feet per minute clock crossflow.

Table A .6.4 DC electrical characteristics

Symbol	Parameter	Minimum	Maximum	Unit
					V DL	Output logic " 0 " voltage		0.4	V
V OLOC	OC output logic " 0 " voltage		0.4	V a
					V CH	Output logic " 1 " voltage	2.4		V
I O	Output current	±100		μA b
					I OOC	The OC output current	4.0	8.0	mA c
I OZ	The output off-state current leakage		±20	μA
					I IN	The input drain capacitance		±10	μA

Table A .6.4 DC electrical characteristics (continuing)

Symbol	Parameter	Minimum	Maximum	Unit
					I CD	The RMS source current		500	mA
C IN	Input capacitance		5	pF
					C OUT	Output I/O electric capacity		5	pF

a、 B, this is the stable state driving force of interface, and transient current may be much higher. C, when OC output irg set, during and pull-down impedance≤100 Ω. A.6.2.1 AC characteristic

Table A .6.5 MPI is read regularly

Number	Characteristic	Minimum	Maximum	Unit	Note a
						25	Low level allows the phase	100		ns
26	High level allows the phase	50		ns
						27	Address or read-write are set to chip enable and go	0		ns
28	Address or read-write keep forbidding coming from chip	0		ns
						29	The output opening time	20		ns
30	The read data access time		70	ns	b

Table A .6.5 MPI is read regularly (continuing)

Number	Characteristic	Minimum	Maximum	Unit	Note
							31	The read data retention time	5		ns
32	The read data turn-off time		20

A, in this example, select enable[0] come start cycle and select enable[1] what finish is arbitrarily. The status of these signals is identical. B, access time are 50pF and appointment for the upper maximum load of each data [7.0]. Larger load may increase the access time.

Table A, 6.6 MPI write timings

Number	Characteristic	Minimum	Maximum	Unit	Note
							33	Write data setup time	15		ns	a
34	Write the continued time of data	0		ns

A, in this example selects enable[0] come start cycle and select enable[1] to come end period be arbitrarily. The status of these signals is identical. A.6.3 interrupt

According to the present invention, " event " is a term that is used for describing state on the chip that a kind of user may want to monitor. The software that event can be indicated a mistake or be can be the user provides information.

There are two single bit registers and each interruption or " event " to interrelate. They are state event register and state mask register. A.6.3.1 state event register

The state event register is a read/write register, and its value is set to 1 by a state that comes across inside circuit. Even be that register also is set to 1 in moment and the situation about now having disappeared at this state. Then register is guaranteed to be set to 1, until user's software is to its reset (or whole chip is reset).

This register is set to 0 by writing 0 value.

Writing 0 to register makes to deposit and is not changed

Register must be established by user software before the appearance of again observing this state

Be set to 0.

Register will be reset to 0 state mask register A.6.3.2 when resetting

The state mask register is a read/write register, if corresponding state event register is set up, it allows an interrupt requests to be produced. If state event is set up when 1 is written into the state mask register, an interrupt requests can be sent at once.

Value 1 allows to interrupt

Register clear 0 when resetting.

Unless be illustrated as other kind of situation, piece after producing an interrupt requests with shut-down operation and will be at state event or state mask register by clear 0 rear resume operations. A.6.3.3 event and mask bit

Event bit and mask bit are the corresponding bit position in the successive byte in the memory map (see Table A.9.6 and A.17.6) by grouping often. This is so that break in service software can use the value of reading from mask register as the shielding of event registers intermediate value; Produced interruption to identify which event. A.6.3.4 chip event and shielding

Each chip has one single " totally " event bit, and it has summarized the activity of event on the chip. The chip event registers provide all have at its mask bit event on 1 the chip or.

One 1 in the chip mask bit makes chip can produce interruption. One 0 in the chip mask bit stops event generation interrupt requests on any chip.

Write 1 to 0 for the chip event and do not produce any impact, when all being eliminated, it just is eliminated in all events (enabling by 1 in their mask bits). A.6.3.5 irq signal

Both be set up such as fruit chip event bit and chip event mask, the irq signal is set.

The irq signal is a Low level effective, " open collector " output, and it requires the outside upper resistance that draws of chip. Irq output is drop-down by 100 Ω or less impedance when effective.

We think that the pull-up resistor of about 4K Ω will be applicable to great majority and use. A.6.4 A.6.4.1 halt circuit permission access of access function resister

In the present invention, if associated therewith is stopped, most of registers just can be modified. Thereby the register group interrelates with an access function resister usually.

The register group that 0 value indication in the access function resister is associated with this access function resister should not be modified. Writing 1 to an access function resister requires a piece to be stopped. Yet piece may not can stop and the access function resister of piece will keep 0 value until it is stopped immediately.

Correspondingly, user software will wait for (write 1 ask access after) until read 1 from access function resister. If the user is set to write a value to configuration register at 0 o'clock at its access function resister, the result is undefined. A.6.4.2 the integer of holding in the register

The least significant bit of any byte interrelates with signal data [0] in the memory map.

Those integer-valued registers that maintain greater than 8 are split into 2 or 4 successive byte positions in the memory map. Byte order is " large number ending " shown in Figure 55. Yet, do not have any hypothesis that is written into the relevant order of this class of multibyte register about byte.

No position will return 0 in the memory map when being read, unless no position keeps signed integer in the register. In this case, the high significance bit of register will be by sign extended. For example, 12 bit sign register will be by sign extended to fill one 16 storage map position (2 byte). 16 memory map positions that maintain 12 signless integers will return 0 from its high significance bit. A.6.4.3 keyhole (Keyhole) address location

In the present invention, some storage map position that more seldom is accessed is placed in " keyhole (Keyhole) " back. One " keyhole " has two associated registers, and one is the keyhole address register, and one is the keyhole data register.

Keyhole address indicates the unit in an expanded address space. Operation access that the keyhole data register is read or write is by the unit of keyhole address register appointment.

In access behind keyhole data register associated keyhole address register produce increment. Arbitrary access in expanded address space only has by writing new value to the keyhole address register and be only possible for each access.

One can have more than one " keyhole " corresponding to chip of the present invention and store Transformation Graphs. Do not interact between the different keyholes. A.6.5 specified register untapped register A.6.5.1

The register or the position that are described to " not using " are exactly those positions of not using in current equipment is implemented in the memory conversion. Usually, can read from these positions 0 value. Write zero without any effect to these positions.

The people of skill will understand as one has in this area like that, and compatible mutually for the variation that keeps might occurring in the future with these products, user software had better not depend on the value that read use location never. Similarly, when configuration device, 0 value should be avoided or be set in these positions. A.6.5.2 keep register

Similarly, the register or the position that are described in the present invention " reservation " do not provide it for the impact of equipment performance as data, should not be accessed. A.6.5.3 detected register

Further, be described to the register of " detected register " or the multiple aspect that the equipment detectability is being controlled in the position. Thereby these registers are not employed in the normal operation of equipment, and do not need to be disposed and control by general device software access. A.7 clock

Corresponding to the present invention, in video decoder system, there are many different clocks to be identified. The example of clock has illustrated in Figure 56.

When data are passed the different clocks zone that video decoder chip concentrates, it by with each new clock more synchronously (on chip). In the present invention, the peak frequency of any input clock is 30MHz. Yet the people with general technology in this area will recognize, other frequency comprises that those greater than 30MHz, also can be used. On each chip, MPI (MPI) and the operation of chip clock synchronous. In addition, the pixel format device can produce a low frequency audio clock synchronous with the visual rate of decoded video. Correspondingly, this clock can be used to provide audio/video synchronization. A.7.1 spatial decoder clock signal

Spatial decoder has two kinds of different (and potential asynchronous) clock inputs:

Table A .7.1 spatial decoder clock

Signal name	I/O	Explanation
			coded_clock	Input	This clock control transmits to the data in the coded data port of spatial decoder. The processing of this clock control coded data on chip is until these data reach coded data buffer.
decoder_clock	Input	Most of processing capacity on the decoder clocks control spatial decoder. Decoder clocks is also controlled data communication device and is crossed output port and pass to the spatial decoder outside.

A.7.2 temporal decoder clock signal

Temporal decoder only has a clock input:

Table A .7.2 temporal decoder clock

Signal name	I/O	Explanation
			decoder_clock	Input	All processing capacities on the decoder clocks control time decoder. Decoder clocks is also controlled data communication device and is crossed its input port to the transmission of temporal decoder and the output by output port.

A.7.3 electrology characteristic

The requirement of Table A .7.3 input clock

Number	Characteristic	30MHz		Unit	Note
						Minimum	Maximum
35	Clock cycle		33		ns
		36					The clock high period	13		ns
37	The clock high period		13		ns

The Table A .7.4 clock initial conditions symbolic parameter V of minimax unit_IHInput logic " 1 " voltage 3.68 V_DD＋0.5    V V _ILInput logic " 0 " voltage GND-0.5 1.43 V I_OZInput leakage current ± 10 μ A are the level of CMOS A.7.3.1

Clock input signal is the CMOS input. V_1HminApproximately be V _DD70% and V_1LmaxApproximately be V _DD30%. Value shown in the Table A .7.4 is those V_1HAnd V_1LAt its poorest V separately_DDIn the situation. V_DD=5.0 ± 0.25V is clock stability A.7.3.2

In the present invention, obtain from input clock signal for driving DRAM interface and the chip clock to chip interface. The sequential specification requirement of these interfaces hypothesis input clock is stable in ± 100PS (picosecond) scope regularly. A.8 JTAG

Arrange more and more intensively along with circuit board, utilize the more and more difficult connection of checking between the element of traditional method to connect, as using the in-circuit test of nail bed (bed-of-nails) means. During solving access issues and standardized trial, JTAG (JTAG) produced on methodology. The work of this group is summed up as " standard testing access port and boundary-scan architecture ", is now adopted as standard 1149.1 by IEEE. Spatial decoder and time decoder are deferred to this standard.

This standard is used a boundary scan chain, and it links to each other with each digital scan pin order on the equipment. The test circuit system is transparent in general operation, but boundary scan chain allows test pattern to be changed in test mode, and puts on the pin of equipment. The resulting signal that comes across JTAG equipment input on the circuit board can be scanned out and be detected by relatively simple test equipment. By this method, the contact between the element can be tested, just as the logic region on the circuit board can be tested.

All JTAG operations are to finish by the test access port (TAP) that is made of 5 pins. Trst (test reset) pin does not power in test mode with assurance equipment to the jtag circuit system reset. Tck (test clock) pin is used to drive serial test pattern to tdi (test data input) pin with clock, and go out from tdo (test data output) pin, at last, the operator scheme of jtag circuit system is set up by suitable position is sequentially entered tms (test mode selection) pin with the clock driving.

The JTAG standard is extendible, takes the circumstances into consideration additional characteristic to adapt to chip manufacturer. At spatial decoder and temporal decoder 9 user instructions are arranged, comprise 3 JTAG imperative instructions. Extra-instruction allows internal unit test to a certain degree to be performed, and additional external testing flexibility is provided. For example, all equipment output can be held by a simple JTAG sequence.

Understand about obtainable equipment with about the full details of instruction how to use jtag port, referring to following JTAG application note. A.8.1 the binding of JTAG pin and non-JTAG system

How Table A .8.1 links JTAG input signal direction explanation trst is inputted this pin and has and draw load on the inside, but must be low when powering on

Level is not even the JTAG characteristics are used. This can pass through public affairs

Trst links to each other with chip reset pin reset and reaches altogether. These pins of tdi have inner upper load, and if jtag circuit not by

Input can not be bonded when using. Tms tck inputs this pin and does not draw load on the tool, if should when not using jtag circuit

When being grounded. Tdo is high impedance when output removes the JTAG scan operation. If JTAG is not made

With, this pin can not be bonded. A.8.2 with IEEE1149.1 meet rank A.8.2.1 the rule

Strictly all rules is all adhered to, although following situation should be noted:

Table A .8.2 JTAG rule rule declaration 3.1.1 (b) trst pin is provided 3.5.1 (b) and guarantees for all common instruction for all common instruction guarantee (seeing IEEE 1149.15.2.1 (c)) 5.2.1 (c). To some private instruction, the TDO pin can

With at Capture-DR, Exit-DR appoints among Exit-2-DR and the Pause-DR

Become under one state effectively. 5.3.1 (a) electrification reset that is used to complete by the trst pin. 6.2.1 (e.f) the BYPASS instruction code is loaded at test-logic-reset mode. 7.1.1 the instruction code that (d) is not assigned with is identical with BYPASS. 7.2.1 (c) do not have the device id register. 7.8.1 (b) external control of single step action need system clock. 7.9.1 (...) do not exist RUNBIST facility 7.11.1 (...) not exist IDCODE instruction 7.12.1 (...) not exist USERCODE instruction 8.1.1 (b) not exist equipment identity register 8.2.1 (c) to guarantee for all common instruction. Path from tdi to tdo shows that length ought

Private instruction code may change under some field is closed when being loaded. 8.3.1 (d-i) guarantee for all common instruction. When private instruction code is loaded, remove

The rising edge of tck is outer At All Other Times, and data may be loaded into.

Table A .8.2JTAG rule (continuing)

Rule	Explanation
		10.4.1(e)	During INTEST, the system clock pin must be subjected to outside control.
10.6.1(c)	During INTEST, be controlled by shifted data by the tdi output pin.

A.8.2.2 suggestion

The satiable suggestion of Table A .8.3

Suggestion	Explanation
		3.2.1(b)	Tck is high impedance CMOS input
3.3.1(c)	Tms has on the high impedance and draws
		3.6.1(d)	For slice, thin piece)
3.7.1(a)	For slice, thin piece)
		6.1.1(e)	Sampling/preloaded instruction code is loaded into during Capture-IR
7.2.1(f)	The INTEST instruction is provided
		7.7.1(g)	During EXTEST, zero is loaded on system's output pin
7.7.2(h)	All system's output may be set to high impedance
		7.8.1(f)	Be loaded into zero on system's input pin during the INTEST
8.1.1(d.e)	The design specialized test data register does not supply public access

A.9 spatial decoder

The 30MHz operation

Decoding MPEG, JPEG, and H.261

The coded data rate reaches 25Mb/S

Video data rate reaches 21MB/S

Variable chroma

Fully JPEG baseline decoding

DRAM interface without bonding (Glue-less)

Single+the 5V power supply

The PQFP type encapsulation of 208 pins

Maximum consumption of power 2.5W

Absolute coding data and decoder clocks

Application standard page-mode PRAM

Spatial decoder is a configurable VLSI decoder chip, is used in multiple JPEG, MPEG and H, and 261 images and video decode are used.

In a minimal configuration that does not contain DRAM outside the chip, the space decoding is the high speed JPEG decoding device of a single-chip. The video image that adds DRAM JPEG coding so that spatial decoder can be decoded. 720 * 480,30Hz, 4:2:2 " JPEG video " can be by real-time decoding.

Temporal decoder has been arranged, and H.261 spatial decoder can be used to decoding and MPEG (and JPEG). 704 * 480,30Hz, the MPEG video of 4:2:0 can be decoded.

Point out that again above-mentioned value just is used for explanation corresponding to the representative value of one embodiment of the present invention, only for need not as restriction for example. Correspondingly, those people with general skill in this area will recognize that other numerical value and/or scope also can be used.

The unconsummated suggestion of Table A .8.4

Suggestion	Explanation
		10.4.1(f)	During EXTEST, drive from the system clock pin and to enter that the signal of logic is provided by the outside on the sheet.

A.8.2.3 allow

The satiable permission of Table A .8.5

Allow	Explanation
		3.2.1(c)	For all common instruction guarantee
6.1.1(f)	Command register is not used for collecting design specialized information
		7.2.1(g)	Some additional common instruction are provided
7.3.1(a)	Some privately owned instruction codes are assigned with
		7.3.1(c)	(rule?) this type of instruction code lists data in
7.4.1(f)	Some extra-codes are entirely same to the effect of BYPASS
		10.1.1(i)	Each output pin has the three-state control of oneself
10.3.1(h)	Parallel latch is provided
		10.3.1(i.j)	During EXTEST, input pin is controlled by shifted data by tdi
10.6.1(d.e)	At the Test-Logic-Reset state, ternary element is not forced to inertia

A.9.1 spatial decoder signal

Table A .9.1 spatial decoder signal

Signal name	Enter/go out	Pin number	Explanation
				coded_clock	I	182	Spatial decoder coded data or token are seen A10.1 part and part A.4.1
coded_data[7：0]	I	172，171，169， 168，167，166， 164，163
			coded_extn	I	174
coded_valid	I	162
			coded_accept	O		161
byte_mode	I	176
			enable[1：0]	I	126，127	MPI (MPI) is seen A.6.1 part
rw	I	125
			addr[6：0]	I	136，135，133， 132，131，130， 128
data[7：0]	O	152，151，149， 147，145，143， 141，140
			irq	O	154

Table A .9.1 spatial decoder signal (continuing)

Signal name	Enter/go out	Pin number	Explanation
				DRAM_data[31：0]	I/ O	15，17，19，20， 22，25，27，30， 31，33，35，38， 39，42，44，47， 49，57，59，61， 63，66，68，70， 72，74，76，79， 81，83，84，85	The DRAM interface is seen A.5.2 part
DRAM_addr[10：0]	O	184，186，188， 189，192，193， 195，197，199， 200，203
			RAS	O		11
CAS[3：0]	O	2，4，6，8
			WE	O		12
OE	O	204
			DRAM enable	I	112
out_data[8：0]	O	88，89，90，92， 93，94，95，97， 98				Output port is part A.4.1
			out_extn	O	87
out_valid	O	99
			out_accept	I	100

Table A .9.1 spatial decoder signal (continuing)

Signal name	Enter/go out	Pin number	Explanation
				tck	I	115	Jtag port is seen A.8 part
tci	I	116
			tdo	O	120
tms	I	117
			trst	I	121
decoder_clock	I	177				The main decoder clock is seen A.7 part
			reset	I	160		Reset

Table A .9.2 spatial decoder test signal

Signal name	Enter/go out	Pin number	Explanation
				tph0ish	I	122	As override=1 then tph0ish and tph1ish be two phase clock input on the sheet, override=0 is established in normal operating. Tph0ish and the tph1ish (ground connection or meet V that is left in the basketDD)
tph1ish	I	123
			override	I	110
chiptest	I	111				Chiptest=0 is established in normal operating
			tloop	I	114		Normal operating ground connection or meet VDD
ramtest	I	109				Allow RAM on the test pieces such as ramtest=1. Ramtest=0 is established in normal operating

Table A .9.2 spatial decoder signal (continuing)

Signal name	Enter/go out	Pin number	Explanation
				pllselect	I	178	Be under an embargo such as phaselocked loop on the pllselect=0 sheet. Normal operation arranges pllselect=1
ti	I	180	Two of the DRAM interface requirement clocks when test operation. Ground connection or meet V during normal operationDD
				tq	I	179
pdout	O	207					For phaselocked loop, this two pins is attached to external filter
			pdin	I	206

Table A .9.3 spatial decoder pin assignment

Signal name	Pin	Signal name	Pin	Signal name	Pin	Signal name	Pin
								nc	208	nc	156	nc	104	nc	52
testpin	207	nc	155	nc	103	nc	51
								testpin	206	uq	154	Dc	102	nc	50
GND	205	nc	153	VDD	101	DRAM_data[15]	49
								OE	204	data[7]	152	out_accept	100	nc	48
DRAM_addr[0]	203	data[6]	151	out_valid	99	DRAM_data[15]	47
								VDD	202	nc	150	out_data[0]	98	nc	46
nc	201	data[5]	149	out_data[1]	97	GND	45
								DRAM_addr[1]	200	nc	148	GND	95	DRAM_data[17]	44
DRAM_addr[2]	199	data[4]	147	out_data[2]	95	nc	43
								GND	193	GND	146	out_data[3]	94	DRAM_data[18]	42
DRAM_addr[3]	197	data[3]	145	out_data[4]	93	VDD	41
								nc	196	nc	144	out_data[5]	92	nc	40
DRAM_addr[4]	195	data[2]	143	VDD	91	DRAM_data[19]	39
								VDD	194	nc	142	out_data[6]	90	DRAM_data[20]	3a
DRAM_addr[5]	193	data[1]	141	out_data[7]	89	nc	37
								DRAM_addr[5]	192	data[0]	140	out_data[a]	88	GND	36
nc	191	nc	139	out_extn	87	DRAM_data[21]	35
								GND	190	VDD	138	GND	86	nc	34
DRAM_addr[7]	189	nc	137	DRAM_data[0]	85	DRAM_data[2]	33
								CRAM_addr[8]	188	addr[5]	136	DRAM_data[1]	84	VDD	32
VDD	187	addr[5]	135	DRAM_data[2]	83	DRAM_data[23]	31
								DRAM_addr[9]	186	GND	134	VDD	82	DRAM_da1a[24]	30
nc	185	addr[4]	133	DRAM_data[3]	81	nc	29
								DEAM_addr[10]	184	addr[3]	132	nc	80	GND	23
GND	183	addr[2]	131	DRAM_data[4]	79	DRAM_data[25]	27
								coded_clock	182	addr[1]	130	GND	78	nc	25
VDD	181	VDD	129	DC	77	DRAM_data[25]	25
								testpin	180	addr[0]	128	DRAM_data[5]	76	nc	24
testpin	179	enaple[0]	127	nC	75	VDD	21
								testpin	17a	enaple[1]	125	DRAM_data[5]	74	DRAM_data[27]	22
dacoder_clock	177	nc	125	VDD	73	nc	21
								byte_cacde	176	GND	124	DRAM_data[7]	72	DRAM_data[23]	20
GND	175	testpin	123	nc	71	DRAM_data[29]	19
								coced_exin	174	testpin	122	DRAM_data[8]	70	GND	18

Table A .9.3 spatial decoder pin assignment (continuing)

The signal name pin	The signal name pin	The signal name pin	The signal name pin
				nc                   208	nc                 156	nc                   104	nc                      52
testpin              207	nc                 155	nc                   103	nc                      51
				testpin              206	uq                 154	nc                   102	nc                      50
GND                  205	nc                 153	VDD                  101	DRAM_data[15]           49
				OE                   204	data[7]            152	out_accect           100	nc                      48
DRAM_addr[0]         203	data[5]            151	out_valid             99	DRAM_data[15]           47
				VDD                  202	nc                 150	out_data[0]           93	nc                      46
nc                   201	data[5]            149	out_data[1]           97	GND                     45
				DRAM_addr[1]         200	nc                 148	GND                   95	DRAM_data[17]           44
DRAM_addr[2]         199	data[4]            147	out_data[2]           95	nc                      43
				GND                  198	GND                146	out_data[3]           94	DRAM_data[16]           42
DRAM_2ddr[3]         197	data[3]            145	out_data[4]           93	VDD                     41
				nc                   196	nc                 144	out_data[5]           92	nc                      40
DRAM_addr[4]         195	data[2]            143	VDD                   91	DRAM_data[19]           39
				VDD                  194	nc                 142	out_data[5]           90	DRAM_data[20]           38
DRAM_addr[5]         193	data[1]            141	out_data[7]           89	nc                      37
				DRAM_addr[6]         192	data[0]            140	out_data[8]           88	GND                     36
nc                   191	nc                 139	out_exm               87	DRAM_data[21]           35
				GND                  190	VDD                138	GND                   86	nc                      34
DRAM_addr[7]         189	nc                 137	DRAM_data[0]          85	DRAM_data[22]           33
				DRAM_addr[8]         188	addr[6]            136	DRAM_data[1]          84	VDD                     32
VDD                  187	addr[5]            135	DRAM_data[2]          83	DRAM_data[23]           31
				DRAM_addr[9]         186	GND                134	VDD                   82	DRAM_data[24]           30
nc                   185	addr[4]    133	DRAM_data[3]          81	nc                      29
				DRAM_addr[10]        184	addr[3]    132	nc                    80	GND                     28
GND                  183	addr[2]    131	DRAM_data[4]          79	DRAM_data[25]           27
				coded_clock          182	addr[1]            130	GND                   78	nc                      26
VDD                  181	VDD                129	nC                    77	DRAM_data[25]           25
				testpin              180	addr[0]            128	DRAM_data[5]          76	nc                      24
testpin              179	enable[0]          127	nc                    75	VDD                     23
				testpin              178	enable[1]          126	DRAM_data[6]          74	DRAM_data[27]           22
decoder_clock        177	nc                 125	VDD                   73	nc                      21
				byte_mode            176	GND                124	DRAM_data[7]          72	DRAM_data[29]           20
GND                  175	testpin            123	nc                    71	DRAM_data[29]           19
				coded_exm            174	testpin            122	DRAM_data[8]          70	GND                     18

Table A .9.3 spatial decoder pin assignment (continuing)

Signal name	Pin	Signal name	Pin	Signal name	Pin	Signal name	Pin
								nc	173	trst	121	GND	69	DRAM_data[30]	17
coded_data[7]	172	tdo	120	DRAM_data[9]	68	nc	15
								coded_data[6]	171	nC	119	nc	67	CRAM_data[31]	15
VCD	170	VDD	118	DRAM_data[10]	66	VDD	14
								coded_data[5]	169	tms	117	VDD	65	nc	13
coded_data[4]	168	tdi	115	nc	64	WE	12
								coded_data[3]	157	lck	115	DRAM_data[11]	63	RAS	11
coded_data[2]	166	testpin	114	nc	62	nc	10
								GND	165	GND	113	DRAM_data[12]	61	GND	9
coded_data[1]	164	DRAM_ecable	112	GND	60	CAS[0]	8
								coded_data[0]	163	testpin	111	DRAM_data[13]	59	nc	7
coded_valid	152	testpin	110	nc	58	CAS[1]	6
								coded_accect	151	testpin	109	DRAM_data[14]	57	VDD	5
reset	150	nc	108	VDD	56	CAS[2]	4
								VDD	159	nc	107	nc	55	nc	3
nc	158	nc	106	nc	54	CAS[0]	2
								nc	157	nc	105	nc	53	nc	1

A.9.1.1 " nc " is without connecting pin

Indicate among the Table A .9.3 that the pin of nc is current not to be used. These pins should not be connected. A.9.1.2 V_DDWith the GND pin

The people of skill will recognize as in tool this area, all V that are provided_DDAll should be connected with suitable power supply with the GND pin. Unless all V_DDAll correctly used with the GND pin, otherwise can not be guaranteed correct equipment operation. A.9.1.3 the test pin of normal operating links

9 pins on the spatial decoder are preserved for close beta.

The default test pin of Table A .9.4 connects

Pin number	Connect
			Ground connection during normal operating
	Meet V during normal operatingDD
			Let alone open circuit during normal operating

A.9.1.4 the JTAG pin of normal operating

See A.8.1 A.9.2 spatial decoder storage map of part

Table A .9.5 spatial decoder memory map list

Address (hexadecimal)	Register name	See Table
			0×00…0×03	The break in service district	A.9.6
0×04…0×07	The input circuit register	A.9.7
			0×08…0×0F	The initial code detected register
0×10…0×15	Buffer starts control register				A.9.8
		0×16…0×17	Do not use
0×18…0×23	The DRAM interface arranges register				A.9.9
		0×24…0×26	Buffer manager for use access and keyhole register	A.9.10
0×27	Do not use
		0×28…0×2F	The Hafman decoding register	A.9.13
0×30…0×39	The re-quantization register				A.9.14
		0×3A…0×3B	Do not use
0×3C	Keep
		0×3D…0×3F	Do not use
0×40…0×7F	Scratchpad register

Table A .9.6 break in service district register

Address (hexadecimal)	Item	Register name	Reference page
					0×00	7	chip_event CED_EVENT_0
6	Do not use
			5	Illegal_length_count_event SCD_ILLEGAL_LENGTH_COUNT
4	reserved may read 1 or 0 SCD_JPEG_OVERLAPPING_START
			3	overtapping_start_event SCO_NON_JPEG_OVERLAPPING_START
2	unrecognised_start_event SCD_UNRECOGNISED_START
			1	stop_after_picture_event SCD_Stop_AFTER_PICTURE
0	non_afigned_start_event SCD_NON_ALIGNED_START
			0×01	7		chip_mask CED_MASK_0
6	Do not use
				5	ltlegal_length_count_mask
4	reservede write O to this location SCD_JPEG_OVERLAPPING_START
				3	non_Jpeg_cventapping_start_mask
2	unrecognlsedd_start_mask
				1	slop_after_plcture_mask
0	non_aligned_start_mask
				0×02	7	idct_too_few_event IDCT_DEFF_NUM
6	idct_too_many_event IDCT_SUPER_NUM
			5		accept_enabte_event BS_STREAM_END_EVENT
4	target_met_event BS_TARGET_MET_EVENT
			3		counter_tlushed_too_early_event BS_FLUSH_BEFORE_TARGET_MET_EVENT
2	counter_flushed_event BS_FLYSH_EVENT
			1		parser_event DEMUX_EVENT
0	huffman_event HUFFMAN_EVENT

Table A .9.6 break in service district's register (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×03	7	ldct_too_few_mask
6	idct_too_many_mask
			5	accept_enable_mask
4	target_met_mask
			3	counter_flushed_too_earty_mask
2	counter_flushed_mask
			1	parser_mask
0	huffman_mask

Table A .9.7 detector for initial code and input circuit register

Address (hexadecimal)	Item	Register name	Reference page
					0×04	7	coded_busy
6	enable_mpl_lnput
		5	coded_extn
4：0	Do not use
		0×05	7：0	coded_data
0×06	7：0				Do not use
		0×07	7：0	Do not use
0×08	7：1				Do not use
		0	starrt_code_detector_access also Input_clrcyut_access CED_SCD_ACCESS
	0×09				7：4	The CED_SCE_STATUS of usefulness not
3		stop_after_picture
				2	discard_extension_data
1		discard_user_data
				0	lgnore_non_aligned
0×0A		7：5	The CED_SCD_CONTROL of usefulness not
	4			insert_sequence_start
		3	discard_all_data
	2：0			start_code_search

Table A .9.7 detector for initial code and input circuit register (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×0B	7：0	Scratchpad register length_count
0×0C	7：0
		0×0D	7：2	Do not use
1：0	start_code_deteclor_coding_standard
			0×0E	7：0	start_value
0×0F	7：4	Do not use
			3：0	plcture_number

Table A .9.8 buffer starts register

Address (hexadecimal)	Item	Register name	Reference page
					0×10	7：1	Do not use
0	startup_access CED_BS_ACCESS
			0×11	7：3
2：0	bit_count_prescale CED_BS_PRESCALE
				0×12	7：0	bit_count_target CED_BS_TARGET
0×13	7：0	bit_count CED_BS_COUNT
				0×14	7：1	Do not use
0	offchip_queue CED_BS_OUEUE
			0×15		7：1	Do not use
0	enable_stream CED_BS_ENABLE_NXT_STM

Table A .9.9DRAM interface arranges register

Address (hexadecimal)	Item	Register name	Reference page
					0×18	7：5	Do not use
4：0	page_start_length CED_n_PAGE_START_LENGTH
			0×19	7：4		Do not use
3：0	read_cycle_length
				0×1A	7：4	Do not use
3：0	write_cycle_lengtn

Table A .9.9 DRAM interface arranges register (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×18	7：4	Do not use
3：0	refresh_cycle_length
			0×1C	7：4		Do not use
3：0	CAS_falling
				0×1D	7：4	Do not use
3：0	RAS_falling
			0×1E		7：1	Do not use
0	intertace_tlming_access
				0×1F	7：0	retresh_interval
0×20	7	Do not use
				6：4	DRAM_addr_strength[2：0]
	3：1	CAS_strength[2：0]
				0	RAS_strength[2]
	0×21	7：6	RAS_strength[1：0]
5：3				OEWE_strength[2：0]
		2：0	DRAM_data_strength[2：0]
0×22				7	For the ACCESS position of filling intensity etc. etc.? untapped CED_DRAM_CONRIGURE
		zero_buffers
	5	DRAM_enable
			4	no_refresh
	32	row_address_blts[1：0]
			1：0	DRAM_data_width[1：0]
0×23	7：0	Scratchpad register CED_PLL_RES_CONFIG

Table A .9.10 buffer manager for use access and keyhole register

Address (hexadecimal)	Item	Register name	Reference page
					0×24	7：1	Do not use
0	buffer_manager_access
			0×25	7：6		Do not use
5：0	buffer_manager_keyhole_address
				0×26	7：0	buffer_manager_keyhole_date

Table A .9.11 buffer manager for use expanded address space

Address (hexadecimal)	Item	Register name	Reference page
					0×00	7：0	Do not use
0×01	7：2
		1：0	cdb_base
	0×02				7；0
0×03		7：0
	0×04				7：0	Do not use
0×05		7：2
	1：0		cdb_length
		0×06			7：0
0×07	7：0
		0×08			7：0	Do not use
0×09	7：0		cdb_read
		0×0A			7：0
0×0B	7：0
		0×0C			7：0	Do not use
0×0O	7：0		cdb_number
		0×0E			7：0
0×0F	7：0
		0×10			7：0	Do not use
0×11	7：0		tb_base
		0×12			7：0
0×13	7：0
		0×14			7：0	Do not use
0×15	7：0		tb_length
		0×16			7：0
0×17	7：0
		0×18			7：0	Do not use
0×19	7：0		tb_read
		0×1A			7：0
0×1B	7：0
		0×1C			7：0	Do not use
0×10	7：0		tb_number
		0×1E			7：0
0×1F	7：0

Table A .9.11 buffer manager for use expanded address space (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×20	7：0	Do not use
0×21	7：0	buffer_limit
				0×22	7：0
0×23	7：0
				0×24	7：4	Do not use
3	cdb_full
			2		cdb_empty
1	tb_full
			0		tb_empty

Table A .9.12 video separator register

Address (hexadecimal)	Item	Register name	Reference page
					0×28	7	demux_access CED_H_CTRL[7]
6：4	huffman_error_code[2：0] CED_H_CTRL[5：4]
			3：0	Private Huffman control bit [3] is selected space CBP, and [2] select 4/8bit fixed length CBP
0×29	7：0	parser_error_code CED_H_DMUX_ERR
			0×2A	7：4	Do not use
3：0	demux_keyhole_address CED_H_KEYHOLE_ADDR
				0×2B	7：0
0×2C			7：0			demux_keyhole_data CED_H_KEYHOLE
	0×2D	7		dummy_tast_picture CEO_H_ALU_REGO. t_dummy_Last_frame_bit
6			tield_into CED_H_ALU_REGO.t_field_into_out
		5：1		Do not use
0			contlnue CED_H_ALU_REGO.r_continue_od
		0×2E		7：0	rom_revislon CED_H_ALU_REGI
0×2F	7：0		The private register

Table A .9.12 video separator register (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×2F	7	CED_H_TRACE_EVENT writes 1 to single step, and after single step is finished, 1 will be read out
6	CED_H_TRACE_MASK is arranged to 1, to enter single-step mode
			5	CED_H_TRACE_RST works as when arranging 1,0 sequence properly, partial reset
4：0	Do not use

Table A .9.13 video separator expanded address space

Address (hexadecimal)	Item	Register name	Reference page
					0×0O 0×0F	7：0	Do not use
0×10	7：0	horiz_pels r_horiz_pels
				0×11	7：0
0×12	7：0					vert_pels r_vert_pels
		0×13	7：0
0×14	7：2			Do not use
		1：0	buffer_size r_bcffer_size
	0×15			7：0
0×16		7：4			Do not use
	3：0		pel_aspect r_pel_aspect
		0×17			7：2	Do not use
1：0	bit_rate r_bit_rate
				0×18	7：0
0×19		7：0
				0×1A	7：4	Do not use
3：0	pic_rate r_pic_rate
			0×1B		7：1	Do not use
0	Restricted r_constrained
				0×1C	7：0	picture_type
0×1D	7：0	h261_plc_type

Table A .9.13 video separator expanded address space (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×1E	7：2	Do not use
1：0	broken_closed
			0×1F	7：5		Do not use
4：0	predicdon_mode
				0×20	7：0	vbv_delay
0×21	7：0
		0×22	7：0	MPEG private register full_pel_fwd, JPEG Pending_frame_change
0×23	7：0					MPGE private register full_pel_bwd, JPEG restart_index
		0×24	7：0	Private register horiz_mb_copy
0×25	7：0					plc_number
		0×25	7：1	Do not use
1：0	max_h
			0×27	7：1	Do not use
1：0	max_v
				0×29	7：0	Private register scratch1
0×29	7：0	Private register scratch2
				0×2A	7：0	Private register scratch3
0×2B	7：0	Nf MPEG unsed1.H261 ingob
				0×2C	7：0	MPGE private register first_group, JPEG first_scan
0×2D	7：0	MPEG private register in_picture
				0×2E	7	dummy_last_picturer_rom_conlrol
6	field_info
			5：1		Do not use
0	Continue
			0×2F		7：0	rom_revision
0×30	72	Do not use
			1：0		dc_huff_0
	0×31	72		Do not use
1：0			dc_huff_1
		0×32		72		Do not use
1：0	dc_huff_2

Table A .9.13 video separator expanded address space (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×33	7：2	Do not use
1：0	dc_huff_3
			0×34	7：2		Do not use
1：0	ac_huff_0
				0×35	7：2	Do not use
1：0	ac__huff_1
			0×36		7：2	Do not use
1：0	ac_huff_2
				0×37	7：2	Do not use
1：0	ac_huff_3
			0×38		7：2	Do not use
1：0	tq_0 r_tq_0
				0×39	7：2	Do not use
1：0	tq_1 r_tq_1
			0×3A		7：2	Do not use
1：0	tq_2 r_tq_2
				0×3B	7：2	Do not use
1：0	tq_3 r_tq_3
			0×3C		7：0	component_name_0 r_c_0
0×3D	7：0	component_name_1 r_c_1
			0×3E		7：0	component_name_2 r_c_2
0×3F	7：0	component_name_3 r_c_3
			0×40 0×63		7：0	The private register
0×40	7：0	r_dc_pred_0
			0×41		7：0
0×42	7：0			r_dc_pred_1
		0×43	7：0
0×44	7：0					r_dc_pred_2
		0×45	7：0
0×45	7：0				r_dc_pred_3
		0×47	7：0
0×48 0×4F	7：0					Do not use

Table A .9.13 video separator expanded address space (continuing)

Address (hexadecimal)	Item	Register name	Reference page
				0×50	7：0	r_prev_mnf
0×51	7：0
			0×52	7：0	r_prev_mvf
0×53	7：0
			0×54	7：0		r_prev_mhb
0×55	7：0
			0×56	7：0	r_prev_mvb
0×57	7：0
			0×58 0×5F	7：0		Do not use
0×60	7：0	r_horiz_mbcnt
			0×61	7：0
0×62	7：0				r_vert_mbcnt
		0×63	7：0
0×64	7：0					horiz_macroblocks r_horiz_mbs
		0×65	7：0
0×66	7：0				vert_macroblocks r_vert_mbs
		0×67	7：0
0×68	7：0					Private register r_restart_cnt
		0×69	7：0
0×6A	7：0				restart_lntervat r_restart_it
		0×6B	7：0
0×6C	7：0					Private register r_blk_h_cnt
		0×6D	7：0	Private register r_blk_v_cnt
0×6E	7：0					Use register r_conpid
		0×6F	7：0	max_component_id r_max_compid
0×70	7：0					coding_standard r_coding_std
		0×71	7：0	Private register r_pattern
0×72	7：0					Private register r_fwd_r_sige
		0×73	7：0	Private register r_bwd_r_sige
0×74 0×77	7：0					Do not use
		0×78	7：2	Do not use
1：0	blocks_h_0 r_brk_h_0

Address (hexadecimal)	Item	Register name	Reference page
				0×850 0×85F	7：0	CED_KEY_MTYPE_P_CPB
0×860 0×86F	7：0	CED_KEY_MTYPE_3_CPB
				0×870 0×88F	7：0	CED_KEY_MTYPE_H251CPS
0×880 0×900	7：0	Do not use
				0×901	7：0	CED_KEY_HDSTROM_0
0×902	7：0	CED_KEY_HDSTROM_1
				0×903 0×90F	7：0	CED_KEY_HDSTROM_2
0×910 0×AB	7：0	Do not use
				0×AC   0	7：0	CED_KEY_DMX_WORD_0
0×AC   1	7：0	CED_KEY_DMX_WORD_1
				0×AC   2	7：0	CED_KEY_DMX_WORD_2
0×AC   3	7：0	CED_KEY_DMX_WORD_3
				0×AC	7：0	CED_KEY_DMX_WORD_4
0×AC   5	7：0	CED_KEY_DMX_WORD_5
				0×AC   6	7：0	CED_KEY_DMX_WORD_6
0×AC   7	7：0	CED_KEY_DMX_WORD_7

Table A 9.13 video distributor expanded address spaces (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×189	7：0	ac_eob_1 CED_H_KEY_EOB_INDEX1
0×18A  0×18B	7：0	Do not use
				0×18C	7：0	ac_zrl_0 CED_H_KEY_ZRL_INDEX0
0×18D	7：0	ac_zrl_1 CED_H_KEY_ZRL_INDEX1
				0×18E  0×1FF	7：0	Do not use
0×200  0×AF	7：0	ac_huffval_0[161：0]CED_H_KEY_AC_ITDO_0
				0×B0  0×2BF	7：0	dc_huffval_0[11：0]CED_H_KEY_DC_ITOD_0
0×2C0  0×2FF	7：0	Do not use
				0×300  0×3AF	7：0	ac_huffval_1[161：0]CED_H_KEY_AC_ITOD_t
0×280  0×38F	7：0	dc_huffval_1[11：0]CED_H_KEY_DC_ITOD_1
				0×3C0  0×7FF	7：0	Do not use
0×800  0×AC     F	7：0	The private register
				0×800  0×80F	7：0	CED_KEY_TCOEFF_CPB
0×810  0×81F	7：0	CED_KEY_CBP_CPB
				0×820  0×82F	7：0	CED_KEY_MBA_CPB
0×930  0×93F	7：0	CED_KEY_MVD_CPB
				0×840  0×84F	7：0	CED_KEY_MYPE_I_CPB

Table A .9.13 video distributor expanded address space (continuing)

				0×79	7：2
1：0	blocks_h_1 r_blk_h_1
			0×7A		7：2
1：0	blocks_h_2 r_blk_h_2
				0×7B	7：2
1：0	blocks_h_3 r_blk_h_3
			0×7C		7：2
1：0	blocks_v_0 r_blk_v_0
				0×7D	7：2
1：0	blocks_v_1 r_blk_v_1
			0×7E		7：2
1：0	blocksv_2 r_blk_v_2
				0×7F	7：2
1：0	blocks_v_3 r_blk_v_3
			0×7F 0×FF		7：0
0×100 0×10F	7：0	dc_bits_0[15：0]CED_H_KEY_DC_CB0
			0×110 0×11F		7：0	dc_bits_1[15：0]CED_H_KEY_DC_CPB1
0×120 0×13F	7：0
			0×140 0×14F		7：0	ac_bits_0[15：0] CED_H_KEY_AC_CPB0
0×150 0×15F	7：0	ac_bits_1[15：0] CED_H_KEY_AC_CPB1
			0×160 0×17F		7：0
0×180	7：0	dc_zssss_0 CED_H_KEY_ZSSSS_INDEX0
			0×181		7：0	dc_zssss_1 CED_H_KEY_ZSSSS_INDEX1
0×182 0×187	7：0
			0×188		7：0	ac_eob_0 CED_H_KEY_EOB_INDEX0

Address (hexadecimal)	Item	Register name	Reference page
				0×AC   8	7:0	CED_KEY_CMX_WORO_8
O×AC   9	7：0	CED_KEY_CMX_WORD_9
				0×AC   A 0×AC   B	7：0	Do not use
0×AC   C	7：0	CEO_KEY_OMX_AINCR
				0×AC   D	7：0
0×AC	7：0		CED_KEY_DMX_CC
		0×AC   F		7：0

Table A .9.13 video distributor expanded address space (continuing)

Table A .9.14 inverse quantizer register

Address (hexadecimal)	Item	Register name	Reference page
					7：0	Do not use
0×30	7：1	Do not use
				0	lq_access
	0×31	7：2	Do not use
1：0				lq_coding_standard
		0×32	7：5			Do not use
4：0	Scratchpad register iq_scale
			0×33		7：2	Do not use
1：0	Scratchpad register iq_component
				0×34	7：2	Do not use
1：0	Scratchpad register inverse_quantiser_ prediction_mode
			0×35		7：0	Scratchpad register jpeg_indirection
0×36	7：2	Do not use
			：0		Scratchpad register mpeg_indirection
	0×37	7：0		Do not use

Table A .9.14 inverse quantizer register (continuing)

Address (hexadecimal)	Item	Register name	Reference page
					0×38	7：0	iq_table_keyhole_address
0×39	7：0	iq_table_keyhole_data

Table A .9.15 Iq (re-quantization) table extended address space

Address (hexadecimal)	Register name	Reference page
				0×00：0×3F	The default base table of JPEG re-quantization table 0 MPEG
0×40：0×7F	The default non-base table of JPEG re-quantization table 1 MPEG
			0×80：0×BF	The long-range base table of packing into of JPEG re-quantization table 2 MPEG
0×C0：0×FF	The long-range non-base table of packing into of JPEG re-quantization table 3 MPEG

A.10 coded data input

Must know that corresponding to system of the present invention which kind of video standard is transfused to for processing. After this, the token that system can accept to be pre-existing in or original word data, then the raw bytes data are put into token by detector for initial code.

Thereby, coded data and token is set can be provided for spatial decoder by two kinds of approach:

The coded data input port

MPI (MPI)

Which paths of choice for use will depend on is used and system environments. For example, when low data rate, might control simultaneously with a single microprocessor multichannel distribution of decoder chip collection and completion system Bit String. In this case, might finish by MPI the input of coded data. Select as another kind, a high coded data rate may require coded data to be provided by the coded data port.

In some applications, may be fit to take the input of MPI and coded data port hybrid. A.10.1 coded data port

Table A .10.1 coded data port signal

Signal name	I/O	Explanation
			coded_clock	Enter	One operation up to the clock control input circuit of 30 megahertzes
coded_data[7：0]	Enter	Realize that the token port transmits desired 11 lines of 8bit data value, see that A.4 part is to the electric description of this interface. Off-chip circuitry must be assembled coded data becomes token
			coded_extn	Enter
coded_valid	Enter
			coded_accept	Go out
byte_mode	Enter				When this signal is that high level represents that then the information through the coded data port transmission is by byte mode rather than token mode.

Can two kinds of patterns be operated corresponding to coded data port of the present invention: token pattern and byte mode. A.10.1.1 token pattern

In the present invention, if byte_mode is low level, the coded data port moves as a token port in conventional method so, and accepts token under coded_valid and coded_ accept control. The electric details of operation of this interface is seen A.4 part.

Signal byte_mode and data[7:0], coded_extn and coded_valid namely are sampled at the rising edge of Coded_Clock simultaneously. A.10.1.2 byte mode

Yet if byte_mode is in high level, data byte is being sent to data[7:0 under the control of two-wire interface control signal coded_valid and coded_accept so] on. In the case, coded_extn is left in the basket. Byte is fitted into the DATA token continuously on chip, until input pattern is changed.

The first character of the token that 1) in the token pattern, provides (" head ").

2) the token the last character (coded_extn becomes low level) that provides.

3) first byte of the data that in byte mode, provide. A new DATA token is produced on chip automatically. A.10.2 provide data by MPI

Token can offer spatial decoder through MPI by the Access Coding Minimal data input register. A.10.2.1 write sign by MPI

Coded data register among the present invention be assembled in the memory map two bytes so that active data transmit. 8 data bit, coded_data[7:0] at a memory cell, and control register, coded_busy, enable_mpi_input and coded_ extn are in second memory cell (seeing Table A.9.7).

When disposing for the token input of passing through MPI, whenever a value is written into coded_ data[7:0], current token is just by the currency expansion with coded_extn. Software should be written into coded_data[7:0 at any the last character of token] before coded_extn be set to 0.

For example, write 1 then to coded_data[7:0 to coded_extn] writing 0 * 04 can an initial DATA token. Then, the initial spatial decoder that is delivered to of this new DATA token is to deal with.

Whenever 8 new place values are written into coded_data[7:0], current token just is expanded. When finishing current token, when for example introducing another token, coded_extn only needs by again access. By writing 0 to coded_extn then to coded_data[7:0] write the last character of current token, the last character of current token can be suggested.

Table A .10.2 coded data input register

Register name	Size/direction	Reset mode	Explanation
				coded_extn
	1    rw	Uncertain	By writing these registers, through MPI, token can offer spatial decoder
				coded_data [7：0]	8     w	Uncertain
coded_busy	1     r	1					This buffer status represents whether spatial decoder can accept to write on coded-data[7:0] in token. Value 1 expression interface is busy, can not accept data. When coded_busy=1, the user attempts coded_data[7:0] situation that writes then can not determine.
			enable_mpl_ input	1    rw	0	The coded data input that this function allows the value of register to control to spatial decoder is by coded data port (0) or by MPI (1)

Writing coded_data[7:0 at every turn] before, coded_busy should be examined to see whether interface has been ready to accept more data. A.10.3 the conversion between the input pattern

Suppose that suitable advance notice is observed, then might dynamically change data entry mode. Usually in fact, the token passing that is undertaken by any approach should finish before translative mode.

Table A .10.3 translation data input pattern

Preceding mode	Next pattern	Behavior
			Byte	Token	On-chip circuit will be used in last byte of providing under the byte mode as last byte of data token, and this data token is accepting to consist of (namely, the extn position will be set to 0) before the next token
The MPI input
	Token	Byte		Under the token pattern, provide the sheet external circuit of token before selecting byte mode, to be responsible for finishing token (the extn position that is the last byte of information is set to 0)
The MPI input			To not be allowed to (being that coded busy maintenance is set to 1) by MPI access input, unless under the token pattern, provide the circuit of token to finish token (the extn position that is the last byte of information is set to 0)
		The MPI input		Byte	Be set to before 0 at enable_mpi_input, control software must be finished this token (the extn position that is the last byte of information is set to 0)
The MPI input

The first byte that provides with byte mode causes a DATA token head to be produced at chip. Any other byte that transmits with byte mode all is affixed to this DATA token after this, until input pattern changes. Recall, the DATA token can comprise required any multidigit again.

The MPI register-bit, coded_busy and signal coded_accept indication spatial decoder will be ready which interface to accept data from. The correct monitoring of these signals can guarantee do not have data to be lost. A.10.4 coded data is accepted speed

In the present invention, input circuit is sent to detector for initial code (seeing A.11 part) with token. Detector for initial code is analyzed the data bit in the DATA token continuously. The normal process speed of detector is one of each clock cycle (coded_clock). Correspondingly, say that typically it is with the coded data of a byte of per 8 coded_clock cycle decoders. Yet, sometimes also need the treatment cycle that adds, for example when a non-DATA token is provided or runs into an initial code in coded data. When this happens, detector for initial code can not be accepted more information within a blink.

After detector for initial code, data enter first a logic coding data buffer. If this buffer is full, detector for initial code can not be accepted more information so.

Thereby, when detector for initial code can not receive more information, from the coded data port or do not have more from MPI that odd encoder data (or other token) are accepted. This will (state of coded_accept and register coded_busy be indicated by signal.

By using coded_accept and/or coded_busy, the user is guaranteed not have coded message and is lost. Yet as having in this area the people of skill will recognize, if spatial decoder can not be accepted data, system must be able to cushion the newly arrived coded data arrival of new data (or stop). A.10.5 coded data clock

Corresponding to the present invention, other function in coded data port, input circuit and the spatial decoder is controlled by coded_clock. Further, this clock can be asynchronous with main decoder _ clock. Data transmit by with chip on decoder_clock synchronous. A.11 detector for initial code initial code A.11.1

Known such as people in this area, but MPEG and H.261 the coding the video string include the discrimination bit model that is called as initial code. The mark code plays similar functions in JPEG. The live part of initial/mark code recognition coding serial data grammer. The analysis of detector for initial code is finished initial/mark code is the first step in the coded data syntactic analysis. Detector for initial code is first piece of following on the spatial decoder in the input circuit back.

Initial/mark code model is designed to and can be identified and the whole bit string that need not to decode. Like this, they can be used to help to find wrong and the starting decoder corresponding to the present invention. Detector for initial code provides facility to detect wrong in encoded data structure and to assist the starting of decoder. A.11.2 detector for initial code register

As previously mentioned, many detector for initial code registers are being used regularly by detector for initial code. Therefore, if detector for initial code just in deal with data, these registers of access will be insecure. The user has a responsibility for guaranteeing that detector for initial code is stopped before its register of access.

Thereby register start_code_detector_access is used to stop detector for initial code and allows its register of access. Have no progeny in it produces one, the initial code register will stop.

Look for and abandon all data patterns at initial code and when can be initiated in addition further restriction. A.11.8 and A.11.5.1 these describing to some extent.

Table A .11.1 detector for initial code register

Register name	Size/direction	Reset mode	Explanation
				start_code _detector_ access	1    rw	0	Write 1 and stop to allow its register of access to this register request detector for initial code. The user need to the value of waiting until 1 from then on register read, stopped and can having carried out access with the expression operation
illegal_length _count_event
		1    rw	0	One counting step illegal event will occur when writing the coding jpeg data, the found value of length gauge digital section is less than 2, this should only appear in the jpeg data and to produce error result such as mask register is set to 1, and interruption can be produced, and the initial code decoder will quit work. If wrong suppressed (mask register is set to 0) follows vicious behavior is uncertain, see A.11.4.1
illegal_length _count_mask					1    rw	0
	ipeg_overlapp- ing_start_ event	1    rw	0				Be JPEG such as coding standard, in to the locking of mark code, sequence 0 * FF 0 * FF is found, and then this event occurs. This sequence is effective padding sequence. Be to be arranged to 1 such as mask register, then interrupt and to be produced, and the initial code decoder will quit work, see A.11.4.2
ipeg_overlapp- ing_start_mask				1    rw	0
	overlapping _start_event	1    rw	0			Be MPEG or H.261 such as coding standard, in to the initial code locking, an overlapping initial code is found, and then this event occurs. Be to be set to 1 interruption can be produced such as mask register, and the initial code decoder will quit work. See A.11.4.2
overlapping _start_mask				1    rw	0

Table A .11.1 detector for initial code register (continuing)

Register name	Size/direction	Reset mode	Explanation
				unrecognised_ start_event
	1    rw	0	If a unrecognizable initial code is run into, this event will occur. Can be produced when mask register is set as 1 interruption, and the initial code decoder will quit work. When the initial code decoder stopped, the initial code value of reading from bit string can obtain in the start_value register. See that A.11.4.3 when normal operating, what comprise among the start_value is initial/up-to-date decode value of mark code. Under H.261 operating, only 4 of start_ value least significant bits are used 4 high significance bits and are 0.
				unrecognised_ start_mask	1    rw	0
start_value	8    ro	Uncertain
				stop_after_ picture_event	1    rw	0	Be set to 1 such as the stop_after_picture register, then " stopping behind the image " event will occur in visual tail and can produce by being set as 1 interruption such as mask register after the initial code decoder, and the initial code decoder will quit work, see A.11.5.1 after visual tail has been detected, stop _ after_picture is by clear 0, therefore need be by directly clear 0.
stop_after_ picture_mask	1    rw	0
			stop_after_ picture	1    rw	0

Table A .11.1 detector for initial code register (continuing)

Register name	Size/direction	Reset mode	Explanation
				non_aligned_ start_event
	1    rw	0	When ignore_non_aligned is set to 1, there is not the initial code of byte location to be left in the basket (treating as normal data) when ignore_non_aligned is set to 0, H.261 will be detected with the MPEG initial code. No matter the byte location also is non-byte location, initiation event all will occur. Be set to 1 such as mask register, then event will cause interruption, and the initial code decoder will stop, if see that A.11.6 coding standard is configured to JPEG, ignore_non_aligned is left in the basket, and the initiation event of non-location will never occur
				non_aligned_ start_mask	1    rw	0
ignore_non_ aligned	1    rw	0
				discard_ extension_ data	1    rw	1	When this register is set to 1, expansion or the user data that can not be decoded by spatial decoder are abandoned by the initial code decoder, see A.11.3.3
discard_ user_data	1    rw	1
			discard_ all_data	1    rw	0	When being set to 1, all data and token are abandoned by the initial code decoder. This situation continue up to that the FLUSH token is provided or register by directly clear 0. The FLUSH token of this register of resetting is left in the basket, and is not exported by the initial code decoder, sees A.11.5.1
insert_ sequence _start	1    rw	1					See A.11.7

Table A .11.1 detector for initial code register (continuing)

Register name	Size/direction	Reset mode	Explanation
				start_ code_ search	3    rw	5	When this register is set to 0, the initial code decoder normally operates, and when being set to high value, the initial code decoder is ignored data, unless the initial code of specified type is detected. When the initial code of appointment is detected, this register is set to 0, and transfers normal operating to. See A.11.3
start_code_ detector_ coding_ standard	2    rw	0	The coding standard that this register configuration initial code decoder uses. Register can directly load or make the CODING_STANDARD token. Whenever initial code decoder generation CODING_ STANDARD token (seeing A.11.7.4), it carries the configuration of present encoding standard. This token will dispose the coding standard that all other parts of decoding chip collection use. See A.21.1 and A.11.7
				picture_ number	4    rw	0	Be produced whenever the initial code decoder detects visual initial code (perhaps H.261 or the equivalent among a JPEG) PICTURE_START token in data flow, it is with the picture_number currency. This register is rised in value subsequently.
length count	16    ro	0	This register comprises the currency of JPEG length counting, and register is modified under the coded data clock control, and can only when the initial code decoder stops, reading by MPI.

A.11.3 initial code is to the transformation of token

In normal operating, the function of detector for initial code is to identify initial code at serial data, then they is transformed into suitable initial code token. In the simplest situation, data offer detector for initial code with single long DATA token form. The output of detector for initial code is that it interleaves the shorter DATA token with the initial code token in a large number.

Corresponding to the present invention, alternative other method is that the input data of detector for initial code can be divided into a large amount of short DATA tokens. How being divided into the DATA token without limits for coded data, except each DATA token must comprise 8 * n position, is an integer at this n.

Other token can be provided directly to the input of detector for initial code. In this case, token does not pass other stage that detector for initial code arrives spatial decoder with not doing any processing. These tokens can only be inserted near locating before an initial code position in the coded data. A.11.3.1 initial code form

Detector for initial code among the present invention can be identified three kinds of different initial code forms. This is to be configured by register start_code_detector_coding_standard.

Table A .11.3 initial code form

Coding standard	Initial code type (hexadecimal)	Initial code value size
			MPEG
	0×00 0×00 0×01(value)	8bit
			JPEG
	0×FF(value)	8bit
			H.261	0×00     0×01(value)	4bit

A.11.3.2 the equivalent of initial code token

After detecting an initial code, the value that detector for initial code research is associated with initial code, and produce a suitable token. Usually, token is to copy the suitable MPEG syntax to be named, yet the people with general skill in this area will recognize that token can defer to other name form. Current selected coding standard disposed initial code value and produce relation between the token. This relation is as shown in Table A .11.4.

Table A .11.4 is from the token of initial code value

The initial code token that produces	Initial code value
					MPEG [hexadecimal)	H251 (hexadecimal)	JPEG (hexadecimal)	JPEG (name)
	PICTURE_START	0×00	0×0C	0×OA					SOS
SLICE_START
	*	0×0110  0×AF	0×0110  0×CC	0×D010  0×D7	RST	010   RST 7
SEQUENCE_START							0×B3		0×De	SOI
	SEQUENCE_END
		0×B7		0×D9	SOI
	GROUP_START
		0×Ba		0×C0	SOF	03
	USER_DATA						0×B2		0×E010  0×EF	APP	040   APP
0×FE		COM
			EXTENSION_DATA
	0×B5			0×C3	JPG
							0×F010  0×FD	JPG	010   JPG D
				0×C210  0×B	RFS
							0×C110  0×C3	SOF 1b   SOF 11
				0×CC	DAC
			DHT_MARKER
				0×C4	DHT
			DNL_MARKER
				0×DD	DNL
			DQT_MARKER
				0×DB	DOT
			DRI_MARKER
				0×DD	DRI

A, token comprise the data segment of a 8bit, and the value that it is loaded is the value that is determined by initial code. B, point out that baseline DCT coded data begins. A.11.3.3 the extension feature of coding standard

Coding standard provides a large amount of gimmicks so that data are embedded in the serial data, and the current standard that is not encoded of the use of serial data defines. This can be " user data " for application that extra facility is provided for a particular manufacturer. As selection, it is " growth data " also. Coding standard authorities have kept in the future and are using growth data to increase the right of feature as coding standard.

The skill of two kinds of uniquenesses is used, JPEG priority user piece and the growth data with mark code. Yet, H.261 inserted " extraneous information " by an extraneous information position indication in the coded data. MPEG can use this two kinds of skill and technique.

Can be detected by detector for initial code corresponding to MPEG/JPEG user's piece of the present invention and the growth data in initial/mark code back. H.261/MPEG " extraneous information " detected by Huffman decoder of the present invention. Referring to A.14.7 " reception of extraneous information ".

Register discard_extension_data and di scard_user_data allow detector for initial code to be configured to abandon user data and growth data. If these data are not dropped at detector for initial code, it can be accessed when arriving video separator. Referring to A.14.6. " reception of user and growth data ".

Spatial decoder of the present invention is supported the baseline characteristic of JPEG. The non-baseline characteristic of JPEG is considered as growth data by spatial decoder. Therefore, all JPEG mark codes before non-baseline jpeg data all are used as growth data and treat. A.11.3.4 JPEG table definition

JPEG supports the long-range Huffman that packs into and quantization table. In jpeg data, belonging to before the definition of these tables is mark code DNL and DQT. When these mark codes were detected, detector for initial code produced token DHT_MARKER and DQT_MARKER. These tokens comprise the coded data (using the form that illustrates among the JPEG) of explanation Huffman or quantization table to the DATA token of video separator indication back. A.11.4 error detection

Detector for initial code can detect some mistake in the coded data, and provides some facility so that decoder recovers (seeing A.11.8 " initial code is looked for ") after a mistake is detected. A.11.4.1 illegal JPEG length is counted

Most JPEG mark codes have 16 bit length count areas that interrelate with it. The indication of this field have how many data therewith the mark code be associated. 0 or 1 length counting is non-method. Illegal length only should occur after an error in data, and in the present invention, if illegal_length_count_mask is set to 1, this will produce an interruption.

Owing to seek the difficulty of initial code in jpeg data, recovering in the mistake from jpeg data also to need other data that indicate application (referring to A.11.8.1). A.11.4.2 overlapping initial/the mark code

In the present invention, overlapping initial code should only occur in the error in data back. The overlapping initial code of MPEG, byte location has illustrated in Figure 64. At this, detector for initial code is at first seen a kind of pattern that seems a similar visual initial code. Then, detector for initial code see this visual initial code by with one group initial overlapping. Correspondingly, detector for initial code produces an overlapping initiation event. And then detector for initial code will produce one and interrupt and stop, if overlapping_start_mask is set to 1.

Which is distinguished in two initial codes is correct and which causes it is very important by an error in data. Yet, abandon first initial code corresponding to detector for initial code of the present invention, and will be second initial code of the serviced rear continuation decoding of overlapping initial code event, " it is correct resembling it ". If there is a series of overlapping initial code, detector for initial code will abandon (for each overlapping initial code produces an event) all except last.

Similarly mistake also is possible (H.261 or possible MPEG) in non-byte navigation system. In this case, the ignore_non_aligned state also must be considered. Figure 65 has described an example, and wherein, the first initial code that finds is byte location, but it and a non-location initial code are overlapping. If ignore_non_aligned is set to 1, second overlapping initial code will be treated as data by detector for initial code so, and thereby the initial code event that can not overlap. This has hidden a kind of possible data communication error. If ignore _ non_aligned is set to 0, detector for initial code will be seen the initial code of second non-location and will see it and the first initial code overlaid. A.11.4.3 unrecognizable initial code

When a unrecognizable initial code is detected, detector for initial code can produce an interruption, if (unrecognized_start_mask=1). The value that causes the initial code of this interruption can be read from register start_value.

Initial code value 0 * B4 (sequence errors) is used to indicate a passage or media mistake in the mpeg decoder system. For example, this initial code can be by in the ECC circuit data inserting, if it detects its mistake that can not correct. A.11.4.4 the order that produces of event

In the present invention, some coded data model (may indicate an error situation) will cause not only that an above-mentioned error situation occurred in the space in a blink. Thereby detector for initial code to the order that coded data detects error situation is:

1) initial code of non-location

2) overlapping initial code

3) unrecognizable initial code

Like this, if the initial code of a non-location initial code and other back is overlapping, the first event that produces is located right and wrong that initial code interrelates. After this event is serviced, the operation of detector for initial code will continue, and detect overlapping initial code after the short time.

Detector for initial code only just attempts to identify initial code after the detection of all non-location and overlapping initial code is finished. A.11.5 decoder starts and closes

New task of a beginning that detector for initial code provides facility so that current decoding task is finished neatly.

The use of these technology has some restrictions, because the JPEG encoded video can comprise the value (seeing A.11.8.1) of simulation mark code as data fragments. A.11.5.1 clean the end decoded

Detector for initial code can be configured to produce an interruption in case the data of current image are finished, and quits work. This by arrange stop_after_picture be 1 and stop_after_ picture_mask 1 reach.

In case the ending of an images is by detector for initial code, a FLUSH token namely is produced (seeing A.11.7.2), and an interruption is produced, and detector for initial code stops. Notice that the image that just has been done will be decoded with normal mode. Yet, in some applications, be suitable for and detect the FLUSH that arrives the output of decoder chip collection, because it will indicate the end of current video sequence. For example, demonstration will be freezed the output in final image.

After detector for initial code stopped, the data that may have from " always " video sequence " fell into " in the buffer of the user's realization between media and decoding chip. Register discard_all_data is set will be made spatial decoder consumption and abandon this data. This will proceed to, and a FLUSH token arrives detector for initial code or discard_all_data is reset by MPU interface.

After " always " sequence has abandoned any data, decoder now has been ready to start working for a new sequence. A.11.5.2 the initial pattern that entirely abandons when

Entirely abandoning pattern will will begin in a minute after being written into the discard_all_data register at one 1. If this carries out during deal with data actively at detector for initial code, the result is unpredictable so.

The pattern that entirely abandons can at any one detector for initial code event (non-location initiation event etc.), produce an interruption and caused safely. A.11.5.3 initial one new sequence

Where be not positioned at certain coded data, the mechanism that can use initial code to look for so if also know the initial of a new encoded video sequence. This method is discarded in the initial any unwanted data before of sequence. A.11.5.4 jump between sequence

This part has been described the application of some above-mentioned technology, and purpose is to "jump" to another part from the part of encoded video sequence. In this example, filing system only allows access data " piece ". This block structure can get from sector-size or error correction system block size of a dish. Like this, inlet point and the exit point position in coding video frequency data can be irrelevant with the filing system block structure.

Stop_after_picture and discard_all_data mechanism allow to be dropped from the data that do not need of presbyopia frequency sequence. Insert the FLUSH token discard_all_data pattern that can reset at place, the end of a upper filing system data block. The initial code pattern of looking for can be used so, is in suitable inlet point any data before in next data block to abandon. A.11.6 byte is located

As ripe well known in the art, different encoding schemes is positioned with for the byte of initial in the serial data/mark code diversely to be treated.

For example, H.261 communication is regarded as bit string, like this, just do not have the concept of initial code byte location. Be 0 by ignore_non_aligned is set, detector for initial code can detect has the initial code that arrange any position. Be 0 by non_aligned_start_ mask is set. The non-location of initial code is interrupted suppressed.

Yet by contrast, JPEG locates guaranteed computer environment design for a kind of byte. Therefore, the mark code should be only detected when byte is located.

When coding standard is configured to JPEG, register ignore_non_aligned is left in the basket, and non-location initiation event will never be produced. Yet suggestion arranges ignore_non_ aligned=1 and non_aligned_start_mask=0 and guarantees compatibility with future products.

On the other hand, MPEG designs for the needs that satisfy simultaneously communication (bit string) and computer (byte-oriented) system. Initial code in the mpeg data generally should be by the byte normal alignment. Yet standard is to look for (unless it is exactly initial code, not the having other MPEG bit model with any location will look like an initial code) designed for the Bits Serial of initial code. Like this, a mpeg decoder can be designed to and will be tolerated in losing that byte is located in the serial data communication.

If a non-location initial code is found, it will indicate a garble that occurred in the past usually. If mistake is " biased moving " in a bit-serial communication system, includes so these wrong data and be transmitted to decoder. This mistake might cause other mistake in the decoder. Yet the new data that arrives detector for initial code can continue decoded after the losing of this byte location.

By ignore_non_aligned=0 and non_aligned_start_mark=1 are set, if a non-location initial code is detected, an interruption can be produced. Response will depend on application. The initial code of all back will be non-location (until the byte location is resumed). Correspondingly, after the byte location has been lost non_aligned_start-mask=0 being set perhaps is appropriate.

The configuration of Table A .11.5 byte location

	MPEG	JPEG	H.261
				ignore_non_aligned	0	1	0
non_aligned_start_mask	1	0	0

A.11.7 automatically produce token

In the present invention, great majority have directly been reflected the syntactic element (syntactic elements) of multiple image and video encoding standard by the token of detector for initial code output. Except these " natural " tokens, some useful " invention " token is produced. For example these proprietary tokens are PICTURE_END and CODING_STANDARD. Token also is introduced into to eliminate some the grammer difference between the coding standard, and goes " tidying up " situation in situation about making mistake.

It is (the seeing Figure 61, " detector for initial code ") that is done after the sequence analysis of coded data that this automatic token produces. Therefore, for directly offering the token of spatial decoder input by detector for initial code and having been detected the token that initial code produces by detector for initial code in coded data, the reflection of system is identical. A.11.7.1 indicate the end of an image

Usually, coding standard indicates the end of an image ambiguously. Yet the detector for initial code among the present invention produces a PICTURE_END token when being moved to end detecting the current image of indication.

The token that PICTURE_END is produced is: SEQUENCE_START, GROUP_ START, PICTURE_START, SEQUENCE_END and FLUSH. Stopping after A.11.7.2 image finishes to select

If register stop_after_picture set, so detector for initial code will a PICTURE_END token by after stop. Then, FLUSH token be inserted into after the PICTURE_END with the end of " promotions " coded data by decoder with make system reset. (seeing A.11.5.1). A.11.7.3 for H.261 insetion sequence is initial

H.261 do not possess one and be equivalent to the initial syntactic element of sequence (seeing Table A.11.4). If register insert_sequence_start is set up, detector for initial code will guarantee that a SEQUENCE_START token was arranged before next PICTURE_START so, that is to say, if detector for initial code was not seen a SEQUENCE_START before a PICTURE_START, will insert one. If had a SEQUENCE_START to exist, will can not introduce again.

This function should not used MPEG and JPEG. A.11.7.4 for each sequence coding standard is set

All SEQUENCE_START tokens that leave detector for initial code always have a CODING_STANDARD token before. This token is loaded the present encoding standard of detector for initial code. It is provided with coding standard for each new video sequences to whole decoder chip collection. A.11.8 initial code is looked for

Can be used in an encoded data stream, look for the initial code of a particular type according to detector for initial code of the present invention. This is so that decoder restarts decoding (abandoning any data of its front after) from a specified level in the system of some coded data. Its application comprises:

Initial code is looked for and will be will begin in a minute after a nonzero value is written into the start_code_search register. If this is to finish when detector for initial code enlivens deal with data, then its result is with unpredictable. Therefore, before initiation one initial code was looked for, detector for initial code should be stopped, and do not have data processed this moment. If any detector for initial code event (non-location initiation event etc.) has just produced an interruption, detector for initial code will always be in this state. A.11.8.1 the restriction of using initial code to look for to JPEG

Most of JPEG mark codes have 16 bit length count areas that interrelate with it. The length of the data segmentation that this field indication and mark code interrelate. This segmentation can comprise the value of imitating the mark code. Normally in service, detector for initial code is not sought initial code in these data sectionals.

In the arbitrary access to some jpeg encoded data in such segmentation " manor (lands) ", the mechanism that initial code is looked for can not reliably be used. Usually, to come be arbitrary access identification inlet point to the video of the JPEG coding external information that will need to add. A.12 the A.12.1 general introduction of decoder starting is controlled in the decoder starting

In a decoder, video shows a bit of time that usually is delayed after coded data obtains first. In the middle of this postpones, accumulate in the buffer of coded data in decoder. This buffer pre-filled guaranteed that buffer never can be empty in decoding, thereby and this guaranteed the decoder new image of in the normal space, can decoding.

Usually, a correct initial decoder needs two kinds of gimmicks. The first, must there be a kind of means to measure existing how many data and be provided for decoder. The second, must there be a kind of gimmick to prevent the demonstration of a new video string. Spatial decoder among the present invention provides a digit counter near its input, have how many data to arrive with measurement, carries near its output

After jumping into an encoded data files, start a decoder (for example, arbitrary access) at a unknown position.

In data, look for a known point to help the recovery behind place's error in data.

For example, Table A .11.6 is shown as the difference configuration of start_code_search and the MPEG initial code looked for. Equivalence H.261 with JPEG initial/the mark code can see in Table A .11.4.

Table A .11.6 initial code is looked for pattern

start_code_search	For ... and the initial code of seeking
		0 a	Normal operating
1	Keep (will show as and abandon data)
		2
3			Sequence is initial
	start_code_search	For ... and the initial code of seeking
4			Group or sequence are initial
	5 b	Image, group or sequence are initial
6			Sheet, image, group or sequence are initial
	7	Next initial or mark code

A. look in the pattern at this, the FLUSH token is positioned at detector for initial code.

B. this is the default mode after resetting.

When a nonzero value is written into the start_code_search register, detector for initial code abandons all arrival data with beginning, until the initial code of appointment is found. Then the start_code_search register will be reset to 0 and normal operation will continue. Supplied initial with the new video string that prevents from being output of an out gate.

The control of these gimmicks has three kinds of levels of complexity

Out gate is always opened

Basic controlling

Senior control

If out gate always leaves, image outpuT will begin after coded data begins to arrive decoder as early as possible. This decoding or demonstration for still image is just suited by the situation that certain other gimmick postpones.

Difference between the senior control of fundamental sum depends on any moment decoder buffer can hold how many short-sighted frequency strings. Basic controlling is enough in great majority are used. Yet senior control makes user software can help the starting of the several very short video strings of decoder management. A.12.2 MPEG video buffer verifier

MPEG has described a kind of " video buffer verifier " that uses for constant data rate system (VBV). (VBV) information of use makes decoder pre-filled its buffer before it begins to show image. Moreover this pre-filled buffer that has guaranteed decoder always can be empty during decoding.

Generally speaking, each MPEG image carries a vbv_delay parameter. This parameter had been specified before the first images is decoded, the data stuffing that how long should be encoded of the coded buffer of " desirable decoder ". After the start delay of observing the first images, the requirement of all back images all will be satisfied automatically.

Thereby MPEG is defined as delay with start request. Yet in a constant bit rate system, one postpones to be converted at an easy rate the position counting. The basis that the starting of space decoder control is moved among the present invention that Here it is. A.12.3 the definition of stream

In this used, term " stream (stream) " was used to avoid to obscure with MPEG term " sequence (sequence) ", and therefore, stream represents multitude of video data of using institute " interested ". Thereby a stream can be many MPEG sequences, perhaps can be a single image.

Decoder starting facility described in this chapter is relevant with the VBV requirement of the first images in the satisfied stream, and the requirement of back image is satisfied automatically in this stream. A.12.4 initial control register

Table A .12.1 decoder plays dynamic register file

Register name	Size/direction	Reset mode	Explanation
				startup_ acce CED_BS- ACCESS	1   rw	0	This register is write 1 require digit counter and door unlatching logic to stop, to allow their configuration register of access
bit_count CED_BS_ COUNT	8   rw	0	When coded data is left detector for initial code, this digit counter increment, once increasing the desired figure place of bit_ count approximately is 2(bit_count_prescale+1)* 512 at the FLUSH token by behind the digit counter, digit counter begins counting, behind the counting goal satisfaction in place, it just by clear 0, then stops increment.
				bit_count _prescale CED_BS_ PRESCALE	3   rw	0
bit_count _target CED_BS _TARGET	8   rw	Indefinite					The desired value of this register pointer counting occurs when following condition becomes true time goal satisfaction event: bit_count 〉=bit_count_ target
			target_ met_event BS_TARGET _MET_ EVENT	1   rw	0	When the counting goal satisfaction of position, this event occurs, and is set to 1 such as mask register, then can produce interruption. Yet digit counter will not stop deal with data. When digit counter increase counting arrives its desired value, event will occur, if the desired value that is written into is less than or equal to the currency of digit counter, event also will occur. Write 0 to bit_count_target and will always satisfy the event of target.
target_ met_mask	1   rw	0

Table A .12.1 decoder plays dynamic register file (continuing)

Register name	Size/direction	Reset mode	Explanation
				counter_ flushed_ event BS_FLUSH _EVENT	1   rw	0	When the FLUSH token by a position counting circuit, this event will occur, can be produced if mask register is set to 1, one interruption, and digit counter will stop.
counter_ flushed_ mask	1   rw	0
			counter_ flushed_ too_early _event BS_FLUSH_ BEFORE_ TARGET_ MET_EVENT	1   rw	0	By the digit counter circuit, and the position counting is also less than the foot-eye value such as the FLUSH token, and this event will occur. Be set to 1 such as mask register, interruption can be produced, and digit counter will stop to stop. See A.12.10
counter flushed_ too_early _mask	1   rw	0
			offchip_ queue CEO_BS_ OUEUE	1   rw	0		This register to 1 is set, and configuration door is opened a logic and is gone for and ask the microprocessor support to be set to 0 when this register, and output gate logic will be controlled the out gate operation automatically. See A.12.6 and A.12.7

Table A .12.1 decoder plays dynamic register file (continuing)

Register name	Size/direction	Reset mode	Explanation
				enable_ stream CED_BS_ ENABLE_ NXT_STM	1    rw	0	Formation is used outside chip, after the ending of stream is passed through it, writes the behavior of enable_staeam control out gate. 1 of this register allows out gate to open. When accept_enable interruption generation, this register will be reset.
accept_ enable _event BS_STREAM _ENO_EVENT	1    rw	0	This event shows the FLUSH token by out gate (causing it to close), and once has an enable signal to allow this door to open. If mask register is set to 1, interruption can produce and register enable_stream will be reset. See A.12.7.1
				accept_ enable _mask	1    rw	0

A.12.5 the out gate of often opening

Out gate can be set to be held open. Decoded or in the time can obtaining some other mechanism and come the starting of managing video decoder, this configuration suits at still image.

Needing after resetting following configuration (by to startup_access) to write 1 has obtained starting the access of control logic):

Offchip_queue=1 is set

Enable_stream=1 is set

Guarantee that all decoder start event mask registers are set to 0 and make them can not interrupt (this is the default setting after resetting).

(seeing A.12.7.1 the explanation to why keeping like this out gate to open). A.12.6 basic operation

In the present invention, the basic controlling of start-up logic is enough for most of MPEG Video Applications. In this mode, digit counter is directly communicated by letter with out gate. When the ending of a video flowing was passed through and be indicated by a FLUSH token, out gate was with autoshutdown. Goalkeeper keeps closing, until when a stream had reached its start bit counting, one allowed signal to be provided by digit counter.

After resetting, need following configuration (by write 1 access that has obtained initial control logic to startup_access):

For the desired extent of coded data rate roughly arranges bit_count_prescale.

Counter_flushed_too_early_mask=1 is set can be detected this error condition.

Need two kinds of interrupt service routines:

The video distributor service thinks that the first images in each new stream obtains the value that vbv postpones.

Counter is removed (flush) service too early to respond this state.

Video distributor (being also referred to as video parser) can produce an interruption when it is a new video stream (the namely image of first width of cloth arrival video distributor after FLUSH) decoding vbv_ delay. Interrupt Service Routine should be bit_count_target and calculates an appropriate value and write it. When digit counter reached this target, it enabled inserting one in one between digit counter and the out gate short team. When out gate was opened, it was removed one and enables from this team. A.12.6.1 a new stream will begin in a minute after another stream finishes

The mpeg stream that for example, will finish is called as A and the mpeg stream that will begin is called as B. A FLUSH token should be inserted into after the ending of A. It promote its coded data last by decoder, and the new stream of a plurality of parts expectations one of announcement decoder.

Usually, when A has satisfied its starting conditions, digit counter will be reset to zero. After FLUSH, digit counter will begin to count the position among the stream B. Decoded when video distributor and to have flow automatically behind the vbv_delay of the first images among the B, an interruption will be produced, so that digit counter is configured.

When the FLUSH of the ending that has indicated stream A passed through out gate, goalkeeper closed. Goalkeeper closes always until B meets its starting conditions. According to a lot of parameters, such as: start delay and the buffer depth of stream B, might will satisfy its starting conditions by B when out gate cuts out. In the case, in team, will have one to enable waiting for, and out gate will be opened immediately. Otherwise stream B must wait for until it has satisfied its starting conditions. A.12.6.2 some short streams is continuous

The capacity of the team between digit counter and out gate is enough to make 3 minutes other video flowings to reach their starting conditions and waiting for that the stream of a front finishes decoded. In the present invention, only have when some very short stream outside decoded or chip buffer with just compare at decoded pixel format just can this thing happens when being very large.

In Figure 69, stream A just opens at decoded and out gate. Stream B and C have satisfied their starting conditions and have been contained in the buffer of being managed by spatial decoder by whole. Stream D still arrives the input of spatial decoder.

Stream B and C enable in team. Therefore, B can begin immediately after stream A is done. Similarly, C can be immediately following behind B.

If A is still by out gate when D satisfies it and plays moving-target, one enables to be added in the formation to fill formation. If (namely, A is still passing through out gate) also do not enable to be removed from formation when the tail end of D passes through digit counter, will there be new stream to begin to pass through digit counter. Therefore, coded data will input stop until A finishes and when out gate be opened so that B by the time one enable to be removed from formation. A.12.7 higher level operation

Corresponding to the present invention, the senior control of start-up logic can make user software can infinite expanding the length that enables formation described in " basic operation " A.12.6. Other control of this level only must be held a series of ratios at Video Decoder and A.12.6.2 just need during the longer short video flowing of the stream of description in " some short streams continuously ".

Except the required configuration of system's basic operation, be required after following being configured in resets (by write 1 access that has obtained initial control logic to the start_up access:

Offchip_queue=1 is set

Accept_enable_mask=1 is set, to enable to allow to send interruption when being removed by formation at one.

Target_met_mask=1 is set, when the position of stream counting target is satisfied, to allow to send interruption.

Also need two additional Interrupt Service Routines:

Acceptance enables to interrupt

Goal satisfaction interrupts

When a goal satisfaction interrupted occurring, service routine should enable one of formation increase and enable outside its chip. A.12.7.1 out gate logic behavior

Write one 1 and namely packed into one to a short formation to the enable_stream register and enable.

When a FLUSH (indicating the end of stream) by out gate, goalkeeper closes. Enable if can obtain one at the end of formation, goalkeeper opens and produces an accept_ enable_event. If accept_enable_mask is set to that 1, one interruption can be produced and one enable to be removed by the end from formation (register enable_stream by position).

Yet, if accept_enable_mask is set to zero, does not interrupt after accept_enable_event, being produced, and enable not removed by the end from formation. This skill can be used for as A.12.5 as described in keep out gate unlatching. A.12.8 count the position

After a FLUSH token passed through digit counter, it began counting. The end of this FLUSH token indication current video stream. In this, digit counter continues counting until it satisfies the position counting target that is arranged in the bit_count_target register. Then a goal satisfaction event is produced, and digit counter is reset to 0 and wait for next FLUSH token.

Digit counter also will stop to increase when it reaches its maximum count (255). A.12.9 in advance scale (prescale) is counted in the position

In the present invention, 2^{(bit_count_prescale＋1)}* 512 are required to increase digit counter No. one time. In addition, bit_count_prescale is 3 bit registers that can get value between 0 to 7.

Table A .12.2 digit counter examples of ranges

n	Range(bits)	Resolution(bits)
			0	0 to 262144	1024
1	0 to 524288	2048
			7	0 to 31457280	122880

The position counting is roughly, because some element of video flowing by token (such as initial code), therefore comprises non-data token. A.12.10 (flushed) counter that is eliminated too early

If a FLUSH token arrived digit counter before reaching position counting target, one can cause an event of interrupting to be produced (if counter_flushed_too_ is early_mask=1). If interrupt being produced, the digit counter circuit will stop so, to prevent further data input. To be responsible for judging after this event occurs when open out gate by user software. Out gate can be written as 0 and is unlocked by the position being counted target. Only have when attempting to decode the video flowing that only continues several images and just these situations should occur. A.13 buffer management

Two logical data buffers of spatial decoder management: coded data buffer (CDB) and token buffer (TB).

CDB cushions the coded data between the input of detector for initial code and Huffman decoder. So just the coding video frequency data for low data rate provides buffering. Data between the output of TB buffering Huffman decoder and the input of space video decoding circuit (countercurrent fashion device, quantizer and DCT). This second logic gate buffer makes the processing time comprise an expansion, processes the image with delta data amount to adapt to.

These two kinds of buffers physically all are contained in the outer single DRAM array of chip. The address of these buffers is produced by buffer-manager. A.13.1 the register of buffer-manager

The spatial decoder buffer manager for use plans to be configured immediately after device reset. In normal operating, do not need to dispose buffer-manager.

Resetting remove from spatial decoder after, it is to be configured that buffer-manager is stopped (its access function resister buffer_manager_access is set to 1 simultaneously) etc. After register is set to, buffer_manager_access can be set to 0 and the decoding can begin.

When buffer-manager in when operation, the most of registers that use in the buffer-manager can not be accessed reliably. Before the register of any buffer-manager was accessed, buffer_manager_access must be set to 1. This is so that in accordance with waiting for that agreement is very important, until can be from buffer_manager_access readout 1. Obtain and break away to access institute's time spent, at these registers of inquiry, resemble cdb_full and cdb_empty, should be considered during with the look aside buffer situation.

Table A .13.1 buffer manager for use register (continuing)

Register name	Size/direction	Reset mode	Explanation
				buffer_ manger_ access	1    rw	1	This access bit stops the operation of buffer-manager, so that each register of manager can be accessed reliably, see A.6.4.1 and note: this access function resister is unusual, default setting after it resets is 1, the posterior bumper manager that namely resets stops, and waits for and by MPI it being disposed.
buffer_ manger_ keyhole_ address	6    rw	Indefinite	Keyhole access expanded address space, this space are that the buffer manager for use register shown in following uses and sees A.6.4.3 relevant more information by the keyhole access register.
				buffer_ manager_ keyhole_ data	8    rw	Indefinite
buffer_
		18    rw	Indefinite	Specify the whole size that is connected to the DRAM array on the spatial decoder. All buffer addresses calculated by delivery by this buffer size thus its DRAM in overlapping circulation.

Table A .13.1 buffer manager for use register (continuing)

Register name	Size/to	Reset mode	Explanation
				cdb_base
	18    rw	Indefinite	These registers point to the base address of coded data (cdb) and token (tb) buffer.
				tb_base
cdb_length					18    rw	Indefinite	These registers point to the length (i.e. size) of coded data (cdb) and token (tb) buffer.
	tb_length
cdb_read		18 read	Indefinite	These register holds point out with respect to the side-play amount of snubber base location where next data is from reading.
	tb_read
cdb_number
		18 is read-only	Indefinite	These registers show currently have how many data to be retained in the buffer.
tb_number
	cdb_full
		1 is read-only	Indefinite	If coded data (cdb) or token (tb) buffer full, these registers will be set to 1.
	tb_full
cdb_empty
		1 is read-only	Indefinite	If coded data (cdb) or token (tb) buffer-empty, these registers will be set to 1.
tb_empty

A.13.1.1 buffer-manager pointer value

Say that typically data are transmitted between the DRAM outside spatial decoder and chip with 64 byte burst modes (using the fast page mode of DRAM). All buffer pointer and length register all relate to these 64 bytes (512 s') data block. Therefore, 18 bit registers of buffer-manager are described the linear address space (namely 128Mb) of a 256K piece.

64 bytes transmit with DRAM interface width (8,16 or 32) irrelevant. A.13.2 the use of the register of buffer-manager

The buffer manager for use of spatial decoder has the register of two kinds of similar buffers of two cover definition. The upper physical limit of buffering limit register (buffer_limit) definition memory space. All addresses are counted as mould take this and are calculated.

Within the restriction of obtainable memory, the scope of each buffer is by two register definitions: snubber base location (cdb_base and tb_base) and buffer length (cdb_ length and tb_length). So far described all registers must be configured before buffer can be used.

The current state of each buffer all can be observed in 4 registers. Buffer read register (cdb_read and tb_read) indication is with respect to a side-play amount of snubber base location, and this volume is moved the next data in address and will be read out. The current data volume that is kept by buffer of number of buffers register (cdb _ number and tb_number) indication. Mode bit cdb _ full, tb_full, cdb_etmpty and tb_empty indication buffer are empty or full.

Described in A.13.1.1, the unit of all registers above-mentioned is 512 bit data block. Correspondingly, the value of reading from cdb_number should be taken advantage of by 512, to obtain the figure place in the coded data buffer. A.13.3 Z-buffer

Do not have still image that " in real time " require use (for example using JPEG) will need to be by the outer buffer of the large chip that buffer-manager is supported. In this case, the DRAM interface can be configured (by writing 1 to the zero_buffers register) ignoring buffer-manager, thereby provides FIFO (first in first out) in the one 128 bit stream sheets for coded data buffer and token buffer.

The Z-buffer selection also can be suitable for the application with low data rate and the operation of little pixel format.

Therefore attention: the zero_buffers register is the part of DRAM interface, should be only be set up during the configuration after the resetting of DRAM interface. A.13.4 buffer operation

Controlled by a Handshake Protocol by the data transmission that buffer carries out. If guaranteed that therefore buffer is full of or full sky does not have the error in data generation yet. If a buffer is filled, attempt so to send the circuit of data to be stopped to buffer, until the space has been arranged in the buffer. If buffer is continuously full, the more multiprocessing stage of buffer " upstream " (" up stream ") * will stop until spatial decoder can not be at its input port receive data. Similarly, if buffer is entirely empty, the circuit of attempting so to remove from buffer data will stop, until data can obtain.

Described in A.13.2, the position of coded data and token buffer and size are specified by snubber base location and length register. The user has a responsibility for disposing these registers and guarantees that two storages between buffer do not conflict in using. A.14 multi-channel video distributor (Demux)

Video distributor perhaps is known as video analyzer (parser), finishes by the initial task of coded data being converted to token of detector for initial code. Four main processing blocks are arranged: analyzer state machine, Huffman decoder (comprising an ITOD), count of macroblocks device and ALU in video distributor.

Analyzer or state machine are observed grammer and other unit of instruction of coding video frequency data. The Huffman decoder becomes integer with different lengths coding (VLC) data transaction. The count of macroblocks device is followed the trail of which part of image just decoded. ALU finishes the mathematical computations that needs. A.14.1 video distributor register

Table A .14.1 top layer video distributor register

Register name	Size/direction	Reset mode	Explanation
				demux_ access CED_H_ CTRL(7)	1    rw	0	This access position stops the operation of video distributor, so that A.6.4.1 its each register is seen by reliably access
huffman_ error_ code CED_H_ CTRL(6：4	3    ro		When video distributor stops, huffman_ _ even interrupts and then producing, and what this 3 bit register retention value is designated as and produces and interrupt, and sees A.14.5.1
				parser_ error_ code CED_H_ DMUX_ERR	8    ro		Produce interrupt requests when video distributor stops to follow parser-event, what these 8 retention values are designated as and produce interruption, see A.14.5.2
demux_ keynole_ address CED_H_ KEYHOLE _ADDR	12    rw	Indefinite	The extended address space of keyhole accessing video distributor. About the more information by the keyhole access register, see A.6.4.3 Table A .14.2, A.14.3 reaching A.14.4 explanation can be through the register of keyhole access.
				demux_ keynole _dadt CED_H_ KEYHOLE	8    rw	Indefinite

Table A .14.1 top layer video distributor register (continuing)

Register name	Size/direction	Reset mode	Explanation
				dummy_last _picture CED_H_ ALU_REGO r_rom_ control r_dummy_ last_frame _bit	1    rw	0	Deposit when this and to be set to 1, video distributor is with regard to generation information, with the base image of " sky " final image as the MPEG sequence. When the time decoding is configured to reorder (seeing that A.18.3.5 image sequence reorders) as automatic image, clear out of temporal decoder in order to make last P or I image, this function is useful. Following situation does not need empty graph to resemble: temporal decoder does not form that other MPEG sequence that reorders will be decoded immediately because this also can dispose final image) the encoder standard is not MPEG
field_ into CED_H_ ALU_REGO r_rom_ control r_field_ into_bit	1    rw	0	When this register puts 1, A.14.7.1 the first byte of any MPEG extra information picture is put in the FIEID_INFO token (sees)
				continue CED_H_ALU REGO r_rom_ control r_continue bit	1    rw	0	Analyse when decoder and to measure when being excessive data, this register allows user software control, and its plans what of additional customer's data of receiving or growth data. (see A.14.6, A.14.7)

Table A .14.1 top layer video distributor register (continuing)

Register name	Size/direction	Reset mode	Explanation
				rom_revision CED_H_ALU_ REG1 r_rom_ revision	8    ro	0	Immediately following after resetting, this register obtains version number's copy of microcode ROM. This register also is used for providing the control software data value of reading from coded data. See that A.14.6 " receiving user and growth data " reaches A.14.7 " reception extraneous information "
huffman_ event	1    rw	0	If find mistake in coded data, the Huffman event is produced, and sees A.14.5. 1 explanation to these events. If mask register puts 1, produce so and interrupt, the multi-channel video distributor will stop. If mask register sets to 0, produce without interrupting, the multi-channel video distributor is attempted to recover from mistake.
				huffman_ mask	1    rw	0
parset_ event	1    rw	0					-Parser event is according to the arrival information request software intervention of the mistake in the coded data or demultiplexer, sees A.14.5.2 the explanation to these events. If mask register is set to 1, produce and interrupt, the multi-channel video distributor stops. If mask register is set to 0, occur without interrupting, the multi-channel video distributor will be attempted to continue.
			parser_ mask	1    rw	0

Table A .14.2 video distributor map architecture register

Register name	Size/direction	Reset mode	Explanation
				component _name_0 component _name_1  component _name_2  component _name_3	8    rw	Indefinite	Keep	8 place values at JPEG duration of work register component_ name_n, (to certain application) represents the important IDn of which kind of chrominance component.
horiz_ pels	16    rw		These registers keep the horizontal and vertical size of the just decoded video take pixel as unit. (seeing A.14.2 joint)
				vert_pels	16    rw	Indefinite
horiz_ macroblocks	16    rw	Indefinite					These registers keep the horizontal and vertical size of the decoded video take macro block as unit. See A.14.2 joint
			vert_ macrobl0cks	16    rw	Indefinite
max_h
		2    rw	Indefinite	These registers keep the wide and high of the macro block that calculates with piece (8 * 8 pixel). The width/that value 0 to 3 expression is 1 to 4. See A.14.2 joint
max_v
		2    rw	Indefinite
max_ component_ id				2    rw	Indefinite	Current	1 to 4 the decoded different video component of value 0 to 3 expression. See A.14.2

Table A .14.2 video distributor map architecture register (continuing)

Register name	Size/direction	Reset mode	Explanation
				Nf
	8     rw	Indefinite	At the JPEG duration of work, this register keeps Parameter N f (in frame image component number)
				blocks h_0 blocks_h_1 blocks_h_2 blocks_h_3	2     rw	Indefinite	To each the register blocks_n_n in 4 chrominance components and plock_v_n keep corresponding to the chrominance component of component IDn vertical and with horizontal direction on macroblock number. See A.14.2
blocks_v_0 blocks_v_1 blocks_v_2 blocks_v_3	2     rw	Indefinite
			tq-0 tq-1 tq_2 tq_3	2     rw	Indefinite	Keep		2 place values by register tg_n, illustrate and when with component IDn decoded data, use which of inverse quantization tables.

A.14.1 register loads and the token generation

A lot of registers in the video distributor have with coding image/video data in the directly related value of the parameter of usually communicating by letter. For example, the horiz_pels register is corresponding to MPEG sequence head information, horizontal_size and JPEG frame head parameter X. These registers are loaded by Video Decoder when suitable coded data is decoded. These registers are also relevant with certain token. For example, register horiz_pels is relevant with token HORIZONTAL_SIZE. (or after this soon) token is produced by Video Decoder when coded data is decoded. Token also can be provided directly to the input of spatial decoder. The value of being carried by token in this case, will dispose associated Video Decoder register.

Table A .14.3 multi-channel video distributor Huffman table register

Register name	Size/dimension	Reset mode	Explanation
				dc_huff_0 dc_huff_1 dc_huff_2 dc_huff_3	2    rw		The value explanation that is kept by register DC_huff_n is when component IDn which of use Huufman decoding table during to the DC coefficient decoding of data. Equally, ac_huff _ used table of n explanation when decoding AC coefficient. Each timebase JPEG needs 2 Huff-man tables, and the tabular value that provides is 0 and 1.
ac_huff_0 ac_huff_1 ac_huff_2 ac_huff_3	2    rw
			dc_bits_ 0[15：0] dc_bits_ 1[15：0]	8    rw		These show each 16 8 place values, and they provide BITS information (seeing the explanation of JPEG Huffman table) to form the part of 2 DC and the explanation of 2 AC Huffman tables. See A.14.3.1.
ac_bits_ 0[15：0] ac_bits_ 1[15：0]	8    rw
			dc_huffval _0[11：0] dc_huffval _1[11：0]	8    rw			These every in tables have 12 12 place values, and they provide HUFFVAL information (seeing the explanation of JPEG Huffman table) to form the part of the explanation of 2 DC Huffman tables. See A.14.3.1.

Table A .14.3 multi-channel video distributor Huffman table register (continuing)

Register name	Size/dimension	Reset mode	Explanation
				ac_huffval _0[161：0] ac_huffval _1[161：0]	8     rw		These every in tables have 162 8 place values, and they provide HUFFVAL information (seeing JPEG Huffman table specification) to form the part of 2 AC Huffman tables. See A.14.3.1.
dc_zssss _0	8     rw		These eight bit registers keep being used as the value of " special circumstances processing ". To accelerate the decoding of some JPEG VLCS commonly used. The size of dc_ssss-DC coefficient is 0. The end of ac_eob-piece. Ac_zrl-16 the zero distance of swimming.
				dc_zssss _1	8     rw
ac_eob_0
		8     rw
ac_eob_1
		8     rw
ac_zrt_0 ac_zrt_1
		8     rw

Other video distributor registers of Table A .14.3

Register name	Size/dimension	Reset mode	Explanation
				buffer _size
	10    rw		When carrying out the mpeg data decoding with the value of the size that represents a required VBV buffer of desirable decoder, this register is loaded. In decoder chip without this value, yet when the configuration codes data buffer size with when determining whether that decoder can be decoded special mpeg data file, the value of this register maintenance may be useful to user software.
				pel_aspect	4    rw		When decoding the MPEG data with the value that represents the pixel length-width ratio, this register is loaded. This value is 4 integers, as the pointer to the fixed table of MPEG. See that mpeg standard is to the definition of this table. In decoder chip, without this value, but show or during output equipment, its retention value may be usefulness to user software when configuration.
bit_rate	18    rw		When decoding the MPEG data with the value of presentation code data transfer rate, this register is loaded. See that mpeg standard is to the definition of this value. Without this value, when the configuration decoder played dynamic register file, its retention value came in handy to user software in decoder chip.
				pic_rate	4    rw		When decoding mpeg data with the value of presentation image rate, this register is loaded. See that mpeg standard is to the definition of this value. In decoder chip, without this value, but show and output when arranging that its retention value comes in handy to user software when configuration.
constrained	1    rw		When the decoding mpeg data when indicating whether that decoded data satisfies the restriction parameter of MPEG, this register is loaded. See that mpeg standard is to the definition of this mark. Without this value, but whether this value determines that to user software the decoder special mpeg data file of decoding may be useful in decoder chip.

Other video distributor table registers (continuing) of Table A .14.4

Table A .14.1 top layer video distributor register (continuing)

Register name	Size/direction	Reset mode	Explanation
				vbv_delay
	16    rw		When representing that minimum start delay value is decoded mpeg data, this register is loaded at the decoding prestart. See for this reason mpeg standard of value definition. Decoder chip is worth without this, but when the configuration decoder played dynamic register file, this value of maintenance may be useful to user software.
				pic_number	8    rw		This register is that image keeps image numbers, and this image is by the current decoding of multi-channel video distributor. When this image arrived here, this number produced by the initial code decoder. See A.11.2 the explanation to image numbers.
dummy_last picture	1    rw	0	These registers also can be seen at top layer. See Table A.14.1
				field_info	1    rw	0
continue	1    rw	0
				rom_revision	8    rw
coding_ standard	2    ro						This register is loaded by the CODING_STANDARD token, with the working method of configuration multi-channel video decomposer. See A.21.1
			restart_ interval	8    rw		Before the decoding beginning, when using the minimum start_up delay value of indication, when jpeg data was decoded, this register was loaded. See that mpeg standard is to the definition of this value.

The interleaving access of Table A .14.5 register pair token

Register	Token	Standard	Note
				component_name_n	COMPONENT_NAME	JPEG	In coded data
MPEG	Need not in standard
		H.261
horiz_pels vert_pels			HORIZONTAL_SIZE VERTICAL_SIZE			MPEG	In coded data
	JPEG
		H.261		Automatically from visual type, obtain
	horiz_macroblocks vert_macroblocks				HORIZONTAL_MBS VERTICAL_MBS	MPEG	Control software obtains in the horizontal and vertical dimension of picture
JPEG
		H.261	Automatically from visual type, obtain
max_h max_v				DEFINE_MAX_ SAMPLING		MPEG	Control software must dispose, and sampling structure is fixed by standard
	JPEG	In coded data
			H.251		It automatically is the 4:2:0 video configuration
	max_component_ld	MAX_COMP_ID				MPEG	Control software must dispose. Sampling structure is by standard
JPEG			In coded data
				H.261	The 4:2:0 video is disposed automatically

The interleaving access (continuing) of Table A .14.5 register pair token

Register	Token	Standard	Note
				tq_0 tq_1 tq_2 tq_3	JPEG_TABLE_ SELECT	JPEG	In coded data
MPEG	Need not in standard
		H.216
blocks_h_0 blocks_h_1 blocks_h_2 blocks_h_3 blocks_v_0 blocks_v_1 blocks_v_2 blocks v_3			DEFINE_SAMPLING			MPEG	Control software must dispose sampling structure by standard
	JPEG	In coded data
				H.261	The 4:2:0 video is disposed automatically
	dc_huff_0 dc_huff_1 dc_huff_2 dc_huff_3	In the probe data				JPEG	In coded data
MPEG_DCH_TABLE			MPEG	Control software must dispose
					H.261	In standard, do not use
ac_huff_0 ac_huff_1 ac_huff_2 ac_huff_3			In the probe data	JPEG			In coded data
		MPEG			In standard, do not use
			H.261
		dc_bits_0[15：0] dc_bits_1[15：0] dc_huffval_ 0[11：0] dc_huffval_ 1[11：0] dc_zssss_0 dc_zssss_1		in DATA Token follwing DHT_MARKER Token		JPEG	In coded data
	MPEG		Control software must dispose
				H.261	Need not in standard

The interleaving access (continuing) of Table A .14.5 register pair token

Register	Token	Standard	Note
				ac_bits_0[15：0] ac_bits_1[15：0] ac_huffval_0 [161：0] ac_huffval_1 [161：1] ac_eok0 ac_eob-1 ac_zrl-0 ac_zrl_1	in DATA Token following DHT_MARKER Token	JPEG	In coded data
	MPEG	Need not in standard
			H.261
	buffer_size				VBV_BUFFER_SIZE	MPEG	In coded data
JPEG		Need not in standard
			H.261
pel_aspect				PEL_ASPECT		MPEG	In coded data
	JPEG	Need not in standard
			H.261
	bit_rate				BIT_RATE	MPEG	In coded data
JPEG		Need not in standard
			H.261
pic_rate				PICTURE_RATE		MPEG	In coded data
	JPEG	Need not in standard
			H.261
	constrained				CONSTRAINED	MPEG	In coded data
JPEG		Need not in standard
			H.261

The interleaving access (continuing) of Table A .14.5 register pair token

Register	Token	Standard	Note
picture_type	PICTURE_TYPE	MPEG	In coded data
				JPEG	Need not in standard
		H.261
			brokern_closed	BROKEN_CLOSED		MPEG	In coded data
JPEG	Need not in standard
		H.261
prediction_mode					PREDICTION_MODE	MPEG	In coded data
	JPEG	Need not in standard
			H.261
	h_261_pic_type			PICTURE_TYPE (when standard is H.261 the time)		MPEG	Have nothing to do in coded data
JPEG
		H.261
vbv_delay			VBV_DELAY		MPEG	In coded data
	JPEG	Need not in standard
				H.261
	pic_number				Carried by： PICTURE_START	MPEG	Produced by detector for initial code
JPEG
		H.261

The interleaving access (continuing) of Table A .14.5 register pair token

Register	Token	Standard	Note
				coding_standard	CODING_STANDARD	MPEG	Arranged in initial code by the control software detector
JPEG
	H.261

A.14.2 map architecture

In the present invention, visual dimension is illustrated to spatial decoder with two kinds of different units: pixel and macro block. JPEG uses pixel to carry out communicating by letter of visual dimension with MPEG. The dimension communication of carrying out with pixel determines to include the buffer area of legal data; This may be less than buffer overall dimension. Determine the buffer sizes that decoder is required with the dimension communication that macro block carries out. The macro block dimension must be got from the pixel dimension by the user. The spatial decoder register relevant with this information is: horiz_pels, vert_pels, horiz_macroblocks and vert_macrobloks.

Spatial decoder register blocks_h_n, blocks_v_n, max_h, the formation (coding unit of minimum among the JPEG) of max_v and max_component_id indication macro block. Each is 2 bit registers, can preserve the value in 0 to 3 scope. All block counts of all indicating 1 to 4 except max_component _ id. For example, if register max_h gets 1, a macro block is that 2 pieces are wide so. Similarly, max_component_id indicates the number of related different colours composition.

The configuration of the various macro block forms of Table A .14.6

	2：1：1	42：2	4：2：0	1：1：1
					max_h	1	1	1	0
max_v	0	1	1	0
					max_component_ld	2	2	2	2
blocks_h_0	1	1	1	0
					blocks_h_1	0	0	0	0
blocks_h_2	0	0	0	0
					blocks_h_3	x	x	x	x
blocks_v_0	0	1	1	0
					blocks_v_1	0	1	0	0
blocks_v_2	0	1	0	0
					blocks_v_3	x	x	x	x

A.14.3 the Huffman of Huffman Table A .14.3.1 JPEG type table explanation

Among the present invention, the form that the explanation of Huffman table is used by JPEG offers spatial decoder to be communicated with the table explanation between encoder. Each table explanation has two element: BITS and HUFFVAL. For how comprehensive description of coding schedule, the user can consult the JPEG specification. A.14.3.1.1 BITS

BITS is a numerical tabular, illustrates how many distinct symbols are each length to VLC have be encoded. Each entrance is one 8 place values. JPEG allow VLC have 16 long, so in every table 16 entrances are arranged.

BIT[0] illustrate there are how many 1 different VLC, and BIT[1] existence how many 2 different VLC are described, by that analogy. A.14.3.1.2 HUFFVAL

HUFFVAL is 8 bit data value tables, by VLC length increase progressively arranged sequentially. The large young pathbreaker of this table decides according to the distinct symbols number that can be encoded by VLC.

How the JPEG specification can be encoded or be decoded as this form for the Huffman coding schedule further describes. A.14.3.1.3 the configuration of token

In a JPEG bit stream, the DHT mark is positioned at before the Huffman table explanation for coding AC and DC coefficient. When detector for initial code identified a DHT mark, it produced a DHT_MARKER token and next DATA token (seeing A.11.3.4) is put in the explanation of Huffman table.

AC and the configuration of DC coefficient Huffman table in spatial decoder can provide DATA and DHT_ MARKER token to be implemented by the input to spatial decoder when spatial decoder is disposed for jpeg operation. This gimmick can be used to the required DC coefficient Huffman table of MPEG operation, yet the coding standard of spatial decoder must be set to JPEG when table is loaded (downloaded) downwards.

Table A .14.7 disposes the Huffman table through token

E76543210	The token name
		100010101	CODING_STANDARD 1＝JPEG
000000001
	000011100	DHT_MARKER
1000001XX			DATA

Table A .14.7 disposes (continuing) through token to the Huffman table

E76543210	The token name
			1tttttttt	T represents that the Huffman table is loaded JPEG and allows 4 tables to be loaded by the higher level. Value 0 * 00 and 0 * 01 specifies DC coefficient coding table 0 and 1 value 0 * 10 and 0 * 11 to specify AC coefficient coding table 0 and 1	Row are shown in single order with n of permission by bright repetition by talkative in this board order
1nnnnnnnn	Li-carries 16 words of BITS information
1nnnnnnnn
		1nnnnnnnn	Vii-carries the word (number of words depends on the distinct symbols number) of HU FFVAL information. If this is that data token end extension bits will be 0 for e-, then will be 1 if in same DATA token, comprise other table explanation.
	ennnnnnnn

A.14.3.1.4 MPI is configured

AC and DC coefficient Huffman table also can directly be write to register by MPI. See Table A. 14.3.

Register dc_bits_0[15:0] and dc_bits_1[15:0] the BITS value of table 0 * 00 and 0 * 01 preserved.

Register ac_bits_0[15:0] and ac_bits_1[15:0] the BITS value of table 0 * 10 and 0 * 11 preserved.

Register dc_huffval_0[11:0] and dc_huffvla[11:0] the HUFFVAL value of table 0 * 00 and 0 * 01 preserved.

Register ac_huffval_0[161:0] and ac_huffval_1[161:0] the HUFFVAL value of table 0 * 10 and 0 * 11 preserved. A.144 the configuration of various criterion

Video distributor is supported MPEG, JPEG and needs H.261. Coding standard is disposed automatically by the CODING_STANDRAD token that detector for initial code produces. A.14.4.1H.261 Huffman shows

Decoding H.261 required all Huffman tables is stored among the ROM in the spatial decoder, or rather, is in analyzer (Parser) state machine at video distributor, does not therefore need user's interference. A.14.4.2H.261 map architecture

H.261 be defined as only supporting two kinds of pixel format: CIF and QCIF. Pixel format in being used is partly used signal instruction at the PTYPE of bit stream. When these data are decoded by spatial decoder, it is placed in h_261_pic_type register and the PICTURE_TYPE token. In addition, all images and macroblock structure register are automatically configured.

Information in various registers also is placed in their associated token (seeing Table A.14.5), and has guaranteed that like this other decoder chip (such as temporal decoder) is correctly disposed. A.14.4.3 MPEG Huffman shows

Decoding MPEG required most of Huffman coding schedule is stored among the ROM in the spatial decoder (being again in the analyzer state machine), does not therefore need user's interference. The required table of DC coefficient of decoding intra-macroblock is an exception. Two tables are required, and one for colourity, and another is brightness. These must be disposed by user software before the decoding beginning.

Table A .14.8 is to H.261 automatic setting

Macroblock structure	CIF/   OCIF	Map architecture	CIF	OCIF
					max_h
	1	horiz_pels	352	176
					max_v	1	vert_pels	288	10
max_component_id	2	horiz_mac roblocks	22	11
					blocks_h_0	1	vert_macroblocks	18	9
blocks_h_1	0
					blocks_h_2	0
blocks_v_0	1
					blocks_v_1	0
blocks_v_2	0

Table A .14.10 has shown the required sequence of tokens of DC coefficient Huffman table in the configuration space decoder. As selection, identical result also can obtain by this information is write to register through MPI.

Which DC coefficient Huffman table register dc_huff_n control uses to each color component. Table A .14.9 has shown how they should dispose for MPEG operates. This can directly finish or finish by use MPEG_DCH_TABLE token by MPI.

Table A .14.9 is selected MPEG DC Huffman table by MPI

dc_huff_0

	0
		dc_huff_1	1
dc_huff_2	1
		dc_huff_3	x

Table A .14.10 MPEG DC Huffman shows configuration

E   [7：0]	The token name
		1   0×15	CODING_STANDARD 1＝JPEG
0   0×01
	0   0×1C	DHT_MARKER
1   0×04			DATA (can be any chrominance component, in this example with 0)
	1   0×00	This Huffman table of 0 indication is DC coefficient coding table 0

Table 14.10 MPEG DC Huffman table configuration (continuing)

E	[7：0]	The token name
			1	0×00	Carry 16 words of multidigit information, altogether 9 different VLC are described 2,2 bit codes 3,3 bit code Isosorbide-5-Nitrae bit codes, 1,5 bit code 1,6 bit codes 1, if 7 bit codes by MPI configuration rather than with the token configuration, these values will be written to dc_bits_0[15:0] in the register
1	0×02
		1	0×03
1	0×01
		1	0×01
1	0×01
		1	0×01
1	0×00
		1	0×00

Table 14.10 MPEG DC Huffman table configuration (continuing)

E	[7：0]	The token name
			1	0×00
1	0×00
		1	0×00
1	0×00
		1	0×00
1	0×00
		1	0×00
1	0×01			Carry 9 words of HUFFVAL information. If by MPI configuration rather than with the token configuration, these values will be written to dc_huffval_0[11:0] in the register
		1	0×02
1	0×00
		1	0×03
1	0×04
		1	0×05
1	0×06
		1	0×07
0	0×08

Table 14.10 MPEG DC Huffman table configuration (continuing)

E	[7：0]	The token name
			0	0×1C	DHT_MARKER
1	0×04	DATA (any chrominance component uses 0 in this example)
			1	0×01	This Huffman table of 1 expression is DC coefficient coding table 1
1	0×00	Carry 16 words of an information, altogether 9 different VLC are described 3,2 bit codes, 1,3 bit code 1,4 bit codes, 1,5 bit code, 1,6 bit code 1,7 bit codes 1, if 8 bit codes by MPI configuration rather than with the token configuration, these values will be written to dc_bits_1[15:0] in the register
			1	0×03
1	0×01
			1	0×01
1	0×01
			1	0×01
1	0×01
			1	0×01
1	0×00
			1	0×00
1	0×00
			1	0×00
1	0×00

Table 14.10 MPEG DC Huffman table configuration (continuing)

E	[7：0]	The token name
			1	0×00
1	0×00
		1	0×00
1	0×00			Carry 9 words of HUFFVAL information. If by MPI configuration rather than with the token configuration, these values will be written to dc_huffval_0[11:0] in the register
		1	0×01
1	0×02
		1	0×03
1	0×04
		1	0×05
1	0×06
		1	0×07
0	0×08
		1	0×D4		MPEG_DCH_TABLE is configured to component 0 use table 0
0	0×00

Table 14.10 MPEG DC Huffman table configuration (continuing)

E	[7：0]	The token name
			1	0×D5	MPEG_DCH_TABLE configuration component 1 uses table 1
0	0×01
		1	0×D6	MPEG_DCH_TABLE configuration component 2 uses table 1
0	0×01
		1	0×15		CODING_STANDARD 2＝JPEG
0	0×02

A.14.4.4 MPEG map architecture

For the macroblock structure of MPEG definition with H.261 employed identical. The dimension of image is encoded in the coded data.

To standard 4:2:0 operation, the macro block characteristic should be configured as Table A .14.8 indicating. This can be by writing register or the input that identical token (seeing Table A.14.5) offers spatial decoder being finished as indication ground.

Disposing the method token of visual dimension will decide according to using. If pixel format knew that the map architecture register of listing in so among the Table A .14.8 can be by suitable value initialization before the decoding beginning. As selection, visual dimension can be from coded data decoded and configuration space decoder. In the case, the user must repair analyzer mistake ERR_MPEG _ SEQUENCE, sees A.14.8 " in the variation of MPEG sequence layer ". A.14.4.5 JPEG

In baseline jpeg, a large amount of codes selections is arranged, they significantly change the complexity of the required control software of operation decoder. Usually, spatial decoder is designed to support minimum required when following condition is satisfied:

The color component number of each frame is less than 5 (Nf≤4) JPEG Huffman table A.14.4.6

Further, JPEG allows the Huffman coding schedule to be loaded to decoder downwards. These tables are used when decoding illustrates the VLC of coefficient. Every one scan allows two tabulation code DC coefficients, 2 tabulation code AC coefficients.

Jpeg file have three kinds dissimilar: interchange format, for the breviary form of compressed image data be the breviary form of table data. Existing compressed image data also has the definition of all required tables of decoding image data (Huffman quantizes etc.) in an interchange format file. The thumbnail image data format file has omitted the definition of table. The contraction table formatted file only comprises the definition of table.

Spatial decoder will be accepted three kinds of all forms. Yet the thumbnail image data file only could be decoded in the situation that all required tables all have been defined. This definition can be done by any of other two kinds of jpeg file types, and perhaps, table can be arranged by user software.

If each Huffman table that uses a cover different that scans, each scanning that is defined in of table is placed in (by encoder) coded data before so. These by the spatial decoder automatic loading in this or any follow up scan, to be used.

For improving the performance of Huffman decoding, some symbol that often uses is packed into especially. They are: numerical value is 0 DC coefficient, the ending of piece AC coefficient and the management of 16 zero AC coefficients. The value of these special occasions should be written into suitable register. A.14.4.6.1 the selection of table

Register dc_huff_n and ac_huff_n are controlling which kind of color component are being used which AC or DC coefficient Huffman table. In jpeg operation, these relations are by the TD of probe poster method_jAnd Ta_jField Definition. A.14.4.7 jpeg picture structure

Exist two kinds of baseline jpeg decoding ranks of being supported by spatial decoder significantly: every frame is less than or equal to four kinds of composition (N_f≤ 4) and every frame greater than four kinds of composition (N_f＞4). If use (N_f＞4), control software need to become more complicated. A.14.4.7.1 N_f≤4

The frame component specifications parameter that is contained in the JPEG frame title disposes macroblock structure register (seeing Table A.14.8) when they are decoded. Do not need user intervention, 4 kinds of required all of different colours composition of decoding illustrate all as definition.

For obtaining more details of the selection that JPEG provides, the reader should learn the JPEG specification. Simultaneously, in the jpeg picture form in A.16.1 cutline is arranged also. A.14.4.7.2 the JPEG that has composition more than four kinds

Spatial decoder can be decoded and be had the nearly jpeg file of 256 kinds of different chrominance components (maximum that JPEG allows). Yet if the component more than 4 kinds of decoding, additional user intervention needs. JPEG at most only allows four kinds of components in any scanning. A.14.4.8 non-standard modification

As mentioned above, spatial decoder supports some to exceed JPEG and the defined pixel format scope of MPEG.

JPEG restriction minimum code unit, so the piece that their each scanning comprises is no more than 10. This restriction is not suitable for spatial decoder, because it can pass through blocks_h_n, blocks_v_n, max_h and max_v illustrate treatable any minimum code unit.

MPEG just defines for the macro block of 4:2:0 (seeing Table A.14.8). Yet spatial decoder can be processed three kinds of other composition macroblock structure (for example 4:2:2). A.14.5 Video Events and mistake

Video distributor can produce two class events: analyzer event and Huffman event. About how processing the description of event and interruption, referring to A.6.3 " interruption ". A.14.5.1 Huffman event

The Huffman event is produced by the huffman decoder. Event by huffman event and huff-man_mask indication judges whether to have produced an interruption. To be produced if huffman_mask is set to 1, one interruption, and the Huffamn decoder will stop. Register huffman_errov_code[2:0] will preserve a value of indicating the event reason.

If 1 is write to huffman_event after break in service, the Huffman decoder will be attempted to recover from mistake. Equally, if huffman_mask is set to 0. (interruption masking and do not stop the Huffman decoder), the Huffman decoder will be attempted automatically to recover from mistake. A.14.5.2 analyzer event (Parser events)

The analyzer event is produced by analyzer. Event is indicated by Parser_event. After this parser_mask judges whether that an interruption is produced. 1, one interruption will be produced and analyzer will stop if parser_mask is set to. Register parser_error_code [7:0] will preserve the value of an indication event reason.

If 1 is written into huffman_event after break in service, the Huffman decoder will be attempted to recover from mistake. Equally, if huffman_mask is set to 0, (interruption masking and do not stop the Huffman decoder), the Huffman decoder will be attempted automatically to recover from mistake.

If 1 is written into parser_event after break in service, analyzer will bring into operation again. If bit stream mistake of event indication, video distributor will be attempted to recover from mistake.

If analyzer is set to 0, analyzer will arrange its event bit, but can not produce an interrupting or stopping. It will continue operation and attempt automatically to recover from mistake.

Table A .14.11 Huffman error code

huffman_eror_code	Explanation
		[2]    [1]    [0]
0       0      0	This mistake does not occur in inerrancy during normal operating
		x
0      1	In 16 of VLC, can not find stop code
		x       1      0	When wishing token, find serial data
x       1      1	When wishing serial data, find token
		1       x      x	Coefficient during decoded information illustrates single is more than 64, and this expression bit stream is wrong, and the piece by video distributor output only comprises 64 coefficients.

Table A .14.12 Parser error code

parser_error code[7：0]	Explanation
		0×00	ERR_NO_ERROR, this event does not occur under normal circumstances
0×10	ERR_EXTENSION_TOKEN EXTENSION_DATA token is detected by Parser. The detection of this token should priority treatment comprises that A.14.6 the DATA token of growth data see
		0×11	ERR_EXTENSION_DATA is followed by the detection of EXTENSION_DATA token, and a data token that comprises growth data is detected, sees A.14.6

Table A .14.12 Parser error code (continuing)

parser_error code[7：0]	Explanation
		0×12	ERR_USER_TOKEN USER DATA token is detected by Parser, and the detection of this token should priority treatment comprises the data token (seeing A.14.6) of user data
0×13	Be the detection of USER_DATA token below the ERR_USER_DATA, comprise that the data token of user data detected, see A.14.6
		0×20	ERR_PSPARE H.261 PSARE information is detected, sees A.14.7
0×21	ERR_GS PARE H.261 GSARE information is detected, sees A.14.7
		0×22	The ERR_PTYPE H.261 value of visual type changes, and register h_261_ pic_type can be examined, and what is to look into new value
0×30	ERR_JPEG_FRAME
		0×31	ERR_JPEG_FRAME_LAST
0×32	ERR_JPEG_SCAN image size or number change
		0×33	The ERR_JPEG_SCAN_COMP component changes
0×34	ERR_DNL_MARKER

Table A .14.12 Parser error code (continuing)

parser_error  code[7：0]	Explanation
		0×40	ERR_MPEG_SEQUENCE in the MPEG sequence layer in the Transfer Parameters one change, see A.14.8
0×41	ERR_EZTRA_PICTURE MPEG extra_information_picture is detected, sees A.14.7
		0×42	ERR_EZTRA_SLICE MPEG extra_information slice is detected, sees A.14.7
0×43	The VSV_DELAY parameter of ERR_VBV_DELAY first image in new MPEG video sequence detects by video distributor, first image after new length of delay can obtain new sequence in register vbv_delay first image is defined as EOS. FLUSH or reset
		0×80	Error format token of ERR_SHORT_TOKEN detects, and this mistake does not occur in normal operation
0×90	ERR_H261_PIC_END_UNEXPECTED is at duration of work H.261, running into visual end signal in side undesirably, and this probably represents to have a mistake in coded data
		0×91	ERR_GN_BACKUP is at duration of work H.261, and piece group one group of number that desired value is little on year-on-year basis meets, and this probably represents to have a mistake in coded data

Table A .14.12 Parser error code (continuing)

parser_error code[7：0]	Explanation
		0×92	ERR_GN_SKIP_GOB is at duration of work H.261, and piece group one group of number that desired value is large on year-on-year basis meets, and this probably shows not have a mistake in coded data
0×A0	ERR NBSE TAB attempts to load a Huffman table at the JPEG duration of work, and this table is not by baseline jpeg support (baseline jpeg is only supported the table 0 and 1 of entropy coding)
		0×A1	ERR_0UANT_PRECISION attempts to load a quantization table at the UPEG duration of work, and this shows not by baseline jpeg support (baseline jpeg is only supported 8 position predictions in the quantization table)
0×A2	ERR_SAMPLE_PRECISION attempts to specify a sampling precision at the JPEG duration of work, and it is greater than baseline jpeg, the precision of support (baseline jpeg is only supported 8 precision)
		0×A3	ERR_NBASE_SCAN JPEG scanning leader parameter S s, Se, Ah and Al one or more are set up a value, and it is not by baseline jpeg support (the continuous approximation value that represents special selection and/or be not supported in baseline jpeg)
0×A4	ERR_UNEXPECTED_DNL in single pass, but is not to run into when scanning for the first time of a frame at DNL mark of JPEG duration of work
		0×A5	ERR_EOS_UNEXPECTED is at the JPEG duration of work, and an EOS mark is undesirably just running into

Table A .14.12 Parser error code (continuing)

parser_error code[7：0]	Explanation
		0×A6	ERR_RESTART_SKIP is at the JPEG duration of work, and one is restarted mark has been undesirable in the value that desired location is not run into or is restarted mark. If one to restart mark found when wishing not have when finding, the Huffman event " finds string data " and will be produced when wishing token
0×B0	ERR_SKIP_INTRA is at the MPEG duration of work, and one has macroblock address increment and in intra (I) image found that greater than 1 macro block this is illegal and may represents the bit stream mistake
		0×B1	ERR_SKIP_DINTRA is at the MPEG duration of work, and one has macroblock address increment and only finds in DC (D) image greater than 1 macro block. This is illegal, may represent a bit stream mistake
0×B2	ERR_BAD_MARKER is at the MPEG duration of work, the futureless value of marker bit. This may represent the bit stream mistake
		0×B3	ERR_D_MBTYPE is at the MPEG duration of work, and only in DC (D) image, the macro block of a macro block (mb) type except 1 is found. This is illegal, may represent a bit stream mistake
0×B4	ERR_D_MBEND is at the MPEG duration of work, and only in DC (D) image, macro block ending is that 0 macro block is found, and this is illegal, may represent a bit stream mistake

Table A .14.12 Parser error code (continuing)

parser_error code[7：0]	Explanation
		0×B5	ERR_SVP_BACKUP is at the MPEG duration of work, and the upright position of a sheet runs into less than the sheet of desired value, probably is illustrated in a mistake in the coded data
0×B6	Sheet greater than desired value runs into ERR_SVP_SKIP_ROWS in the upright position of a sheet of MPEG duration of work. Probably be illustrated in the mistake in the coded data
		0×B7	ERR_FST_MBA_BACKUP is at the MPEG duration of work, and a macroblock address is run into less than the macro block of desired value. Probably be illustrated in a mistake in the coded data
0×B8	ERR_FST_MBA_SKIP is at the MPEG duration of work, and a macro block has run into a macroblock address greater than desired address. This probably is illustrated in mistake in the coded data
		0×B9	ERR_PICTURE_END_UNEXPECTED is at the MPEG duration of work, and a PICTURE_END token is undesirably just running into, and this probably is illustrated in mistake in the coded data
0×E0…     0×EF	Mistake is that the close beta program keeps
		0×E0	ERR_TST_PROGRAM reaches in estimating program abstrusely
0×E1	If the ERR_NO_PROGRAM test program is not included in wherein

Table A .14.12 Parser error code (continuing)

parser_error code[7：0]	Explanation
		0×E2	ERR_TST_END tests end
0×F0… 0×FF	Keep mistake
		0×F0	ERR_UCODE_ADDR gross error
0×F1	ERR_NOT_INPLEMENTED

Every kind of standard is used different subsets of the analyzer error code of definition.

Table A .14.13 analyzer error code and various criterion

The token name	MPEG	JPEG	H261
				ERR_NO_ERROR	/	/	/
ERR_EXTENSION_TOKEN	/	/
				ERR_EXTENSION_DATA	/	/
ERR_USER_TOKEN	/	/
				ERR_USER_DATA	/	/
ERR_PSPARE			/
				ERR_GSPARE			/
ERR_PTYPE			/
				ERR_JPEG_FRAME		/
ERR_JPEG_FRAME_LAST		/
				ERR_JPEG_SCAN		/

Table A .14.13 analyzer error code and various criterion (continuing)

The token name	MPEG	JPEG	H251
				ERR_JPEG_SCAN_COMP		/
ERR_DNL_MARKER		/
				ERR_MPEG_SEQUENCE	/
ERR_EXTRA_PICTURE	/
				ERR_EXTRA_SLICE	/
ERR_VBV_DELAY	/
				ERR_SHORT_TOKEN	/	/	/
ERR_H251_PIC_END_UNEXPECTED			/
				ERR_GN_BACKUP			/
ERR_GN_SKIP_GOB			/
				ERR_NBASE_TAB		/
ERR_QUANT_PRECISION		/
				ERR_SAMPLE_PRECISION		/
ERR_NBASE_SCAN		/
				ERR_UNEXPECTED_DNL		/
ERR_EOS_UNEXPECTED		/
				ERR_RESTART_SKIP		/
ERR_SKIP_INTRA	/
				ERR_SKIP_DINTRA	/
ERR_BAD_MARKER	/
				ERR_D_MBTYPE	/
ERR_D_MBEND	/
				ERR_SVP_BACKUP	/
ERR_SVP_SKIP_ROWS	/
				ERR_FST_MBA_BACKUP	/
ERR_FST_MBA_SKIP	/
				ERR_PICTURE_END_UNEXPECTED	/
ERR_TST_PROGRAM	/	/	/
				ERR_NO_PROGRAM	/	/	/
ERR_TST_END	/	/	/
				ERR_UCODE_ADOR	/	/	/
ERR_NOT_IMPLEMENTED	/	/	/

A.14.6 receive with corpse and growth data

MPEG and JPEG use similar gimmick to deposit user and growth data. There is an initial/mark code data front. Lose interest in if use these class data, detector for initial code will be deleted these data (seeing A.11.3.3). A.14.6.1 recognition data is originated

The analyzer event, ERR_EXTENSION_TOKEN and ERR_USER_TOKEN are in the arrival of video distributor indication EXTENSION_DATA or USER_DATA token. If these tokens are produced (seeing A.11.3.3) by detector for initial code, the value that they will carry initial/mark code makes detector for initial code produce token (seeing Table A.11.4). This value can be read by reading the rom_revision register when the analyzer break in service. Video distributor stops maintenance until 1 be written into parser_evetn (seeing A.6.3 " interruption "). A.14.6.2 read data

A DATA token that carries expansion or user data should tightly be followed in EXTENSION_DATA and USER_DATA token back. This DATA token arrives video distributor will produce an ERR_EXTENSION_DATA or an ERR_USER_DATA syntax analyzer event. The first byte of DATA token can be read by reading the rom_revision register when break in service.

After event was eliminated, the state of video distributor register " continue " was determining state. If this register holds 0 value, any event can be eliminated and not produce to any remaining data all in the DATA token by video distributor so. If continue is set to 1, each byte of expansion or user data all can have an event to be produced when arriving Video Decoder. This will continue until the DATA token is consumed or continue is set to 0. Attention:

1) always the first byte of expansion/user data is expressed by the rom_revision register no matter the state of continue.

2) event that does not exist last byte of indication extension/user data to be read. A.14.7 receive external information

H.261 allow the information of expansion coding standard to be loaded in image and piece group (H.261) or the sheet (MPEG) with MPEG. Its gimmick is different from expansion and user data employed (A.14.6 in the part explanation being arranged). Do not have initial code in the data front, therefore, it can not be deleted by detector for initial code.

In H.261 operating, analyzer event ERR_PSPARE and ERR_GSPARE indication detect this information. Corresponding event in MPEG is ERR_EXTRA_PICTURE and ERR_ EXTRA_SLICE.

When the analyzer event is produced, the first byte of additional information is presented by register rom_ revision.

Behavior after video distributor register continue decision event is eliminated. If this register value is 0, so any remaining additional information all will be eliminated by video decoder and the event that do not have produces. If continue to be set to 1, each byte of additional information all can have an event to be produced when arriving video distributor. This will last till that additional information runs out or continue is set to 0.

Attention:

1) regardless of the state of continue, the first byte of expansion/user data always manifests by the rom_revision register.

2) event that does not exist last byte of indication extension/user data to be read. A.14.7.1 the generation of FIELD_INFO token

In the MPEG operation, if register field_info is set to 1, the first byte of any extra _ information_picture is put in the FIELD_INFO token. This behavior is not included by the standardization activity of MPEG. Table A .3.2 has shown the definition of FIELD_INFO token.

If FIELD_INFO is set to 1, the first byte of extra_information_picture is not had the analyzer event be produced. Yet, have the event generation for any subsequent byte of extra_infor-mation_picture. If extra_infor-mation_picture only has a single byte, do not have the analyzer event and produce. A.14.8 the variation of MPEG sequence layer

The MPEG sequence-header has been described the following characteristic of video that will be decoded:

The horizontal and vertical size

Pixel the ratio of width to height

The image rate

The coded data rate

Video buffer verifier buffer size

If any one when a sequence-header of spatial decoder decoding in these parameters changes, analyzer ERR_MPEG_SEQUENCE will be produced. A.14.8.1 the change of image size

If image size changes to some extent, the value of horiz_pels and vert_ pels should be read by user software, and calculates the new value that will be loaded into register horiz_macroblocks and vevt_ macroblocks. A.15 space decoding

Corresponding to the present invention, space decoding betides between the output of the output of token buffer and spatial decoder. The formant that three kinds of responsible space decodings are arranged: countercurrent fashion device, inverse quantization device and reverse discrete cosine transform device. Entering this part (from token buffer) input, the DATA token comprises the quantization parameter of a distance of swimming and level expression. At output (inverse-DCT), 8 * 8 pixel informations of DATA token. A.15.1 countercurrent fashion device (The Inverse Modeler)

DATA token in the token buffer comprises about the value of quantization parameter with by the information of 0 number in the coefficient that represents. The countercurrent fashion device is about 0 distance of swimming extend information, so that each DATA token comprises 64 values. In this, the value in the DATA token is quantization parameter.

No matter what the coding standard of current use is, it all is identical that the countercurrent fashion device is processed, and does not need to be configured.

In order to understand better medelling and all needs of countercurrent fashion function, the reader can check any picture coding standard. A.15.2 inverse quantization device

In an encoder, quantizer removes the output of DCT to reduce the resolution ratio of DCT coefficient. In a decoder, the function of inverse quantization device is to take advantage of the DCT coefficient of these quantifications to recover their approximate original values. A.15.2.1 the criterion and quantity scheme is summarized

The quantization scheme of every kind of different coding standard use has remarkable difference. For obtaining the detailed understanding for every kind of employed quantization scheme of standard, the reader can study the correlative coding normative document.

The operation of register iq_coding_standard configuration inverse quantization device is to satisfy the needs of various criterion. In general operation, this register is by CODING_STANDARD token automatic loading. Obtain the more information about coding standard configuration, referring to part A.21.1.

Main Differences between the quantization scheme is the source of the numeral that quantization parameter will be multiplied by. These are summarized below. In required algebraic operation (round off etc.) nuance is also arranged, do not explain herein. A.15.2.1.1 IQ summation H.261

In H.261, one single " scale factor " is used to scale factor. Encoder can this scale factor of periodically-varied to adjust the data transfer rate that produces. Rules slightly different in the in-line coding piece is applied in " DC " coefficient. A.15.2.1.2 JPEG IQ summation

Baseline jpeg allows an images to comprise nearly 4 kinds of different color components in each scanning. Each can specify the quantization table of 64 entrances to these 4 kinds of colors are divided into. Each entrance of these tables is used as in 64 quantization parameters " scale " factor of one.

The value of JPEG quantization table is included in also will be by the quantization table of automatically packing in the coding jpeg data. A.15.2.1.3 MPEG IQ summation

H.261 MPEG uses and the JPEG quantification technique. As JPEG, MPEG can use 4 quantization tables, and each quantization table has 64 entrances. Yet the use of table is completely different.

Consider two " class " data: inner and non-internal data. Every kind of data type is used a different table. Two default tables are defined by MPEG. One is used for internal data and another is used for non-internal data (see Table A.15.2 with Table A .15.3). These default tables must mpeg decode become may before be written into the quantization table memory of spatial decoder.

MPEG also allows two " loading " quantization tables downwards. One is for internal data, and another is for non-internal data. The value of these tables is contained in the mpeg data stream and will be written in the quantization table memory by automatic mounting.

The value of output is by the scale factor correction from table. A.15.2.2 inverse quantization device register

Table A .15.1 anti-phase quantizer register

Register name	Size/direction	Reset mode	Explanation
				iq_access
	1    rw	0	This access bit stops the work of inverse quantization device, so its various registers can be by reliable access
				iq_coding _standard
	2    rw	0	The coding standard of being used by the anti-phase quantizer thus register arranges this register and directly loads or use the CODING_STANDARD token. (seeing A.21.1)
				iq_keyhole _address	8    rw	x	Keyhole access 4 quantization tables wherein see to be the more information of passing through the keyhole access function resister A.5.4.3, see A.5.4.3
iq_keyhole _data	8    rw	x

In the present invention, the iq_acces register must be set up before the quantization table memory is accessed. If attempt to read the quantization table memory when iq_access is set to 0, it will return null value. A.15.2.3 dispose the inverse quantization device

In general operation, need not dispose the coding standard of inverse quantization device, because it will be disposed automatically by the CODING_STANDARD token.

To H.261 operation, quantization table is not used. Without any need for particular arrangement. To jpeg operation, the table that the inverse quantization device needs should with the information that from coded data, extracts together by automatic loading.

The MPEG action need loads and lacks the x quantization table. This should be set to finish in 1 o'clock at iq_access. Value among the Table A .15.2 should be written into 0 * 00 to the 0 * 3F position (can pass through keyhole register iq_keyhole_address and iq_ keyhole_data access) of the expanded address space of inverse quantization device. Similarly, the value among the Table A .15.3 should be written into 0 * 40 to 0 * 7F position of the expanded address space of inverse quantization device.

Table A .15.2 is to the default mpeg table of based encode piece

i	W i.0 b	i	W i.0	i	W i.0	i	W i.0
								0     1     2     3     4     5     6     7     8     9     10     11     12     13     14     15	8     16     16     19     16     19     22     22     22     22     22     22     26     24     26     27	16     17     18     19     20     21     22     23     24     25     26     27     28     29     30     31	27     27     26     26     26     25     27     27     27     29     29     29     34     34     34     29	32     33     34     35     36     37     38     39     40     41     42     43     44     45     46     47	29     29     27     27     29     29     32     32     34     34     37     38     37     35     35     34	48     49     50     51     52     53     54     55     56     57     58     59     60     61     62     63	35     38     38     40     40     40     48     48     46     46     56     56     58     69     69     83

A quantizes tabular value with respect to the start offset b of quantization table memory

Table A .15.3 is to the default mpeg table of non-based encode piece

i	W i.1	W i.1	W i.1	i	W i.1	i	W i.1
								0  1  2  3  4  5  6  7  8  9  10  11  12  13  14  15	15  16  16  16  16  16  16  16  16  16  16  16  16  16  16  16	16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31	16  16  16  16  16  16  16  16  16  16  16  16  16  16  16  16	32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47	15  15  15  16  16  16  16  16  16  16  16  16  16  16  16  15	48  49  50  51  52  53  54  56  56  57  58  59  60  61  62  63	16  16  16  16  16  16  16  16  16  15  16  16  16  16  16  16

A.15.2.4 token allocation list

As a kind of the substituting by MPI configuration inverse quantization table, they also can be initialized by token. These tokens are provided by coded data port or MPI.

The QUANT_TABLE token illustrates in Table A .3.2. It has two a bit fields ratio, indicates in 4 (0 to 3) table position which and is defined by token. To MPEG operation, table 0 and 1 default definition need to be loaded. A.15.2.5 quantize tabular value

For JPEG and MPEGA, the quantization table entrance all is 8 figure places. 255 to 1 value is legal. 0 value is illegal. A.15.2.6 the numerical order of quantization table

Quantizing tabular value is used with " Z-type (zlg-zag) " scanning sequency (seeing coding standard). Table should be seen as the one dimension of 64 values and arrange (rather than 8 * 8 matrixes). Table enters at the low address corresponding to low frequency DCT coefficient.

When the quantification tabular value was carried by the QUANT_TABLE token, first value behind the token title was the table entry of " DC " coefficient. A.15.2.7 inverse quantization device detected register

Table A .15.4 vectorization scratchpad register

Register name	Size/direction	Reset mode	Explanation
				iq_quant _scale
	5    rw		This register keeps the currency of quantization scaling factor, and it is loaded by the QUANT_SCALE token, and this is obsolete at the JPEG duration of work.
				iq_component	2    rw		2 component ID that this register maintenance is got from nearest data token head. This value is included in the selection of quantization table. This register also will keep this Table I D to load this table after the QUANT_TABLE token arrives.
iq_Prediction _mode	2    rw		This keeps 2 least significant bits of nearest PREDICTION_MODE token.
				iq_jpeg_ indirection	8    rw		Position component ID number that this register makes the DATA token is with should be relevant by the table number of the just quantization table of usefulness. Position 1:0 specifies the table number that will be used by component 0. Position 3:2 specifies the table number that will be used by component 1. Position 5:4 specifies the table number that will be used by component 2. Position 7:6 specifies the table number that will be used by component 3. This register is loaded by JPEG_TABLE_SECE--CL token.

Table A .15.4 inverse quantization scratchpad register (continuing)

Register name	Size/direction	Reset mode	Explanation
				iq_mpeg_ indrection
	2    rw		Whether this two bit registers record loads quantization table with default value or by inner or non-internal data by the higher level. Should be used at the default table of bit position expression for one 0, one 1 expression should be used by higher level's load table. Position 0 relates to internal data, and position 1 relates to non-internal data, and register is loaded by token MPEG_TABLE_ SELECT usually.

A.15.3 reverse discrete cosine transform

H.261 reverse discrete transform processor among the present invention meets CCITT recommends, the requirement of IEEE specification P1180, and meet the requirement of describing in the current MPEG revision draft.

Where no matter use coding standard, the reverse discrete cosine transform processor is identical. Do not need the user to be configured.

There are two events relevant with reverse discrete transform processor.

The anti-phase DCT event registers of Table A .15.5

Register name	Size/direction	Reset mode	Explanation
				ldct_too_ few_event
	1    rw	0	Oppositely DCT requires all DATA tokens to comprise accurately 64 values. If find less than 64 values, that generation event produces interruption so if mask register is set to 1 very little, and oppositely DCT will stop. This event should occur over just immediately following mistake in coded data.
				idct_too _few_mask	1    rw	0

The anti-phase DCT event registers of Table A .15.5 (continuing)

Register name	Size/direction	Reset mode	Explanation
				idct_too_ many_event
	1   rw	0	Oppositely DCT requires all DATA tokens to comprise accurately 64 values. If find that greater than 64 values it is too many to produce so event, if mask register is set to 1, can produce interruption so, oppositely DCT stops. This event should occur over just immediately following mistake in coded data.
				idct_too_ many_mask	1   rw	0

For understanding better DCT and inverse-DCT function, the reader can check any picture coding standard. A.16 the output of connection space decoder

The output of spatial decoder is a standard token port with 9 bit wide data words. Want to know the more information of interface electrical property, referring to part A.4.

The token that output shows will depend on the coding standard of use. For example, this part of announcement is to consider the output of spatial decoder when disposing for jpeg operation. The sequence of tokens of having observed at the output of temporal decoder when this part has also been described jpeg operation is not because temporal decoder changes the sequence of tokens that gets from decoding JPEG.

Yet, MPEG and H.261 all need the use of temporal decoder. Want MS in for MPEG with H.261 operate the information of the output binding of the temporal decoder when disposing, referring to part A.19.

In addition, this part determines can obtain which token at the output of spatial decoder, and which token is the most useful when design circuit is exported to show. Other token also occurs, but need not be used for showing output, does not therefore discuss at this.

This part mainly shows:

How beginning and the end of recognition sequence.

How beginning and the end of recognition image.

When how to confirm shows image.

Where the how to confirm pictorial data should be placed into demonstration. A.16.1 the structure of jpeg picture

This part provides the summation of some feature of JPEG system. Want to know full details, see also coding standard.

JPEG provides multiple gimmick for the single image of encoding. JPEG does not attempt to illustrate that how together a large amount of images of coding are to provide a kind of gimmick of encoded video.

According in the present invention, the baseline that spatial decoder is supported JPEG is (baseline sequential) mode of operation continuously. Three main ranks are arranged: image, frame and scanning in the system. One width of cloth consecutive image includes only a single frame. One frame can comprise 1 to 256 kind of different image (color) component. These image components can be grouped into various ways and be scanning. Every one scan can comprise 1 to 4 kind of image component (seeing Figure 81, " JPEG baseline continuous structure summation ").

If one scan comprises a single image component, it is non-interlaced; Surpass a kind of image component if it comprises, it is an interlacing scan. One frame can comprise the mixing of interlacing and non-interlace. 256 restrictions of the image component number that the number of scans that one frame can comprise can be comprised by a frame and determining.

In interlacing scan, data are organized into minimum coding unit (MCU), and these coding units are similar with the macro block of H.261 middle use to MPEG. These MCU press grating and arrange in an images. In a non-interlace, MCU is one single 8 * 8. These equally also are that grating is arranged.

Spatial decoder can be decoded easily and be comprised the jpeg data of 1 to 4 kind of different colours composition. Describe that more the information of multicomponent amount number also can be decoded. Yet for adapting to the component that next group will be decoded, some between needs can being scanned reconfigures. A.16.2 sequence of tokens

The jpeg marker code is converted to the token (see Table A.11.4, see Figure 82 " token jpeg picture ") of a similar MPEG name by detector for initial code. A.17 temporal decoder

The 30MHz operation

For MPEG and H.261 Video Decoder time decoder is provided

H.261 CIF and QCIF form

The MPEG video resolution reaches 740 * 480,30Hz, 4:2:0

Chroma flexibly

Can reset the MPEG image sequence

Glue_Less DRAM interface

Single positive 5 volts of power supplys

208 pin PQFP encapsulation

Maximum power consumption 2.5W

Application standard page DRAM

Temporal decoder is a paired chip of spatial decoder. It provides H.261 required with MPEG time decoder.

Temporal decoder is finished MPEG and required all predictions Formation and characteristics H.261. By means of a single 4Mb DRAM (for example, 512k * 8), the temporal decoder H.261 video of CIF and QCIF of can decoding. By means of 8Mb DRAM (for example, 2256k * 16), 740 * 480,30Hz, 4:2:0 MPEG video can be decoded.

For in-line coding scheme (such as JPEG) when not required between decoder. If temporal decoder is included in more than one in the standard decoder, it will make decoded jpeg picture by its output. Attention: above-mentioned value only is for example as the explanation of one embodiment of this invention, need to be as restriction. Do not depart from the present invention and use other numerical value and scope will to be appreciated yet. A.17.1 temporal decoder signal

Table A .17.1 temporal decoder signal

Signal name	I/O	Pin number	Explanation
				in_data[8：0]	I	173，172，171， 169，168，167， 166，164，163	Input port, this is a standard two wire interface, links the spatial decoder output port when normal. See A.4 and A.18.1
in_extn	I	174
			in_valid	I	162
in_accept	O					161
			enable[1：0]	I	126，127			MPI (MPI). See A.6.1 page or leaf 59
rw	I	125
			addr[7：0]	I	137，136，135， 133，132，131， 130，128
data[7：0]	O	152，151，149， 147，145，143， 141，140
			irq	O	154

Table A .17.1 temporal decoder signal (continuing)

Signal name	I/O	Pin number	Explanation
				DRAM_data [31：0]	I/ O	15，17，19，20， 22，25，27，30， 31，33，35，38， 39，42，44，47， 49，57，59，61， 63，66，68，70， 72，74，76，79， 81，83，84，85，	The DRAM interface. See A.5.2
DRAM_addr [10：0]	0	184，186，188， 189，192，193， 195，197，199， 200，203
			RAS	0	11
CAS[3：0]	0	2，4，6，8
			WE	0	12
OE	0	204
			DRAM_enable	I	112
out_data [7：0]	0	89，90，92，93， 94，95，97，98				Output port, this is a standard two wire interface. See A, 4 and A, 19
			out_extn	0	87
out_valid	0	99
			out_accept	I	100

Table A .17.1 temporal decoder signal (continuing)

Signal name	I/O	Pin number	Explanation
				tck	I	115	Jtag port. See A.8
tdi	I	116
			tdo	0	120
tms	I	117
			trst	I	121
decoder_ clock	I	177				The main decoder clock. See A.7.2
			rest	I	160		Reset

Table A .17.2 temporal decoder test signal

Signal name	I/O	Pin number	Explanation
				tphOish	I	122	If override=1, Tphoish and tphish are as the input of two phase clock on the chip so. Correct operating and setting override=0 tphoish and Tphiish be left in the basket (thereby link GND or VCC)。
tphlish	I	123
			override	I	110
chiptest	I	111				Correct work arranges chiplist=0.
			tloop	I	114		When correct work, link GND or VDD。

Table A .17.2 temporal decoder test signal (continuing)

Signal name	I/O	Pin number	Explanation
				ramtest	I	109	If ramtest=1 allows RAM on the test pieces, it is normal operating that ramtest=0 is set.
pllselect	I	178	If the phase-locked evil idea of pllselect=0 on chip is under an embargo. In normal operation, establish pilselecl=1.
				ti	I	180	During test job, the DRAM interface is needed 2 clocks. Receive ground or V in normal work periodDD。
tq	I	179
			pdout	O	207	These two pins are that phaselocked loop connects external filter
pdin	I	206

Decoder pin assignment between Table A .17.3

The signal name pin	The signal name pin	The signal name pin	The signal name pin
				nc                208	nc           156	nc             104	nc                  52
testpin           207	nc           155	nc             103	nc                  51
				testpin           206	irq          154	nc             102	nc                  50
GND               205	nc           153	VDD            101	DRAM_data[15]       49
				OE                204	data[7]      152	out_accept     100	nc                  48
DRAM_addr[0]      203	data[6]      151	out_valid      99	DRAM_data[16]       47
				VDD               202	nc           150	out_data[0]    98	nc                  46
nc                201	data[5]      149	out_cata[1]    97	GND                 45
				DRAM_addr[1]      200	nc           148	GND            96	DRAM_data(17]       44
DRAM_addr[2]      199	data[4]      147	out_data[2]    95	nc                  43
				GND               198	GND          146	out_data[3]    94	DRAM_data[18]       42
DRAM_addr[3]      197	data[3]      145	out_data[4]    93	VDD                 41
				nc                196	nc           144	out_data[5]    92	nc                  40

Table A .17.3 temporal decoder pin assignment (continuing)

The signal name pin	The signal name pin	The signal name pin	The signal name pin
				DRAM_addr[4]      195	data[2]       143	VDD                 91	DRAM_data[13]       39
VDD               194	nc            142	out_data[6]         90	DRM_data[20]        38
				DRAM_addr[5]      193	data[1]       141	out_data[7]         89	nc                  37
DRAM_addr[6]      192	data[0]       140	nc                  88	GND                 35
				nc                191	nc            139	out_extn            87	DRAM_data[21]       35
GND               190	VDD           138	GND                 86	nC                  34
				DRAM_addr[7]      189	addr[7]       137	DRAM_data[0]        85	DRAM_data[22]       33
DRAM_addr[8]      188	addr[6]       136	DRAM_data[1]        84	VDD                 32
				VDD               187	addr[5]       135	DRAM_data[2]        43	DRAM_data[23]       31
DRAM_addr[9]      186	GND           134	VDD                 82	DRAM_data[24]       30
				nc                185	addr[4]       133	DRAM_data[3]        81	nc                  29
DRAM_addr[10]     184	addr[3]       132	nc                  80	GND                 28
				GND               183	addr[2]       131	DRAM_data[4]        79	DRAM_data[25]       27
nc                182	addr[1]       130	GND                 78	nc                  25
				VDD               181	VDD           129	nc                  77	DRAM_data[25]       25
testpin           180	addr[0]       128	DRAM_data[5]        76	nc                  24
				testpin           179	enable[0]     127	nc                  75	VDD                 23
testpin           178	enaple[1]     125	DRAM_data[6]        74	DRAM_data[27]       22
				decoder_clock     177	nC            125	VDD                 73	nc                  21
nc                176	GND           124	DRAM_data[7]        72	DRAM_data[23]       20
				GND               175	testpin       123	nc                  71	DRAM_data[29]       19
in_extn           174	test pin      122	DRAM_data[8]        70	GND                 18
				in_data[8]        173	trst          121	GND                 69	DRAM Gata[30]       17
in_data[7]        172	tdo           120	DRAM_data[9]        58	nc                  16
				in_data[6]        171	nc            119	nc                  57	DRAM_data[31]       15
VDD               170	VDD           113	DRAM_data[10]       66	VDD                 14
				in_data[5]        169	tdo           117	VDD                 65	nc                  13
in_data[4]        168	tdi           116	nC                  64	WE                  12
				in_data[3]        167	tck           115	DRAM_data[11]       63	RAS                 11
in_data[2]        166	testpin       114	nc                  62	nc                  10
				GND               165	GND           113	DRAM_data[12]       61	GND                 9
in_data[1]        154	DRAM_enable   112	GND                 60	CAS[0]              3
				in_data[0]        163	test pin      111	DRAM_data[13]       59	nc                  7
in_valid          162	testpin       110	nc                  58	CAS[1]              6
				in_accept         161	testpin       109	DRAM_data[14]       57	VDD                 5

Table A .17.3 temporal decoder pin assignment (continuing)

The signal name pin	The signal name pin	The signal name pin	The signal name pin
				reset    160	nc     108	VDD        56	CAS[2]       4
VDD      159	nc     107	nc         55	nc           3
				nc       158	nc     106	nc         54	CAS[3]       2
nc       157	nc     105	nc         53	nc           1

A.17.1.1 " nc " do not link pin

The pin that indicates nc among the Table A .17.3 is currently among the present invention not use and keep for product in the future. These pins should not be connected. They should not be linked to V_DD, GND should not be connected to each other or be connected in any other signal. A.17.2V_DDWith the GND pin

All V that provide are provided as people_DDMust be linked to corresponding power supply with the GND pin. All V_DDAll need correct the use with the GND pin, otherwise device will can not move normally. A.17.1.3 the pin of general operation links test

9 pins of temporal decoder are given over to close beta and are used.

The default test pin of Table A .17.4 links

Pin number	Link
			For normal operation links ground
	For V is linked in normal operationDD
			Unsettled for working

A.17.1.4 the JTAG pin of general operation

See A.8.1 part

The guide look of Table A .17.5 temporal decoder storage image

The address	Register name	See Table
			0×00…0×01	The break in service district	A.17.6
0×02…0×07	Need not
			0×08	The chip access	A.17.7
0×09…0×0F	Need not
			0×10	Picture sequences	A.17.8
0×11…0×1F	Need not
			0×20…0×2E	DRAM interface configuration register	A.17.9
0×2F…0×3F	Need not
			0×40…0×53	Buffer configuration	A.17.8
0×54…0×5F	Need not
			0×60…0×FF	Scratchpad register	A.17.11

Table A .17.6 break in service district register

The address	The position	Register name	Page number
					0×00	7	chip_event
6：2	Need not
			1	chip_stopped_event
0	count_error_event
			0×01	7		chip_mask
6：2	Need not
				1	chip_stopped_mask
0	count_error_mask

Table A .17.7 chip access resistance

The address	The position	Register name	Page number
					0×08	7：1	Need not
0	chip_access

Table A .17.8 image sequencing

The address	The position	Register name	Page number
					0×10	7：1	Need not
0	MPEG_reordering

Table A .17.9 DRAM interface configuration register

The address	The position	Register	Page number
					0×20	7：5	Need not
4：0	page_start_length[4：0]
			0×21	7：4		Need not
3：0	read_cyc[e_length[3：0]
				0×22	7：4	Need not
3：0	write_cycle_length[3：0]
			0×23		7：4	Need not
3：0	refresh_cycle_length[3：0]
				0×24	7：4	Need not
3：0	CAS_falling[3：0]
			0×25		7：4	Need not
3：0	RAS_falling[3：0]
				0×26	7：1	Need not
0	Interface_timing_access
			0×27		7：0	Need not
0×28	7：6	RAS_strength[2：0]
			5：3		OEWE_strength[3：0]
	2：0	DRAM_data_strength[3：0]
			0×29		7	Need not
6：4	DRAM_addrstrength[3：0]
				3：1	CAS_strength[3：0]
0	RAS_strength[3]

Table A .17.9 DRAM interface configuration register (continuing)

The address	The position	Register name	Page number
					0×23	7	not usad
6：4	DRAM_addr_strengtn[3：0]
			3：1	CAS_strength[3：0]
0	RAS_strength[3]
			0×29	7：6		RAS_strength[2：0]
5：3	OEWE_strength[3：0]
				2：0	DRAM_data_strength[3：0]
0×2A	7：0	refresh_intervat
			0×2B	7：0	not used
0×2C	7：5	not used
			5	DRAM_enable
	4	no_refresh
			3：2	row_address_bits[1：0]
	1：0	DRAM_data_width[1：0]
			0×20	7：0	notused
0×2E	7：0	Test registers

Table A .17.10 buffer configuration register

The address	The position	Register name	Page number
					0×40	7：0	Need not
0×41	7：2
		1：0	picture_butter_0[17：0]
	0×42				7：0
0×43		7：0
	0×44				7：0	Need not
0×45		7：2
	1：0		picture_butter_t[17：0]
		0×46			7：0
0×47	7：0

Table A .17.10 buffer configuration register (continuing)

The address	The position	Register name	Page number
					0×48	7：0	Need not
0×49	7：1
		0	component_off set_0[16：0]
	0×4A				7：0
0×4B		7：0
	0×4C				7：0	Need not
0×4D		7：1
	0		component_off set_1[16：0]
		0×4E			7：0
0×4F	7：0
		0×50			7：0	Need not
0×51	7：1
		0	component_offset_2[16：0]
	0×52				7：0
0×53		7：0

Table A .17.11 scratchpad register

The address	The position	Register name	Page number
					0×2E	7…4	The PLL resistor
3…0
	0×50	7…6	Need not
5…4					codfng_standard[1：0]
		3…2	picture_type[1：0]
1					H251_filt
		0	H261_s_f
0×51					7…6	component_id
	5…4	prediction_mode
				3…0	max_sampting
	0×62	7…0	samp_h
0×63				7…0	samp_v

Table A .17.11 scratchpad register (continuing)

The address	The position	Register name	Page number
					0×54	7…0	back_h
0×65	7…0
			0×66	7…0	back_v
0×57	7…0
			0×68	7…0		forw_h
0×59	7…0
			0×5A	7…0	forw_v
0×5a	7…0
			0×5C	7…0		width_in_mo
0×6D	7…0

A.18 temporal decoder operation A .18.1 data input

The input FPDP of temporal decoder is a standard token port with 8 bit wide data words. In great majority were used, this will directly link to each other with the output token port of spatial decoder. Wish obtains the more information about this interface electric characteristics, referring to part A.4. A.18.2 automatically configuration

Register in the token automatic mounting angle of incidence decoder that the parameter relevant with the pixel format of encoded video produced by spatial decoder.

Table A .18.1 is through the configuration of the temporal decoder of token

Token	Configuration
		CODING_STANDARD	The coding standard of temporal decoder is configured automatically by the CODING_STANDARD token. At every turn, a new sequence is started, and produces these configurations by spatial decoder, sees Figure 58.
DEFINE_SAMPLING	Horizontal and vertical chroma samples information to each chrominance component is configured automatically by the DEFINE_SAMPLING token.
		HORIZONTAL_MBS	Horizontal width in the image of macro block is disposed automatically by HORIZONTAL_ MBS token.

A.18.3 human configuration

The user must dispose (passing through MPI) on using the parameter of deciding. A.18.3.1 when dispose

Temporal decoder should only be configured when not carrying out the data processing. Here it is at the default setting that resets after being removed. Temporal decoder can be stopped, and reconfigures to write 1 by face chip_ access register. After configuration is finished, should in chip_access, write 0.

About when disposing the details of DRAM interface, referring to part A.5.3. A.18.3.2 DRAM interface DRAM interface sequence must might predictability decoding and coding video (for example H.261 or MPEG) be configured before. See A.5 part, " DRAM interface ".

Table A .18.2 temporal decoder register

Register name	Size/direction	Reset mode	Explanation
				chip_access
	1    rw	1	For reconfiguring, chip_access is write 1, the request time decoder quits work. Temporal decoder will continue normal operation, until arrive the end of current video series. Except chip_access=1, namely decoder is stopped the time after resetting. When chip stops, produce chip and stop event. If chip_stopped_mask=1 produces interruption.
				chip_stopped _event	1    rw	0
chip_stopped _mask	1    rw	0
				count_error _event	1    rw	0	Temporal decoder has an adder, and adder is added to prediction on the misdata. If different between misdata byte number and the prediction data byte number, so miscount event produces. If count_error_mask=1 produces interruption, forming prediction will stop. This event only produces immediately following hardware error.
count_error _mask	1    rw	0
			picture buffer_0	18    rw	x	These specify the base address of image buffer
picture_ buffer_1
		18    rw	x
component_ offset_0				17    rw	x	These specify image buffer pointer offset amount, each chrominance component of storage in buffer. The data of ID=n component are to be stored as starting point by the position of component_ offset_n indication. See A.3.5.1 " component identification number ".
	component_ offset_1	17    rw	x
component_ offest_2				17     rw	x

Table A .18.2 temporal decoder register (continuing)

Register name	Size/direction	Reset mode	Explanation
				MPEG reordering
	1     rw	0	This register is set to 1, makes temporal decoder change visual order, becomes correct display order from non-causA1 MPEG image sequence. See A.18.3.5. JPEG and H.261 this register of duration of work should ignore.

A.18.3.3 the number in the image buffer register

Image buffer pointer (18) and component skew (17) register piece (8 * 8 byte) address of indication rather than a byte address. A.18.3.4 image buffer distributes

For the video of the predictability ground coding of decoding (H.261 or MPEG), temporal decoder must be managed two image buffers. Wish obtains more about how using the information of these buffers, referring to part A.18.4 and A.18.4.4.

The user must guarantee at each image buffer pointer (picture_buffer_0 and picture_buffer_1) the single image (with other image buffer not overlapping) of enough memory spaces to store a required video format arranged. Usually, in the image buffer pointer one will be set to 0 (be memory at the bottom of), and another will be set to point to the middle part of memory space. A.18.3.4.1 MPEG or a general configuration H.261

H.261 and MPEG all using one 4 between the different chrominance components: 1: 1 ratio (that is, the luminance pixel number is four times in the number of pixels in a colourity composition).

Described in A.3.5.1 " component identification number ", component 0 will be the brightness composition, and component 1 and 2 will be colourity.

A kind of example configuration of component biasing register is, component_offset _ 0 be set be 0 so that component 0 begin at image buffer pointer place. Similarly, component_ offset_1 can be set to 4/6 of image buffer size, and component_offset_ 2 can be set to 5/6 of image buffer size. A.18.3.5 image sequence is reset

MPEG uses three kinds of different visual types: inner (I), prediction (P) and two-way insertion (B). The category-B image is based on the prediction that derives from two images: a width of cloth is from the future, and a width of cloth was from the past. Picture sequences is modified at encoder, so that I and P class image can be decoded from coded data before it is required to decode the category-B image.

Image sequence must be corrected before these images can be shown. Temporal decoder can provide this image to reset (by register MPEG_reodering=1 is set). As selection, the user may wish the image rearrangement is finished as his part of display interface function. Setup time decoder with provide visual rearrangement may reduce can be decoded video resolution, referring to part A.18.5. A.18.4 prediction forms

H.261 the prediction of decoding and mpeg decode formation requirement is distinct. CODING_ STANDARD token automatic setup time of decoder is to adapt to the prediction requirement of various criterion. A.18.4.1 jpeg operation

When disposing for jpeg operation, because JPEG without any need for time decoder, does not therefore predict. A.18.4.2 H.261 operation

In H.261, prediction is only from firm decoded image. Motion vector only refers to the pixel accuracy of integer. The result that encoder will indicate a low pass filter to be used to predict.

Because every images is all decoded, it is written into an image buffer in the outer DRAM of chip, so that DRAM can be used to next image of decoding. Come across the output of temporal decoder during the DRAM of decoded image outside they are written into chip.

About the details of prediction and the mathematical operation that relates to, the reader can be with reference to standard H.261. Temporal decoder of the present invention is consistent fully with H.261 requirement. A.18.4.3 MPEG operation (not resetting)

For three kinds of different MPEG image types (I, P and B) each, the operation of clock coder changes to some extent.

The further decoding of decoder that do not take time of " I " class image, but must be stored in an image buffer (frame storage), in order in decoding P and category-B image, use in the future.

Decoding P class image need to form prediction by decoded P or I class image from a width of cloth front. Decoded P class image is stored in the image buffer to use in decoding P and category-B image. MPEG allows motion vector indication half-pixel accuracy. Wave filter provides and inserts to support this half-pixel accuracy in the chip.

The category-B image need to be from the prediction of two kinds of image buffers. Similar P class image, half picture element movement vector resolution ratio precision need interpolation on the chip of pictorial information. The category-B image is not stored in the outer buffer of chip. They are instantaneous.

All images come across the output of temporal decoder when it is decoded. Like this, image sequence will identical with its sequence in the encoded MPEG data (seeing the top of Figure 85).

About predicting details and the mathematical operation that relates to, the reader can be with reference to the mpeg standard draft that proposes. These require to be satisfied by temporal decoder of the present invention. A.18.4.4 MPEG operation (with resetting)

When be image reset the MPEG operative configuration time, (MPEG_reordering=1), the operation that forms prediction as top described in the part A.18.4.3. Yet additional data transmit and are carried out in order to reset image sequence.

The decoding of category-B image as A.18.4.3 the part described in. Yet I and category-B image are not output when they are decoded. They are written into the outer buffer (as previously mentioned) of chip, and only arrive at a follow-up I or P class image and just be read out when decoded. A.18.4.4.1 decoder starting characteristic

The output of the first width of cloth I class image is delayed, until the P of back (or I) class image begins decoding. This should be considered when estimating the Video Decoder starting characteristic. A.18.4.4.2 decoder closing property

Temporal decoder dependence back P or I class image go out buffer the chip (frame storage) with the clear picture of front except (Flush). This is making a difference with at the new video sequence of beginning the time in the ending of video sequence. Spatial decoder provides equipment, produces " puppet " P/I image to remove last P (or I) image with the ending at video sequence. Yet this " puppet " image will be eliminated when a postorder video sequence begins.

Spatial decoder provides to be selected to get rid of this " puppet " image. Knowing after Geju City sequence is moved to end and will have a new video sequence to be provided for the decoder place, this will be useful at once. The first images of this new sequence will brush last images of last sequence. A.18.5 video resolution

The video resolution that the time decoder can be supported when decoding MPEG is subject to the restriction of the memory bandwidth of its DRAM interface. For MPEG, need to consider two kinds of situations: use and reset without the MPEG image.

A.18.5.2 and A.18.5.3 part has been discussed the requirement of the required worst condition of the current draft of MPEG specification. The subset of MPEG can expect to have lower memory bandwidth requirement. For example, only use integer resolution ratio motion vector, perhaps, as selection, do not use the category-B image, can reduce significantly the memory bandwidth requirement. These subsets are not done analysis at this. A.18.5.1 DRAM interface features

The periodicity of taking by DRAM interface transmission data depends on many factors:

The DRAM interface is for adapting to the time configuration of selecting DRAM used

Data-bus width (8,16 or 32)

The type that data transmit

8 * 8 read or write

Be the prediction half-pixel accuracy

Be prediction integer pixel accuracy

About the details of DRAM interface configuration, referring to A.5 the part " DRAM interface ".

Table A .18.3 has shown how many DRAM interfaces " cycle " the data transmission for every type needs.

The data transfer time of Table A .18.3 temporal decoder

Data-bus width (position)	Read and write 8 * 8	From fallout predictor (half-pixel accuracy)	From fallout predictor (integer pixel accuracy)
				8	1 page address+64 transmission	4 page address+81 transmission	4 page address+64 transmission
16	1 page address+32 transmission	4 page address+45 transmission	4 page address+40 transmission
				32	1 page address+16 transmission	4 page address+27 transmission	4 page address+24 transmission

Table A .18.4 has adopted the numerical value among the Table A .18.3 and " typically " DRAM has been estimated them. In this example, supposed the clock of 27 megahertzes. It should be understood that although use 27 megahertzes at this, it is not as a kind of restriction. Access is initial to have occupied 11 tick marks (Tick) (102ns) and data transmit and occupied 6 tick marks (56ns). A.18.5.2 without the MPEG resolution ratio of resetting

The load of memory peak bandwidth occurs when decoding category-B image. In one " worst condition " scheme, the B frame can form by prediction, and prediction derives from 2 image buffers, and all predictions all are half-pixel accuracies.

Table A .18.4 " typical case " DRAM explanation

Data-bus width (position)	Read or write 8 * 8	From the fallout predictor half-pixel accuracy)	From fallout predictor (integer pixel accuracy)
				8	3657ns	4907ns	3963ns
16	1880ns	2907ns	2185ns
				32	991ns	1907ns	1741ns

Use for example data among the Table A .18.4 to find out, for reading two kinds of required data (by the interface of 32 bit wides) of accurate half-pixel accuracy prediction of x, the DRAM interface will spend 3815ns. The resolution ratio that temporal decoder can be supported is determined by the quantity of these predictions that can finish within a visual time. In this example, temporal decoder can be processed 8737 8 * 8 (for example, to one 30 hertz video) in single visual cycle of 33 milliseconds.

If required video format is 704 * 480, so every images comprises 7920 8 * 8 (considering the 4:2:0 chroma samples). Can find out that this video format takies about 91% (before taking into account such as factors such as DRAM refresh) of obtainable DRAM interface bandwidth. Correspondingly, temporal decoder can be supported this video format. A.18.5.3 the MPEG resolution ratio that has rearrangement

When adopting the MPEG image to reset, when decoding P class image, can run into worst case scenario. At this time, 3 kinds of loads are arranged on the DRAM interface:

Form prediction

Write back the result

Read P or the I image of front

Use is from for example numeral of Table A .18.3, and we can find in the time can obtaining the interface of 32 bit wides, each time that will spend in this work. Form prediction cost 1907ns/n, and read and write respectively to be used 991ns, is 3899ns altogether. This is so that temporal decoder can be processed 8485 8 * 8 piece within the cycle of 33ms.

Therefore, the video of processing 704 * 480 will use about 93% (ignore and refresh) that can obtain the memory bandwidth. A.18.5.4 H.261

H.261 only support two kinds of pixel formats (30 hertz of CIF (352 * 288) and QCIF (172 * 144) and visual rates. One width of cloth CIF image comprises 2376 8 * 8. Required unique memory operation is to write 8 * 8 piece and form prediction with the integer precision motion vector.

Memory interface for 8 bit wides uses from for example numeral among the Table A .18.4, can find out that writing each piece will use 3 657ns, and be that a piece formation prediction will be used 3963 ns/n, so each piece will spend 7620ns. Therefore, the processing time of each single CIF image is about 18ms, much smaller than supporting 30 hertz of 33ms that video is required. A.18.5.5 JPEG

The JPEG that can be supported " video " resolution ratio will be determined by capacity or the display interface device of spatial decoder of the present invention. Temporal decoder does not affect JPEG resolution ratio. A.18.6 event and mistake A.18.6.1 chip stop

In the present invention, for writing 1 to chip_access, require the temporal decoder shut-down operation so that reconfigure. Once be received, temporal decoder will continue normal operation, until it arrives the end of current video sequence. Then, temporal decoder is stopped.

When chip stopped, a chip stopped event and will occur. If chip_stopped _ mask=1 will have one to interrupt producing. A.8.6.2 miscount

Temporal decoder of the present invention comprises an adder, prediction is added in the misdata goes. If between the byte number of the byte number of misdata and prediction data difference is arranged, can produce so a miscount event.

If count_error_mask=1, an interruption will be produced, and the formation of prediction will stop.

Write 1 to count_error_event and just removed event, and temporal decoder is continued. Thereby the DATA token that produces that leads to errors will continue. Yet, cause that wrong DATA token will can not be correct length (64 byte). This might cause further problem. Therefore, only when having occured, a remarkable hardware error just can produce a miscount. A.19 link the output of temporal decoder

The output of temporal decoder is one to have the standard token port of 8 bit wide data words. Further information about interface electric characteristics sees also A.4 part.

Whether the token that appears at the temporal decoder output will depend on employed coding standard, in the situation of MPEG, then depend on image and be rearranged. In this part identification token which can obtain at the output of temporal decoder, and which is the most useful when showing that output at design circuit. Other token will occur, but need not to show output, therefore be not discussed at this. This part focuses on display:

How the initial sum of recognition sequence is terminal

How the initial sum of recognition image is terminal

How to identify and when show image

Where A.19.1 the JPEG how the recognition image data should be put in the demonstration exports

In decoding during jpeg data, by the sequence of tokens of temporal decoder output and the output of spatial decoder seen the same. In retrospect, JPEG when not required between the processing carried out of decoder. Yet temporal decoder testing inner data token (from the accurate result of the finite mathematics of IDCT in the spatial decoder) replaces with zero negative value.

About the further discussion of the output sequence in jpeg operation, observed, referring to part A.16. A.19.2 H.261 export the A.19.2.1 starting and ending of process

H.261 in video data, there is not the starting and ending signal in the video flowing. But, this will be implicit by using. For example, begin when telecommunications links time series, when line interruption, finish. Like this, the highest layer is " image layer " in the video system.

According to the present invention, the detector for initial code of spatial decoder so that SEQUENCE_START and CODING_STANDARD token be automatically inserted into before first PICTURE_START. A.11.7.3 and A.11.7.4 referring to.

At last (namely when circuit close) of process H.261, the user should insert a FLUSH token in the back of coded data end. This has many effects (referring to appendix A .31.1):

It has guaranteed that PICTURE_END is produced, to indicate the end of last images.

It has guaranteed that the end of coded data is pushed through decoder. A.19.2.2 the acquisition of image

The layer of each image in system is comprised of the element that is called layering. When decoding H.261, reflect this structure in the sequence of tokens of temporal decoder output. A.19.2.1 visual layer

There is a PICTURE_START token each visual front, and the back is followed by a PICTURE_END token. H.261 do not comprise originally that an image finished. This token is to insert by the detector for initial code of spatial decoder is automatic.

Behind the PICTURE_START token, TEMPORAL_REFERENCE and PICTURE TYPE token will be arranged. The TEMPORAL_REFERENCE token carries 1 figure place (wherein only having 5 lowest orders (LSB) to be used) in H.261, when this number indication image should be shown, this should be considered by any display system, because H.261 encoder may omit image (to realize lower data transfer rate) from sequence. Because time mark has increased between two consecutive images not only No. one, the omission of image can be detected.

Next step, the PICTURE_TYPE token carries the information about pixel format. One display system can consider that this information is to check that whether CIF or QCIF image are just decoded. Yet, also can obtain by the register in the research Huffman decoder about the information of pixel format. (please refer to Huffman decode four parts) be piece layer group A.19.2.2.2

Every width of cloth H.261 image is made of a large amount of " piece group ". There is a SLICE_START token (by H.261 group number and group initial code obtain) each front in them. This token carries one 8 value, and where this 8 place value indicator collet group should be placed in the demonstration. This just makes its secondary synchronization again after error in data for decoder provides a chance. In addition, do not need additional information to describe their image region if having, aforesaid way also provides a kind of gimmick of jumping piece for encoder. When SLICE_START decoder time of advent output, this information just becomes very unnecessary, because spatial decoder and temporal decoder have used this information to guarantee every images and comprise correct piece number and these pieces are in correct position. Therefore, only by calculating the number of the piece that has been output after the initial beginning of image, just might calculate and place wherein the data block of being exported by temporal decoder.

The number that is carried by SLICE_START is than the piece number of group H.261 little by 1 (about more information, referring to H.261 standard). Figure 94 has shown in CIF and QCIF image the H.61 location of piece group. Attention: in the present invention, shown block number is identical with the number that is carried by SLICE_START. Be different from H.261 convention for these groups of numbering.

Between SLICE_START (it indicates the initial of each piece group) and the first macro block, also other token may be arranged. These can be ignored, because subsequently displaying transmitted image data does not need them. A.19.2.2.3 macroblock layer

Macroblock sequence in each piece group is by H.261 definition. There is not the special token information of describing each macro block position. The user should calculate by macroblock sequence, determines to show wherein each bar information.

Figure 96 has shown the order that macro block is placed in each piece group.

Each macro block comprises 6 data tokens. Per 6 one group DATA token sequentially is by H.261 macroblock structure is defined. Each DATA token should comprise 64 data bytes just for 8 * 8 pixel areas of a single chrominance component. Chrominance component is carried (referring to A.3.5.1) by 2 figure places in the DATA token. Yet the order of chrominance component is defined in H.261.

Before each group DATA token a large amount of tokens are arranged, these token communications are about the information of motion vector, quantization scaling factor etc. Show that image does not need these tokens, therefore can be left in the basket.

Each DATA token comprises 64 data bytes to its single chrominance component of 8 * 8. Deposit with raster order. A.19.3 MPEG output

Have more multi-layered in the system of MPEG. They are accepted such as video sequence and group of picture. A.19.3.1 MPEG sequence layer

A sequence can have a plurality of entrances (sequence is initial), but should only have an exit point (EOS). Decoded when the heading code of a MEPG sequence, spatial decoder produces a CODING_STANDARD token, is thereafter a SEQUENCE_START token.

After SEQUENCE_START, the token of a large amount of sequence-header information will be arranged, their explanation video formats etc. About the information of indication in the sequence-header, referring to the mpeg standard draft; How to be converted into the information of token about these data, referring to Table A .3.2. The information of this explanation video format also can obtain in the register in the Huffman decoder.

If a MPEG sequence has several entrances, this sequence standard information can occur several times in this sequence. A.19.3.2 the image layer is organized

MPEG group of picture provides dissimilar " entrance " points in that sequence is initial. Sequence-header provides the information about image/video format. Correspondingly, if decoder is not known the video format that uses in the sequence, it must begin at a sequence section start, yet, in case video format is configured into decoder, should in any one group of picture, begin decoding.

MPEG is not limited in visual number in the group. Yet in the middle of many application, a group was corresponding to about 0.5 second, because it provides random-access reasonable unit.

The initial of one picture group elephant indicated by a GROUP_START token. The header that provides after GROUP_START comprises two kinds of useful token: TIME_CODE and BROKEN_ CLOSED.

TIME_CODE carries a subset of smpte time code information. This is useful making in the middle of Video Decoder and other signal synchronization. BROKEN_CLOSED carries MPEG closed_gap and broken_link position. About the more information of the enforcement of arbitrary access and the video sequence edited of decoding, can be referring to A.19.3.8. A.19.3.3 visual layer

The initial indication by the PICTURE_START token of the new image of one width of cloth. After this token, TEMPORAL_REFERENCE and PICTURE_TYPE token will be arranged. If temporal decoder is not to dispose in order to provide image to reset, time tag information may be useful. If display system is wished the initial special treatments B class image at an open GOP, visual type information may be useful (seeing A.19.3.8).

Each image consists of by many. A.19.3.4 lamella

A.19.2.2.2 employed group in having discussed H.261. Sheet among the MPEG plays similar effect. Yet chip architecture is not determined by standard, and the 8 place values ratio that is carried by the SLICE_START token is little by 1 with " the sheet upright position " of MPEG communication. About the explanation of lamella, referring to the mpeg standard draft.

When the output of the SLICE_START decoder time of advent, this information function is unnecessary, because spatial decoder and temporal decoder have used this information to comprise the piece of correct number in correct position to guarantee each images. Therefore, only by count the quantity of the piece that has been output after image begins, where the data block that just should calculate temporal decoder output places.

About using the discussion of the effect that the MPEG image resets, referring to A.19.3.7. A.19.3.5 macroblock layer

Each macro block comprises 6 pieces. They appear at the output (pointed such as MPEG specification draft) of temporal decoder with raster order. A.19.3.6 piece layer

Each macro block comprises 6 DATA tokens. Each contains in the group of 6 tokens, and the sequence of DATA token is by MPEG specification draft defined (this with H.261 macroblock structure is identical). To a single chrominance component, each data token should comprise at 8 * 8 pixel area lucky 64 data bytes. Chrominance component is carried (seeing A.3.5.1) by 2 figure places in the DATA token. Yet the chrominance component sequence among the MPEG is defined.

Before each group DATA token a large amount of tokens are arranged, these tokens are to carrying out communication about the information of motion vector, quantization scaling factor etc. Show that image does not need these tokens, so they are left in the basket. A.19.3.7 the MPEG image effect of resetting

Described in A.18.3.5, temporal decoder can be configured to provide the MPEG image to reset (MPEG_reordering=1). The output of P and I class image is delayed, until temporal decoder begins next the P/I image in the decoded data stream. At the output of temporal decoder, replace the DATA token of the P/I image of new decoding from the DATA token of old P/I image.

When resetting the P/I image, outside image is written into chip during image buffer, visual PICTURE_START, TEMPORAL_REFERENCE and PICTURE_TYPE token temporarily are stored on the chip. When image was read out to show, the token of these storages was resumed. Correspondingly, the P/I image of rearrangement has correct PICTURE_START, TEMPORAL_ REFERENCE and PICTURE_TYPE value.

All other tokens below the image layer are not rearranged. When the P/I image after resetting was read out to show, it picked up the non-DATA token of low level of the image that just has been rearranged. Thereby the token of these image subsection layers should be left in the basket. A.19.3.8 arbitrary access and editor's sequence

Spatial decoder provides equipment to help carrying out correct video decode for the video data of the MPEG video data behind the editor and formation after arbitrary access. A.19.3.8.1 open GOP (Open Gops)

One group of picture (GOP) can be with the beginning of category-B image, and this B image is to be got by the prediction of the image of the P class among the previous GOP, and this is called " Open GOP ". Figure 107 is illustrated it. Figure 17 and 18 is B images that second GOP begins. If GOP is open to the outside world, encoder may use from the prediction of P image 16 and I image 19 this two images is encoded so. As selection, encoder also can be limited to the prediction of only using from I image 19. In this case, second GOP is one " closing GOP ".

If a decoder just begins video decode at first GOP, when running into second GOP, it will not have any problem, even GOP is open. The P image 16 because it has been decoded. Yet if decoder has carried out an arbitrary access and begun decoding at second GOP, its can not decode B17 and B18 is if these two images are (that is to say, if GOP is open) that rely on P16.

If first GOP that spatial decoder of the present invention runs into after once resetting is open GOP, perhaps it receives a FLUSH token, and it will suppose an arbitrary access to opening GOP has occured. In this case, the Huffman decoder will be take general fashion as B the image usage data. Yet it will export the B image of predicting with (0,0) motion vector outside the I image. The result will be that visual B17 and B18 (going up in the example) will be identical with I19.

This specific character has guaranteed the work of MPEG VBV rule. Simultaneously, it has guaranteed that the B image is present in the output, and is in the desired position of other data channel in output stream. For example, the mpeg system layer provides the displaying time information that voice data and video data are interrelated. Video displaying time mark refers to the shown image of first width of cloth in a GOP, and namely the time benchmark is 0 image. In the above example, first width of cloth after second GOP carried out arbitrary access shows that image is B17.

The BROKEN_CLOSED token carries MPEG closed_gop position. Therefore, can judge at the output of temporal decoder, the B image of output is genuine or spatial decoder is introduced " substitute ". In some applications, when " substituting ", these may wish to take some special measurement when image occurs. A.19.3.8.2 the video of being edited

If an application is edited a MPEG video sequence, it may interrupt two contacts between the GOP. If GOP is an open GOP after editor, it can not be correctly decoded the B image that is positioned at the GOP section start. After editor, the application of editing MPEG data can arrange broken_link among the GOP with the indication decoder its these B image of can not decoding.

If spatial decoder runs into a GOP with a binding that has been interrupted, Huff-man decoder will be take general fashion as B image decoding data. Yet it will export the B image of predicting with (0,0) motion vector outside the I image. The result will be. Image B17 will be identical with I19 with B18 (in upper example).

The BROKEN_CLOSED token carries MPEG broken_link position. Therefore, just might judge that at the output of temporal decoder the B image of output is really or by spatial decoder to introduce " substitute ". When " substituting " image occurring, some application may wish to take some special measurement. A.20 write late DRAM interface (Late Write DRAM Interface)

Interface can dispose with two kinds of methods:

The detailed timing of interface can be configured to adapt to multiple different DRAM type.

" width " of DRAM interface can be configured to price/Performance Ratio of providing superior.

Table A .20.1 DRAM interface signal

Signal name	I/O	Explanation
			DRAM data [31：0]	Enter/go out	The DRAM data/address bus of 32 bit wides. Optional this bus can be configured to 16 or 8 bit wides.
DRAM_addr [10：0]	Go out	22 bit wide DRAM interface IP addresses are the timesharing multichannels on 11 bit wide buses.
			RAS	Go out	The DRAM rwo address strobe signals.
CAS[3：0]	Go out	The DRAM column address gating signal, each byte of the data/address bus of interface provides a signal. All CAS signals are simultaneously driven.
			WE	Go out	DRAM writes enable signal.
OE	Go out	DRAM output enable signal.
			DRAM_ enable	Enter	When input signal when low, make that all output signals are high impedance on the interface, the DRAM interface is stopped action.

Table A .20.2 DRAM interface configuration register (continuing)

Register name	Size/direction	Reset mode	Explanation
				modify_ DRAM_ timing	1 bit  rw	0	This function allows the addressable DRAM interface of register timing configured register. When this register keeps null value, should not revise. This register is write 1, revise this configuration register with regard to request access. Zero write this register after, the DRAM interface will be brought into use the new value in the visual configuration register.
page_start _length	5 bit  rw	0	Specify the initial length of access take tick as unit, what this minimum of a value can be used was 4 (representing 4 ticks). 0 selects maximum length 32 ticks.
				read_cycle _length	4 bit  rw	0	Specify the soon length of page or leaf read cycle with ticks, available minimum of a value is 4 (i.e. 4 tick). 0 selects the maximum length of 16 ticks.
write_cycle _length	4 bit  rw	0	Specify the rear write cycle time length of fast page or leaf with ticks, available minimum of a value is 4 (representing 4 tick) 0 to select the maximum of 16 ticks.
				refresh_ cycle_ length	4 bit  rw	0	With the length of ticks specified refresh period, its available minimum of a value was 4 (representing 4 ticks), and 0 selects the maximum of 16 ticks.
RAS_falling	4 bit  rw	0	Specify in after the access starting, it was 4 (representing 4 ticks) that the available minimum of a value of this ticks number is specified in RAS decline, and 0 selects the maximum length of 16 ticks.

Table A .20.2 DRAM interface configuration register (continuing)

Register name	Size/direction	Reset mode	Explanation
				CAS_faliing
	4 bit  rw	8	In the starting read cycle, after the write cycle time, perhaps specify this tick number after the CAS decline access starting. Available minimum of a value was 1 (representing 1 tick), and 0 selects the maximum length of 16 ticks.
				DRAM_data _width	2 bit  rw	0	Appointment is used in DRAM interface data bus DRAM _ data[31:0] on figure place. See A.20.4.
row_address _bits	2 bit  rw	0	Appointment is used in the figure place of the row address part on the DRAM interface IP address bus. See A.20.5.
				DRAM_enable	1 bit  rw	1	To this register value of writing 0, force the DRAM interface to enter high-impedance state. If the DRAM_enable signal is low or zero having write in this register, then 0 will from then on read in the register.
refresh interval	8 bit  rw	0	This value specify 16 decode clock cycles be cycle unit refresh with during the interval. The scope of value is configurable 1 ... in 255. Value 0 automatic loading after resetting, and force the DRAM interface continue to carry out the refresh cycle until after an effective refresh interval was configured to reset, refresh_interval should dispose once at every turn.
				no_refresh	1 bit  rw	0	To this register value of writing 1, prevent the execution of any refresh cycle.

Table A .20.2 DRAM interface configuration register (continuing)

Register name	Size/direction	Reset mode	Explanation
				CAS_ strength
	3 bit  rw	6	The output that these 3 bit registers arrange the DRAM interface signal drives intensity. Allow the various different loads of interface configuration. See A.20.8.
				RAS_ strength
addr_ strength
				DRAM_data_ strength
OEWE_ strength

A.20.1 interface timing (tick marks)

In the present invention, the DRAM interface is regularly from a clock, and this clock is with the speed operation (decoder_clock) of the input clock rate that is four times in equipment. This clock is produced by PLL on the chip.

For for simplicity, the cycle of this high-frequency clock is called as tick marks (tick). A.20.2 interface operation

Interface uses the DRAM fast page-mode of determining. Three kinds of dissimilar accesses can be supported:

Read

Write

Refresh

Each reads or writes access and transmits a string pulse between 1 to 64 byte of a single DRAM page address. In a single access, the transmission of read and write does not mix mutually. For a new DRAM page, each consecutive access is all treated with an arbitrary access. A.20.3 access structure

Each access is made of two parts:

Access begins

Data transmit

Each time access is with an initial beginning of access, follows thereafter one or more data transfer cycles. In the access initial sum data transfer cycles any one has reading and writing and refreshes.

In the ending that last data of primary access transmit, interface enters its default setting and keeps this state, until beginning is prepared in a new access. Finish the preparation that beginning has been carried out in stylish access if work as last access, so new access will begin immediately. A.20.3.1 access starting (Access start)

The access starting provides the page address for reading or writing to transmit, and sets up some initial signal condition. Three kinds of different access startings are arranged:

Read starting

Write starting

Refresh starting

In each case, RAS and row address sequential are all by RAS_falling and the control of page_ start_length register. OE and DRAM_data[31:0] state will remain to RAS from the end that upper data transmit always and become low level. The difference of three kinds of different initial types of access only is they are how to drive OE and DRAM_ data[31:0 when RAS is in low level]. Referring to Figure 109.

Table A .20.3 accesses start-up parameters

Number	Characteristic	Minimum of a value	Maximum	Unit	Note
							38	RAS preliminary filling by register RA S_falling setting	4	16	tick
39	Access duration of starting by register paqe_start_lenqth setting	4	32
					40	CAS pre-charging time by register CAS_falling setting	1	16	a
41	Fast page or leaf read cycle length by register read_cycle_Length setting	4	16
					42	Fast page or leaf write cycle time length by register write_cycle_Length setting	4	16
43	Tick of WE decline after CAS
					44	By register refresh_cycle refresh cycle length is set	4	16

A, this value must refresh generation to guarantee CAS less than RAS_falling before RAS. A.20.3.2 data transmit

Three kinds of dissimilar data transfer cycles are arranged:

The quick page read cycle

Write cycle time behind the quick page

Refresh cycle

One is refreshed initial back a refresh cycle is only arranged. Reading (or writing) initial back for one can follow one or more quick pages and read (or writing) cycle.

In the beginning of read cycle CAS, RAS is driven to high level, and new column address is driven.

Write cycle time is used after one. WE is driven to low level than the slow label of CAS. The output data are more driven than the slow tick marks in address (Tick).

Owing to be refreshed initial initialization of cycle at the CAS of RAS before the refresh cycle, within the refresh cycle, do not exist interface signal effective. The purpose of refresh cycle is to reach the required minimum RAS low-level period of DRAM. A.20.3.3 interface default setting

In the ending of primary access, interface signal enters a default setting:

RAS, CAS and WE high level

Data and OE keep its original state

Addr keeps stable A.20.4 data-bus width

Two bit register DRAM_data_width so that the width in DRAM interface data path can be configured. This is so that the price of DRAM is minimum when it is worked with little pixel format.

Table A 20.4 arranges DRAM_data_width

DRAM_data_width

		0 a	To DRAM_data (31:24) 8 bit wide data/address bus
1	To DRAM_data (31:16) 16 bit wide data/address bus
		2	To DRAM_data (31:0) 32 bit wide data/address bus

A, the default value after resetting

B, obsolete signal keep A.20.5 address bit of high impedance

One 24 address is produced at chip. How this address is used to form the row and column address depends on the width of data/address bus and the figure place of selecting for row address. Some configuration does not allow to use all internal address bit (and therefore generation " hidden bit ").

Row address is extracted out from the mid portion of address. This speed that DRAM is refreshed naturally is maximum. A.20.5.1 low level column address bit (Low order column address bits)

Low 4 to 6 of column address is used to provide the address for the fast page mode that reaches 64 bytes transmits. Control transmits the width (seeing A.20.4) that required address size depends on data/address bus. A.20.5.2 row address bit

The number of the position of taking out from the mid portion of 24 home addresses, be used for providing row address is disposed by register row_address_bits.

Table A .20.5 arranges row_address_bits

row_address_bits	Row address is wide
		0	9
1	10
		2	11

The width of employed row address will depend on employed DRAM type, and whether the MSB of row address is decoded with a plurality of bodies of access DRAM outside chip.

Attention: row address is that the middle of address extracted out internally. If some of row address is decoded to select the DRAM body, all probable values of these " body is selected the position " must be selected a DRAM body so. Otherwise the cavity will appear in address space.

Table A .20.6 selects the value of row_address_bits

row_adCress_bits	Row address bit	Body is selected	The DRAM size
				0	DRAM_addr[3：0]		255k
1	DRAM_addr[8：0]	DRAM_addr[9]	256k
				DRAM_addr[9：0]		512k
	DRAM_addr[9：0]		1024k
				2	DRAM_addr[3：0]	DRAM_addr[10：9]	256k
DRAM_addr[9：0]	DRAM_addr[10]	512k
			DRAM_addr[9：0]		DRAM_addr[10]	1024k
DRAM_addr[10：0]		2043k
			DRAM_addr[10：0]			4096k

A.20.6 DRAM interface enable

There are two kinds of ways can make all signals on the DRAM interface become high impedance. DRAM_ enable register and DRAM_enable signal. Register and signal all must be that logic is 1 could move for the DRAM interface. If any one is low level, interface just becomes high impedance so, and is ended by the data transmission that interface carries out.

It is in order to make other parts can test or use the DRAM that is controlled by spatial decoder (or temporal decoder) when not being used at spatial decoder (or temporal decoder) that the ability that makes the DRAM interface take high impedance is provided. Normally in service, do not wish that other parts share memory. A.20.7 refresh

The DRAM interface will refresh DRAM with CAS automatically within the intermittent phase that is determined by register refresh_interval, unless owing to writing register no_refesh it can not be done like this.

Value in the refresh_interval indicated in a stage with 16 decoder_ clock cycles, the interval between the refresh cycle. Can dispose from 1 to 255 value. After resetting, 0 value is forced the DRAM interface to carry out the refresh cycle constantly (in case can carry out), until a legal refresh interval is configured by automatic loading. Suggestion is only disposed once refresh_interval after resetting at every turn. A.20.8 signal strength signal intensity

The output of DRAM interface drives intensity and can be disposed by the user, uses 3 bit register CAS_strength during configuration, RAS_strength, addr_strength, DRAM_data_ strength, OEWE_strength. The value of the highest significant position of this 3 place value is selected fast or border rate at a slow speed. Two lower outputs to different loads electric capacity of validity are configured.

Default intensity after resetting is 6, and it disposes output, if load is 12pF, and GND and V_DDBetween the driving signal be approximately 10ns.

Table A .20.7 output intensity arranges

Intensity level	Drive characteristic
		0	When load is 6pf near 4ns/v
1	When load is 12pf near 4ns/v
		2	When load is 24pf near 4ns/v
3	When load is 48pf near 4ns/v
		4	About 2ns/v when load is 6pf
5	About 2ns/v when load is 12pf
		6a	About 2ns/v when load is 24pf
7	About 2ns/v when load is 48pf

A, rear default value resets

When an output by the load of its driving by general arrangement, it will meet the AC electrical characteristics that Table A .20.n points out in A.20.12. In configuration when appropriate, each output all with its load approximate match, thereby after the signal conversion minimum overshoot will appear. A.20.9 after resetting

After resetting, DRAM interface configuration register will all reset to their default value. In these default configurations the most meaningfully:

The DRAM interface is made can not and to be allowed to become high impedance

Refresh interval newly is configured to particular value 0, and it means lasting the execution refresh cycle after interface is enabled again.

The DRAM interface is provided as it and disposes the most slowly.

Most of DRAM need to be had 100 μ s to " time-out " between the 500 μ s at power supply after applying first before can carrying out general operation, be thereafter many refresh cycles.

After resetting, the DRAM interface remains static immediately, until DRAM_enable register and DRAM_enable signal are set up. After these are set up, the DRAM interface will be carried out the refresh cycle (every approximately 400ns once decides on employed clock frequency), until the DRAM interface is configured.

The user should be responsible for guaranteeing DRAM after energising " time-outs " and enabling after the DRAM interface time enough is arranged, to guarantee before the data transmission, to have the refresh cycle appearance of required number.

After affirmation resetted, the DRAM interface can not refresh DRAM. Yet decoder chip is enough lacked required resetting time, reset them before therefore should disappearing in the content of DRAM, then again enables the DRAM interface. This may need in debugging (debugging) process.

Table A .20.8 maximum rating

Symbol	Parameter	Minimum of a value	Maximum	Unit
					V DD	Supply voltage relatively	-0.5	6.5	V
V IN	Any pin input voltage	GND-0.5	V DD+0.5	V
					T A	Operating temperature	-40	+85	℃
T S	Storage temperature	-55	+150	℃

Table A .20.9 DC condition of work

Symbol	Parameter	Minimum of a value	Maximum	Unit
					V DD	Supply voltage relatively	4.75	5.25	Voltage
GND	Ground
			0	0	Voltage
V IH	Input logic 1 voltage					2.0	V DD+0.5	Voltage
		V IL	Input logic 0 voltage	GND-0.5	0.8				Voltage
T A	Operating temperature					0	70	℃ temperature

A, with the crossflow of TBA wire feet per minute clock

Table A .20.10 DC electrical characteristics

Symbol	Parameter	The minimum of a value maximum	Unit
				V OL	Output logic " 0 " voltage	0.4	V a
V OH	Output logic " 1 " voltage	2.8	V
				l O	Output current	±100	μA b
l OZ	Output disabled leakage current	±20	μA
				l LZ	The input leakage current	±10	μA
l DO	The RMS source current	500	mA
				C DN	Input capacitance	5	pF
C OUT	Output/IO electric capacity	5	pF

A, AC parameter V_OLmax=0.8V is designated as measuring level

B, this is the stable state driving force of interface, and immediate current can be much larger. A.20.10.1 AC characteristic

Table A .20.11 is poor to the nominal value of gating

Number	Parameter	Minimum time	Maximum time	Unit	Note
							45	Cycle time, routine tPC	-2	-2	ns
46	Cycle time, routine tRC	-2	+2	ns
						47	High impulse such as tRP, tCP, tCPN	-5	+2	ns
48	Low pulse such as tRAS, tCAS, tCAC, tWP, tRASP, tRASC	-11	+2	ns
						49	Cycle time is such as tACP/tCPA	-8	+2	ns

A. the driving intensity of signal must be configured to adapt to its load.

Two gatings of Table A .20.12 ask the poor of nominal value

Number	Parameter	Minimum time	Maximum time	Unit	Note
						50	Be strobed into the time-delay between gating, such as tRCD, tCSR	-3	+3	ns
51	The low level retention time, such as tRSH, tCSH, tRWL, tCWL, tRAC, tOAC/OE, tCHR	-13	+3	ns
						52	Be strobed into preliminary filling such as the tCRP of gating, tRCS, tRCH tRRH, tRPC	-9	+3	ns
In DRAM between any two CAS signals the pulse of CAS preliminary filling for example tCP or RAS rise with CAS decline between preliminary filling, such as tRPC	-5	+2	ns
					53		Preliminary filling before forbidding is tRHCP/CPRH for example	-12	+3	ns

The driving intensity of a, 2 signals must be configured to adapt to their load. B.1 B.1.1 detector for initial code (Start Code Detector) is summarized

As shown in Figure 11, detector for initial code (SCD) is first piece in the spatial decoder as front. Its main application is to detect MPEG in input traffic, and JPEG and initial code are H.261 also replaced them with appropriate token. It also allows the user to access input traffic by MPI, and finishes pre-formatting and " arrangement " (tidying up) token data stream. Remember that detector for initial code both can be accepted unprocessed byte data or the data that have been assembled into the token form.

MPEG, H.261 the typical initial code with JPEG is respectively 24,16 and 8 bit widths. Detector for initial code reads by byte the input data, and no matter these data are come or come from token/byte port from MPI (upi), and make the displacement of input data by three shift registers. First register is 8 parallel-by-bit input string line outputs. Second register programmable length is 16 or 24, and here initial code is detected. The 3rd register width is 15, is used for data are reformated into 15 token. Also have two " mark " shift registers (SR) and the second and the 3rd shift register parallel running. Whether these registers comprise mark has off-position good to indicate in the data register. The byte that arrives is not the part of data token, and detector for initial code can not be identified them. These bytes are allowed to walk around shift register, and are output when all three shift registers are eliminated (clearancen), and these contents successfully are output. The non-data token that is identified is used for disposing detector for initial code, skips trap, or sign is set. They also walk around shift register, and by not output with changing. B.1.2 main circuit block

The hardware of detector for initial code comprises 10 state machines (State machines). B.1.2.1 input circuit (scdipc.sch.iplm.M)

Input circuit has three kinds of modes of operation: token, byte and MPI. These modes allow data with any following form input: as a unprocessed byte stream (but still using two line interfaces), input by MPI as token streams or by the user. In all cases, input circuit produces the data token head in suitable place, so it always exports correct data token. Be transformed into the MPI mode or be transformed into alternate manner from the microprocessor mode synchronous with system clock. MPI can be forced to wait for, until a point of safes in the data flow just obtains access after arriving. The byte mode pin determines that input circuit is in the token mode or in byte mode. In addition, under arbitrary mode of three kinds of modes, can accomplish that reporting system is about to any standard decoding when beginning. (therefore can produce a CODING_STANDARD token). B.1.2.2 token decode device (scdipnew.sch, scdipnem.M)

The token that this piece decipher arrives is also given an order to other piece.

B.1.1, the input token that table is identified

The input token	The order of sending	Note
			Empty	Wait for	Sky is removed
Data	Normally	Next byte first shift register of packing into
			Coding _ standard	Walk around	Brush clear shift register, fill, export and be transformed into bypass mode. CODING_ STANDARD register is loaded
Brush is clear	Walk around	With filling the clear shift register of brush, export and be transformed into bypass mode
			Other (token that can not identify)	Walk around	With filling the clear shift register of brush, export and be transformed into bypass mode

Annotate: after shift register is brushed clearly, the change of coding standard will be sent to all pieces by two line interfaces. Guaranteed like this to occur in the whole detector for initial code on certain correct point from the change that data flow to another data flow. This principle is applicable to whole explanation, so the change of coding standard can be flow through whole chip before new stream. B.1.2.3 JPEG (scdjpeg.sch scdjpegm.M)

Initial code among the JPEG (sign) is very different, so that JPEG has a state machine that belongs to it fully. In this invention, this state machine is processed the detection of JPEG sign, length computation/checks, and clear data and wait whole work. The JPEG that is detected sign is marked as initial code (text that sees below with v_not_t-), and goes out of use (overridden) and be forced to bypass from the order that scdipnew comes. The most handy code is described its mechanism.

              switch(state)

              {

               case(LOOKING)：

                if(input＝0×fT)

                {

                 state＝GETVALUE；/*Found a marker*/

                 remove；/*Marker gets removed*/

              }
				<!-- SIPO <DP n="357"> -->
				<dp n="d357"/>
             state＝LOOKING；
         break；
         case(GETVALUE)；
           if(input＝＝0×ff)
           {

             state＝GETVALUE；/*Overlapping markers*/

             remove；
           }
             else if(input＝＝0×00)
             {
               state＝LOOKING；/*Wasn′ta marker*/

               insert(0×ff)；/*Putthe 0×ff back*/
            }
          else
          {

           command＝BYPASS；/*overTide command*/

            if(lc)/*Does the marker have a length count*/

               state＝GETLC0；

             else

               state＝LOOKING；
         break；
         case(GETLC0)：

          loadlc0；/*Loadthe top length count byte*/

          state＝GETLCI；

          remove；
        break；
				<!-- SIPO <DP n="358"> -->
				<dp n="d358"/>
              case(GETLCI)
               loadlc1；
               remove；
               state＝DECLC；
             break；
             case(DECLC)：
               lcnt＝lcnt_2
               state＝CHECKLC；
             break；
             case(CHECKLC)：
               if(lcnt＝＝0)

                  state＝LOOKING；/*No moreto do*/
                elseif(lcnt＜0)

                  state＝LOOKING；/*generate Illegal_Length_Error*/
                else
                state＝COUNT；
              break；
              case(COUNT)：
                decrement length count untill 1
                if(c＜＝1)
                   state＝LOOKING；
            }

B.1.2.4 input shift unit (scinshft.sch, scinshm.M)

The basic role of this piece is very simple. The byte that it fetches data from input circuit, its shift register of packing into, output after the displacement. Yet, it also obeys the order of input decoder, and process conversion (clear other shift register of brush) from the alternate manner to the bypass mode or from the bypass mode to the alternate manner: when receiving a bypass order, not the halfbyte shift register of packing into is arranged. And " rubbish (rubbish) " (tag=1) shifted out, make any data that keep in other shift register be forced to output. Then this piece is waited for " brushing clearly " signal, and this signal indicates this " rubbish " and appeared at the token reconstructor. So the input byte directly passes to the token reconstructor. B.1.2.5 detector for initial code (scdetect.sch, scdetm.M)

This piece comprises two shift registers, and initial code detects logic and " effectively content " detects logic. The width of two shift registers is programmed for 16 or 24. The MPEG initial code requires whole 24, and H.261 only requires 16.

In the present invention, first shift register is used for data. Second shift register carries sign. These signs show in the data shift register everybody whether effectively-very close to each other and stop (on the meaning of two line interfaces) in shift register. But when they were just clear by brush, the position that they comprise can be invalid (rubbish). When detecting an initial code, some positions of sign shift register are set up, and are invalid in order to make the content of detector shift register.

Only all just can detect initial code effectively the time in all the elements of shift register. The initial code that non-byte align is good can be detected and be made mark. In addition, when detecting an initial code, overlapping initial code by verification before, this initial code can not be identified definitely. In order to realize this function, " value " of the initial code that is detected (following a byte after initial code) is shifted, and directly passes through scinshift, and scdetect enters scoshift. Because it arrives scoshift and does not remove to detect another initial code, overlapping initial code is eliminated. This initial code just is identified as effective initial code. B.1.2.6 export shift unit (scoshift.sch, scoshm.M)

The basic role of output shift unit is to get serial data (and mark) from scdetect, data is made up (pack) and becomes 15 words and output. Other function is: data stuffing (Data padding) B.1.2.6.1

Output is comprised of 15 words, but input can be any digit. So in order to brush clearly (flush), need to increase figure place and make last word reach 15. These extra positions are called filling, and they must and be removed by the identification of Huffman (Huffman) piece. Filling is defined as:

After last position of data, to insert one " zero ", the back forms one 15 word along with abundant " 1 ".

Comprise data word when output of filling with a low extension bits, show that it is the ending of data token. B.1.2.6.2 " brush clearly " generation (flushed)

According to the present invention, the effect that produces " brushing clearly " signal comprises that detecting all shift registers is all brushed the clear moment, and input shift register is signaled. " rubbish " that inserts when the input shift unit reaches the terminal point of output shift unit, and Output Shift Register just produces " brushing a clearly " signal when having finished its filling. Before the input shift unit can enter safely bypass mode, this " brushes clearly " signal must pass through the token reconstructor. B.1.2.6.3 the effective sign of initial code

If scdetect shows that it has found an initial code, filling is done, and current data is output. The value of initial code (next byte) is shifted by detector, to eliminate overlapping initial code. If when this " value " reaches the output shift unit, do not detect other initial code, then it is not superimposed. This value will with the output of v_not_t (ValueNot.Token) sign, be an initial code value to show it. But, as when the output shift unit is just being waited for this value, detect another initial code (detecting with scdetect), then produce one overlapping initial (overlapping_start_error) mistake. In the case, first value is cancelled, and system waits for second value subsequently. Second value also may be superimposed. Repeat so above step, until find a underlapped initial code. B.1.2.6.4 the later housekeeping of initial code

After having detected and exported a good initial code, when data (not being rubbish) when beginning to arrive, produce a new data head. B.1.2.7 data flow reconstructor (sctokrec.sch, sctokrem.M)

The data flow reconstructor has two-wire interface input: input from scinshift for the token of bypass for one, another is for data splitting and open and begin yard to input from scoshift. When only having current token (any from two sources) to be done (low extension bits arrives), just allow between two sources, to exchange. B.1.2.8 initial value converts starting symbol (scdromhw.sch, schrom.M) to

The step that initial value is transformed to token was divided into for two steps. This piece is mainly processed the problem that relies on coding standard, and it reduces to 16 call numbers that have nothing to do with coding standard to more than 520 possible codes.

As previously mentioned, the different of initial value (initial value that comprises JPEG) and all other numerical value are in mark (value_not_token). Be high such as v_not_t, this piece just is transformed to 4 starting symbols that have nothing to do with standard to 4 or 8 place values according to CODING_STANDARD, and any unrecognized initial code is made sign.

It is as follows that initial code number is listed:

Show B.1.2 initial code number (index)

Initial/flag code	Index	Token as a result
			not_a_start_code
	0
			sequence_start_code	1	SEQUENCE_START
group_start_code
		2	GROUP_START
picture_start_code
		3	PICTURE_START
slice_start_code
		4	SLICE_START
user_data_start_code
		5	USER_DATA
extension_start_code
		5	EXTENSION_DATA
sequence_end_code
		7	SEQUENCE_END
Jpeg marker
			DHT
	8	DHT
			DQT
	9	DOT
			DNL
	10	DNL
			DRI
	11	DRI
			Can be mapped to the JPEG mark of MPEG/H.251 token
SOS	picture_start_code	PICTURE_START
			SOI	seqUence_start_code	SEOUENCE_START

Show B.1.2 initial code number (index)

Stan/Marker Code	lndex(start_number)	Resulting Token
			EOI	sequence_end_code	SEQUENCE_END
SOFO	group_start_code	GROUP_START
			Produce the jpeg marker of expansion or user data
JPG	extension_start_code	EXTENSION_DATA
			JPGn	extension_start_code	EXTENSION_DATA
APPn	user_data_start_code	USER_DATA
			COM	user_data_start_code	USER_DATA
Annotate: all unrecognized jpeg markers produce an extn-start-code index

B.1.2.9 initial code number is to the conversion (sconvert.sch, sconverm.M) of token

The second step of conversion is that above-mentioned initial code number (or index) is converted to token. Also process the token expansion at suitable this piece of place, discarded expansion, user data and retrieval mode. Retrieval mode is a kind of method that enters data flow at a certain random point. Retrieval mode can be set to one of following eight values:

0: normal operating---search next initial code.

1/2: do not retrieve in the level of the system that spatial decoder is realized.

3: retrieve sequence or higher person

4: retrieval group or higher person

5: searching image or higher person

6: retrieval sheet (slice) or higher person

7: retrieve next initial code

Before the initial code of the needs higher person of (or on the syntax (in the syntax)) was detected, any non-zero retrieval mode all made data go out of use.

These parts also add the token expansion to the initial token of figure and sheet:

PICTURE_START uses PICTURE_NUMBER as expansion. PICTURE_NUMBER is one four count value of image.

SLICE_START expands with SVP (sheet upright position) conduct. It is that initial code " value " subtracts 1 (MPEG, H.261), or " value " of initial code subtracts 0 * DO (JPEG). B.1.2.10 the format (scinsert.sch, scinserx.M) of data flow

In this invention, the format of data flow is closed and PICTURE_END, FLUSH, and CODING_STANDARD, the insertion of having ready conditions of SEQUENCE_START token is relevant with the generation of STOP_ AFTER_PICTURE event. Software below its function is the most handy is simplified and is described:

             switch(input_data)
              case(FLUSH)
                1.if(in_picture)
                   output＝PICTURE_END
                2.output＝FLUSH
                3.if(in_picture & stop_after_picture)
                  sap_error＝HIGH
                  in_picture＝FALSE；
                4.in_picture＝FALSE；
               break
               case(SEQUENCE_START)
                1.if(in_picture)
                  output＝PICTURE_END
                2.if(in_picture&stop_after_picture)
                  2a.output＝FLUSH
                  2b.sap_error＝HIGH
                   in_picture＝FALSE
                3.output＝CODING_STANDARD
                4.output＝standard
                5.output＝SEQUENCE_START
                6.in_picture＝FALSE；
               break
               case(SEQUENCE_END)case(GROUP_START)：
                1.if(in_picture)
                  output＝PICTURE_END
                2.if(in_picrure & stop_after_picture)
				<!-- SIPO <DP n="365"> -->
				<dp n="d365"/>
                  2a.output＝FLUSH
                  2b.sap_error＝HIGH
                   in picture＝FALSE
                3.output＝SEQUENCE_END or GROUP_START
                4.in_picture＝FALSE；
               break
               case(PICTURE_END) 1.output＝PICTURE_END
               2.if(stop_after_picture)
                 2a.output＝FLUSH
                 2b.sap_error＝HIGH
               3.in_picture＝FALSE
              break
              case(PICTURE_START)
               1.if(in_picture)
                 output＝PICTURE_END
               2.if(in_picture&amp;stop_after_picture)
                 2a.output＝FLUSH
                 2b.sap_error＝HIGH
               3.if(insert_sequence_start)
                 3a.output＝CODIN_STANDARD
                 3b.output＝standard
                 3c.output＝SEQUENCE_START
                  insert_sequence_start＝FALSE
               4.output＝PICTURE_START
                 in_picture＝TRUE
              break
              default：Just pass it through

B.2 Huffman (Huffman) decoder and Parser foreword B.2.1

This section is described Huffman decoder and Parser circuit according to this invention.

Figure 118 is the high level block diagram of Huffman decoder and Parser. For clarity, many signals and bus all have been omitted on this figure, particularly in several places (within illustrated systemic circulation) that data are presented backward. In fact, the Huffman decoder of this invention and Parser form (bottom along figure illustrates) by many dedicated processes parts. These parts are controlled by a programmable state machine.

From the coded data buffer, accept data with " input displacement " piece. Mainly will run into two category informations here: coded data and initial code. Coded data is entrained by data token. Initial code is replaced with their tokens separately by detector for initial code. Also may run into other token, but all tokens (except the data token) are treated equally all. Token (initial code) is treated as special circumstances, the overwhelming majority of data will be encoded (H.261, among JPEG or the MPEG).

In this invention, all data of being carried by data token are sent to the Huffman decoder, and they transmit with serial mode (one one). Certainly, it is not the field of Huffman coding that these data comprise many, but they are with fixed-length code (FLC). Yet these data are still delivered to the Huffman decoder with serial mode. If the Huffman coded data, then the Huffman decoder is only finished the first step of decoding. In this step, real Huffman code is replaced by a call number. If N different Huffman code arranged in the specific code table that will decode, then this " Huffman index " arrives in the scope of N-1 0. In addition, the Huffman decoder has a kind of " noop ", i.e. " inoperation " mode. This mode allows the Huffman decoder that data or token information are not done any processing and are sent to next stage.

Data directory unit (Index to Data Unit) is a relatively simple piece in the circuit. It finishes look up table operations. It draws its name from the second level that the Huffman decoding is processed. In this one-level, be transformed into real decoded data by the call number that obtains in the Huffman decoder with a simple look-up table. Data directory unit and the cooperation of Huffman decoder are as the unity logic cell operation.

Next piece is ALU, and it is used for realizing to other conversion of decoded data. The suitable work in data directory unit relatively shone upon arbitrarily, and it is more suitably local that ALU can be used on algorithm. ALU comprises a register group. ALU can operate the various parts that it realizes decoding algorithm. Particularly keep the register of vector prediction and DC prediction to be also contained in this piece. ALU is based on a simple adder with operand selection logic. It also comprises the special circuit of sign extended type operation. Probably provide shifting function, but this may finish under serial mode, not have barrel shifter (barrel shifter).

According to this invention, the token formatter is the decline of video Parser. Its task is that decoded data are assembled to token at last. These tokens can be sent to the remainder of decoder. So far, the token that will use for this width of cloth particular image of decoder has all had.

Parser state machine width is 18, in order to work with two-wire interface and to adopt it. Its task is to coordinate the operation of other parts. In fact, it is a very simple state machine, and it produces very wide " microcode " control word. This control word is sent to other parts. Figure 118 show coding line with data from a block movement to another piece. Situation is so really. Understanding is very important by the transmission between the two-wire interface control different masses.

In this invention, a two-wire interface is arranged between each piece in video Parser. In addition, the Huffman decoder namely input ground input data of shift unit (inshifter), and the two can be worked all to control token to serial data. Correspondingly, two kinds of modes of operation are arranged. As by data token the Huffman decoder being inputted data, then ground of data passes through shift unit. Have again, between input shift unit and Huffman decoder, two line interfaces are arranged. Yet other token is not one time one (serial) displacement, but in the head displacement of token. As input a data token, and the head that then comprises address information is deleted, and the data in the back, address are shifted by a ground. Not a data token such as input, whole token then, namely head and all is all delivered to the Huffman decoder immediately.

In this invention, the unusual of two line interfaces of understanding video Parser is that it has two active lines. This point is important. Single line is that serial is effective, and single line is that token is effective in addition. In addition, two lines can not be confirmed simultaneously. One or another root can be identified, perhaps, as there not being valid data, though two active lines are then arranged, neither may be identified. Should be understood that at other direction and only have an acceptance line. Yet this is not a problem. The Huffman decoder knows that it needs serial data or token information, and this depends on what current grammer next step this does. Thereby useful signal and acknowledge(ment) signal are correspondingly arranged. Send an acknowledge(ment) signal Accept to input shift unit (inshifters) from the Huffman decoder. If have suitable data or token to exist, the input shift unit is just sent a useful signal.

For example, a typical instruction can be done conversion to it to a Huffman code decoding in data directory unit the Index to Data Unit, revise its result in ALU, and then this result is formed a token word. A single micro-code instruction word is produced. This word has comprised the full detail of doing this work. The Huffman decoder is directly delivered in order, and latter's request transmits from one one ground of data that " input shift unit " parts transmit, until it is complete a complete symbol decoding. The control token is parallel input. In case when input was arranged, decoded index value and original microcode word were sent to data directory unit (the Index to Data Unit) together. Notice that the Huffman decoder will need several cycles to finish this operation. In fact, the periodicity that needs is by wanting decoded data to determine really. The data directory unit will shine upon this value with a table. This table is identified in the micro-code instruction word. This value is sent to again next parts, ALU. Microcode word is originally transmitted in the past together. In case ALU has finished suitable operation (periodicity again can be relevant with data), just suitable data and microcode word are sent to token format part together. The mode that microcode word control token word forms.

ALU has many condition lines or title " condition code ", and these codes send back to the Parser state machine. This just allows this state machine executive condition transfer instruction. In fact, all instructions all are conditional branch instructions. One of selectable condition is to be hard wired to " False (vacation) ". Method with this condition of selection can consist of one " non-transfer " instruction.

According to this invention, the token formatter has two inputs: a data field from ALU and/or the emit field of coming from the Parser state machine. In addition, an instruction is arranged, it tells how many positions the token formatter should get from a source, then fetches other required when altogether gathering together enough 8 position from another source. For example, HORIZONTAL_SIZE has 8 bit fields, and it is a constant address, shows that it is a HORIZONTAL_SIZE token. In this case, 8 are all come from emit field, do not have data to come from ALU. Yet if a data token probably will have 6 from emit field, what show chrominance component hangs down two from ALU. Correspondingly, the token formatter is got this information and it is put into a token, and is used for the other parts of system. Notice that from the figure place in each source just for illustrative purposes, the people that one's own profession is had general technical ability will appreciate that the figure place that arbitrary source is come all is variable in the upper example.

ALU has one group of (bank) counter. Counter is used for to the structure counting of whole image. The size of image is programmed sends into the register relevant with counter. " micro-programmer " regards these counters as the part of register group. Some condition codes are from this counter group output. The counter group allows the conditional jump based on " image beginning " situations such as " macro block begin ".

Notice that the Parser state machine is also referred to as " demultiplex state machine " Demultiplex State Machine ". Two nouns are all used in the presents.

The input shift unit

In this invention, the input shift unit is in the circuit very simple one. It is comprised of the Zcells (" hfi ") of two-stage pipeline data path (" hfidp ") and control usefulness.

At first order streamline, carry out token decode. Only have data token to be identified in this one-level. Ground of the data that comprise in the data token moves into the Huffman decoder. Second level streamline is shift register. In the most last word of data token, adopted specific coding, so may send by the coded data buffer position of arbitrary number. The below is all possible pattern of last data word.

Table is the possible model in the digit order number in the end B.2.1

E	D	C	B	A	9	8	7	6	5	4	3	2	1	0	No.of Bits
																0	1	1	1	1	1	1	1	1	1	1	1	1	1	1	None
x	0	1	1	1	1	1	1	1	1	1	1	1	1	1	1
																x	x	0	1	1	1	1	1	1	1	1	1	1	1	1	2
x	x	x	0	1	1	1	1	1	1	1	1	1	1		3
																x	x	x	x	0	1	1	1	1	1	1	1	1	1	1	4
x	x	x	x	x	0	1	1	1	1	1	1	1	1	1	5
																x	x	x	x	x	x	0	1	1	1	1	1	1	1	1	6
x	x	x	x	x	x	x	0	1	1	1	1	1	1	1	7
																x	x	x	x	x	x	x	x	0	1	1	1	1	1	1	8
x	x	x	x	x	x	x	x	x	0	1	1	1	1	1	9
																x	x	x	x	x	x	x	x	x	x	0	1	1	1	1	10
x	x	x	x	x	x	x	x	x	x	x	0	1	1	1	11
																x	x	x	x	x	x	x	x	x	x	x	x	0	1	1	12
x	x	x	x	x	x	x	x	x	x	x	x	x	0	1	13
																x	x	x	x	x	x	x	x	x	x	x	x	x	x	0	14

When in shift register, one one of data bit is to when moving, and the bit pattern of " 0 heel with all be 1 " is (filling) of expectation. This show in shift register remaining everybody be invalid. They go out of use. Notice that This move only occurs in the last word of data token.

As previously mentioned, all other tokens are the parallel Huffman decoders that import into. They still are loaded into second level streamline, but are not subjected to displacement. Notice that data head goes out of use, and does not deliver to the Huffman decoder fully. Two " effectively " lines (out_valid and serial_valid) are provided. Only have a line to be identified in preset time, it shows that the data in which kind of type of this moment are provided. B.2.2 Huffman decoder

The Huffman decoder has many modes of operation. The most significant is that it can to the decoding of Huffman code, become the Huffman call number to them. In addition, it can be decoded by the fixedly long code that coding line determines to its length (with some bit representations). The Huffman decoder is also accepted token from input displacement (inshift) piece.

The Huffman decoder comprises a very little state machine. It uses to piece level (block-level) information decoding the time. This be because Parser state machine needed time of making decision oversize. (because it must wait data flow to cross after data directory unit (the Index to Data Unit) and the ALU, could make decision and send a newer command these data). When using this state machine, Huffman decoder oneself says the word to data directory unit and ALU. The state machine of Huffman decoder can not be controlled all micro-code instruction positions, so it can not send FR order to other parts. B.2.2.1 operating principle

The Huffman decoder of this invention adopts a kind of computational methods that the code that arrives is decoded into the Huffman call number when separating the Huffman code. This number be (to a code table that N (entries) arranged) between 0 to N-1. From one one ground of input shift unit received bit signal.

For the ease of the operation of controlling organization, need many tables. These table regulations are for each possible figure place in the code (1 to 16), the code with this length have what. Can expect that this information is used for stipulating that a common Huffman code is sufficient not in a typical case. Yet, at MPEG, H.261 with JPEG in, what select is the Huffman code, so that singly be that this information just can regulation Huffman code table. The exception of this being only had a misfortune: from the T coefficient table (T Coeefficient table) that H.261 comes. This table also is used among the MPEG. This just requires an additional table, and this table is illustrated elsewhere. (in H.261, have a mind to introduce this exception, imitate to avoid initial code).

Some used in Huffman decoder tables are accurately identical with the table that transmits in JPEG, and it is very important understanding this point. This just allows directly to use these tables. And if other Huffman decoder design then will require to generate internal table from the table that transmits. This conversion just may require extra memory and extra processing. At MPEG and H.261 because the table in (it has above-mentioned exception) can be described with the same manner, standard decoder becomes feasible more than one.

One section following " C " program description decode procedure:

    int total＝0；
    int s＝0；

    int bit＝0；

    unsigned long code＝0；

    int index＝0；

    while(index＞＝total)

    {

    if(bit＞＝max_bits)

    fail(”huff_decode：ran off end of huff table＼n”)；

        code＝(code＜＜1)Inext_bit0；

        index＝code-s+total；

    total+＝codes_per_bit[bit] ；

        s＝(s+codes_per_bit[bit])＜＜1；

        bit++；
     }

In general, this process is directly converted to the realization of silicon chip, although also can utilize such fact, namely before some intermediate value of needs, can with clock phase they be calculated first.

We see from the source code section:

     EQ1.total _n＋1＝total _n+cpb _n

     EQ2.′s _n＋1＝2(′s _n+cpb _n)

     EQ3.code _n＋1＝2code _n+bit _n

     EQ4.index _n＋1＝2code _n+bit _n+total _n-′s _n

Yet, easier use of the equation group of revising of proof in hardware. Variable in this equation group " shifted " is used to replace variable " S ". In this case:

     EQ 5.shifted _n＋1＝2shifted _n+cpb _nConsequently:

         EQ6.； _n＝2shifted ₄It so for returning equation 4, can be found out:

    EQ7.index _n＋1＝2(code _n-shifted _n)＋total _n+bit _n

Except calculating continuous " index " value, must know also when calculating is finished. From " C " source code section, can find out, when:

            EQ8.index _n＋1＜total _n＋1The time we have just finished.

With formula 7 and formula 1 substitution, can find out, when:

       EQ9.2(code _n-shifted _n)+bit _n-cpb _n＜0 o'clock, we just finished.

In hardware implementation process of the present invention, the public keys (code in equation 7 and the equation 9_n -shifted _n) than the first phase calculation of the remainder of these equations, the information of " finishing " to provide end product and calculating.

Some warning: in different " C " chip segments, especially at characteristic coding and decoding (behavioral compiled code) Huffman decoder with in Sm4code scheme (projects), " C " program segment almost directly is used, but variable " S " in fact is known as " shifted ". So there are two different variablees to be known as " shifted ". One is in " C " code, and another is in hardware is realized. These two variablees differ a factor 2. B.2.2.1.1 the negate of data bit (inverting)

The Huffman code is correctly decoded also needs in addition some knowledge. The polarity of Here it is coded data. Originally H.261 adopt opposite agreement with JPEG. Itself is reflected in this fact, and everybody is 0 for initial code H.261, and the flag byte in JPEG everybody be 1.

In order to process two kinds of agreements, when coded data is read into the Huffman decoder, must be every negate of coded data, to the H.261 Huffman code decoding of style. Obviously, just can finish with an XOR gate. Attention: only to the upset of Huffman code, be nonphase-inverting in data when fixedly long code is decoded.

MPEG adopts the mixing of two kinds of agreements. To the mode from H.261 coming, adopt agreement H.261. Those from (decoding of the inner coefficient of DC) that JPEG comes, are adopted the JPEG agreement. B.2.2.1.2 conversion coefficient table

When using the conversion coefficient table that H.261 reaches among the MPEG, have some abnormal conditions. At first, the table among the MPEG is a superset (super-set) of H.261 showing. In hardware of the present invention is realized, these two kinds of standards are shared everything; This means, contain from the table the extension the code (being the MPEG code) H.261 code stream will be decoded " correctly ". Certainly, the other side of compression standard is probably impaired. For example: these extended codes can cause the emulation of initial code in H.261.

Secondly, the conversion coefficient table has a kind of unusual, and this occurs when code length is six unusually, and it means can not normally use by bit code (codes_per_bit) table describes. These six bit word are substituted code word regularly and are replaced. In encoder, at first obtain correct result with the normal mode coding. Then, for all six or longer code, with simple table lookup operation once with its first six digits with other six alternative. According to the present invention, in decoder, just the 6th solve before, decode procedure interrupts, and uses look-up method to replace code word, then continues decoding.

In this situation, only have ten kinds of six bit codes that may occur, thereby required look-up table capacity is minimum. To operation advantageously, after operation, high two invariant positions of code. Therefore the genuine look-up table of unnecessary use can be finished suitable conversion by the circuit that a small amount of door is barricaded as. The module of doing this work is called " hftcfrng ". The replacement of this type codes can be described as " ring " at this, because each code of possibility code collection collects another code alternative (not introducing new code, also the old code of not cancellation) with this.

In addition, first first coefficient of piece has been used unique implementation method. Since it is so the symbol of frequent appearance, the code of ' this termination of a block ' just can not occur, therefore, the conversion coefficient table be improved, so that can use this to be considered in other cases the code of this termination of a block. This just can save one. The result shows, uses decode structures system of the present invention, adapts to easily above-mentioned improvement. In brief, for first of the first coefficient, if " index " (" index ") is null value, think that then decoding " finishes ". In addition, after an independent decoding, " index " only has two probable values, is not 0 to be exactly 1, need only test one and get final product. B.2.2.1.3 the figure place of register and adder

Huffman decoder of the present invention can be processed the Huffman code that may reach 16. Yet decoder only has 8 bit widths. This may accomplish, because the maximum of the known Huffman index that solves is 255. In fact, this just occurs in the JPEG of expansion; In current application, greatest limit is than this slightly low (but greater than 128, therefore still disliking not enough for 7).

The result shows that for all legal Huffman codes, the not only end value of " index ", and all medians is also all in 0 to 255 scope. But, for improper code, namely to attempt to a code in current code table when not decoding (this yard may factor data make mistakes due to), index value just may exceed 255. Because our usefulness is eight machines, might in decoding at the end be dropped because inform each higher significance bit of makeing mistakes, the final value of " index " does not exceed 255. If therefore whenever exponential quantity the wrong decoding of also abandoning just occurs greater than 255 (that is: the adder carries of formation index) in decoding.

" code " 12 are saved. For translating the Huffman code, this is also unnecessary, and eight bit register should be enough. Needing these high positions is in order to read the fixed-length code of 12 of as many as. B.2.2.1.4 for the operation of fixed-length code

With regard to the code of regular length, the value of " by bit code " is forced to zero. In other words, " total " and " shifted " remains zero in whole operating process, thereby " index " is identical with code. In fact, adder etc. standard is that " index " produces one 8 value. Therefore, when fixed-length code was decoded, each high position of output word was directly taken from " code " register. When separating the Huffman code, these high positions are forced zero.

Infer whether read enough figure places from input in obvious mode. Comparator is compared desirable figure place with " position " counter. B.2.2.2 to the decoding of coefficient data

According to the present invention, the Parser state machine is general only for quite senior decoding. 8 take advantage of 8 data blocks with interior lowermost level decoding, directly process without this state machine. The Parser state machine says the word to the Huffman decoder with the form of " piece is decoded ". Under the control of the state machine (it is within the Huffman decoder in fact) of a special use, Huffman decoder, data directory unit (Index to Data Unit) and calculation are stated logical block and are worked harmoniously. This arrangement allows that the coefficient data to encoding with entropy carries out the high decoding of performance. In this mode of operation, also has the other feedback path in action. For example: in the decoding of the JPEG that VLC is decoded obtain SIZE (code is wide) and RUN (operation) information, SIZE information directly feeds back to the Huffman decoder by the output of data directory unit, has how many FLC positions to read to inform the Huffman decoder. In addition, also have some accelerators to replenish. For example, use same example, observed the Huffman index value before this one-level of data directory unit, suppressing in this way all VLC values generation SIZE is null value. In other words, as long as SIZE value non-zero, the Huffman decoder can just read of FLC before knowing the actual value of SIZE. That is to say, do not waste the clock cycle, search required single clock cycle overlaid because read first of FLC with in the data directory unit, finishing. B.2.2.2.1 MPEG and H.261 AC coefficient data

Figure 127 is illustrated in MPEG and reaches the H.261 coding/decoding method of middle AC coefficient. The flow chart of displaying Huffman decoder operation detail is seen Figure 119.

Process is from reading the VLC code. In the normal procedure of event, the Huffman index is mapped directly to the value of six RUN of expression and expression coefficient absolute number. Then read a FLC to provide the symbol of coefficient. ALU obtains the final value of coefficient with this sign bit and the combination of coefficient absolute value.

Notice that data format herein is symbol-numerical value, this operation does not have any difficulty. The RUN value is transferred to six secondary buses, and coefficient value (LEVEL) is then delivered to normal data/address bus.

Have two kinds of special circumstances and observed first the index value that process is decoded before the operation that is become data by index, both of these case can enter sunken, and they are the termination of a block (EOB) and ESC (Escape) coded data. If EOB, the fact that this situation occurs is imported data directory unit and ALU unit into, so token formatter (Token Formatter) can correctly close the DATA token that make and break.

The Escape coded data is comparatively complicated. Six on the head of RUN is read, and directly imports the data directory unit into and deposit the ALU unit in. Then read FLC one. Here it is at MPEG and the highest significant position of 8 Escape codes describing H.261, and it provides the symbol of level (level). Symbol directly reads in this device, this be because for negative value and on the occasion of, must send different orders to ALU, thereby allow that ALU is sign magnitude with twos complement value transform in the bit stream. No matter be to bear just, then read seven of the remainders of FLC. If its value is zero, just must read again 8.

In the present invention, the internal state machine of Huffman decoder is responsible for producing both having drawn oneself up and is also controlled the various command of data directory unit, ALU and token formatter. Shown in Figure 124, the command source of Huffman decoder is in following thrin: the Parser state machine, the Huffman state machine is stored in an instruction in certain register and this instruction receives from the Parser state machine before this. In brief, be retained in the register from the presumptive instruction of Parser state machine (it makes the Huffman state machine take over control and reads coefficient value), just use it when namely needing new VLC at every turn. All remaining instructions of decoding usefulness are all provided by the Huffman state machine. B.2.2.2.2 MPEG DC coefficient data

The processing method of these data is with JPEG DC coefficient data. Use identical (can pack into) table, be responsible for guaranteeing that by the microprocessor of control the content of each table is correct. Be that with the unique real difference of mpeg standard each prediction device is reset to zero (as in JPEG), the correction of for this reason carrying out is then finished in inverse quantizer. B.2.2.2.3 JPEG coefficient data

Figure 120 is that the present invention is to the hardware block diagram of JPEG AC coefficient decoding. Because the process of DC coefficient is the simplification of JPEG process in itself, this block diagram is all applicable to AC and DC coefficient. Unique real replenishing to aforementioned MPEG AC coefficient block diagram be, " SSSS " field is fed and may be taken as the part of Huffman decoder order, the FLC figure place that will read with regulation. The remaining section of order is provided by the Huffman state machine.

The flow chart of Huffman decoding is made in Figure 121 displaying to AC and DC coefficient.

At first process the decode procedure of AC coefficient. This process is from using suitable table (have two AC table) to read the VLC value. In the data directory unit, the Huffman index is transformed into RUN and SIZE value. At Huffman index level (stage), two values suppressed (trapped) are arranged, they are corresponding with EOB and ZRL respectively. This is not read everybody two unique values of FLC. If when the decoding index was not one of this two value, the Huffman decoder read of FLC immediately, meanwhile, table lookup operation is finished in its wait data directory unit, to determine really to need several. If EOB, the Huffman state machine in the Huffman decoder no longer further processes, and reads another order from the Parser state machine.

If ZRL just do not need each FCL position, but piece finishes not yet. If so, the Huffman decoder begins immediately again to next VLC decoding (using as same front table).

Follow ZRL and EOB in detection and aspect the index value that produces, a special problem is arranged. This owing to (from H.261 to reach MPEG different) but each table of Huffman is the higher level pack into (down-loadable). To two AC table of JPEG, respectively provide two registers (to ZRL, give EOB for). When the table higher level packed into, two register civilian dresses entered. They keep index value and suitably symbol is relevant.

ALU must become suitable symbol-numerical value with the FLC code conversion of SIZE position. When the table higher level packed into, the sign magnitude civilian dress entered. They keep index value and suitably symbol is relevant.

ALU must become suitable symbol-numerical value with the FLC code conversion of SIZE position. This can finish like this, at first symbol is had the value of mistake to carry out sign extended. If sign bit is set, then with all the other everybody negate (complement code).

If some DC coefficients, then the decision-making at the Huffman decode phase is easy a little, because there be not the thing suitable with the ZRL field. Everybody is that unique symbol of zero is that indication DC difference is that symbol of zero to make the FLC that will read. This is suppressed (trapped) in the Huffman index stage again, because for every (but (downloadable) that the higher level packs into) JPEG DC table provides a register, to keep this index.

ALU of the present invention has task to keep the portion copy of last DC coefficient value, is used for forming the final DC coefficient through decoding (this cries prediction usually). Needing four predicted values, is that four effective chrominance components are respectively established one. When the DC difference was decoded, ALU added that suitable predicted value is to form decoded value. This value is stored up again, as the poor predicted value of next DC of this chrominance component. Because the DC coefficient has negative (because the DC biasing is arranged) just arranged, require to transform to symbol-numerical value from twos complement. Then, this is worth output, and the RUN of companion is zero. In fact, finish a few stages of these last several stage work, its instruction is not to be provided by the Huffman state machine. They are just carried out by the Parser state machine.

Similar to AC coefficient situation, it is poor that ALU must form DC by each SIZE position of FLC. But, in this situation, need a twos complement value to be added to predicted value and get on. This can form as follows: at first carry out sign extended as front with wrong symbol. For negative, then must add 1 to produce correct value such as the result. Certainly, carry digit can be filled in adder, add 1 when adding predicted value with such method. B.2.2.3 error handling processing

Error handling processing is worth mentioning. In fact the error source of finding has following four kinds:

The tail that exceeds table.

Hope is token, but is serial data.

Hope is serial data, but is token.

Coefficient in one is too much.

Error of the first kind occurs under two kinds of occasions. If digit counter arrives 16 (legal value is 0 to 15), then make mistakes, because the longest legal Huffman code is 16. If arbitrary median of index surpasses 255, then appearance as B.2.2.1.3 described mistake.

The second mistake appears at when wishing to be token, but runs into serial data. The third mistake appears at opposite situation.

Last a kind of mistake appears in the piece to be had in the situation of multiple index. This is actually and detects in the data directory unit.

No matter which kind of situation occurs, mistake is write down in the Huffman error register, and Pars-er state machine is interrupted. Process reparation order wrong and that send necessity, this is the responsibility of Parser state machine.

In order to ensure correct operation, interrupting constantly, the Hfffman state machine is combined with the Parser state machine. When the Huffman decoder interrupts the Parser state machine, may there be a new order just waiting in the output of Parser state machine and be accepted. The Huffman decoder can not accepted this order in two complete cycles after it interrupts the Parser state machine. This just allows that the Parser state machine removes once the order there (it not should in present execution), and changes it into a suitable order. After these two period expires, the enabling of Huffman decoder. If there is an effective order there, just accept this order. Otherwise just do nothing, until the Parser state machine provides an effective order.

No matter which kind of mistake occurs, the event bit of " Huffman mistake " (event bit) is set. If mask bit (mask bit) is set, then piece will stop, and the microprocessor of control also will be interrupted with normal mode.

Under some occasion, look like it is wrong thing, in fact but not mistake, this has just brought complex situations. The most important occasion that this situation occurs is when reading the address of macro block. MPEG, H.261 with the syntax of JPEG in, it is legal token occurring in the place that is contemplated to macroblock address. If this situation occurs legally, the Huffman error register is loaded into zero (meaning inerrancy), but the Parser state machine still is interrupted. It is " inerrancy " state that the code of Parse state machine must identify this, and responds by this. In this case, then the event bit of " Huffman mistake " is with not set, and piece does not stop to deal with yet.

Must tackle several situations. The first, token occurs immediately, and the front does not have some serial bits. As if this is really true, " wishing serial data, but is the mistake of token " can appear originally. But, in fact " inerrancy " mistake of just now describing appears.

A few serial bit is arranged before the second, token. In the case, forming one determines. If before the token everybody is 1 (do not forgotten H.261 reaching coded data is anti-in the MPEG, so in encoded data files, these positions all are zero), therefore do not make mistakes. If but wherein having zero, they just are not effectively to load the position, then make mistakes, and be the mistake of " wishing serial data, but is token " really.

The third has many positions before token. In the case, carry out identical decision. If all 16 all is 1, they are taken as the filling position, once " inerrancy " mistake just occurs. If wherein have zero, the mistake of " exceeding Huffman table scope " then appears.

Another kind of occasion of not wishing to occur token is in JPEG. When processing some Huff-manl tables or quantizer table, the table of any amount can appear in same marker field (Marker segment). The Huffman decoder is not known this quantity. Therefore after finishing each table, it reads another 4 FLC, thinks that this is the number of new table. If but new marker field begins, can meet with token rather than 4 FCL. This requirement is unpredictable, has therefore added the command bit of " ignoring mistake (Ignore errors) ". B.2.2.4 Huffman order

Here be that the Parser state machine is in order to control some positions and the definition thereof of Huffman decoder component. Notice that the number order position of data directory unit is also contained in Ben Biaonei. From microprogram programmer's viewpoint, Huffman decoder and data directory unit resemble works the logical block of a compactness.

Show B.2.2 Huffman decoder order

The position	Title	Function
				11	Ignore Errors (ignoring wrong)	For the mistake of forbidding occuring in some cases.
10	Download (lower dress)	Name for the table of removing stage makeup and costume, or data are discharged into this table.
			9	Alutab (ALU table)	Remove to specify table number (or figure place of FLC) with the information that the ALU register comes.
8	Bypass (walking around)	Walk around Index to Data unit
			7	Token (token)	Token (rather than to FLC or VLC) is deciphered.
6	First Coeff (first coefficient)	Select first coefficient skill, be used for Tcoeff table and other particular form.
			5	Special (special order)	Such as this position, position, the control of Huffman state machine adapter.
4	VLC (non-FLC)	Specify VLC or FLC.

Show B.2.2 Huffman decoder order (continuing)

The position	Title	Function
				3	Table[3]	The table of specifying VLC to use
2	Table[2]	Or the FLC figure place that will read
			1	Table[1]
0	Table[0]

B.2.2.4.1 read FLC

Ignore Errors in the manner, Download, ALutab, Token, First Coeff, Special and VLC are zero, and Bypass is set, because exist without the conversion that indexes data.

Binary number in table [3:0] is pointed out to read those several.

Numeral 0 to 12 is legal, value zero really reads 0 (as desired) and this instruction is Huffman decoder NOP instruction, value 13,14 and 15 meanings are not worked, and when the Huffum state machine represented to use " SSSS " to go to read as the figure place of FLC, its value was 15. B.2.2.4.2 read VLC

In the manner, Ignore Errors, Download, Alutab, Token, First Coefficient and Special are zero. VLC is 1. Bypass normally 0, therefore exists from the conversion that indexes data.

In the manner, Token, First Coefficient and Special are zero, and VLC is 1.

Table[3:0] in binary number indication will be with table, as follows

Show B.2.3 Huffman table

Table[3：0]	The VLC table of using
		0000	TCoefficient (H.261 MPEG reaches)
0001	The encoding block sample
		0010	Macroblock address
0011	The activity vector data
		0100	Interior M type
0101	The M type of prediction
		0110	The M type of interpolation
0111	H.261M type
		10×0	JPEG(MPEG)DC Table 0
10×1	JPEG(MPEG)DC Table 1
		11×0	JPEG AC Table 0
11×1	JPEG AC Table 1

Note that if remain on table in the RAM (being the JPEG table) do not use position 1, therefore the selection of table occurs twice. If what consist of is non-baseline (non-baseline) JPEG decoder, four DC tables and four AC tables are just arranged, just need Table[1].

If Table[3] be zero, then input data-conversion, for example, for each table correctly as H.261 form read. If Table[3:0]=0, then also carry out suitable Ring (ring) and revise. B.2.2.4.3 NOP instruction

As aforementioned, read one everybody be that the action of zero FLC is taken as an inoperation (No Operation) instruction and uses. Do not have data to read (token, serial data) from input port, the Huffman decoder is zero data in company with coding line output numerical value. B.2.2.4.4 the first coefficient of TCoefficient

H.261 with MPEG TCoefficient table a special non-Huffman code is arranged, it is as the first coefficient on the head in the piece. For the top at piece solves TCoefficient, first coefficient bits (First Coefficient bit) can be set in company with a VLC instruction that obtains with table zero (Table[0]). One of many effects of first coefficient bits are that this code is solved.

Note, under normal operation, seldom send " simply " order of reading TCoefficient VLC. This is because usually give the Huffman decoder control to special bit (Special Bit) set. B.2.2.4.5 read token word (Token Words)

In order to read the token word, token position (Token bit) must put 1. Special bit and first coefficient bits are necessary for zero. If Table[0] position correctly works, and the VLC position also must set.

In the manner, Table[0] position and Table[1] to be used for changing the characteristic of reading token as follows in the position:

The position	Meaning
		Table[0]	Abandon each filling position of serial data
Table[1]	Abandon all serial datas

If Table[0] and Table[1] all be zero, serial data then before token, occurs and be considered to mistake, can write down the mark of makeing mistakes.

If Table[1] set, then all serial datas are dropped, until run into the token word. The appearance of these serial datas can not produce mistake.

If Table[0] set, then each filling position is dropped. Certainly, must know the polarity of each filling position. This is by Table[3] determine, and identical when reading the VLC data. If Table[3] be zero, at first will input data-conversion, then abandoning any is the position of " 1 ". If Table[3] put 1, the not negate of input data, but abandon position, each " 1 ". Because according to Table[3] position data negate This move is depended on the VLC position, this position must put 1. If the position that runs into is not filling position (that is, in the position, each " 1 " that H.261 reaches among the MPEG), reporting errors.

Attention is only read an independent token word in these instructions. Do not remove to comprehend the state of extension bits (extension bit), testing this and moving accordingly is the responsibility of Demux. The present invention also provides some instructions of reading a plurality of words-see special instruction one joint. B.2.2.4.6 the ALU register is specified table

" if Alutab " position, position, each register in the register group of ALU can be with deciding the actual table number (table number) that will use. Which ALU register the table number that provides in order together with the VLC position, determines to have used.

Show the B.2.4 selection of ALU register

VLC	table[3：0]	The ALU table
			0	X0XX	fwd_r_size
0	X1XX	bwd_r_size
			1	X0XX	dc_huff[compid]
1	X1XX	ac_huff[compid]

If the code of some regular lengths is just read for the figure place to each vector decoding. If r_size is zero, just produce a NOP no-operation instruction (NO-OP).

If some Huffman codes, the table number that then produces makes table[3] put 1, therefore, the result draws number refers in each JPEG table one. B.2.2.4.7 special order

The instruction (or mode of operation) of describing so far all is considered to " simply " instruction. For each order of receiving, the right quantity of input data (serial data or token data) is read, and result data is output. If do not find mistake, each order just produces an output just.

In the present invention, special order has such characteristics: a single instruction can produce more than one output word. In order to realize this function, the internal state machine of Huffman decoder is obtained control, and understands and oneself send some essential instructions, until it judges that the instruction that Parser asks finishes.

In all special orders, sequence the first pending real instruction (first real instruction) is arranged along with special bit (Special bit) puts 1 and send. This means that all sequences all must have the first instruction of a monodrome. The benefit of this scheme is first the real instruction that can obtain sequence, and needn't carry out the search operation done based on the order of receiving from Parser.

The special order of approval has following four kinds:

·TCoefficient

·JPEG DC

·JPEG AC

·Token

Conversion coefficient (Transform coeffic-ients) that H.261 reaches MPEG etc. is read in the first instruction, until read the symbol of this termination of a block. If piece (non_ intra block) in this piece right and wrong, this order can be read whole. In the case, " first coefficient " position (" First coefficient " bit) should set, to use first coefficient skill. If this piece is interior (intra block), then the DC item should read, so " first coefficient " position should be zero.

If be interior in H.261, the DC item is read with " simply " instruction, in order to read 8 FLC values. In MPEG, following explanation " JPEG DC " special order is used.

" JPEG DC " order is used for reading the DC item (comprising the SSSS position FLC by the VLC indication) of JPEG form. This order is also used in MPEG. The necessary set of first coefficient bits is so that the counter in the data directory unit (number of design factor) is reset.

" JPEG AC " order is used for reading piece after reading the DC item remaining section, until meet with EOB, or until read the 64th coefficient.

" Token " order is used for reading complete token. Token word (token words) is read, until the extension bits zero clearing. This is a kind of method that makes things convenient for of processing some unrecognised tokens. B.2.2.4.8 higher level's table of packing into

In the present invention, the table of Huffman decoder can both carry out the higher level with " higher level packs into " position (" Download " bit) and pack into. The first step is which table of indication wants the higher level to pack into. Position and first coefficient bits pack into all in the situation of set the higher level, finish even if send an order of reading FLC. Process because be used as NOP, thus in fact do not read everybody, but table number be stored into certain register and be used for the higher level of recognition sequence pack in which table pack into.

Show B.2.5 JPEG table

table[3：0]	The table of being named
		10XX	JPEG DC Codes per bit
11XX	JPEG AC Codes per bit
		00XX	JPEG DC Index to Data
01XX	JPEG AC Index to Data

As above shown in the table, or AC table or the DC table can be loaded into table[3] what then determine to pack into is step-by-step code table (codes-per-bit table) or data directory (Index to Data table).

In case show designatedly, data just higher level are packed into wherein. Its method is that the higher level packs into and sends an order to read required FLC number (always 8 figure places) in the situation of position, position (and first coefficient bits zero setting). This just writes in the specified table data through decoding. At the current address data writing, then address counter rises in value according to the address Counter Value. Whenever a designated address counter of table is reset to zero.

When the higher level packs into when indexing data and respectively showing, monitoring data and address. Notice that the address is the Huffman call number, and this address of packing into is final symbol through decoding. This information is used for automatic load register, and the interested symbol of these register pairs has kept the Huffman call number. Therefore, in JPEG AC table, when having numerical value with the ERL analog value when being identified, the current address just writes register CED_H_KEY_ ZRL_INDEXO or the CED_H_KEY_ZRL_INDEX1 that is indicated by table number.

Because the data phase place (phase) after decoding through decoding just writes by bit code (codes-per-bit) table, can not be during this position from show read data. Therefore sending immediately the instruction of attempting to read VLC higher level's load after will be failed. In any practical application (when namely carrying out JPEG), such sequence has no reason occur. But, might set up the simulated test of so doing. B.2.2.5 Huffman state machine

According to the present invention, the Huffman state machine provides various command for the Huffman decoder, and these orders are inner generations in some cases. Also all may offer the Huffman decoder with Demux with issuable all orders of internal state machine.

The basic structure of state machine is as follows. When a certain order is sent to the Huffman decoder, it also is stored in a series of auxiliary latch, so can re-use afterwards. This order is also carried out by the Huffman decoder and is analyzed by the Huffman state machine. If it is known command sequence and special bit (SPECIAL bit) set that order is recognized, then Huffman decoder states machine is from the control of Parser state machine reception to the Huffman decoder.

Here, three sources are arranged for the various instructions of Huffman decoder:

1) Parser state machine-after special order finishes (in decoded such as EOB), just do this selection, and next demux order is accepted.

2) Huffman state machine. The Huffman state machine can be to oneself providing certain bar to order arbitrarily.

3) initial order of being sent by the Parser state machine is with enabled instruction.

In situation (2), might be provided by the feedback from the data directory unit by table number, this will change the field (field) in Huffman state machine ROM.

In situation (1), under some occasion, each table number provides (for example, if AC and DC table number and F-table number) by the value that ALU register group obtains. These values are stored in the auxiliary order reservoir, so when this order was reused afterwards, table number was exactly that stored. This table number no longer restores from ALU, because in general, each counter has advanced in order to point to next piece.

Owing to the selection of next the bar instruction that will use just depended on to make resolution in the later stage of one-period in decoded data. Therefore, general structure is such: all possible instruction all is ready to parallel mode, and composite combined, determines actual instruction in the later stage in cycle.

Notice that in each case the ROM of state machine also determines the instruction that will depend on current data, then to be added on the ALU because these data pass to the data directory unit except the instruction that determines will be used by the Huffman decoder in next cycle. All three kinds of instructions are got ready with parallel mode all identically, then make one's options in the later stage in cycle.

In addition, this part of instruction also has three kinds of selections corresponding to three kinds of selections of next Huffman decoder instruction:

1) is applicable to constant (constant) instruction of block end.

2) Huffman state machine. The Huffman state machine may provide certain bar arbitrary instruction for the data directory unit.

3) by the issued initial order of Parser, with enabled instruction. B.2.2.5.1 EOB comparator

The output of EOB comparator forces in fact to select constant instruction, gives the data directory unit with it, and it also can make next Huffman instruction is next instruction from Parser. The definite function of comparator is controlled by some positions in the Huffman state machine ROM.

The backing of device has four registers as a comparison, and they remain on the index of EOB symbol in each AC and the DC JPEG table. If the DC table does not have end of block character certainly, but zero-width (zero-size) symbol is arranged, it produces by zero DC is poor. Because this makes the FLC figure place that will read with the EOB symbol is zero just the samely, so entirely same to their processing.

Four index values in remaining on each register, constant value 1 also can use. This is at the index that H.261 reaches the EOB symbol among the MPEG. B.2.2.5.2 ZRL comparator

In the present invention, this is more general comparator. It is used for the initial order of selecting Huffman state machine instruction or data directory to use.

There are four values to make the backing of ZRL comparator. Wherein two in register, they remain on the index of ZRL code in the AC table. Two values are constants in addition, the one, and value of zero, another is 12 (index of ESCAPE in H.261 MPEG reaches).

Constant is used separately in the situation that FLC occurs. When table number during less than 8 (and VLC), use constant 12. If table number then uses one of two registers greater than 7 (and VLC), this low level by table number determines.

One among the state machine ROM offers and enables comparator, and another one has been used for inverting function.

If the position, token position in the instruction, then the output of comparator is out in the cold, and substitutes with expansion (extn) position. Till this just allows that running to token finishes. B.2.2.5.3 the ROM of Huffman state machine

Each instruction field in the Huffman state machine is as follows:

nxtstate[4∶0]

This is the address that will use in next cycle. It can be changed.

statectl

Permission is changed the NextState address. If be zero, the state machine address does not change, otherwise the least significant bit of address is substituted as follows by the value of one of two comparators:

nxtstate[0]
		0	When conforming to, EOB substitutes least significant bit
1	When conforming to, ZRL substitutes least significant bit

Attention: under any circumstance, if next Huffman instruction is chosen as " reruning original order (re-run original command) ", state will forward to ordering suitable position 0,1,2 or 3.

eobct[1∶0]

It goes to control the selection of next Huffman instruction according to EOB comparator and extension bits, and is as follows:

eobctl[1∶0]
		00	Without result-see Zrlct[1: 0]
01	If EOB then gets new (Parser) order
		10	If extn is low, then get new (Parser) order
11	Unconditional Demux instruction

Zrlct[1∶0]

It goes to control the selection of next Huffman instruction according to the ZRL comparator. If satisfy condition, it just gets state machine instruction, otherwise it reruns original instruction. No matter which kind of situation occurs, adopt a demux instruction such as a certain eobctl*+ condition, then this (eobctl *+) gets following priority:

Zrlct[1∶0]
		00	Always do not get SM (always reruning)
01	Always get the SM order
		10	If ZRL conforms to, SM then
11	If ZRL does not conform to, SM (state machine) then

smtab[3∶0]

In the present invention, if selected instruction is state machine instruction, then table number is exactly the table number that the Huffman decoder will use. But, if the ZRL comparator conforms to (mat-ches), preferentially use zrbtab[3: 0] and field.

If do not require that whether look ZRL meets and use different table numbers, then smtab[3: 0] and zrltab[3: 0] can have same value. But, notice that this can cause the problem of modelling that some are strange in Lsim. If MPEG, those indicate the register (the unique structure that has of a kind of JPEG-a JPEG only construction) of the Huffman call number of ZRL not exist obvious requirement to go to pack into. But, these registers are still selected, the output of ZRL comparator becomes " the unknown ", although and in the ZRL comparator may all situations for " the unknown ", smtab[3: 0] with zrltab[3: 0] identical value (so which is selected unimportant) is both arranged, next state what one turns to for guidance or support belongs to " the unknown ".

zrltab[3∶0]

If the instruction of selecting is that state machine instruction and ZRL comparator conform to, Here it is table number that the Huffman decoder will use.

smvlc

If the instruction of selecting is state machine instruction, each VLC position of Huffman decoder use that Here it is.

aluzrl[1∶0]

This field control passes toward the selection of the instruction of ALU. Instruction or from the order of Parser state machine (it when command sequence begins, store under), or from the order of state machine:

aluzrl[1∶0]
		00	The Parser state machine command of always going bail for and depositing
01	Always get the Huffmanm state machine command
		10	As not being that EOB then gets Huffman SM order
11	As not being that ZRL then gets Huffman SM order

alueoq

This line passes toward the change of the instruction of ALU according to the situation control of EOB comparator. It forces into " zinput " with the way of output of ALU simply. This is a kind of choosing at random; Any way of output is just enough so long as not " what neither (none) ". This is in order to ensure the block end command word being passed to token formatter piece (Token Formatter block), and this command word is controlled the correct format of each data token (DATA Tokens) there:

alueob
		0	Do not change ALU outsrc field
1	If EOB conforms to, then force " zinput " to enter outsrc

The remainder of various field is the ALU instruction field. Relevant data is provided in the explanation of ALU rightly. B.2.2.5.4 the modification of Huffman state machine

In a kind of specific embodiment of state machine, the data directory unit need " knowing " when the RUN part of the TCoefficient of an escape code (escape-coded) passing toward the data directory unit. Although in control ROM, use certain suitable position can accomplish this point, for fear of revising ROM, used a kind of alternative. Here it is, monitors to enter the address of ROM and find address value 5. It is exactly the correct position of the RUN field of designated treatment in ROM. Certainly, obviously ROM uses some other selected address values when programming. That narrated in the past in addition, uses the method for a certain position originally also can utilize in control ROM. B.2.2.6 sketch is browsed

In the present invention, the Huffman decoder is called " hd ". From in logic, " hd " in fact comprises data directory unit (this is that the various restrictions that generate of the code through compiling are desired). Therefore, " hd " comprises following critical piece:

Show B.2.6 Huffman module

Module name	Explanation
		hddp	Huffman decoder (arithmetic) data path
hdstdp	Huffman state machine data path
		hfitod	The data directory unit

By the general, explain in subsystems zone (areas) being finished the following explanation to each Huffman module. These subsystems have been done more detailed displaying in the drawings. These figure understand easily to the people with the general technical ability of one's own profession. B.2.2.6.1 the explanation of " hd "

The logic of two-wire (two-wire) interface control usefulness generally includes three ports by two-wire interface control: data input, data output and order. In addition, there are two from " effectively " line of input shift unit; Token-effectively (token_valid), it indicates certain token just appearing at in_data[7: 0] on, and serial _ effectively (serial_valid) it, designation data is just in serial transfer.

In the signal that produces, the most important thing is that those are sent to the enable signal of each latch. And wherein most important be the enable signal of using to each ph1 latch. Most of pho latch and are not to enable, and only have wherein two to enable, and they are: the eo relevant with serial data and the relevant eot with token data.

In the present invention, the signal relevant with " finishing " (done, done0 and notdone0 that notdone and ph0 derive from) indicates the order of original Huffman when to finish.

In the situation that the Hufffman state machine command is performed, when each the original order that forms whole state machine command was finished, " done " was identified. The notnew signal prevents from accepting the newer command from the Parser state machine, until whole Huffman state machine command is finished.

As for the control of the information of receiving from the data directory unit, during the decoding of JPEG coefficient, the control logic of " size " field is fed back to the Huffman decoder. In fact two kinds of situations can appear. If width (size) just in time is 1, just feed back with special signal notfboneO. Otherwise width is by the output of data directory unit (out_data[3: 0]) feedback, and this part thing is just occuring in signal fbvalidl indication. Signal muxsize occurs, and with control the feedback data multichannel is combined into command register (seeing sheet 10).

Also have in addition just in time 64 feedbacks that coefficient has been decoded. Because in JPEG, EOB is not encoded in the case, so produce signal forceeob. In fact this has two kinds of methods to finish, and is similar with above-mentioned two kinds of signals with the width feedback. Or use jpegeob (this is a kind of ph1 signal), or use jpegeboO. Notice that if that carry out is normal feedback (jpegebo), latch i-971 just is fed data and packs into, until admit ability zero clearing behind the new Parser state machine command. Only after the Huffman code was decoded, in fact signal forceeob just generated. Therefore, fixed-length code (being the every of size) is unaffected, but the compulsory block end of next Huffman coded message substitutes. When width is 1 and when using jpegeboO, only read 1, so i_ 1255 and i_1256 with signal delay to constantly correct. Attention is in this situation, and width can not occur is zero, only has EOB and ZRL because have the symbol of width zero.

To producing tcoeff_tabO (using the Huffman decoding of Tcoeff table), mba-tabo (using the Huffman decoding of MBA table) and the decoding of nop (inoperation) order are quite at random. Produce nop several reasons are arranged. First fixed code code is wide to be zero, and it two is forceeob signal (even because export to signal EOB, also should not from input shift unit read data), and is last, the table higher level pack into name be its three.

Notfrczero (producing by the FLC of width zero or by NOP) guarantees that the result is zero when using the NOP instruction. In addition, when invert indicates the serial data should negate (seeing a B.2.2.1.1 joint) before the Huffman decoding, and when the ring indication should add conversion coefficient ring (seeing B.2.2.1.2 joint).

Finishing of decoding is also relevant with addressing code_Pr_bit ROM. Code_per_bit ROM is made by some ROM of short data route (small dataPath). (such as csha and csla) copies to each signal, is in order to obtain enough drivings purely, and the latter is by being divided into two each ROM to reach. The address is desirable from digit counter (bit[3: 0]) or take from MPI address (key_addr[3: 0]), and this depends on that UPI accesses that selected part.

The UPI that additional decoding involves some registers reads, such as the register (EOB, ZRL etc.) that keeps the Huffman index value for some JPEG tables. Also comprise the control of the relevant three-state driver of these registers and respectively read by the UPI of bit code RAM.

The data path decoding of arithmetic still is provided for some important item. The first coefficient skill of the use of first_bit and Tcoeff is relevant, and bit_five involves in the Tcoeff table and uses ring (ring). Note the usage of forceeob, the action that its simulation EOB comparator is consistent with decoded index value.

As for extension bits, if shift unit reads is token from input, then related extension bits is read out with token. Otherwise the last value of expansion is saved. This just allows whenever to expand (extn) position with the micro code program test after reading token.

When assert be zerodat the time, high 4 of Huffman output data are forced zero. Because only just there is virtual value these positions when separating fixed-length code, when when decoding VLC or token or because of any reason NOP, carrying out instruction with they zero setting.

When each order is finished, other electric circuit inspection to and produce " done (finishing) " signal. In fact, the reason that becomes " done " is divided into two classes, and they are: normal reason and exception reason. Each is processed by one of multiplexer (MUX of two three tunnel.

Following multiplexer (MUX (i-1275) is processed normal reason. If the situation of FLC is just used the ndnflc signal. This is the comparator output that digit counter is compared with table number. If the situation of VLC is just used the ndnvlc signal. This is the output of arithmetic data path (arith-metic datapath), and it has directly reflected formula 9. If the situation of NOP instruction or token is only required one-period, therefore, native system unconditionally " is finished ".

In the present invention, upper multiplexer (MUX (i-1274) is processed exception. If decoder is just expecting that the feedback (fbexpctdO) of size is 1 (notfboneo) from size in the JPEG decoding, then decoder is finished, because only need one. If decoder is first of first coefficient with Tcoeff table, if then the position 0 of current index is zero, even if (seeing B.2.2.1.2 joint) finished in decoding. If none satisfies these conditions, then there is not the exception reason of finishing.

NOR door (i-1293) solves the condition of " finishing " at last. Force " finishing " by the condition (being the invalid conditions of data) that i_570 produces. This may it seems a bit strange. It mainly uses after just resetting, and enters " finishing " state (" finishing " resets all counters, register etc.) to force machine when preparing first command. Notice that any error condition also " is finished " all by force.

When detecting various mistake, need to use the notdonex signal. Can not use each normal " finishing " signal, this is because when detecting mistake, also force at " finishing " state. Use " finishing " may cause (combinatorial) backfeed loop of combination.

Error detection and processing are finished in the circuit that can detect all possible errors conditions. ' or ' together in i_1190 for these conditions. In the case, i_1193, i_585, i_584 form three Huffman error register. Please note i_1253 and i-1254, they forbid mistake (seeing B.2.2.3 joint) in the various situations that do not have " real " mistake.

In addition, i_580, i_579 and the circuit that links thereof become a simple state machine, and it is in the reception that detects wrong rear control first command.

As previously shown, each control signal is delayed time, to be engaged in some pipelining delays among data directory unit and the ALU.

Itod_bypass is the actual by-passing signal that passes to the data directory unit. When fixed-length code was decoded, the Huffman state machine was in the driver's seat, and it forces bypass, and this moment, Itod_bypass was just changed.

Aluinstr[32] be to make ALU be able to the position that (with each condition code) feeds back to the Parser state machine. In addition, when the Huffman state machine was controlled at hand, importantly each signal only was identified once (rather than when one of each original order is finished).

Aluinstr[36] be the position that allows ALU stepping (step) block counter (if some other ALU command bits also designated increments). This is also only permitted is identified once.

In addition, these requirement can only be applicable to data are outputed to those ALU instructions of token formatter. Otherwise each counter may with regard to increment before outputing to the token formatter for the first time, cause incorrect " CC " value in certain DATA token.

Have in the illustrated embodiment in the present invention, if ALU exports to token formatter, alunode[1] or alunode[0] be low just.

Figure 118 and Figure 27 are similar, and the Huffman state machine data path that is called as " hdstdp " is shown. Also have a UPI decoder, be used for the output of reading Huffman state machine ROM.

In order to process this situation of being specified (seeing B.2.4.6) table number by the ALU register cell, provide frequency multiplexing technique.

Aluinstr[3: 2] change to be used for ALU outsrc instruction field is forced to not be what neither (non_none) (seeing the explanation that B.2.2.5.3 saves alueob).

As for the command register of establishing for Huffman decoder block (x), each of order has the various relevant multiplexer (MUXs that may originate of select command. Four control signals are controlled this selection:

Selhold, it makes register keep its current state.

Selnew, it is loaded into a newer command from the Parser state machine. It also enables packing into of each register, and these registers keep original Parser state machine command for future use.

Selold, it causes packing into from the next original Parser state machine command of above-mentioned each register.

/ selsm, it causes packing into from the order of Huffman state machine ROM.

If table number, then situation is complicated a little, and (selholdt and mux size) latch remains on the current address among the Huffman state machine ROM because table number also may be packed into the output data of data directory unit. The order that the logic circuit detection is being carried out is which bar in possible four. If a newer command, then these signals mix to form low two of initial address mutually.

Logic circuit also detects the when output meaningless (usually ordering because order is one " simply ") of state machine ROM. Signal notignorerom is the operation of illegal state machine effectively, especially forbids doing any change towards the instruction of ALU.

The circuit that produces fixstateO is controlled the limited transfer ability of this state machine.

Also provide decoding to drive signal to the ROM of Huffman state machine. This ROM is the combination ROM of data path form.

Being created in B.2.2.5.4 of escape_run narrated in the joint.

Keep register such as the call number of ZRL and EOB symbols for those, also provide decoding for them. These registers can be packed into by UPI or data path. Central authorities (es[4: 0] and ZS[3: 0] the Port Multiplier that is decoded as generate and select signal, these Port Multipliers to select which register or constant value to want and compare through the Huffman index of decoding.

The control logic of using about the Huffman state machine. Herein, mix with various different conditions from each " instruction " position of Huffman state machine ROM, to determine what is next and how to go to change the coding line that arranges as ALU.

In the present invention, signal notnew, notsm and notold are because being used for the operation of control Huffman decoder command register on the sheet 10. Clearly, they are to be produced together by some control bit states and Huffman index comparator (neobmatch and nzrlmatch) among the state machine ROM (seeing B.2.2.5.3 explanation).

Selecting also is to be made by the command source that leads to ALU. Actual multiplexing is finished in Huffman state machine data path " hfstdp ". Produce four kinds of control signals.

When never running into the situation of block end, can produce one of aluseldmx (selecting the instruction of Parser state machine) or aluseism (selecting the instruction of Huffman state machine).

In the situation that never runs into block end, can produce one of aluseleobd (selecting the instruction of Parser state machine) or aluseleobs (selecting the instruction of Huffman state machine). " outsrc " field of ALU instruction is changed in addition, becomes " zinput " to force it.

During the higher level packed table into, a register kept having named the table number of table. For respectively providing decoding by bit code codes_per_bit RAM. When additional decoding can be identified the symbol of EOB and ZRL and so on and packed into by the higher level, so each Huffman call number register can be packed into automatically.

As for digit counter, a comparator can record when read correct figure place when reading certain FLC. B.2.2.6.2 the explanation of " hddp "

Each comparator detects the explicit value of Huffman index. Each register shows to keep these values for the energy higher level packs into. Port Multiplier (meob[7: 0] and mzr[7: 0] select used value, gating (gating) and some XOR gates form each comparator.

Each formula of explanation during some adders and register directly calculate and B.2.2.1 save. Here just needn't do again more speak more bright. Used an XOR gate, with the data (i_807) of negate explanation in B.2.2.1.1 saving.

The width of " code " register is 12. " ring " shape of explanation was replaced during the multichannel structure had realized B.2.2.1.2 saving.

Consider through the serial data (index[7: 0]) of decoding and the data between the token data (ntokenO [7: 0]) and multiplex various streamline and delay time that the index value of Huffman has decided with ZRL and EOB symbol.

Which Codes_Per_bit ROM and their multiplexed being used for determine to use open table. Use this structure to be because table selection information arrives lately. Then access all tables and choose correct table.

Consider Codes_Per_bit RAM, (Codes_per_bit) ROM's is multiplexed at last, and the output of Codes_Per_bit RAM is carried out in " hdepbram " piece. B.2.2.6.3 the explanation of " hdstdp "

In the present invention, " Hdstdp " has two modules. " hdstdel " participates in each control bit of Parser state machine is deferred to suitable flow line stage, for example when these positions are added to ALU and token format. It only processes about coding line that is sent to ALU for half, and all the other are then processed by another module " hdstmod ".

" Hdstmod " comprised Huffman state machine ROM. Some position of this instruction returns Huffamn state machine control logic to use. Everybody is used for the part ALU coding line (it is from the Parser state machine) that replacement is disregarded at " hdstdel " for all the other.

" Hdstmod " is apparent, need not to explain-only have some flowing water delay registers.

" Hdstdel " is also very simple, and it changes some Port Multipliers manipulations that the ALU instruction is used by a ROM and some. The remaining part of circuit is about UPI the half that each Huffman state machine ROM exports to be carried out read access. Also used buffer for number control signal. B.2.3 token formatter

According to the present invention, Huffman decoder token formatter is positioned at the end of Huffman piece. Such as its title prompting, its function is that the data format from the Huffman decoder is changed into suitable token structure. Under the control of microinstruction word command field, the data multiplex in input data and the microinstruction word. This piece has two kinds of mode of operation: DATA_WORD and DATA_TOKEN. B.2.3.1 microinstruction word

B.2.7, the microinstruction word that table is comprised of 7 fields

Field name	Figure place
		Token (token)	0∶7
Mask (mask)	8∶11
		Piece type (Bt)	12∶13
Outside Extn (Ee)	14
		Demux Extn(De)	15
Block end (Eb)	16
		Order (Cmd)	17

 17            16         15          14          12          8            0

Cmd

Eb

De

Ee

Bt

Mask

Token

The management that microinstruction word equally is subjected to same accept with data word is mode of operation B.2.3.2

Show the B.2.8 distribution of Bit position

Cmd	Mode

	0	Data_Word
1			Data_Token

B.2.3.2.1 data word

Under the manner, the high eight-bit of input feeds back to output. Minimum eight is input or the token field of microinstruction word, or both mixing, and this depends on the mask off code field. Mask off code represents the input figure place in the mix, that is:

out_data[16∶8]＝in_data[16∶8]

out_data[7∶0]＝(Token[7∶0]&(ff＜＜mask))indata[7∶0]

When mask off code is made as 0 * 8 or when larger, the output data will equal to input data. The manner is used for exporting various words in some non_DATA (non-data) token. Mask off code is set at 0 o'clock, out_data[7: 0] will be the token field of microinstruction word. The manner is used for exporting the various token heads (Token headers) that do not comprise data. When the token head comprised data, the figure place of data was provided by the mask off code field.

If outside Extn (Ee) is set, out_extn=in_extn then, otherwise out_extn=Deo

Bt and Eb are " needn't be concerned about (don ' t care) ". B.2.3.2.2 data token

The manner is used for the data token is formatd, and it has two kinds of functions, depends on signal first_coefficient. When resetting, first_coefficient set. When first data coefficient arrived with a microinstruction word being put 1 by cmd, out_data [16: 2] was set to 0 * 1, and out_data[1: 0] get the value of Bt field in the microinstruction word. The head of Here it is data token. When this word is received, followed the coefficient of order to be loaded into register RL, and first_coefficient get the value of Eb. When next coefficient arrives, out_data[16: 0] get one and be stored in the interior coefficient of RL. Then upgrade RL and first_coefficient. This just guarantees when running into block end and Eb set, with first_coefficient set, for next data token is got ready, that is:

                  If(first_coefficient)
                  {
                    out_data〔16∶2〕＝0×1
                    out_data〔1∶0〕＝Bt〔1∶0〕
                  RL〔16∶0〕＝in_data〔16∶0〕
                 }
                 else
                 {                   out_data〔16∶0〕＝RL〔16∶0〕
                   RL〔16∶0〕＝in_data〔16∶0〕
                 }
                 out_extn＝-Eb

B.2.3.3 explanatory discussion

According to the present invention, most of command bits are normally provided by the Parser state machine. But in fact two in the field provided by other circuit. Above-mentioned " Bt " field directly links to each other with the output of ALU piece. This one or two bit field provides the currency of " CC " or " chrominance component (color component) ". Therefore, when certain data token head is set up, minimum two from get chrominance component from the ALU counter. Secondly, whenever End_of_block (block end) accords with when decoded, (perhaps, if JPEG, when being assumed to 1, because the last coefficient of piece is through coding) " the Ebt position just is identified in the Huffman decoder.

The in_extn signal obtains in the Huffman decoder. Only have when extension bits normally provides together with the token word, this signal could be meaningful to each token. B 2.4 Parser state machines

Parser state machine of the present invention is actually very simple circuit. Complicated is the programming of microcode ROM, and B.2.5 this discussing in joint.

In brief, the machine keeps the register of current address to form by one. In microcode ROM, search this address to produce microcode word. This address increment in a simple incrementer, the address behind the increment are that NextState will one of may addresses with two. Another address is the field in microcode ROM itself. Therefore every instruction may be transfer instruction all, can be transferred to the position of program appointment. If do not shift, control the next unit of the ROM that arrives.

A string 16 condition code bits are provided. Can select these conditions any (being selected by certain field in the microcode ROM). In addition, each condition code bit can negate (being again in microcode ROM). The signal that draws behind increment the address or the jump address in microcode ROM in select one. One of condition is hard wired (hard_wired), to be judged as " vacation ". If choose this condition, just can not shift. On the other hand, if choose the then in addition negate of this condition, redirect always occuring then, namely becomes unconditional branch.

Show B.2.9 condition code bit

Item	Title	Explanation
				0	user[0]	These four all are connected to a register, and this register can be programmed from MPI by the user. Their allow the condition code of " defined by the user ", and these condition codes can be tested with expense seldom. Wherein two are defined as control off-gauge " coded block pattern (Coded block Pattern) " processing, are used for 4 and 8 macroblock structure of experiment.
1	user[1]
		2	cbp_eignt
3	cbp_spec∶al
		4	he[0]	These directly receive the Huffman error register of Huffman decoder
5	he[1]
		6	he[2]

Show B.2.9 condition code bit (continuing)

Item	Title	Explanation
				7	Extn	Extension bits (being used for each token)
8	Blkdtn	The block mode shift unit
			9	MBstan	In the macro block starting point
10	Picstart	In visual starting point
			11	Restart	Resetting interval starting point
12	Chngdet	" not nature " changes detecting position
			13	Zero	ALU zero condition
14	Sign	The ALU sign condition
			15	False	Be hardwired to False (vacation)

B.2.4.1 two-wire interface control

According to the present invention, two-wire interface is controlled in these parts and a bit makes an exception. A two-wire interface is arranged between Parser state machine and Huffman decoder. It is used for the carrying out of control command. Before a certain given order was accepted, the Parser state machine can be waited for always. Then set about from ROM, reading next command. In addition, each condition code is fed via the single line from ALU.

Every order has one in microcode ROM, allows to specify it should wait to be feedback. If do this appointment, after then this instruction has been accepted by the Huffman decoder, new order no longer appears, until be identified from the feedback line of ALU. This line is fb_valid, and current each condition code that is just providing of its expression ALU is effective in following meaning: they have reflected and the data that require to wait for that feedback command is relevant.

According to the present invention, this characteristic (feature) is to be used for consisting of various conditional branch instructions, according to the result of one section special data of decoding (or processing), the NextState that their decisions will be jumped to. Do not have this facility, just can not test any condition that depends on data in the streamline, this is to mean that the given processing block of a certain order arrival (namely be ALU in this situation) is uncertain because two-wire is controlled.

The Huffman decoder is all passed in non-and all instructions. Some instruction may not need data pipeline just can carry out. They tend to is jump instruction. One of microcode ROM is used for selection instruction and whether gives the Huffman decoder. If do not bother to see me out, just not the Huffman decoder does not receive this instruction, even therefore pipeline blocking in these cases carries out also can continue. B.2.4.2 event handling

Two event bit are arranged in the Parser state machine. One is the Huffman event, and another is the Parser event.

The Parser event is the simplest event. " condition " that is being monitored by this event be in the microcode ROM just. Therefore, an instruction just may cause Par-ser event with this position, position. The below is typical case: this instruction writes a suitable constant in the rom_control register, thereby interrupt service routine can determine the reason of interrupting.

Be (if the event of masking is then gone back immediately) after the Parser Event Service, control continues to get back to the place that it leaves again. If the instruction of firing event has a transfer to make (its condition is assessed as very), then shift and normally carry out. Therefore use shifting the method for coding, just may after service, jump to error handler.

The Huffman event is then different a little. The condition that just is being monitored is the "or" of three Huffman error bits. In fact, very similar to the Parser event to the processing of this condition. But, when mistake occurs, be identified from an outer ledger line huffintr-pt of Huffman decoder. This just makes controls the error handling processing that jumps in the micro code program.

Therefore, when the Huffman mistake occurred, sequence relates to producing interrupted and stop piece. After service, control forwards error handling processing to. Do not have " calling " mechanism, it does not resemble ordinary interruption, there should be no return to the place in the microcode before makeing mistakes after error handling processing.

Might in the situation that does not produce the Huffman mistake, assert huffintrpt. This occurs in the situation that B.2.2.3 saves " inerrancy " mistake of discussing. If so, do not send interruptions (to MPI), but control and still forward to (in the microcode) error handling processing. Because in the case Huffman error register zero clearing, so microcode error handling processing device can determine it is to want error handling processing and make corresponding response. B.2.4.3 special element (locations)

Several special elements are arranged in microcode ROM. Four entrances that the unit is main program among the ROM. When resetting, control forwards of these four unit to. The unit that is transferred depends on the coding standard of selecting, coding_std in the ALU register. Because this element itself is by the real reset-to-zero that resets, control forwards zero location to. But also may reset separately with the UPI register-bit CED_H_TRACE_RST in CED_H_TRACE the Parser state machine. The coding_std register does not reset in the case, and control forwards suitable that in four unit to.

Second group of four unit (0 * 004 to 0 * 007) use when the Huffman interruption occurs. Typical case is: put an instruction of transferring to actual error handling processing device in each part of Unit four. The unit also is that the result according to coding standard selects. B.2.4.4 follow the tracks of

Means as auxiliary diagnosis provide follower. It allows microcode to carry out single step run. This operation is controlled in CED_H_TRACE_EVENT position in the CED_H_TRACE register and CED_H_ TRACE_MASK position. As its name suggests, their operation and some normal event bit are very approximate. But, because some differences (especially never producing UPI interrupts) are arranged, they and other event bit are not classified as a class.

When CED_H_TRACE_MASK put 1, follower was connected. From ROM, read every micro-code instruction, but delivering to before the Huffman decoder goes, a secondary tracking event occurring. In the case, CED_H_TRACE_EVENT is 1. Must inquire about it, because can not produce interruption. Whole microcode word can obtain in the register of CED_H_KEY_DMX_WORD_0 to CED_H_KEY_DMX_ WORD_9. If necessary, can carve at this moment the change instruction. Writing 1 to CED_H_TRACE_EVENT just makes instruction carry out and with the CED_H_TRACE_EVENT zero clearing. At the moment soon, when reading the microcode word that next will carry out from ROM, a new tracking event just appears. B.2.5 microcode

The programming of microcode is by using this a kind of very simple instrument of assembler " hpp ", and many extraction work (abstraction) are by finishing with grand preprocessor. But " C " preprocessor " cpp " of Application standard for this reason.

Being described as follows of code:

Ucode.u is master file. At first, it comprises the tokens.h that defines each token. Secondly, the register image (map) of regfile.h definition ALU. All fields in the fields.u definition microcode word, it provides a symbol table that descends definition, and these symbols are corresponding to each possible bit pattern in the field. Secondly, each label of using in the code is defined again. After finishing this step, it is grand that instr.u removes to define " cpp " that be used in a large number defining elementary instruction. Then, the errors.h definition is used for defining the number of each Parser event. Again, the order of laying field in the microcode word is set up in the unword.u definition.

The remainder of ucode.u is micro code program itself. B.2.5.1 instruction

This section is described in the various instructions that define among the ucode.u. All instructions are not discussed herein, because in many cases, they are the minor variations (especially ALU instruction) under the same subject. B.2.5.1.1 Huffman and data directory instruction

In the present invention, the H_NOP instruction is used by the Huffman decoder. This is nonoperable instruction. To the data decoding, in this sense, what Huffman do not do. The data that this instruction produces are always zero. Therefore, about being sent to ALU, instruction gets on.

Some instructions of next are token class: H_TOKSRCH, H_TOKSKIP_PAD, H_ TOKSKIP_JPAD, H_TOKPASS and H_TOKREAD. These instructions are all read one or several token from the input shift unit, and they are passed to the remainder of machine. H_TOKREAD reads a single token word. H_TOKPASS can be used to read a complete token, until with the word of zero extension bits and comprise it. Information concerning order repeats each token word. H_TOKSRCH abandons the front all serial datas of token, then reads a token word. H_ TOKSKIP_PAD skips all filling positions (H.261 reaching MPEG), then reads a token word. H_TOKSKIP_JPAD does same thing to JPEG filling position.

H_FLC (NB) reads the fixed-length code of " NB " figure place.

H_VLC (TBL) reads a table with a pointed vic (table name mnemonic transmission, such as H_ VLC (tcoeff)).

H_FLC_IE (NB) and H_FLC similar, but the "ignore errors (ignore errors)" Bit.

H_TEST_VLC (TBL) similar H_VLC, but the bypass bit (bypass bit) is set, So Huffman index does not change through the data indexing unit.

H_FWD_R and H_BWD_R read a FLC, respectively, by its bit wide ALU register r_fwd_ r_size and r_bwd_r_size instructions.

Read JPEG format H_DCJ of DC coefficients, the table number from the ALU.

H_DCH read an H.261 DC items.

H_TCOEFF and H_DCTCOEFF transform coefficients are read. In H_DCTOCOEFF in First coefficient position bits for the non-base block, and the DC term is used H_TCOEFF has been read after The base block.

H_NOMINATE (TBL) named a table after downloading.

H_DNL (NB) NB-bit read them all downloaded to the named table. B.2.5.1.2 ALU instruction

Can not explain in detail all of the ALU instructions, because they are just too many. Will be discussed Constitute the basic method of mnemonics, which should make the directive read. In addition, these mnemonics For the person of ordinary skill in the industry should be easy to understand.

Most ALU instructions and data from a transfer to his office, and therefore through the use of Use of the "load (load)" instruction. A_LDxy the mnemonic, of course, the content of y loading Into x, that is listed first goal, after listing source.

Table B.2.10 used to indicate possible sources of data and the purpose of some letters

Alphabet	Significance
		A	A register
R	Run register
		I	Data Input
O	Data Output
		F	ALU register set
C	Constant
		Z	Constant zero

As an example, LDAI the data into the A register, the data from the ALU input port. If you specify an ALU registers, then the mnemonic to bring addresses, so LDAF (RA) will be The contents of register RA group of cells into A.

When the data from the source to the destination when, ALU change it. If this is the case, Arithmetic part of the source data representation. Thus Mnemonic LDA_AADDF (RA) of the A register The current contents of the register, together with the register bank specified in section A of the content loaded. Another Example is LDA_ISGXR, which takes input data, according to the RUN register indicates that a feed Sign-extended, and the result is stored in the A register.

In many cases, the same results specify more than one purpose. As another example, LDF_LFA_ASUBC (RA), it will be the result of A minus a constant loaded into the A register is also both Load registers.

Other mnemonic certain actions. Such as "CLRA" are used to clear the A register Device, "RMBC" macro-block counter is used to (macroblock counter) is reset. These Mnemonic quite obvious that the annotations instr.u have their instructions.

By using a non-conventional suffix "_0", which is used to indicate normal behavior in addition to outside, Operating results will be sent to the token formatter, so LDFI_O (RA) storing the input data and It to the token formatter. Or, if you prefer, this can be a LDF_LDO_I (RA). B.2.5.1.3 token formatter command

T_NOP "no operation" instruction. This is the improper use of the name, because it is impossible to build Establish a no operation instruction. But every time because so far no output ALU and instruction card formatter Unimportant when it is used.

T_TOK output a token word.

T_DAT lose a DATA Token word (only with some of the Huffman state machine directive Use).

T_GENT8 generates a field based on an 8-bit constant token words.

T_GENT8E similar T_GENT8, but the extension bit is 1.

T_OPD (NB) - data bits from the output of the lowest NB NB bits, the remaining bits from constant Digital section.

T_OPDE (NB) is similar T_OPD, but the extension bit is high.

T_OPD8-is T_OPD (8) shorthand.

T_OPD8E-is T_OPDE (8) shorthand. B.2.5.1.4 Parser state machine instruction

D_NOP No Operation instruction: Address usual appreciation and Parser state machine then do not do any of the What additional things. Remnants of the instruction sent to the data lines. Does not appear to wait.

D_WAIT with D_NOP similar, but waiting for feedback soon.

Simple branch instruction groups. If the conditions are met, such as D_JMP (ADDR) and D_JNX (ADDR) is generated like the mnemonic transfers. Directive does not output to the Huffman decoder.

External transfer instruction set. Its mnemonic as D_XJMP (ADDR) and D_XJNX (ADDR). They are simple counter with the above part similar, but the command output to the Huffman decoding Makers.

Transfer and wait for the instruction set. Its mnemonic as D_WJNZ (ADDR). These instructions are input Out to the Huffman decoder in assessing conditions before, Parser wait for feedback from the ALU.

The following mnemonics used in some condition itself.

Table B.2.11 mnemonic used to indicate conditions

Mnemonic		Meaning
			JMP		Unconditional jump
JXT	JNX	If extn = 1 (extn = 0) then jump
			JHE0	JNHE0	If Huffman error bit 0 is set (cleared) Jump
JHE1	JNHE1	If Huffman Error bit 1 set (clear) Jump
			JHE2	JNHE2	If Huffman error bit 2 (cleared) Jump
JPTN		If the mode is the least significant bit shifter Jump
			JPICST	JNPICST	In the image point (not in picture point) Jump
JRSTST	JNRSTST	If the (absent) to restart the starting point of the jump interval
				JNCPBS	If no special coding CPB Jump
	JNCPB8	If it is not eight (i.e., if a 4) Jump macroblock
			JMI	JPL	If is negative (positive) Jump
JZE	JNZ	If zero (non-zero) Jump

Table B.2.11 mnemonic used to represent the conditions (continued)

Mnemonic		Meaning
			JCHNG	JNCHNG	If you change the detection bit (cleared) Jump
JMBST	JNMBST	If the (absent) Jump starting macroblock

D_EVENT result in an event.

D_DFLT used to create a default instruction. It leads to an event, and then transferred to the Labeled "dflt" units. This instruction should never be executed because they are used to fill ROM makes the transfer to a unit into the room without depression.

D_ERROR cause an event, and then transferred to the label "srch_dispatch", In an attempt to recover from the error. B.3 Huffman decoder ALU B.3.1 Introduction

According to the present invention, the Huffman Decoder ALU sub-components of Huffman decoder block Provide regular arithmetic and logic functions. It can do a variety of addition and subtraction operations, various types of Type of sign extension operations and the input data formats into a run-sign-level three- (triples). It also has a flexible structure, the accurate operation and forms a Microinstruction word specifies the microinstruction word synchronization with the input data arrive ALU, which is double Under the control of the interface.

In addition to 36 instructions and 12-bit data input port outside, ALU and the run ends 6 Port and 8-bit constant port (which actually resides on the token bus). In addition microinstruction Words, all of the ports are through the ALU data path width to drive their respective Bus. Are represented in a microinstruction word alone an extended position, even the 17-bit extensions of run-sign-level (out_data) together with the output. At each end of the ALU datapath A two-wire interface. A set of condition codes along with their own valid signal cc_valid together Output. There is also a register set, the other by the Huffman Decoder ALU sub-component can be To access it, computer interface can also access it. B.3.2.2 basic structure ...

In addition to 36 instructions and 12-bit data input port outside, ALU and the run ends 6 Port and 8-bit constant port (which actually resides on the token bus). In addition microinstruction Words, all of the ports are through the ALU data path width to drive their respective Bus. Are represented in a microinstruction word alone an extended position, even the 17-bit extensions of run-sign-level (out_data) together with the output. At each end of the ALU datapath A two-wire interface. A set of condition codes along with their own valid signal cc_valid together Output. There is also a register set, the other by the Huffman Decoder ALU sub-component can be To access it, computer interface can also access it. B.3.2.2 basic structure ...

Input block 400

Output block 401

Condition code block 402

"A ... register 403, the source of multi-

Run register (6 bits) 404, and its source is multiplexed input

Adder / subtractor 405, and its source is multiplexed input

Sign extension logic 406, and its source is multiplexed input

Register group 407

Each of these blocks (except the output block) drives its output data to the one through Path on the bus, which in turn, as the block of the bus multiplexed input source. For example, Adder has its own data path bus, which is the possible number of the A register Inputs. Similarly, A register has its own bus, which formed Addition The number of possible inputs. In this respect there is only a subset of all possibilities, Section 7 microinstruction word in detail.

May execute in a single cycle in addition based instruction or perform a To sign-extended based instruction. But can also allow the simultaneous execution in a single cycle two Instruction, as long as their operating strictly parallel. That is to say, does not allow the added first Expansion symbol or symbols after the first expansion of the sum of the sequence. In a single cycle, register Groups can either read or write, but not both read and write.

The output data has three fields:

Being translated ...

Being translated ...

Being translated ...

If the data to be directly through the ALU, the least significant input data register 11 Locked into sign and level fields.

There may be a finite number of multi-cycle ALU operations to be programmed. In this regard, the required The number of cycles set by the register where the contents of the cell is given the address of the register bank locations Designated by the microinstruction; when iteration counter to 1, the same operation is repeated. This Convenient conditions typically used to implement the left: Use the A register contents adder to itself Canada, and the result is stored back to A register. B.3.3 adder / subtractor block

This is a 12-bit wide adder input2 can choose its value is set to a negative Values ​​are included for carry (carry-in bit) can be set or not set selection. The output is a 12-bit and does not use its carry output (carry-out). There are seven operating modes:

· ADD: Carry, carry position zero: input1 + input2

· ADC: Carry, carry Position 1: input1 + input2 +1

· SBC: input2 negated, into the bit position zero: input1-input2-1

· SUB: input2 negated, into bit position 1: input1-input2

· TCI: if input2 <0, use the SUB, otherwise use the ADD.

This mode is used from the two's complement value gives to the size, when used input1 Set to zero.

· DCD (DC Poor): If inpt2 <0 is carried ADC, or for ADD.

· VRA (vector residual value plus): If input1 <0 is carried ADC, or conduct SBC. B.3.4 sign extension sub-block

This is a 12-bit unit, which in different ways according to the input size of the input data Sign extension. The size is a 4-bit binary number, a value of 0 to 11 (0 corresponds to the The least significant bit, 11 corresponds to the most significant bit). The output is a change in the value of 12-bit data Plus "sign" bit.

In SG × MODE = NORMAL mode, above all in the first place size (including the first bit size Size of you take the first bit value. All of the following you are left unchanged. Symbols take the first bit size Value. For example:

data (data) = 101010101010

size＝2

output (output) 0000 0000 0010, sign (symbol) = 0

In SG × MODE = 1NVERSE way, all in the first size bit more (including the first size Bit) of you take the first size bit counter value, and all of the following Members remain unchanged. The sign No. size bit counter value. For example:

data＝1010 1010 1010

size＝0

output＝1111 1111 1111，sign＝1

In SG × MODE = DIFMAG way, if the first bit is zero size, all in the first size bit less (including the first size bits) of you negated, and all of the above you are left unchanged. If the first size to 1, all you are left unchanged. In both cases, symbols are taken of size-bit counter value. The method for obtaining the AC magnitude of the difference. For example:

data＝0000 1010 1010

size＝2

output＝0000 1010 1101，sign＝1

data＝0000 1010 1010

size＝1

output＝0000 1010 1010，sign＝0

In SG × MODE = DIFCOMP way, all in the first size bit more (excluding the first size bits) of you take the first size-bit counter value, and all of the following Members (including the first size) Remain unchanged. Symbols take the first size bit counter value. This method is used to obtain the difference of the two DC The complement value. For example:

data＝1010 1010 1010

size＝0

output = 1111 1111 1110, sign = 1 B.3.5 condition code

Huffnan block code used for each condition with two bytes (16 bits), where some bits By the ALU / register bank generated. The condition code is: Sign (Symbol) condition code, Zero (Zero) condition code, Extension (extended) condition code and change detection bit (Change Detect bit). Since the last two codes Parser usage and several other different, these last two Species is not a true condition code.

Sign, Zero and Extension condition code in issuing an update command Parser Update; corresponding each of these instructions the condition code valid signal is a positive pulse is formed.

Sign condition code is only symbolic sign extension output latch, and if A register Register input is zero Zero condition code set. Extension condition code is latched input expansion Booths, and OUTSRC irrelevant.

Condition code can be used to assess certain conditions type:

· Result equal to a constant - and the Zero conditions using subtraction

· Result equals register value - Zero using subtraction and conditions

· Register equal to a constant - and the Zero conditions using subtraction

· Register bit - Use Sign (sign) to expand and Sign Conditions

· Results bit - Use Sign (symbols) and Sign Conditions

Note that when using the sign extension and Sign condition code combinations, only a single assessment may Rather than using the usual specified bit logic 'and' assessment as to a plurality of bits.

In the present invention, the change detection bit is set by the same logic Zero condition code generation, but It is not accompanied by a valid signal. The one microinstruction indicates if the current is being written Register set value different from the value that already exists (which means that requires two clock cycles, the first One cycle will REG-MODE is set to READ, the second cycle will REGMODE set to WRITE), on Change detection position should be updated. If it detects a change in the value, the microprocessor then began Interrupts. Change detection position by the usual effective way to reset it, but this REGMODE is set to READ.

Hardwired macroblock counter structure (register part of a group - see below) Also produces the following condition codes: Mb_Start, Pattern_Code, Restart and Pic Start. B.3.6 register set (Register File)

Register bank address conversion table below shows. It uses a total of ALU data path and UPI A seven-bit address space, some addresses are not accessible ALU, since these are usually hard- Wiring within the structure of a macroblock counter or registers within the ALU itself. The latter has designated With the access address, but it is the address conversion table UPI component. Some multi-byte single Million (to increase the size of the table with "0", there is a single ALU address, but multiple UPI Address. Similarly, there are several types with component count (component count) CC (in the table With I "indicates) ALU index registers are treated as a single location. This is initialized Reset (resetting) and the operation of micro-macro block programming convenience. ...

Register bank address conversion table below shows. It uses a total of ALU data path and UPI A seven-bit address space, some addresses are not accessible ALU, since these are usually hard- Wiring within the structure of a macroblock counter or registers within the ALU itself. The latter has designated With the access address, but it is the address conversion table UPI component. Some multi-byte single Million (to increase the size of the table with "0", there is a single ALU address, but multiple UPI Address. Similarly, there are several types with component count (component count) CC (in the table With I "indicates) ALU index registers are treated as a single location. This is initialized Reset (resetting) and the operation of micro-macro block programming convenience. ...

In the present invention, some of the contents of the cell are hard wired to the Huffman coding subsystem (subsystem_coding) standard other parts, which are: two r-size locations, And go to the Huffman Decoder Every ac huff tables and dc huff table single unit (2 words).

Some addresses indicated in bold can be accessed ALU and UPI, the other only by UPI Access. Not by the ALU some guidance through the CC register class can have an instruction word Specify a single ALU address, CC will select the physical unit which you want to access. But ALU address Any one of the class register address, though often should use the first address. Multi-byte Unit is also true, you should use address pairs (pair) the lowest that, although the real On occasion to meet with the two addresses are sufficient. Note that the unit 2E and 2F can be at the highest level (top- level) in the address conversion table is accessed (with "T" means), which not only through some keyhole (keyhole, showing hip) register. These two units have been reset to zero. ...

Some addresses indicated in bold can be accessed ALU and UPI, the other only by UPI Access. Not by the ALU some guidance through the CC register class can have an instruction word Specify a single ALU address, CC will select the physical unit which you want to access. But ALU address Any one of the class register address, though often should use the first address. Multi-byte Unit is also true, you should use address pairs (pair) the lowest that, although the real On occasion to meet with the two addresses are sufficient. Note that the unit 2E and 2F can be at the highest level (top- level) in the address conversion table is accessed (with "T" means), which not only through some keyhole (keyhole, showing hip) register. These two units have been reset to zero. ...

Table B.3.1 Table 1: Huffman shift register group address table

I	37	ac huff3		MJ		79	h1
										I	38	tq0		MJ	7A	h2
I	39	tq1		MJ	7B	h3
									I	3A	tq2		MJ	7C	v0
I	3B	tq3		MJ	7D	v1
									I	3C	c0		MJ	7E	v2
I	3D	c1		MJ	7F	v3

Table B.3.1 Table 1: Huffman shift register group address table (continued)

JPEG differences

	10	horiz pels 1
					11	horiz pels 0
	12	ven pels 1
					13	ven pels 0
	14	buff size 1
					15	buff size 0
	16	pel asp.ratio
					17	bit rate 2
	18	bit rate 1
					19	bit rate 0
	1A	pic rate
					1B	constrained
	1C	picture type
					1D	H261 Picture type
	1E	broken closed
					1F	pred mode
	20	vbv delay 1
					21	vbv delay 0
	22	pending frame ch
					23	restart index
	24	horiz mb copy
					25	pic number
	26	max h
					27	max v
	28	-
					29	-
	2A	-
					2B	-
	2C	first scan
					2D	in picture
	2E	rom control
					2F	rorm revision

Table B.3.2 JPEG differences

H.261 differences

	10	horiz pels 1
					11	horiz pels 0
	12	vert pels 1
					13	vert pels 0
	14	buff size 1
					15	buff size 0
	16	pel asp.ratio
					17	bit rate 2
	18	bit rate 1
					19	bit rate 0
	1A	pic rate
					1B	constrained
	1C	picture type
					1D	H261 picture type
	1E	broken closed
					1F	pred mode
	20	vbv delay 1
					21	vbv delay 0
	22	full pel fwd
					23	full pel bwd
	24	horiz mb copy
					25	pic number
	26	max h
					27	max v
	28	-
					29	-
	2A	-
					2B	in gob
	2C	first group
					2D	in picture
	2E	rom control
					2F	rom revision

Table B.3.3 H.261 differences

	2C	first group
					2D	in picture
	2E	rom control
					2F	rom revision

B.3.7 microinstruction word

According to the present invention, ALU microinstruction word is divided into several fields, each field control A different aspect of the above structure. The total use of the instruction word is 36 bits (plus a For the extension bit input), with a minimum cross-field coding, so keep the hardware configuration Maximum flexibility. See below detailed instruction word segmentation. The default field values​​, that is, those not changed Variable ALU or register group status values ​​are given in italic typeface.

Being translated ...

Being translated ......

RZADD run, zero, the output of the adder 1001

RIADD input operation, zero output of the adder

ZSADD zero, symbols output from the adder 1010

ZZADD zero, zero, output of the adder 1011

NONE No valid output-out_valid Zero 11XX REGADDR 00-7F access register used for ALU in groups 7 REGSRC ADD driven to the output of the adder input register bank 0

Top SGX will be sign-extended output driver to lose a register bank

Into the above REGMODE READ read from the register bank 0 WRITE write register group 1 CNGDET TEST If REGMODE is WRITE, the update changes 0

Detect Change detection does not update the change detection HOLD bit 1 CLEAR if REGMODE to READ the change detection reset 0 RUNSRC RUNIN will run the input drive to run the register input of 0

On (Running source) ADD driven to the output of the adder inputs 0 runs register

Top

Table B.3.4 Table 2: Huffman ALU microinstruction fields (continued) Bit Field Value Description RUNMODE LOAD update run register 0 HOLD do not update run register 1 ASRC ADD the adder output drive to the A register input above 00 (A Storage INPUT The input to the A register input data driven above 01 For source)

SGX will be sign-extended to the A register input output driver 10

On

REG output driver will register set to the A register input of 11

On AMODE LOAD update A register 0

HOLD do not update the A register 1 SGXMODE NORMAL sign extension to take the same value of 00 (Sign extension INVERT sign extension negated value 01 Exhibition mode, DIFMAG sign bit is 0 if you take anti-10 lower See 3.4) DIFCOM sign extension, starting from the next high negated value 11 SIZESRC CONST the constant input drive to the sign-extended size lose 00

Into the above (Sign extension A of the A register is driven to sign extension size input 01 Exhibition on

Table B.3.4 Table 2: Huffman ALU microinstruction fields (continued) Bit Field Value Description SIZF lose REG output driver will register set to sign extension size 10 Enter into the top Source) RUN will run the register drives to sign extension size 11 Loss

Into the above SGXSRC INPUT driven to the input data sign extension size input 0

Top (sqx Input) A sign of the A register is driven to expand size of an input

On ADDMODE ADD Input 1 + Input 2000 (Adder input ADC input 1 + 2 + 001

Mode See 3.3) SBC Input 1 - Input 2-1010

SUB Input 1 - Input 2011

TCI If you lose 22 <0 SUB, or ADD-2's complement of 100

Code

DCD If you enter 2 <0 ADC, or ADD-DC Poor 101

VRA If you enter a <0 ADC, or SBC-vector 110

Residual value plus ADDSRC1 A drive of the A register to the adder input a top 00 (REG to register group adder output driver input to the adder 101 Enter the above

Table B.3.4 Table 2: Huffman ALU microinstruction fields (continued) Bit Field Value Description A source - INPUT The input data to the adder input a driver over 10 Not inverted) ZERO to zero drive to the adder input a top 11 ADDSRC2 CONST the constant drive to the adder input 2 over 00 (Take A to A register input to the adder input 2 drives over 01 Anti source) INPUT drive input data to the adder 10 on input 2

REG output driver will register set to the adder input 2 of 11

On CNDCMODE TEST update the condition code 0 (Condition code) HOLD do not update the condition code 1 CNTMODE NOCOUNT the counter does not add value × 00 (Macro block junction BCINCR block counter and pulse (ripple) added 001

Constitutive counts Way) CCINCR mandatory component count value 010

RESET within the structure of the macro block 011 resets all counters

DISABLE disables all counters 1 × × INSTMODE MULTI-election on behalf of the current instruction 0 times

SINGLE is only a single-cycle instruction B.4 Buffer Manager (Buffer Manager) B.4.1 Introduction

According to the invention, this document describes the cache manager (bman) uses, effects and The specific devices. B.4.2 Overview

Buffer manager provides four addresses for the DRAM interface. These addresses are the DRAM Page address. Within a DRAM DRAM interface contains two FIFO, coded data buffer and make Card data buffer. Thus, for these four addresses, each have a buffer read address And a write address. B.4.3 Interface

Buffer manager receives only DRAM interface and the microprocessor. Microprocessor is only used Set the "Initialize register" (see Table B.4.4). The interface with the DRAM interface is a four 18-bit addresses, each address by a request / response (REQuest / ACKnowledge) protocol control The system. (Because the Cache Manager is not in the data path, and would therefore not buffer manager There are two-wire interface. )

Furthermore, the buffer manager for operation without (operates off) DRAM interface clock Generator, but (on) DRAM interface, the scan chain (scan chain). B.4.4 address calculation

Each buffer read address and write address consists of nine 18-bit register to generate:

Initialization Register (read by the microprocessor)

· BASECB-coded data buffer base address

· LENGTHCB-coded data buffer maximum size (Unit: page)

· BASETB-token data buffer base address

· LENGTHTB-token data buffer maximum size (Unit: page)

· LIMIT-DRAM capacity (Unit: page)

Dynamic register (from the microprocessor read)

· READCB-relative BASECB the coded data buffer read pointer

· NUMBERCB-relative READCB the coded data buffer write pointer

· READTB-relative BASETB token data buffer read pointer

· NUMBERTB-relative READTB token data buffer write pointer

Address formula:

readaddr (read address) = (BASE + READ) mod LIMIT

writeaddr (read address) = (((READ + NUMBER) mod LENGTH) + BASE) mod LIMIT

Used "mod LIMIT" term is because the cache can overlap around DRAM (Wrap around DRAM). B.4.5 Description of the blocks

In the present invention, as shown in Figure 127, the buffer manager connected in a ring from the three Top (top level) modules, rings peeking device (snooper) monitoring the DRAM interface Connections. These modules are bmprtize (prioritized), bminstr (instruction) And bmrecalc (recalculate), are arranged in this order in a ring, and bmsnoop (Kuice device) arranged in each address output. Module Bmprtize processing REQ / ACK protocol and each buffer FULL / EMPTY (full / empty) flag, it contains each of the ground Site state that "This is a valid address?." Based on this information, it provides bminstr should be recalculated which address (assuming there is one). It also manages BUF_CSR (State) microprocessor register, indicating the FULL / EMPTY flag; and manage buf_ Microprocessor register access, and control the microprocessor of the storage buffer manager The write access. ...

In the present invention, as shown in Figure 127, the buffer manager connected in a ring from the three Top (top level) modules, rings peeking device (snooper) monitoring the DRAM interface Connections. These modules are bmprtize (prioritized), bminstr (instruction) And bmrecalc (recalculate), are arranged in this order in a ring, and bmsnoop (Kuice device) arranged in each address output. Module Bmprtize processing REQ / ACK protocol and each buffer FULL / EMPTY (full / empty) flag, it contains each of the ground Site state that "This is a valid address?." Based on this information, it provides bminstr should be recalculated which address (assuming there is one). It also manages BUF_CSR (State) microprocessor register, indicating the FULL / EMPTY flag; and manage buf_ Microprocessor register access, and control the microprocessor of the storage buffer manager The write access. ...

Module Bmrecalc in bminstr recalculated under the instruction address. This module every two Cycles run a command, it contains all the initialization registers and dynamic registers, Also includes a do addition, subtraction modulo arithmetic simple ALU. When it is complete address Calculation or it detects FULL / EMFTY state, put these states to inform bmprtize. B.4.6 Block implementation B.4.6.1 Bmprtize

In the reset state, buf_access microprocessor register is set to 1 to allow the early Initialization registers. When buf_access read back to 1, do not start address is calculated, Because there is no valid initialization register these calculations would be meaningless.

Once buf_access removed confirmation (de_asserted) (it writes zeros), bmprtize embarking make all addresses as valid (used to recalculate these addresses), because Its purpose is to keep all four addresses are valid. At present, the buffer manager is "Start" (ie, not all addresses calculated), the request is not recognized. Once all the Address becomes effective, the startup phase comes to a close, all requests are confirmed. Since then, When an address becomes invalid (because it has been used and the response too), the address on the re- Calculation.

Never need to set the priority level for each address, since the capacity is the DRAM interface Fast every 17 cycles using an address and the ability to buffer manager 12 cycles per Recalculate an address. So after each start is always only one address is invalid. Therefore bmprtize will recalculate any invalid address are not currently calculated.

In the present invention, when buf_access is confirmed, the start will be re-entered, as Here, the microprocessor during each visit, will not have the address provided to the DRAM interface. B.4.6.2 Bminstr

Bminstr module contains a mold 12 cycle counter (used for generating an address Number of cycles). Note that even one instruction cycle is initiated, the end of an odd-numbered cycles Instruction. 3 together with the highest calculated which is read or write calculations together are decoded into bmreca- lc the following command:

For the read address:

Table B.4.1 read address calculation A bus B bus cycle operation results symbolic significance of the results 0-1 ADD READ BASE 2-3 MOD accumulator LIMIT address 4-5 ADD READ "1" 6-7 MOD Accum LENGTH READ 8-9 SUB NUMBER "1" NUMBER 10-11 MOD "0" Accum SET_EMPTY

                                             (NUMBER＞＝C)

For write address:

Table B.4.2 for the write address calculation A bus B bus cycle operation results symbolic significance of the results 0-1 ADD NUMBER READ 2-3 MOD Accum LIMIT 4-5 ADD Accum BASE 6-7 MOD Accum LIMIT Address 8-9 ADD NUMBER "1" NUMBER 10-11 MOD Accum LENGTH SET_FULL

                                        (NUMBER＞＝

LEHGTH) Note: The result of the last operation is always retained in the accumulator.

When there is no need to recalculate the address when idle cycle counter at zero value, Generating an instruction does not write to any register. This does not have any effect. B.4.6.3 Bmrecalc

Module Bmrecalc every two clock cycles to complete an operation. In an even count Control period (start_alu_cyc) inside, it will come from the bminstr instruction (and which Buffers, input or output) latches come in an odd counter cycle (end _alu_cyc) within the latch operation result. Operating results in addition to the specified stored in the instruction register Kept inside, but also always be stored in a named "Accum" the register. In addition, end_alu_cyc cycle, bmrecalc inform bmprtize address just calculated to With a full or empty buffer causes, and when the address and full / empty has been successfully calculated load_addr).

Full / empty result of the operation is the use of the sign bit to be calculated.

Module is not true modulo operation, A mod B is achieved by:

(A＞B？(A-B)：A)

However, this was just an error in the following situations:

A＞(2B-1)

This will never occur. B.4.6.4 Bmsnoop

Module consists of four 18 Bmsnoop super spy device (snoopers) composition, they Monitors the DRAM interface provides the respective addresses. Spy must be "super" (i.e. Can be accessed at run-time clock), to permit on-chip testing of the external DRAM. These Spy device must REQ / ACK (request / response) way, so the use of the device And other spy devices are different.

In this interface uses the REQ / ACK instead of wire protocol because it sends information (ie Response) to return to the sender without receiving. So, which strictly monitors the various means FIF0 Needles. B.4.7 register

In order to obtain the microprocessor write access to the initialization registers, should buf_ access to write one, and then only when buf_access read back a given access. On the contrary, to put Abandoned microprocessor write access, you should write to buf_access zero. When buf_access Reading Back to zero before giving access. Note, buf_access reset to 1.

The present invention can be dynamically register and initialize the registers to read at any time. However, in order to ensure that the dynamic register without gradually changing (are not changing) microprocessor Processor, you must obtain write access.

Only going to be written once for each initialization registers. They may lead to re-write The buffer does not operate correctly. But can I count on-the-fly when you want to increase the buffer length Degree (length) and at the appropriate time to make the total buffer manager use the new length.

Never not initialize the registers of each value within the line checks to ensure their practical (Such as to ensure that the cache does not overlap with each other). It is the user's responsibility.

Table B.4.3 Buffer manager non-keyhole registers

Register name	Usage	Address
			CED_BUF_ACCESS	xxxxxxxD	0x24
CED_BUF_KEYHOLE_ADDR	xxDDCDDD	0x25
			CED_BUF_KEYHOLE	DDDDDDDD	0x26
CED_BUF_CB_WR_SNP_2	xxxxxxDD	0x54
			CED_BUF_CB_WR_SNP_1	DDDDDDDD	0x55
CED_BUF_CB_WR_SNP_0	DDDDDDDD	0x56
			CED_BUF_CB_RD_SNP_2	xxxxxxDD	Dx57
CED_BUF_CB_RD_SNP_1	DDDDDDDD	0x58
			CED_BUF_CB_RO_SNP_0	DDDDDDDD	0x59
CED_BUF_TB_WR_SNP_2	xxxxxxDD	0x5a
			CED_BUF_TB_WR_SNP_1	DDDDDDDD	0x5b
CED_BUF_TB_WR_SNP_0	DDDDDDDD	0x5c
			CED_BUF_TB_RD_SNP_2	xxxxxxDD	0x5d
CED_BUF_TB_RD_SNP_1	DDDDDDDD	0x5e
			CED_BUF_TB_RD_SNP_0	DDDDDDDD	0x51

Table D indicates the register bits, X is not a register bit.

Table B.4.4 in the buffer manager keyhole registers

Keyhole register name	Usage	Keyhole address
			CED_BUF_CB_BASE_3	xxxxxxxx	0x00
CED_BUF_CB_BASE_2	xxxxxxDD	0x01
			CED_BUF_CB_BASE_1	DDDDDDDD	0x02
CED_BUF_CB_BASE_0	DDDDDDDD	0x03
			CED_BUF_CB_LENGTH_3	xxxxxxxx	0x04
CED_BUF_CB_LENGTH_2	xxxxxxDD	0x05
			CED_BUF_CB_LENGTH_1	DDDDDDDD	0x06
CED_BUF_CB_LENGTH_0	DDDDDDDD	0x07
			CED_BUF_CB_READ_3	xxxxxxxx	0x0B
CED_BUF_CB_READ_2	xxxxxxDD	0x09
			CED_EUF_CB_READ_1	DDDDDDDD	0x0a
CED_BUF_CB_READ_0	DDDDDDDD	0x0b
			CED_EUF_CB_NUMSER_3	xxxxxxxx	0x0c

B.4.8 checksum

Check carried out in Lsim, with some small FIFO added simulated (dummy) DRAM Interface, the use of C code chip as the top part of the simulation. B.4.9 Test

The test is done by covering bman various spy devices within bmsnoop (Snoopers), each Dynamic register (see Section B.4.4) and using the scan chain to carry out. The scan chain is DRAM Interface scan chain. B.5 inverse model control (Inverse Modeler) B.5.1 Introduction

According to the invention described in this document Reverse stylers (imodel) and this card formatter (hsppk) the purpose, role and concrete realization.

Keyhole register name	Usage	Keyhole address
			CED_BUF_CB_NUMBER_2	xxxxxxDD	0x0d
CED_BUF_CB_NUMBER_1	DDDDDDDD	0x0e
			CED_BUF_CB_NUMBER_0	DDDDDDDD	0x01
CED_BUF_TB_BASE_3	xxxxxxxx	0x10
			CED_BUF_TB_BASE_2	xxxxxxDD	0x11
CED_BUF_TB_BASE_1	DDDDDDDD	0x12
			CED_BUF_TB_BASE_0	DDDDDDDD	0x13
CED_BUF_TB_LENGTH_3	xxxxxxxx	0x14
			CED_BUF_TB_LENGTH_2	xxxxxxDD	0x15
CED_BUF_TB_LENGTH_1	DDDDDDDD	0x16
			CED_BUF_TB_LENGTH_0	DDDDDDDD	0x17
CED_BUF_TB_READ_3	xxxxxxxx	0x18
			CED_BUF_TB_READ_2	xxxxxxDD	0x19
CED_BUF_TB_READ_1	DDDDDDDD	0x1a
			CED_BUF_TB_READ_0	DDDDDDDD	0x1b
CED_BUFTB_NUMBER_3	xxxxxxxx	0x1c
			CED_BUF_TB_NUMBER_2	xxxxxxDD	0x1d
CED_BUF_TB_NUMBER_1	DDDDDDDD	0x1e
			CED_BUF_TB_NUMBER_O	DDDDDDDD	0x11
CED_BUF_LIMIT_3	xxxxxxxx	0x20
			CED_BUF_LIMIT_2	xxxxxxDD	0x211
CED_BUF_LIMIT_1	DDDDDDDD	0x22
			CED_BUF_UMIT_0	DDDDDDDD	0x23
CED_BUF_CSR	xxxxDDDD	0x24

Table B.4.4 in the buffer manager keyhole registers

Note: hsppk in the system is the Huffman decoder part, but in function, but Part is the reverse stylers. So be discussed in this section is better. B.5.2 Overview

Token buffer is imodel and hsppk between, it can accommodate a large number of data, These data all on-chip (off_ohip) of DRAM. In order to ensure effective use of the Memory, the data must be 16-bit format. Formatter from the Huffman decoder Data "package" (paoks) to fit today licensing buffer this format. Thereafter, Inverse model is now licensing the data from the buffer format "unpack (unpaoks)" out.

However, the inverse model's main function is to the "run / level (run / level) Code expansion, and become a zero-data run, successor a level. In addition, reverse The model is to ensure that the DATA tokens have at least 64 coefficients, it provides a "gate (gate)" Used to stop the never meet their criteria for those starting stream (streams). B.5.3 Interface B.5.3.1 Hsppk

In the present invention, Hsppk a Huffman Decoder as input and the Token buffer as As output. These two interfaces are dual type, the input is a 17 port token (Port), the output is 16 "packed data", plus a FLUSH signal. In addition Hsppk clock from Huffman clock generator, so it is connected to the Huffman scan Chains. B.5.3.2 Imodel

Imodel start with the token buffer output gate logic (start_up output gate logic) (bsogl) as inputs and inverse quantizer (Inverse Quantizer) as the output. Input from the token cache 16-bit "packed data", plus block_end (block End) signal coming from a wirestream_enable bsogl signal. The output is An 11-bit token port. All interfaces are protected by wire interface protocol (protocol) control. Imodel has its own clock generator and the scan chain.

Imodel and Hsppk microprocessor access only to the two blocks at the output of each of them A spy device. B.5.4 Description of the blocks B.5.4.1 Hsppk

Hsppk from Huffman taken into 17 data, and output 16-bit data to the token buffer. This process is accomplished: first, the input data truncation (truncating) or of Cutting (splitting) into a number of 12-bit words, these words will next packaged into 16-bit format. B.5.4.1.1 Split

Hsppk from Inverse Huffman received 17 data. Use the following format This data is formatted into 12 bits.

Where F = the specified format; E = extended position; R = RUN bit; L = length of the bit (in accordance with the Symbol Value arrangement) or data token bit; X = without care.

    FLLLLLLLLLLLFormat 0

    ELLLLLLLLLLLFormat 0a

    FRRRRRR00000Format 1

Normal token occupy only a minimum 12-bit, in the form of:

    ExxxxxxLLLLLLLLLLL

This is truncated format 0a. However, each word in the data token in a run and a level, in the form of:

    ERRRRRRLLLLLLLLLLL

This is divided into the following format:

       ERRRRRRLLLLLLLLLLL-＞FRRRRRR00000Format 1

ELLLLLLLLLLLFormat 0a Alternatively, if the run is zero format 0 is used:

       EOOOOOOLLLLLLLLLLL-＞FLLLLLLLLLLLFormat 0

As can be seen in the format 0, the extension bits missing, assuming it is 1. Therefore, when the expansion Booth zero can not be used Format 0. In this case, format 1 is unconditionally used. B.5.4.1.2 packing (packing)

After the split, all data words are 12-bit width. Each of the four 12-bit word was beaten Pack into three 16-bit words:

Table B.5.1 packing methods

Each input word	Each output word
		000000000000	0000000000001111
111111111111	1111111122222222
222222222222	2222333333333333
		333333333333

B.5.4.1.3 buffer flushing (flushing)

DRAM interface of the present invention in the collection of a (32 16 "After the package" of the word) of the Later, and then write it to the buffer. This means that if the block is only partially complete, then the number It is available in a stream (stream) at the end stuck inside the DRAM interface. Therefore, a need for a Rinse skills. Accordingly, Hsppk signals the DRAM interface unconditionally write its current portion Of complete blocks. B.5.4.2.1 Imup (UnPcker, unpacker)

Imup accomplish three functions:

1) unpack the data from its 16 format into a 12-bit word.

Table B.5.2 unpack methods

Enter the word	Output word
		0000000000001111	000000000000
1111111122222222	111111111111
		2222333333333333	222222222222
	333333333333

2) Clear the token buffer maintained during the correct data.

When the DRAM interface with unconditional write current section complete block method flush when Waste (rubbish) data is retained in the block. imup must delete junk data is deleted All data from the FLUSH token, until the end of the block.

3) Save the data in place until the start criterion (statr_up Criteria) is full Foot

The output data from the block condition is: for each different stream received from the buffer Starting device (Buffer Startup) of the "active" signal (stream_enable). Thus, 12-bit data is output to the hsppk. B.5.4.2.2 Imex (Expander expander)

In the present invention, Imex all the run-length code (run length codes) extension Charge for a number of values ​​is zero run, successor to a level. B.5.4.2.3 Impad (PADder, loader)

Impad body to ensure that all data token containing 64 (or more) words. It is The last word of the token number 0 to do the loading. Data token is not checked on it There are 64 more than in the body of the word. B.5.5 block implementation B.5.5.1 Hsppk

Typically, the segmentation and packaged in a single cycle. B.5.5.1.1 segmentation (splitting)

First, you must determine the format

IF(datatoken)

IF(lastformat＝＝1) use format 0a；

ELSE IF(run＝＝0) use format 0；

ELSE use format 1；

ELSE use format 0a；

Second, you must determine the format bits

format 0 format bit＝0；

format 0a format bit＝extension bit；

format 1 format bit＝1；

If you use the Format 1, in the next cycle should not accept new data because code level there must be output. B.5.5.1.2 packaged

Each of the four valid data packing process cycle time. 16-bit word output from retained The last significant word and its successor words. If this component is invalid, then the output is not Effect. Process:

Table B.5.3 packaging process

	Reserved words	Succeeding word	Compound word
					Effective period 0	XXXXXXXXXXXX	000000000000	XXXXXXXXXXXXXXXX	Must not Export
Effective Cycle 1	000000000000	111111111111	0000000000001111	Export
					Effective Period
2	111111111111	222222222222	1111111122222222	Export
					Effective Cycle
3	222222222222	333333333333	2222333333333333	Export

An x indicates undefined bits.

During the effective period 0, there is no word output, since the word is not valid.

Effective counter-dimensional endless number of cycles to be. Increment the counter by the division of the effective Data, and an output to control accepted.

When you receive FLUSH token (or picture_end) and the token itself ready output, FLUSH signal is also output to the DRAM interface so that the effective period is reset to zero. If FLUSH Tokens in addition to any time period 3 came outside, then FLUSH signal is delayed one week to To ensure the token itself is output. B.5.5.2 Imodel B.5.5.2.1 Imup (UnPacker unpacker)

The same as with the packer, the last valid entry is stored, and with the next input Combined, then allowed to unpack.

Table B.5.4 unpacking process

	Succeeding word	Reserved words	After unpacking the word
					Effective period 0	0000000000001111	xxxxxxxxxxxxxxxx	000000000000	Enter
Effective Cycle 1	1111111122222222	0000000000001111	111111111111	Enter
					Effective Period 2	2222333333333333	1111111122222222	222222222222	Enter
Effective Cycle 3	2222333333333333	1111111122222222	333333333333	Do not enter

Where x is undefined bits.

Effective cycle consists of a ring counter to maintain. Unpacked data contains the token Data, FLUSH, and decoded by the FLUSH PICTURE_END signal. Additionally, format and extension Booth also unpack the data from the decoded.

formatbit_is extn＝(lastformat＝＝1) ll databody

format＝databody && (formatbit && lastformatbit)

Used to decode the token and send it to imex.

When a FLUSH (or picture_end) out of the token is unpacked and output to imex , All data is deleted (Valid is forced low) until the block received from the DRAM interface End signal. B.5.5.2.2 Imex (expander)

According to the present invention, imex is the run / level codes out of the four-state machine expansion. That State machine are:

· State 0: From the run code into rum count.

· Status 1: run down counting, the output you zero.

· State 2: input data and output levels; default state.

· State 3: Illegal state. B.5.5.2.3 Impad (loader)

Data token header consists imex inform Impad. Next, impad coefficients of the token body Was counted. If the token is reached before the end of the 64 coefficients, then the end of the token Insert the value of zero coefficients, the coefficients of the token 64. For example, data is not extended There are 64 heads in a subsequent zero coefficients inserted. With 64 or more coefficients of the data token from impad impact. B.5.6 register

The invention imodel and hsppk no microprocessor registers, but their glimpse Detector excluded.

Table B.5.5 Imodel and hsppk register Register Name Usage Address CED_H_SNP_2 VAxxxxxx 0X49 CED_H_SNP_1 DDDDDDDD 0X4a CED_H_SNP_0 DDDDDDDD 0X4b CED_IM_SNP_1 VAExxDDD 0X4a CED_IM_SNP_0 DDDDDDDD 0X4d

Where V = Valid bit; A = acceptor site; E = extended position; D = data bit. B.5.7 checksum

The selected flow through Lsim simulation run. B.5.8 Test

Tokens in the input buffer output peeking through the device, the output itself through imodel The control to achieve the imodel Kuice tests. By imodel own scan chain to achieve Logic.

hsspk output can be output through the huffman Kuice browser to access. Logic can pass Over huffman scan chain to observe. B.6 cache starter (Butfer Start_up) B.6.1 Introduction

Described in this section according to the present invention, methods and implementation starting buffer. B.6.2 Overview

In order to ensure smooth and continuous image stream can be displayed, before the start of the decoding can be Collect a certain amount of data. This is called starting conditions. Coding standard specifies a VBV Delay, this delay can be substantially converted to the amount of data to be collected. "Cache start" the Purpose is to ensure that in every stream of data from the token buffer advance to allow decoding Before the start of the stream to meet its conditions. Stream is a nominal (notional) gate (input Out) held in each buffer. This door is in the output of the token buffer (i.e. Inverse model inside), it is only the start of the flow conditions have been met when the stream open. B.6.3 Interface ...

In order to ensure smooth and continuous image stream can be displayed, before the start of the decoding can be Collect a certain amount of data. This is called starting conditions. Coding standard specifies a VBV Delay, this delay can be substantially converted to the amount of data to be collected. "Cache start" the Purpose is to ensure that in every stream of data from the token buffer advance to allow decoding Before the start of the stream to meet its conditions. Stream is a nominal (notional) gate (input Out) held in each buffer. This door is in the output of the token buffer (i.e. Inverse model inside), it is only the start of the flow conditions have been met when the stream open. B.6.3 Interface ...

As shown in Figure 130, Bscnbit located within the data path. The pathway in the start code detection Detectors and between the coded data buffer. Bscntbit This leaves the single-cycle components for Valid data block word count, and this number must be loaded by the microprocessor Kai Dynamic conditions (or called the target) compared. Once the target is reached, the notification bsogl. Number It is not bscntbit impact.

As shown in Figure 130, Bscnbit located within the data path. The pathway in the start code detection Detectors and between the coded data buffer. Bscntbit This leaves the single-cycle components for Valid data block word count, and this number must be loaded by the microprocessor Kai Dynamic conditions (or called the target) compared. Once the target is reached, the notification bsogl. Number It is not bscntbit impact....

Only a certain queue depth, however, can be disconnected in the queue within bsogl and allows Xu microprocessor monitors the queue, with this method, the depth can be infinitely expanded. These Institutions are referred to within the queue and queue outside queue. B.6.5 function block implementation B.6.5.1 Bsbitcnt (cache start bit counter)

Bscntbit starter for all valid input to the buffer word count. Counter (bsctr) 16 to 24 is a programmable counter bit width. In addition, bsctr with lookahead (carry look ahead) to give the line fast enough. The width Bsctr ced_bs_prescale to programming. Is to force 8-16 is high, which makes these bits Always transmit a carry. So in fact they are not used. Only the highest 8 bsctr Bit is used with the target (ced_bs_target) for comparison.

Compare (ced_bs_count> = ced_bs_target) is bscmp complete.

Goal is to flow in the Huffman decoder of the time obtained from the stream, and it also Is calculated using a microprocessor. So it's just after the start of the stream was only set up sometime Position. Before starting, target_valid is set to low. Write on ced_bs_target Into the target_valid is set to high, and allow bscmp for comparison. When comparing the The results show ced_bs_count> = ced_bs_target time, target_valid is set Is low. Objectives have been met.

When the target is met, the count is reset. Note that it is not the end of the stream multiplexing Bit. In addition, after the target is met prohibited count if it is before the end of the stream Words. The saturation value of 255 counts.

Bsbitcnt detected when the end of the primary flow (i.e. a FLUSH), it Produce abs_flush_event. If the stream ends before the target to meet, but also generate additional An event (bs_flush_before_target_met_event). When any of these events A occurs, the block is stopped. This allows the user to re-start the search for the next stream Target, or if it is bs_flush_before_target_met_event event, Or:

1) Write zero goals, oblige once target_met

Or:

2) noted that in the past did not reach the target, allowing the next stream forward until it Together on a stream reach the target. This is the next target of a stream could / should be adjusted accordingly Whole. B.6.5.2 BSOGL (cached starter output gate logic)

As mentioned earlier, Bsogl is used to indicate a flow indicator team goals have been met Columns. Queue type with ced_bs_queue settings (internal queue is 0, the external queue is one). Reset select internal queue. Satisfying the condition queue depth determines the maximum number of streams. Flow Can be coded data buffer, Huffman or token buffer inside. When this number is reached (Ie, the queue is full) when, bsogl forces stopped at bsbitcnt at the datapath.

Using an internal queue movement required from the microprocessor. However, if necessary Increase the queue depth, you can set an external queue (method: ced_bs_access be Set, to gain access to ced_bs_queue, which should be set, target_met _event and stream_end_event is enabled, then access is withdrawn).

External queue (by the microprocessor care (maintain) the count value) is inserted inside Queue. External queue consists of two events target_met_event and stream_end_event And a register ced_bs_enable_nxt_stream to take care of (maintain). Both Events are referred to simply service_queue_input and service_queue_ output. In fact, target_met_event is to provide (supply) forces within the queue The upstream end of the column (up stream end). Similarly, ced_bs_enable_nxt_stream Is absorbed (consume) the downstream end of the queue's internal queue (down stream end) Similarly, stream_end_event is provided downstream queue (down stream quence) request; stream_end_event make ced_bs_enable_nxt_stream reset.

The use of these two events should be as follows:

  /*TARGET_MET_EVENT*/
  j＝micro_read(CED_BS_ENABLE_NXT_STM)；
  if(j＝＝0)/*Is next stream enabled？*/
  (1*no，enable it*/
   micro_write(CED_BS_ENABLE_NXT_STM，1)；
   printf(-enable next stream(queue＝0×％×)\n*，(context-＞quaue))
 }
 else/*yes，increment the queue of-target_met-streems*/
 {
   queue++；
   printf(*stream already enabled(queue＝0×％×)\n*，(context-
 ＞queue))；
 }
				<!-- SIPO <DP n="456"> -->
				<dp n="d456"/>
    /*STREAM_EVENT*/
    if(queue＞0)/*are there any ＂target_mets＂left？*/

    (/*yes，decrement the queue and enable anotner stream*/

     queue--；

     micro_write(CED_BS_ENABLE_NXT_STM，1)；

     printf(＂enable next stream(queue＝0×％×)\n＂，(cntex-＞queue))；

     }

    else

    printf(＂queue empcy cannot enable next stream(queue＝0×％×)\n＂，
  queue)；
  micro_write(CED_EVENT_1，1＜＜BS_STREAM_END_ENTEVT)；/*clear event
  */

Queue types can be converted at any time by the internal external (using the above method), but Only when the external queue is empty (according to the above "queue = 0") only when the queue class Type from the outside into the queue within the queue. Conversion is: ced_bs_access is set, Ced_bs_queue to gain access to the latter should be set, target_met_event And stream_end_event is masked, then access is withdrawn.

On the other hand, can not start convection conditions for inspection, the ced_bs_queue (external) Set, will target_met_event and stream_end_event masked, then ced_bs_enable_nxt_stream set.

In this way, all streams will always be enabled. B.6.6 Microprocessor register

Register name	Usage	Address
			CED_BS_ACCESS	xxxxxxxD	0x10
CED_BS_PRESCALE*	xxxxxxDDD	0x11
			CED_BS_TARGET *	DDDDDDDD	0x12
CED_BS_COUNT *	DDDDDDDD	0x13
			BS_FLUSH_EVENT	rrrrrDrr	0x02
SS_FLUSH_MASK	rrrrrDrr	0x03
			BS_FLUSH_BEFORE_TARGET_ME  T_EVENT	rrrrDrrr	0x02
BS_FLUSH_BEFORE_TARGET_ME  T_MASK	rrrrDrrr	0x03

Table B.6.1 BSCNTbit register

Register name	Usage	Address
			TARGET_MET_EVENT	rrrDrrrr	0x02
TARGT_MET_MASK	rrrDrrrr	0x03
			STREAM_END_EVENT	rrDrrrrr	0x02
STREAM_END_MASK	rrDrrrrr	0x03
			CED_BS_OUEUE *	xxxxxxxD	0x14
CED_BS_ENABLE_NXT_STM	xxxxxxxD	0x15

Table B.6.2 Bsogl register

Here

· D is a register bit

· X is a non-existent register bit

· R is a reserved register bits

· To gain access to these registers, ced_bs_access must be set to 1 and Until it is read back a query, except in an interrupt service routine. The ced_bs_ access set to zero to give up access. B.7DRAM Interface B.7.1 Overview

In the present invention, the spatial decoder, decoding and video formatter time have a Special chip DRAM interface components. In all three devices, DRAM interface uses Is provided by the address generator block address data from the chip to the external DRAM and from Transferred to the external DRAM chips.

In a typical case, DRAM interface is used for both the work and the address generator asynchronous clock, And also data through the different parts of the clock asynchronous. However, this place is easy to get asynchronous Management, because the clocks are operating at substantially the same frequency.

DRAM interface data is typically between the rest of the chip in units of blocks of 64 bytes For transmission (the only exception is the time of the prediction data in the decoder). Transmitted by the use of A process called "alternate buffer" of the device. This, in essence, is a pair of double-buffer structure Form work of RAM, the DRAM interface filling (filling) or a blank (emptying) a RAM, while the other part of the chip empty or filled with another RAM. Each swing buffer Devices are hung separately on the bus at the individual bus addresses by the address generator.

Each chip has four alternate caches, but the function of these buffers in each Chip is different. In the spatial decoder, one swing buffer is used to the encoded Data to the DRAM, one for reading the encoded data from the DRAM, the third is for the Tokenized data has been transmitted to the DRAM, the fourth token from a DRAM read the data. The decoder at a time, one swing buffer is used the base (Intra) or predicted (Predicted) image data is written to DRAM, DRAM read from second base with a number or predict According to the other two to read forward and backward prediction data. In the video formatter, one A swing buffer is used to transfer data to the DRAM, another three for the read data from the DRAM. Luminance (Y) and red and blue color difference data (namely, Cr and Cb) each with one of the three alternative Cache. ...

Each chip has four alternate caches, but the function of these buffers in each Chip is different. In the spatial decoder, one swing buffer is used to the encoded Data to the DRAM, one for reading the encoded data from the DRAM, the third is for the Tokenized data has been transmitted to the DRAM, the fourth token from a DRAM read the data. The decoder at a time, one swing buffer is used the base (Intra) or predicted (Predicted) image data is written to DRAM, DRAM read from second base with a number or predict According to the other two to read forward and backward prediction data. In the video formatter, one A swing buffer is used to transfer data to the DRAM, another three for the read data from the DRAM. Luminance (Y) and red and blue color difference data (namely, Cr and Cb) each with one of the three alternative Cache. ...

Referring to Figure 131, the address generator 420 data interface and the supply connection of each block Mouth are two-wire interface. Address generator 420 generates an address or can be controlled as a receiver Token results, or produce only a fixed sequence of addresses. DRAM interface 421 in a particular Dealt with the address generator for those two-wire interface. It is not ready to receive land Addresses will be accepted when the line (accept line) remains high, while waiting for the address generator to mention For a valid address, to deal with this address, and then in one clock cycle will accept Line Set high. Thus, it is to achieve the request / response (REQ / ACK) protocol.

DRAM interface, a unique feature is its ability to communicate with the address generator, but also Completely independent with those parts of the supply or accept data communication. For example, the address generator Capable of generating a write data in the alternate buffer address, but no action, Until the write swing buffer signals that there is a block of data written to the external DRAM is ready 422. However, no action occurs until the address generator will be provided to the appropriate address On the bus. In addition, once wrote alternately one of the RAM buffer has been put into the data, and the other A RAM data input may be completely filled before the stop was "alternate" to the DRAM Interface side (wire interface accept signal is set low). ...

DRAM interface, a unique feature is its ability to communicate with the address generator, but also Completely independent with those parts of the supply or accept data communication. For example, the address generator Capable of generating a write data in the alternate buffer address, but no action, Until the write swing buffer signals that there is a block of data written to the external DRAM is ready 422. However, no action occurs until the address generator will be provided to the appropriate address On the bus. In addition, once wrote alternately one of the RAM buffer has been put into the data, and the other A RAM data input may be completely filled before the stop was "alternate" to the DRAM Interface side (wire interface accept signal is set low). ...

Each DRAM interface comprises a decision for the next time the service which alternate buffer Methods. Generally speaking, this or a kind of "cycle (ound robin)", or as an excellent First-level encoder. In the "cycle" method, the alternate buffer is serviced is the next Recent never turn can be obtained that alternating buffer. In the priority encoder mode, By the service are those alternating buffer, their higher priority than others. In the In both cases above, there is the additional requests from the refresh request generator (refresh requ- est generator) to it than all other requests of a higher priority. Refresh request by the Refresh timer, the refresh counter can be given via the microprocessor interface programming. B.7.2.1 alternate buffer ...

Each DRAM interface comprises a decision for the next time the service which alternate buffer Methods. Generally speaking, this or a kind of "cycle (ound robin)", or as an excellent First-level encoder. In the "cycle" method, the alternate buffer is serviced is the next Recent never turn can be obtained that alternating buffer. In the priority encoder mode, By the service are those alternating buffer, their higher priority than others. In the In both cases above, there is the additional requests from the refresh request generator (refresh requ- est generator) to it than all other requests of a higher priority. Refresh request by the Refresh timer, the refresh counter can be given via the microprocessor interface programming. B.7.2.1 alternate buffer ...

1) valid data appears on the input terminal 430 (data input). As each data block is Accepted, it is written RAM1 and the address value.

2) When RAM1 full, the input side (side) to relinquish control and put a signal to the read side, To indicate that RAM1 is now ready to be read out. This signal is passed between the two asynchronous clock, Therefore, synchronization flip-flop through three.

3) to the input side of the next data item to be written is still empty RAM2.

4) When the loop method or priority encoder indicates that the turn of this swing buffer has been read When, DRAM interface can read the contents of RAM1 and writes them to the external DRAM. Then a Signal is returned via the asynchronous interface, as in (2), to indicate that RAM1 is now ready again Good is loaded.

5) if the DRAM interface RAM1 out empty and filled in the input side will RAM2 it before "Alternate", the data can be continuously received are alternately buffer; otherwise when RAM2 is filled Is full, an alternate buffer will set its accept signal low until RAM1 has been "alternating" Back to the input side can be used.

6) This process is repeated infinitely down.

Read alternating buffer process is similar, but the input data and output data bus total Line in opposite positions. B.7.2.2 external DRAM, and alternate buffer addressing

DRAM interface is designed to make available the maximum memory bandwidth. So it safe Row such that each 8 × 8 block of data is stored in the same DRAM page. Which can take advantage of DRAM fast page access method, these methods in a given row address, and a number Column address. A facility is also provided, allowing to the external RAM data bus width 8, 16, or 32 bits, so that the number of DRAM can be used for specific applications and the size and with Width requirements match.

In this case (it does illustrate the spatial decoder in the DRAM interface is to Work), the address generator to the DRAM interface is provided for each read and write buffer portion alternately Email address. This address is used as the DRAM row address. 6-bit column address from the DRAM interface Providing body, these bits are also used as the buffer RAM address alternately. Receiving the alternating buffer The number of data bus is 32 bits wide, so if the bus width to the external DRAM is less than 32 Bit, then the next word alternately from one buffer to read or write the next word is written to a cache read alternately Is (read and write the external DRAM is the conveying direction for a), the need for two or four Times the external DRAM access. ...

In this case (it does illustrate the spatial decoder in the DRAM interface is to Work), the address generator to the DRAM interface is provided for each read and write buffer portion alternately Email address. This address is used as the DRAM row address. 6-bit column address from the DRAM interface Providing body, these bits are also used as the buffer RAM address alternately. Receiving the alternating buffer The number of data bus is 32 bits wide, so if the bus width to the external DRAM is less than 32 Bit, then the next word alternately from one buffer to read or write the next word is written to a cache read alternately Is (read and write the external DRAM is the conveying direction for a), the need for two or four Times the external DRAM access. ...

In the present invention, DRAM Interface Timing block uses timing chains to enable the DRAM signals Edge of the system clock accurate to the fourth cycle. Used data from the phase-locked loop two mutual difference Quarter cycle of the clock. They combine to form twice the nominal clock (notional 2 × clock). Then, any one link in parallel with the two shift registers Formed to "double the clock," the normal and reversed phase work.

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In the reset state, the chain is clear, while there is a pulse generator. This pulse is generated by DRAM interface guidelines state information along the chain of transmission. DRAM interface clock is used This pulse is generated. Each DRAM interface clock period corresponds to one cycle of the DRAM. The Therefore, because the DRAM cycles have different lengths, DRAM interface clock speed is not fixed Unchanged.

In addition, the regular chain of pulses from said chain from the DRAM interface to the message with Mixed to produce the output strobe and an enable (notoas, notras, notwe, not- oe). B.8 inverse quantizer (Inverse Quantizer) B.8.1 Introduction

According to the invention of this document describes the inverse quantizer (iq) the purpose, role and reality Present. B.8.2 Overview

Inverse quantizer using the quantized coefficients, quantization step size and weighted to rebuild the Factor. All of these are used in an amount within the data stream transfer. B.8.3 Interface

iq in the data path in reverse modeling and the inverse DCT between, it connects to the micro- Processor. Data path through the two-wire interface link. The input data is 10 bits wide, The output is 11 bits wide. B.8.4 inverse quantization math B.8.4.1 H.261 equation

For a group (intra) encoded blocks:i＝0       

$C_i=\min (\max (C_i^{*}-2048).2047)$

For all other coded block mode: $C_i=\min \left(\max (C_i^{*}-2048)2047\right)$ B.8.4.2 JPEG equation $C_i^{*}=W_{i.j}{Q}_i+1024--i=0$               

0＜i＜64 $C_i^{*}=\min (\max (C_i^{\&prime;}-2048).2047)$ / = Ipeg_table_indiretion (c) B.8.4.3 MPEG equation

For base encoded blocks:i＝0               $C_i=\min (\max (C_i^{*}-2048).2047)$

DC in the base, and calculate the prediction value of each huffman to add 1024 when they Is reset to zero.

For all other coded blocks:

$C_i=\min (\max (C_i^{*}-2048).2047)$ B.8.4.4 JPEG variation equation

i＝0          

0＜i＜64 $C_i=\min (\max (C_i^{*}-2048).2047)$ j = jpeg_table_indirection (c) B.8.4.5 All other tokens

In addition to data tokens, all tokens must pass iq not be quantified.

Here:

                 

Floor (a) returns an integer, so

     (a-1)＜ηoor(a)sa      a≥0

      a≤ηoor(a)＜(a＋1)    a≤0

Q: Is quantized coefficients. C_iAfter the reconstruction coefficients W_i，jThe quantization table values ​​in the matrix i is the coefficient of the Z-shaped label j is the number of quantization table matrices (0 <= j <= 3) B.8.4.6 variety of standard integrated

All of the above can be seen that the standards and their variations (also to be changed is not iq Control data) can be mapped to a single equation: $\mathrm{OUTPUT}=\frac{(21\mathrm{NPUT}+k)\left(\mathrm{xy}\right)}{16}$ Inverse quantization processing functions:

· Canada 1024

· The symbolic values ​​into two's complement representation

· Direction to 0 all the even-numbered rounds to the nearest odd number.

· Saturating the result of +2407 or -2048

For each standard variable changes in the value k, x and Y, and they use the function shown in Table B.8.1.

Table B.8.1 control decoding

Standard		X Weighted		Y Scale	K	Plus 1024	Rounding Even	Saturation Result		Convert Two's complement
											H261	Base DC		8		8	0	No	No	Yes		Yes
Base	16		iq_quant _scale	1	No	Yes	Yes		Yes
										Other		16		iq_quant _scale	1	No	Yes	Yes		Yes
JPEG	DC	W		ij		8	0	Yes	No												Yes		Yes
										Other	W		ij		8	0	No	No	Yes					Yes
	MPEG	Base DC	W		ij		8	0	Yes												No	Yes			Yes
Base										W ij		iq_quant _scale	0	No	No	Yes		Yes
		Other	W ij		iq_quant _scale	1	No	Yes	Yes										Yes
XXX											DC	W ij		iq_quant _scale	0	Yes	No	Yes		Yes
	Other	W ij		iq_quant _scale	0	No	No	Yes		Yes

Table B.8.1 Control Decoder (continued)

Standard	X Weighted	Y Scale	K	Plus 1024	Rounding Even	Saturation Result	Convert Two's complement
								Other tokens	1	8	0	No	No	No	No

B.8.5 function block structure

From B.8.4.6 and Table B.8.1, you can see more than one standard inverse quantizer can use Single structure. Its calculation block 133 shown in FIG. "Arithmetic Block":

Arithmetic blocks of the control function can be divided into two parts by:

· Token decoding load status register or quantization tables.

· Status register decoded control signal.

Token igca decoding, iqca control cycle, that is stored in registers iqcb Unit. It also controls the access to the four quantization tables igram. The arithmetic section, the two Multipliers and some post-processing functions in igarith inside. iq complete block shown in FIG. 134. B.8.6 function block implementation B.8.6.1 Iqca

In the present invention, iqca is a state machine for decoding the token pairs igram And the registers in igcb control signal. State machine as the status of each token Machine is more suitable since it is reset by each new token. For example:

Right QUANT_SCALE (see B.8.7.4, "QUANT_SCALE") and QUANT_ TABLE (see B.8.7.6, "QUANT_TABLE") The code is as follows:

     if(tokenheader＝＝QUANT_SCALE)
     {

      sprintf(preport，*QUANT_SCALE*)；

      reg_addr＝ADDR_IQ_QUANT_SCALE；

      rnotw＝WRITE；

      enable＝1；
    }
    if(tokenheader＝＝QUANT_TABLE)/*QUANT_TABLE token*/
    switch(substate)
    {

     case 0：/*quentisation table header*/

      sprintf(preport，＂QUANT_TABLE_％s_s0＂，

       (headerextn？＂(full)＂：＂(empty)＂)}；

      nextsubstate＝1；

      insertnext＝(headerextn？0∶1)；

      reg_addr＝ADDR_IQ_COMPONENT；

      rnotw＝WRITE；

      enable＝1；

       break；

      case 1：/*quantisation table body*/

       sprintf(preport，＂QUANT_TABLE_％s_sl＂，

        (headerextn？＂(full)＂：＂(empty)＂))；

       nextsubstate＝1；

       insercnext＝(headerextn？0：(qtm_addr_63＝＝0))；

       reg_addr＝USE_QTM；
				<!-- SIPO <DP n="469"> -->
				<dp n="d469"/>
     rnotw＝(headerextn？WRITE：READ)；

     enable＝1；

     break；

    default：

     sprintf(preport，＂ERROR in iq quantisation table tokendeccder
 (substate ％x)\n＂，

       substate)；

       break；

     }
    }

This sub-state (substate) is a state within the token, such QUANT_ SCALE is only a sub-state. However, QUANT_TABLE has two sub-states, one is First, the second is the token body.

PLA state machine to achieve. Unrecognized token does not cause the word line (word line) l High, so that some of the default output from PLA (harmless) control.

In addition, iqca using traditional characters (BodyWord) counter supply address to igram, and put Words into the stream, for example, in a not extended QUANT_TABLE (see B.8.7.4). It is used in maintaining output is active, stop the importation of the way to get. In a subsequent block (iqub or iqarith) These words can be populated with the correct data.

iqca is controlled by two-wire interface data path in a single cycle. B.8.6.2 iqcb

In the present invention, iqcb save iq status register. It is under the control of the iqca These values ​​are loaded from the data path or remove.

Status register is decoded (see Table B.8.1) to iqarith control line, To control the XY multiplier term and after quantization (post quantization) function.

The sign bit data path is separated here and sent to the post quantization functions. There is more data Zero value on the channel word to be detected is also here. Thus operation is ignored and zero is multiplexed pass To the data path. This is to comply with iq "0 into; 0" provides the easiest way.

Only when the register iq_access has been set back to 1:00 and read the status register to From the microprocessor accesses. In this case, iqcb data path has been suspended, so to ensure send Has a stable value register in the data path is no data corruption.

Iqcb in the data path in a single cycle, the data path from the two-wire interface. B.8.6.3 Iqram

Iqram must support four quantization table matrices (QTM), each 64 * 8 bits. So it Is a 256 * 8 bits six transistor RAM, once per cycle or a write once read. This RAM installed In the two-wire interface logic within the control and accept it to write data from iqca. It is read out According to iqarith. Similarly, iqram occupy the same period of the data path, as iqcb.

RAM read back in iq_access 1:00, you can read and write from the microprocessor. RAM is placed in a A keyhole registers, iq_qtm_keyhole back with iq_qtm_keyhole_addr search Address. Visit iq_qtm_keyhole make it points to save on iq_qtm_keyhole _addr the address increases. Similarly, iq_qtm_keyhole_addr be written directly. B.8.6.4 iqarith

Note, iqarith is a three-function pipeline, divided in three cycles on. Its Functions are discussed below (see Figure 133) B.8.6.4.1 XY multiplier

This is a 5 (X) by 8 (Y) bit carry save unsigned multiplier, fed to the data communication Road multipliers. Multiplier and multiplicand to the control line with iqcb choice. Multiplication of the first Cycles, solving adder (resolving adder) in the second cycle.

The multiplier input data from iqram to be multiplexed to the data path Up, to read out the data path QUANT_TABLE. B.8.6.4.2 (XY) * multiplier datapath

The 13 (XY) by 12 (data path) bit carry save unsigned multiplier points in the block The three cycles. Three partial products in the first cycle, seven in the second cycle, the remainder Of the two in the third cycle.

Because all the output from the multiplier is less than 2047 (non_coefficient non factor) Or saturated to +2407 / -2048, the highest 12 never needed solving. Correspondingly, demand Xie adder only two wide. In the high-order bit multiply remainder, a zero detect sufficient for Is a saturated signal. B.8.6.4.3 quantitative post-processing functions (Post quantization functions) quantify Post-processing functions are:

· Canada 1024

· The symbol values ​​into two's complement representation.

· The 0 direction all round to the nearest even number of odd.

· The results are saturated +2047 or -2048.

· Set the output to zero (see B.8.6.2)

First three functions in a 12-bit adder is implemented (in the second and third cycles Flowing water). From this, you can see what each of the functional requirements, which then merge (combine) to a single adder.

Table B.8.2 quantization processing adder function

Function	if datapath＞0	if datapath＞0
			Converted into two's complement	Do nothing	Negate plus 1
Rounding all even	Decrement	Plus a
			Canada 1024	Canada 1024	Canada 1024

As a person having ordinary skill will appreciate the Bank to re-compile these functions Procedures must be careful, because when combined, they are very dependent on each other.

Saturation value, 0, and 0 at the end of 1024 in the third cycle is multiplexed to the data path. B.8.7 inverse quantizer token

The following description provides the inverse quantizer for each token in response to its work tp Situation. In all cases, the token is transferred to the inverse quantizer output. In most Circumstances, the token is not modified reverse phase quantizer, only a few exceptions noted below. All unrecognized tokens transferred without change to the inverse quantizer output. B.8.7.1 SEQUENCE_START

This token enable register iq_prediction mode [1:0] and iq_mpeg_indi- rection [1:0] is reset to 0. B.8.7.2 CODING_STANDARD

This token makes iq_standard [1:0] into the current standard based decoding (MPEG, JPEG or H.261) appropriate values​​. B.8.7.3 PREDICTION_MODE

This token loading iq_prediction_mode [1:0]. Although PREDICTION_ MODE carry more than two, reverse quantizer simply visit the two lowest order. These decisions Set the block is or is not based coding. B.8.7.4 QUANT_SCALE

This token load iq_quant_scale [4:0]. B.8.7.5 Data

In the present invention, this token is carrying real quantization coefficients (quantized coe- fficients). Token header contains the identification of the two color components, which are loaded iq_ comment [1:0]. 64 following words contain the quantized coefficients token. These are modified inverse Result of the process to the quantizer, the reconstruction coefficient (reconstructed coefficients) Instead.

If the token is not present in the expansion exactly 64 words, the operation of inverse quantizer Is uncertain.

In the inverse quantizer input data token carries quantized coefficients. These coefficients to comply Number value format is 11 bits (10 bits plus one sign bit). The value "negative zero" should not, But can be correctly interpreted as 0.

In the inverse quantizer output carry outside reconstruction coefficient data token. These coefficients are 2 's Complement format with 12 indicates (11 plus a sign bit). At the output of the data token The extension has a token words in the inverse quantizer input phase has a number of premises, a Samples. B.8.7.6 QUANT_TABLE

This token can be used to load a new quantization table or to read an existing table. Code Said type, the inverse quantizer, the token is used to load a bit stream decoded from New table. Reading out an existing table of the former to the encoder quantizer is useful, If this table into the bit stream to be coded words.

Token header contains two to identify the use of the table number. These bits are placed iq_compon- ent [1:0] in the. Note that this register now contains a "table number" instead of one A color component.

If the token header extension bit is 1, the inverse quantizer want to make exactly 64 extensions Brand words. Each of which is as a quantization table value, in the appropriate table successive positions, Starting from position 0. Each extension Token word has the 9th bit is ignored. No modification to the token Normal way to the inverse quantizer output.

If the token header extension bit is 0, the inverse quantizer will read the appropriate connection tables Continued position, starting from position 0. Each location becomes an extension Token word (No. 9 to 0). The end of this operation, the token will contain exactly 64 extend token words.

For all extension numbers, other than 0 and 64 corresponding to the inverse quantizer this token The operation is not defined. B.8.7.7 JPEG_TABLE_SELECT

This token is used to insert or remove a component from the color table number to convert to / from iq_ipeg_ indirection. These conversions used in JPEG and other standards.

Token header (Token Head) contains two, to identify the current color of interest Volume. These bits are placed iq_component [1:0] in.

If the token header extension bit is 1, the token should contain an extended character, the minimum two Bits are written iq_ipeg_indirection [2 * iq_Component [1:0] +1:2 * iq_ Component [1:0]] units. Just read out the value of the extension becomes a token word (high seven will be Zero). In the end of this operation, the token will contain exactly one token extension word.

Table B.8.3 JPEG_TABLE_SELECT role

Head of the color component	iq_ipeq_indirector bit access
		0	[1∶0]
1	[3∶2]
		2	[5∶4]
3	[7∶6]

B.8.7.8 MPEG_TABLE_SELECT

When processed by the MPEG standard, this token is used to determine the default table or User-defined quantization table. Token header contains two. Bit 0 of the head, then decide if you want to write Which one is written iq_mpeg_indirection. Bit 1 wrote that unit.

Because iq_mpeg_indirection [1:0] register is SEQUENCE_START token Cleared only if the user-defined quantization table has been sent into the bitstream only when it is necessary to use Tokens. B.8.8 Microprocessor register B.8.8.1 iq_access

To make the microprocessor to any one iq registers are accessed, iq_access must be set to 1, And it queries until it is read back a date (see B.8.6.2). Failing this, will A register being read data path is still controlled by, It is unstable. About igram, access is closed, read back 0.

Write 0 to iq_access, will control the withdrawal to the data path. B.8.8.2 Iq_Coding_Standard [1:0]

This register holds the coding standard, which is implemented using standard inverse quantizer.

Table B.8.4 coding standard values

iq_coding_standard	Coding Standards
			0	H.261
1	JPEG
		2	MPEG
3	XXX

This register by the CODING_STANDARD token loaded.

Although this is a two registers, but now it occupies in the memory image of the 8, can be realized in the future processing of more than the above standards. B.8.8.3 Iq_mpeg_indirection [1:0]

In the MPEG decoding operation, the two register is used to maintain a quantization table to be Records used.

Iq_mpeg_indirectin [0] control coding block used as the base table. If it is 0, then With quantization table 0, request contains the default quantization table. If it is a 1, then use the quantization table 2, for Based coding block contains the user-defined using a quantization table.

This register is MPEG_TABLE_SELECT token loaded with SEQUENCE_ START token will reset it to 0. B.8.8.4 Iq_ipeg_indirection [7:0]

This 8-bit register, as occurs in the JPEG scan four possible color components Each component, determined by four in the quantization table which one.

· Bit [1:0] to save weight 0 to use the table number.

· Bit [3:2] to save component a table number to use.

· Bit [5:4] to save weight 2 to use the table number.

· Bit [7:6] to save weight 3 to use the table number.

This register is affected by JPEG_TABLE_SELECT token. B.8.8.5 iq_quant_scale [4:0]

This register holds the current value of the quantization scale factor. This register is used QUANT_ SCALE token loaded. B.8.8.6 iq_component [1:0]

This register usually holds a value that is converted to a quantization table number matrix (Quantization Table Matrix number). It was some of the token loaded.

Data token header to enable the register block to be processed with a color component loaded. The letter Information is only used in the JPEG and JPEG some variables to determine the QTM number by visiting iq_ipeg _indireetion [7:0] to do it. In other standards, iq_Component [1:0] Is ignored.

JPEG_TABLE_SETECT token enables the registers are loaded with a color component. It then After being used as a point iq_ipeg_indirection [7:0] pointer. ig_ipeg_ indirection [7:0] with the token body access.

QUANT_SCALE token enables the registers are loaded with QTM number. So from now on this table or Load card (such as an expanded form of the order), or read out from the table to form a co- Appropriate extension token. B.8.8.7 iq_prediction_mode [1:0]

The two registers hold subsequent block prediction mode to use. Inverse quantizer right The only use of this information is to decide whether to use based coding (intra codings). If you register two are 0, then each subsequent block is based coding.

This register is loaded with PREDICTION_MODE token with SEQUENCE_START Token register is reset to 0.

Changes in the JPEG and JPEG modes Iq_prediction_mode [1:0] does not affect the operation of Made. B.8.8.8 Iq_ipeg_indirection [7:0]

Iq_ipeg_indirection be used as a lookup table. This table is the color component transfer Replaced QTM number. Accordingly, iq_Component finger as iq_ipeg_indirection Pin, as shown in Table B.8.3.

As a token of extended form, the register unit with JPEG_TABLE_SELECT Direct write token.

As a token of non-expanded form, this register unit with JPEG_TABLE_ SELECT token read directly. B.8.8.9 Iq_quant_table [3:0] [63:0] [7:0]]

There are four quantization tables, each with 64 locations. Each unit is an 8-bit value. In Any unit should not use the value 0.

These registers are used as in B.8.6.3 "Igram" is described to implement a RAM Now the.

These tables can be loaded with QUANT_TABLE token.

Note that in these tables by the data storage Zig-Zag scanning order. Many files The value of the quantization table number of the 8 × 8 matrix. DC term is usually at the top left, with the level of Frequency increases from left to right, from top to bottom with vertical frequency increases. These tables must along Zig_ Zag scan path read, because the number of quantization table is in order "i" inserted. B.8.9 Microprocessor register map

Table B.8.5 Memory Map

Register	Unit location	Direction	Reset state
				iq_access	0x30	R/W	0
iq_coding_standard〔1∶0〕	0x31	R/W	0
				iq_quant_scale〔4∶0〕	0x32	R/W	？
iq_component〔1∶0〕	0x33	R/W	？
				iq_orediction_mode〔1∶0〕	0x34	R/W	0
iq_jpeg_jndirection〔7∶0〕	0x35	R/W	？
				iq_mpeg_jndirection〔1∶0〕	0x36	R/W	0
iq_qtm_keyhole_addr〔7∶0]	0x38	R/W	0
				iq_qtm_keyhole〔7∶0〕	0x39	R/W	？

B.8.10 Test

To achieve the inverse quantizer of the test, when the input is the output of the inverse model Kuice device, the output is through the inverse quantizer Kuice own devices. Logical volume with reverse Equalizer own scanning to achieve.

If ramtest signal is asserted, can be obtained on igram's access without going Visit iq_access. B.9IDCT B.9.1 Introduction

The inverse discrete cosine transform (IDCT) block is the purpose of this description, to provide IDCT engineering information sources. It includes the following information:

· IDCT purpose and main features

· It is how to design and verification

· Structure

This statement is intended for a person with ordinary skill in the Bank to provide sufficient information To promote or assist the following tasks.

· Appreciate the IDCT is a "Silicon Macro Processor"

· IDCT integrated into another device

· To develop test procedures IDCT silicon

· IDCT modifications, re-design or maintenance.

· Develop future DCT components. B.9.2 Overview

A discrete cosine transform / Zig-Zag (DCT / ZZ) the pixel block to achieve transformation. In Where each block represents an 8 by 8 pixel high-pixel wide area of ​​the screen. Transformation projects Is to put the pixel block in sorting by frequency in the frequency domain representation. Because the image of the eye Sensitive to the DC component, but the sensitivity of the high-frequency component is much more backward, the frequency data allows The size of each component in accordance with the sensitivity of the eyes is reduced. Reducing the amplitude are referred to as Quantified. Quantization process reduces the information contained in the image, which is a lossy quantization process. Lossy eliminate some of the information processing method to achieve the total data compression. Frequency data Are classified, so that all frequency occur consecutively. Most likely to be quantized to zero frequency. These consecutive zero means a run-length encoding method which encodes the quantized data More data compression, although run-length coding is generally not a lossy process. ...

A discrete cosine transform / Zig-Zag (DCT / ZZ) the pixel block to achieve transformation. In Where each block represents an 8 by 8 pixel high-pixel wide area of ​​the screen. Transformation projects Is to put the pixel block in sorting by frequency in the frequency domain representation. Because the image of the eye Sensitive to the DC component, but the sensitivity of the high-frequency component is much more backward, the frequency data allows The size of each component in accordance with the sensitivity of the eyes is reduced. Reducing the amplitude are referred to as Quantified. Quantization process reduces the information contained in the image, which is a lossy quantization process. Lossy eliminate some of the information processing method to achieve the total data compression. Frequency data Are classified, so that all frequency occur consecutively. Most likely to be quantized to zero frequency. These consecutive zero means a run-length encoding method which encodes the quantized data More data compression, although run-length coding is generally not a lossy process. ...

Decompressing the system image pixels with integer instructions. ICD7 block member is part of the system. This means IDCT components required to take and produce integer values. However, since the IDCT function is not Integer-based, the internal number representation of a decimal part to maintain internal accuracy. With full floating-point calculation is more appropriate, but the specific implementation described here (implementation) with Fixed-point calculations. With fixed-point calculations have some loss of precision, but the precision achieved over H.261 and precision specified by IEEE. B.9.3 designed

% E6% 8C% 89% E7% 85% A7% E6% 9C% AC% E9% A1% B9% E5% 8F% 91% E6% 98% 8E% EF% BC% 8C% E8% AE% BE% E8 % AE% A1% E4% B8% BB% E8% A6% 81% E7% 9B% AE% E7% 9A% 84% E6% 98% AF% E8% A6% 81% E8% AE% BE% E8% AE % A1% E4% B8% 80% E4% B8% AA% E5% 8A% 9F% E8% 83% BD% E6% AD% A3% E7% A1% AE% E7% 9A% 84IDCT% E5% 9D% 97 % EF% BC% 8C% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E6% AD% A4% E5% 9D% 97% E7% 94% A8 % E7% 9A% 84% E7% A1% 85% E7% 89% 87% E9% 9D% A2% E7% A7% AF% E6% 9C% 80% E5% B0% 8F% E3% 80% 82% E8 % AE% BE% E8% AE% A1% E4% B9% 9F% E8% A6% 81% E6% B1% 82% E5% 9C% A8% E6% 8C% 87% E5% AE% 9A% E7% 9A % 84% E6% 93% 8D% E4% BD% 9C% E6% 9D% A1% E4% BB% B6% E4% B8% 8B% EF% BC% 8C% E6% 97% B6% E9% 92% 9F % E9% 80% 9F% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E5% BA% A6% E4% B8% BA30MHz% E3% 80% 82 % E6% AD% A4% E8% AE% BE% E8% AE% A1% E4% B9% 9F% E8% 80% 83% E8% 99% 91% E5% 88% B0% E5% AF% B9% E6 % 9C% AA% E6% 9D% A5% E7% 9A% 84% E9% 80% 82% E5% BA% 94% E6% 80% A7% E3% 80% 82% E6% 9C% AA% E6% 9D % A5% E9% 9C% 80% E8% A6% 81% E6% 9B% B4% E9% AB% 98% E7% 9A% 84% E6% 97% B6% 0A% 20% 20% 20% 20% 20 % 20% 20% 20% 20% 20% 20% 20% E9% 92% 9F% E9% 80% 9F% E7% 8E% 87% E3% 80% 82% E5% 87% A1% E6% 98% AF % E5% 8F% AF% E8% 83% BD% E7% 9A% 84% E5% 9C% B0% E6% 96% B9% EF% BC% 8C% E8% AE% BE% E8% AE% A1% E7 % 9A% 84% E7% BB% 93% E6% 9E% 84% E9% 83% BD% E5% 85% 81% E8% AE% B8% E8% BF% 99% E6% A0% B7% E5% 81 % 9A% E3% 80% 82% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20B.9.4% C2% A0IDCT% E6% 8E% A5% E5% 8F % A3% E6% 8F% 8F% E8% BF% B0

IDCT block has the following interfaces:

· A 12 width token data input port

· A 9 width token data output port

· A microprocessor interface port

· A system service input port

· A test interface

· Re-synchronization signal

Two token data ports are said before the standard two-wire interface type. Said Width is the number of bits of data representation, not the port number of the whole line. In addition, the input order Card data port associated with the clock and reset signals. The reset signal is used with the front member of the Output resynchronization. Token data with the output port on the back there are two synchronous clock, They are used for the subsequent part.

The microprocessor interface is standard, with four said address. There have been three in the external Decoded select inputs, which are used for all events, all internal registers and all test Storage Select address space. This body is the IDCT address space into a different card in the core Different locations to provide flexibility. There is also a single event output, idctevent, and Two I / O signals, n_derrd and n_serrd. They are event three-state data lines for IDCT and externally connected to the microprocessor data bus non-appropriate bits.

System service ports contain standard clock and reset input signal, as well as two-phase ultra vires Bell (override clocks) and associated clock override mode selection input.

JTAG test interface includes clock and reset signals, the scan path data (scan_path data) and control signals as well as RAM test (ramtest) and chip testing (chiptest) lose Into signals.

In normal operation, the microprocessor port is inactive. Because IDCT does not require any Microprocessor access to get its assigned function. Similarly, only the required tests or school Test is valid when the test interface. B.9.5 mathematical foundations of the discrete cosine transform

In video bandwidth compression, the input image data represents a rectangular area, so To be used in a two-dimensional transform. Two-dimensional transform is difficult to efficiently calculated. However, two-dimensional DCT There can be separated in nature. Separate transformation can be calculated separately for each dimension with other dimensions without Off. The achieved using a one-dimensional IDCT algorithm. This algorithm is specially designed for conversion to the hardware and set up Meter, the software model inappropriate. This one-dimensional algorithm successive applications to obtain a two-dimensional knot Fruit.

For an N by N block of pixels, two-dimensional DCT mathematical definition is as follows:

Equation 10 Forward DCT $Y(j,k)=\frac{2}{N}c\left(j\right)c\left(k\right)\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\underset{n=0}{\overset{N-1}{\mathrm{\&Sigma;}}}X(m,n)\cos \left[\frac{(2m+1)\mathrm{j\&pi;}}{2N}\right]\cos \left[\frac{(2n+1)\mathrm{k\&pi;}}{2N}\right]$

Equation 11 inverse DCT $X(m,n)=\frac{2}{N}\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\underset{k=0}{\overset{N-1}{\mathrm{\&Sigma;}}}c\left(j\right)c\left(k\right)Y(j,k)\cos \left[\frac{(2m+1)\mathrm{j\&pi;}}{2N}\right]\cos \left[\frac{(2n+1)\mathrm{k\&pi;}}{2N}\right]$

Here

             j，k＝0，1，...，N-1            

Mathematically equivalent to the above definition two N by N matrix multiplication, twice, in two Multiplication between, do a matrix transpose. One-dimensional DCT is mathematically equivalent to the two N × N matrix Multiplied. Mathematically the two-dimensional case:

                  Y＝[XC]TC

Furthermore, C is a matrix of cosine terms.

So DCT matrix processing is sometimes used to describe. Describe the transformation matrix mathematics Simplify more convenient. But it must be emphasized that this is only the notation easier. Note 2 / N Affect the DC level constant term C (j) and C (k), known as the normalization factor. B.9.6 IDCT transform algorithm

If in a subsequent more detailed description of said IDCT is used to calculate the exact algorithms should be A "quick" algorithm. The algorithm to be optimized to obtain efficient hardware structure And implementation of devices. The algorithm is to use the main features of theProportion, in order to reduce a multiply Method, and a conversion algorithm. This algorithm is designed to the upper half and the lower half per Between more symmetrical. This symmetry result is that many of the most expensive component was calculated To effectively re-use.

In the description of this algorithm diagram (Fig. 136), the symmetry between the upper and lower halves The middle part in the figure clear. The last column of adders and subtractors also has symmetry with Can be a relatively small price adder and subtractor merger (4 adder / subtractor significantly smaller The illustrated four adder subtractor +4).

Note that the one-dimensional transform all output by

Ratio increases. Means that the last two Increases in proportion to two-dimensional answer. Rounding the final saturation level, the shift of the method can be very Easily be corrected.

The algorithm has shown double-precision floating-point C code, the calculation results with the reference IDCT (By direct matrix multiplication) comparison. Then, further preparation of the algorithm using C precision Place-level integer (bit_accurate integer version) (not including time Information). It can be used to verify the performance and accuracy of the algorithm, as it has on the wafer Body to achieve the same. In the H.261 standard provides a variety of allowable error transform. In this way Method has been used to drill (exercise) precise level models and measurements in place to deliver the essence of Use Degree (delivered accuracy).

Figure 137 shows the overall IDCT structure described in the above section and the sense Common between the lower part, but also show some point, these points, the intermediate results need to be To store. This line is a time multiplexed (time multiplexed), allowing at Part and the lower part separately. B.9.7 IDCT transform structure

As mentioned above, IDCT algorithm is optimized to achieve high efficiency of the structure. The junction formed Key features of structure is as follows:

· Calculation costly operation is effectively reused

· A small number of multipliers. These multipliers are all constant coefficients, rather than pass With a purpose (to reduce the size and exclude individual multiplier coefficient storage needs)

· Small number of latches, no more than required for pipelining the structure

· Operation is arranged so that each stage pipeline requires only a single operation to solve

· Can be arranged according to the natural order to produce results

· No complicated conversion or a large crossbar multiplexer (both in the most After much consideration when they were implemented)

· Use the results in order to remove the solution of two carry-save operation (one addition, One subtraction)

· Structure allows each stage uses four clock cycles, namely the elimination of fast (large) is calculated Operational requirements

· Structure will support 30MHZ than the current pixel - clock operation much faster operation. This Simply solve operation of the small / slow ripple carry, is changed to a larger / faster first Travel-bit form. These solve operation each level occupy the largest part of the time required, so Only accelerate the speed of these operations on the overall operating speed has a huge impact. While doing so The total size of the transformed only relatively small increases. To increase the depth of the pipeline can be further added Rapid.

· Transformed data stream (transform data_flow) control is very simple and efficient.

One-dimensional transform microstructure (Fig. 141) described how the algorithm is transformed to a small Hardware resources, and how to get into the pipeline so that the necessary conditions have been full performance constraints Foot. A "control shift register" and the data flow pipeline match, the use of such Method for the control of this structure. This control design is simple, efficient layout in silicon Rate.

In Figure 141 a control signal has been named (latch, Sel_byp, etc.) are the various enable Signal for controlling the latch, thereby controlling the signal flow. Clock signal to the latch Not shown.

-Transformation structure to meet the required standards of accuracy, while the size of the shift to a minimum, In this regard, a number of implementation details is very meaningful. The techniques used are generally classified into two Main categories.

• In each intermediate state, with individual control point location approach to the fixed word-wide Maintain maximum number of dynamic range.

· In order to use a calculation operation selected to achieve precision (rather than simply increasing the entire A transformation to increase the accuracy of word-wide), the use of the accuracy requirements of the statistical definition.

Simple way to design a transform comprises a sufficiently large fixed word width, perform simple To obtain a single fixed-point arithmetic precision. Unfortunately, this method cause excessive word width, Therefore, a conversion is made ​​greater. Used in the present invention of a method that allows fixed location In the transformation process of change, change in such a manner, that for any particular Use of the intermediate value to the maximum available dynamic range, to obtain the greatest possible accuracy.

Because the result is a statistical description of the allowed and can be cut to any intermediate value operations are selected Selectively adjusted in order to improve overall accuracy. The selected adjustment is LSB (least significant bit) meter Calculate some simple operations. This treatment would cost less or no consideration. Another such technique Contain obvious way is to increase the value of word-wide. Regulation to be effective in a given direction for the last Results for "weighting", if we find that in the former, then the opposite direction to take care of these results. By adjusting the fractional part of the result can be effective to change overall average of these results (shifting). B.9.8 IDCT block diagram description

IDCT block diagram indicates that all the token stream processing the blocks. This Fig. 138, does not indicate the clock, testing, and microprocessor accesses and events agency details. To provide a glimpse into the test access mechanism not shown in the figure. B.9.8.1 data error checker

The first block is a data error check and corrector, called "decheck". It picked up and produce a 12-bit wide token stream, the stream analysis and calibration data token. All other tokens are ignored and directly. Extension number is not equal to some 64 data make License to do verification. Possible errors are referred to as "insufficient (deficient)" (<64 extensions), Namely idct_too_few_event, and the "extra (supernumerary) (> 64 extensions), Namely idct_too_many_event. Institutions using standard event signaled these errors. However, this block is also attempting to use the token stream processing method to make a simple error recovery. In the event of insufficient Error, the data token is a number "0" filled expanded (to stop receiving input and execute Row is inserted), to complement the correct 64 extensions. Redundant error occurs when the expansion of the first 64 Forced to "0" and removed from the token stream all the extra extensions. B.9.8.2 reverse Zig_Zag ...

In Figure 138, the spatial decoder of the next block is a random access memory reverse Zig_Zag 441, iZZ, it is also the acquisition and production of a 12-bit wide token stream. All other blocks with a Samples to be analyzed flow, but only the data token is recognized. All other tokens pass without change Too. Data token is passed, but the extended order is changed. This block relies on the correct The data token (ie, only 64 extensions). If not the case, then the operation is not added regulation Fixed. According to the standard model of reverse Zig_Zag reordered by default, into the Row reordered or to provide the level of the IDCT output scan data. Change the sorting method Provides a vertical scan output is possible. In addition to standard IZZ Sort outside this block Each 8-word line to accomplish an additional rearrangement. This is a one-dimensional IDCT transform block specific to Seek and do. As a result, the order of the line output is (1,3,5,7,0,2,4,6) without Is (0,1,2,3,4,5,6,7). B.9.8.3 input formatter ...

In Figure 138, the spatial decoder of the next block is a random access memory reverse Zig_Zag 441, iZZ, it is also the acquisition and production of a 12-bit wide token stream. All other blocks with a Samples to be analyzed flow, but only the data token is recognized. All other tokens pass without change Too. Data token is passed, but the extended order is changed. This block relies on the correct The data token (ie, only 64 extensions). If not the case, then the operation is not added regulation Fixed. According to the standard model of reverse Zig_Zag reordered by default, into the Row reordered or to provide the level of the IDCT output scan data. Change the sorting method Provides a vertical scan output is possible. In addition to standard IZZ Sort outside this block Each 8-word line to accomplish an additional rearrangement. This is a one-dimensional IDCT transform block specific to Seek and do. As a result, the order of the line output is (1,3,5,7,0,2,4,6) without Is (0,1,2,3,4,5,6,7). B.9.8.3 input formatter ...

As shown in Figure 138, the next block is the first single dimension IDCT transform block 443, "oned". The block inputs and outputs 22-bit wide token stream. As usual, the stream is analyzed, the number of According to the token identified. Other token does not change through the. Data tokens flowing through a Line of the data path, where the completion of a one-dimensional 8 × 8 inverse discrete cosine transform. In First dimension output data word 7 decimal places. All other tokens only through a shift Bit register data path operation. This pathway is only required to wait for the data conversion Time coordinated. These tokens in the output before they are combined into a token stream. B.9.8.5 transposition random access memory ...

As shown in Figure 138, the next block is the first single dimension IDCT transform block 443, "oned". The block inputs and outputs 22-bit wide token stream. As usual, the stream is analyzed, the number of According to the token identified. Other token does not change through the. Data tokens flowing through a Line of the data path, where the completion of a one-dimensional 8 × 8 inverse discrete cosine transform. In First dimension output data word 7 decimal places. All other tokens only through a shift Bit register data path operation. This pathway is only required to wait for the data conversion Time coordinated. These tokens in the output before they are combined into a token stream. B.9.8.5 transposition random access memory ...

As shown in the next block is one-dimensional IDCT transform another occasion. In every respect It is the case of the first dimension. The output of this dimension has four decimal places. B.9.8.7 rounding and saturation

Rounding and saturation block 446 in FIG 138, "ras" take 22-bit wide token stream. Stream contains 22 fixed-point data format extensions. Block output is a 9-bit wide token streams, where the data expansion Exhibition has been rounded (toward positive infinity direction) into an integer, and saturation become nine two's complement Representation. All other tokens have been directly through. B.9.9 Block Hardware Description

Tokens for all processing streams conceptual block has a standard (notional) structure, As shown in Figure 139. This is the two-wire interface latch from the implementation of the token stream processing section separately. The changes in the structure may include additional internal blocks (such as a random access memory core (RAMcore)). Some blocks shown in the figure, in the structure diagram is not obvious (though However, it does still exist). This is because the need for all the data paths "logical combination of a From, and put it with all of the standard logical storage units (standard cell logic) of Open sake. In a very simple block, such as "ras", to the locking of out_acce- pt wire directly into the input latch without logic. B.9.9.2 "Decheck" - data error checking / recovery ...

Tokens for all processing streams conceptual block has a standard (notional) structure, As shown in Figure 139. This is the two-wire interface latch from the implementation of the token stream processing section separately. The changes in the structure may include additional internal blocks (such as a random access memory core (RAMcore)). Some blocks shown in the figure, in the structure diagram is not obvious (though However, it does still exist). This is because the need for all the data paths "logical combination of a From, and put it with all of the standard logical storage units (standard cell logic) of Open sake. In a very simple block, such as "ras", to the locking of out_acce- pt wire directly into the input latch without logic. B.9.9.2 "Decheck" - data error checking / recovery ...

The pipeline depth of two blocks, complete with zcells implementation. Enter the two-lane access Port latch is "in front (front)" type. This means that when the block (in the IDCT Front) and its previous power supply mode are separated, then all input arrival crystal Transistor gate to allow safe operation. The work of this block token stream, so that non-data Order Cards directly through. When they find a data token, token header after the discovery in the expansion Number to start counting. When the count is not equal to 63 if the extension bit is found to be "0", the resulting An error signal (it rushed event logic). According to that event mask bit state, "Decheck" or is stopped (ie, no longer receives input or produce output) or begin Error recovery. Recovery mechanism of the "insufficient" error with counter control to insert the token stream Into the correct extension number (the value inserted is always "0"). Clearly, the insertion is carried out, Does not receive input. When they find on the 64th extension extension bit is not "0", it generates An "excess (super numerary)" error. 64 with oblige extension bit is "0" Way to complete the data token. And then continue to receive data while its output ineffective approach All with extended bit is set to "1" subsequent words are deleted from the token stream. ...

The pipeline depth of two blocks, complete with zcells implementation. Enter the two-lane access Port latch is "in front (front)" type. This means that when the block (in the IDCT Front) and its previous power supply mode are separated, then all input arrival crystal Transistor gate to allow safe operation. The work of this block token stream, so that non-data Order Cards directly through. When they find a data token, token header after the discovery in the expansion Number to start counting. When the count is not equal to 63 if the extension bit is found to be "0", the resulting An error signal (it rushed event logic). According to that event mask bit state, "Decheck" or is stopped (ie, no longer receives input or produce output) or begin Error recovery. Recovery mechanism of the "insufficient" error with counter control to insert the token stream Into the correct extension number (the value inserted is always "0"). Clearly, the insertion is carried out, Does not receive input. When they find on the 64th extension extension bit is not "0", it generates An "excess (super numerary)" error. 64 with oblige extension bit is "0" Way to complete the data token. And then continue to receive data while its output ineffective approach All with extended bit is set to "1" subsequent words are deleted from the token stream. ...

"Izz" 441 (reverse Zig-Zag random access memory) and "tram" 444 (transpose Random access memory) considered together here. Achieve the same function due to changes of the two, they Similarities than differences. These two blocks are to obtain a token stream, and the respective data token Reordering expanded, leaving all other tokens through without change. The width of the handle extensions And reordering the sequence is different, but each random access memory control logic majority Is the same, but actually is composed of a "common control" block. In this block Each random access memory is described in the figure. The width of the control part of this difference did not affect the Rang. So just as the core of each random access memory with a RAM with different "sequentially Address Generator ", and have the appropriate width of two-wire interface components. ...

The main characteristics of each RAM is the total FIFO (First In First Out) features. The token level This is absolutely correct, but the expansion of the data word token output order made special modifications. FIFO depth is 128. In order to meet the system can withstand the requirements of 30MHz, which Is necessary because the output of the data token is detected after starting, FIFO the output of Stop (held up). This is because the sequence used for reordering the characteristics required in the rearrangement Sequence output can begin before the FIFO collected in a 64-bit extensions entire block. More precisely, the reverse Zig_Zag and the transposed sequence requires the minimum number is different, In both cases, slightly less than 64. However, the control of length of the FIFO is not a power of 2 Is very complex. This means that a small amount of the RAM core would result in saving control logic required Logic is more complex and not worth the candle. ...

The main characteristics of each RAM is the total FIFO (First In First Out) features. The token level This is absolutely correct, but the expansion of the data word token output order made special modifications. FIFO depth is 128. In order to meet the system can withstand the requirements of 30MHz, which Is necessary because the output of the data token is detected after starting, FIFO the output of Stop (held up). This is because the sequence used for reordering the characteristics required in the rearrangement Sequence output can begin before the FIFO collected in a 64-bit extensions entire block. More precisely, the reverse Zig_Zag and the transposed sequence requires the minimum number is different, In both cases, slightly less than 64. However, the control of length of the FIFO is not a power of 2 Is very complex. This means that a small amount of the RAM core would result in saving control logic required Logic is more complex and not worth the candle. ...

Is used in the range 0 → 63 generates a read address specific sequence ("sequence address generation") Way to complete reordering operation, but not according to the natural order of reordering conducted. Need The sequence is specified using standard Zig_Zag sequence (for eight horizontal or vertical scan) or with a positive Constant matrix transpose sequences required. Because the one-dimensional IDCT transform block request, these standard serial Since the column is further reordering. Reordering are per line to odd / even format (ie (1,3, 5,7,0,2,4,6) instead of (0,1,2,3,4,5,6,7)) output requirements into Line.

% E8% BD% AC% E7% BD% AE% E5% 9C% B0% E5% 9D% 80% E5% BA% 8F% E5% 88% 97% E7% 9A% 84% E4% BA% A7% E7 % 94% 9F% E5% 9C% A8% E7% AE% 97% E6% B3% 95% E4% B8% 8A% E6% 98% AF% E5% BE% 88% E7% AE% 80% E5% 8D % 95% E7% 9A% 84% E3% 80% 82% E7% 9B% B4% E6% 8E% A5% E7% 9A% 84 (straight)% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E8% BD% AC% E7% BD% AE% E5% BA% 8F% E5% 88% 97% E7% 9A% 84% E4% BA% A7% E7% 94% 9F% E5% 8F% AA% E8% A6% 81% E6% B1% 82% E5% 88% 86% E5% 88% AB% E4% BA% A7% E7% 94% 9F% E8% A1% 8C% E5% 92% 8C% E5% 88% 97% E7% 9A% 84% E5% 9C% B0% E5% 9D% 80% E3% 80% 82% E4% B8% A4% E8% 80% 85% E9% 83% BD% E7% 94% A8% E8% AE% A1% E6% 95% B0% E5% 99% A8% E5% AE% 9E% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E7% 8E% B0% E3% 80% 82% E8% A1% 8C% E9% 87% 8D% E6% 8E% 92% E5% BA% 8F% E7% 9A% 84% E8% A6% 81% E6% B1% 82% E5% 8F% AA% E4% B8% 8D% E8% BF% 87% E6% 84% 8F% E5% 91% B3% E7% 9D% 80% E5% 9C% B0% E5% 9D% 80% E6% 98% AF% E7% 94% A8% E4% B8% 80% E7% AE% 80% E5% 8D% 95% E7% 9A% 84% E7% 89% B9% E5% AE% 9A% E7% 8A% B6% E6% 80% 81% E6% 9C% BA% E8% 80% 8C% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E4% B8% 8D% E6% 98% AF% E8% 87% AA% E7% 84% B6% E8% AE% A1% E6% 95% B0% E5% 99% A8% E4% BA% A7% E7% 94% 9F% E7% 9A% 84% E3% 80% 82

Inverting Zig-Zag sequences generated in the algorithm is not so simple. Because of the fact A small ROM is used to store all 64 6-bit address value. This ROM with rows and columns count Number of control to addressing. These counters can be exchanged so that the horizontal and vertical scanning of the Room changed. A ROM with a generator can quickly designed. It also has a good Office, is this: to achieve positive Zig-Zag (ROM reprogramming) or other possible increase in the future The sequences are not required to spend a high price. B.9.9.4 "oned" - a one-dimensional IDCT transform

This block has a depth of 20 assembly line, this line in the blocked (sta- lled) when strong (rigid)'s. This greatly simplifies the design robust and does not Measurably affect the overall dynamics. This is because the pipeline depth is not so great, and Two one-dimensional converters are located in RAM after, RAM provides a certain amount of buffer.

This member according to the standard structure, but the data token extensions (which are to be processed) And all other items, the inside has a separate path. All other items are those that should not be changed Through the items. Note: The illustration is drawn in a special way. First, due to the Seeking to combine all of the data path logic, second, because of the requirement to allow automatic generation Decoding (which shows the control logic at the top).

Token is analyzed as usual, then the data expansion and other values ​​in the same multi-way switch Select discouraged combinations were previously prescribed route through two different parallel paths. And more Road transport in the output two-wire interface latch means the front. Parallel paths are required, because Value by changing the data path for the transfer could not be changed. With a simple shift register Token memory to handle the rest of the stream, the transformed data to obtain the waiting time match path With.

"Oned" need to analyze the control part of the token stream and a control token segmentation and reassembly Together. Another of its main part of the control change data path. The data path control Major institutions is a control shift register. It matches the data path pipeline, it is divided into Next, each of the data path pipeline to provide the necessary level of control signal.

"Oned" block has such a requirement, is this: it can only complete line of data expansion, Expansion is a complete line of eight groups began to operate, it can not be processed in the middle of each row are not legitimate Data ("gap), despite the fact that," izz "and" tram "work has confirmed Paul output is a complete data block. This data block 64 is a valid extension values ​​are not Intermittent sequence. B.9.9.4.1 transform data path

Microstructure transformed data path, "t_dp", previously shown in Figure 141. Note that Certain details (e.g., clock, shift, etc.) not shown. However, this figure shows the number of How pipelined data path to any one of the four values ​​simultaneously operate. The base data path Book structure that three main parts can also be seen (e.g., pre-common block, common block, After the common block), the required computing resources and latch resources are also able to see. Named control System is a pipeline latch signal (processing / down selector) enable signal. They are by Controlled shift register state decoding order. Note that each pipeline stage the actual Length is four clock cycles. ...

Microstructure transformed data path, "t_dp", previously shown in Figure 141. Note that Certain details (e.g., clock, shift, etc.) not shown. However, this figure shows the number of How pipelined data path to any one of the four values ​​simultaneously operate. The base data path Book structure that three main parts can also be seen (e.g., pre-common block, common block, After the common block), the required computing resources and latch resources are also able to see. Named control System is a pipeline latch signal (processing / down selector) enable signal. They are by Controlled shift register state decoding order. Note that each pipeline stage the actual Length is four clock cycles. ...

The main requirements of computing elements are as follows:

· Some fixed coefficient multiplier (carry-save output)

· Carry-save adder

· Carry-save subtractors

· Solving adder

· Solving adder / subtractor

All calculations in two's complement notation is completed. This can be either normal (already solved) Form, it can be carry-save form (i.e. two numbers and their sum represents the true value) In all previous numbers have been deposited in solving out, but only once per stage pipeline operation solving Make, because this is the most time consuming operation. Here all the operations done by solving a simple Pulsation. This means that the solver is quite small, but relatively slow. Because solving the total time at each level Between the dominant, the use of fast solution arithmetic unit, apparently have the opportunity to accelerate the entire Transformation. B.9.9.5 "Ras" - rounding and saturation

In this item invention, "ras" block task is the second dimension "oned" output Get 22 fixed-point, the number of these requirements into a proper rounding and saturation of 9 band breaks Integer result. This block is also inherent in the program must complete a divided by 4 (2 / N items) and re- By 2 to compensate for each dimension of the two-dimensional pre-scaled by √ 2. This is 8 In addition to fixed-point position is seen as show than expected to move to the left 3. That is, the result as 15 Bit integer notation and seven decimal (rather than four decimal places). Rounding mode is achieved "Rounding toward positive infinity direction (round to positive infinity)", ie positive Good is 0.5 plus a decimal. This is mainly because it is easiest to achieve rounded square Style. In rounding (the integer part of the conditions for an increase) is completed, the results are checked to see the 9 Bit signed result is saturated to the range required maximum or minimum. This work Used for incremental Carry out the highs and the original check with an integer value method to complete. ...

In this item invention, "ras" block task is the second dimension "oned" output Get 22 fixed-point, the number of these requirements into a proper rounding and saturation of 9 band breaks Integer result. This block is also inherent in the program must complete a divided by 4 (2 / N items) and re- By 2 to compensate for each dimension of the two-dimensional pre-scaled by √ 2. This is 8 In addition to fixed-point position is seen as show than expected to move to the left 3. That is, the result as 15 Bit integer notation and seven decimal (rather than four decimal places). Rounding mode is achieved "Rounding toward positive infinity direction (round to positive infinity)", ie positive Good is 0.5 plus a decimal. This is mainly because it is easiest to achieve rounded square Style. In rounding (the integer part of the conditions for an increase) is completed, the results are checked to see the 9 Bit signed result is saturated to the range required maximum or minimum. This work Used for incremental Carry out the highs and the original check with an integer value method to complete. ...

This component is a simple decoder, its four microprocessor interface address lines And "sel_test" input decoding, as individual components (look into the depths, and RAMs) Test Access Q Select line. This component contains only zcells combinational logic. Decoded selection (selects) are shown in Table B.9.1.

Table B.9.1 IDCT test address space

Address (hex)	Bit No.	Register name
			0x0
	7..1	Need not
				0	TRAM keyhole address
	0x1
		7..0
	0x2		7..0	TRAM keyhole data
0x3
		7..0	TRAM keyhole dataa
0x4				7..0	IZZ keyhole address
	0x5
		7..0	IZZ keyhole data

Table B.9.1 IDCT test address space (continued)

Address (hex)	Bit No.	Register name
			0x6
	7..3	Need not
				2	ipfsnoop test select signal
	1	ipfsnoop effective
				0	ipfsnoop accepted
	0x7	7..5	Need not
5..0				ipfsnoop bit [21:16]
		0x8	7..0		ipfsnoop bits [15:8]
0x9	7..0			ipfsnoop Bit [7:0]
		0xA	7..3		Need not
2	d2snoop test selection
			1	d2snoop effective
0	d2snoop accepted
			0xB	7..6	Need not
5..0	d2snoop bit [21:16]
		0xC		7..0	d2snoop bits [15:8]
0xD	7..0		d2snoop Bit [7:0]

Table B.9.1 IDCT test address space (continued)

Address (hex)	Bit No.	Register name
			0xE
	7	outsnoop test selection
				6	outsnoop effective
	5	outsnoop accepted
				4..2	Need not
	0xE	1..0	outnoop Data [9:8]
0xF				7..0	outnoop Data [7:0]

a. duplicate address B.9.9.7 "Idctregs"-IDCT Control Register and events

This block contains the present invention is the standard event handling logic blocks insufficient data errors and redundant Error instance (instances), there is a separate memory mapped bit "vscan", It is used to change the "izz" reordering, the IDCT output is a vertical scanning. This bit is Is reset to "0", the default mode is the horizontal scan output. Two possible events are 'Or' together form a idctevent signal, this signal is used as an interrupt signal. Register and events addresses and bit position see Section B.9.10. B.9.9.8 clock generator

In the IDCT using the two "standard" type ("clkgen") clock generator. Thus there are two separate scan paths. Clock generator called "idctcga" and "Idctcgb". The only difference is that the function "idctcgb" need to generate "not- rstl "signal two clock generators, each of the clock and reset outputs of the buffer device The total amount is set, each tailored to each clock and reset driven real load. Negative match Out of the final layout and printing line gate (track) of the actual measured capacitance.

When completed the top IDCT block arrangement and wiring (Place and Route), we Global routing using the interactive features to increase the ability of the first part of the clock distribution tree wire The width of the remaining weight for negative clock (Pho-b and Phi-b), because on these lines will More current flows. B.9.9.9 JTAG control block

Because IDCT has two separate scan chains and two clock generators, so there are two Standard JTAG control block "jspctie" instance. These test ports and control means Scan path is formed between the two interfaces. B.9.10 events and control register

IDCT can generate two events, there is a single control bit. These two events are idct_too_few_event and idct_too_many_event. If incorrect data The token is detected in front of the IDCT "decheck" component to produce these events. Separate control bit is "vscan", requires IDCT output vertical scanning, put it set. So this one controls the "iZZ" blocks. Transform the entire event logic and memory control bits Are placed in "idctregs" block.

From the IDCT perspective, these registers placed in the following locations. Tristate i / o lines n_ derrd and n_serrd used at the right time to read and write these units.

Table B.9.2 IDCT control register address space

Address (hex)	Bit No.	Register name
			0x0
	7..1	Need not
				0	vscan

Table B.9.3 IDCT address space event

Address (hex)	Bit name	Register name
			0x0	n_derrd	idct_too_few_event
n_serrd	idct_too_many_event
		0x1		n_derrd	idct_too_few_mask
n_serrd	idct_too_many_mask

B.9.11 methodological issues B.9.11.1 logic design methods

According to the present invention, in the design of all the IDCT blocks in an attempt to use a unified simple logic Design countermeasures. Such an approach could mean a quick and simple way to make a "safe" setting Meter. Most of the control logic, when using only a master - slave relationship simple solution. Asynchronous set / reset input connected only to the correct system reset. Although, it seems often to Can put forward ingenious nonstandard line configuration to more effectively perform the same function, but this party Case has the following advantages.

· Simple concept

· Easy to design

• Operation speed is very obvious (the latch → Logic → Latch> Logical design than Over), and appropriate for the automatic analysis

· No glitch on a waveform (glitches) problems (compared with SR latch)

· Initialization only system reset,

· Allow the scan path correctly

· Allow automatic compiled C-code generation

There are many places with a transparent and d-type latches, which are listed below.

Input and output wire interface standard block structure using latches. Two lines in the output lock Ters and subsequent two-wire latch input does not exist between logic. B.9.11.1.2 ROM Interface

Because ROM circuit timing requirements at the output of the ROM IZZ sequence generator using The latch. B.9.11.1.3 transformed data path and control shift register

Each pipeline is possible to use full storage level master - slave to achieve, but for want Seeking the cause of storage, with the latch can greatly save. However, this solution requires The user to consider several factors.

· Control the shift register is used to enable and must now produce two phases (phases) The control signal (i.e., the shift register latches required)

· Adopt latch timing analysis is more complex

· "T-postc" will no longer automatically generates compiled code, because a latch Is output to the other in the same phase the latch (since the timing is enabled, the line for this Not a problem)

However, due to savings in area with latch, making the inventions worthy of acceptance because these Su. B.9.11.1.4 Microprocessor Interface

Because this interface is the nature of the event and register block "idctregs" in RAM Core logic keyhole latch (and re-synchronizer) have some requirements. B.9.11.1.5 JTAG test control

These standard blocks using latches. B.9.11.2 circuit design issues

In addition to the design library units work done outside, does not require any grain in the IDCT Transistor level circuit design. Library unit (library cells) for IDCT design (standard single Yuan, datapath library, RAM, ROM, etc.). To the conversion of some known data channel The shortest path to do some circuit emulation (using Hspice), on those close to the permissible The maximum length of the path is, Hspice also used to verify the shortest path analysis (CPA) ENGINEERING A result.

Note that, in normal operation, IDCT is fully static (i.e., we can indefinitely To stop the system clock), but can be scanned (scanable) latches in the dynamic node, The test clock is stopped (or very slow) when they disappear. Not due to some node Recovery, they show a Vt landing (such as multi-output), so that in the static IDCT May not "micro-power" (micro-power) of. B.9.11.3 layout method

The invention of the layout to achieve the overall approach was used BPR (some manual intervention) cloth Set a full IDCT. IDCT of many zcells and a small macro blocks. These macroblock These hand-edited layout (e.g., RAM, ROM, clock generators, data path); if Is "oned" block, then use the BPR put more zcells and data path composition.

Data path with kdplib units. In addition, kdplib unit of local requirements Change Layout be defined and used in a good place to improve size. In each oned block The data path used, "oned_d" is the largest single component design, then for A great deal of effort to the size of this data path (height) to be optimized.

Transform data path "t_dp" organization is quite critical, because the data path within The exact ordering of components will affect the internal connections are handled. Reducing the "overs" (not The sub-blocks connected to the vertical line) is the number of very important. This happens in the most crowded spot, Because there is a maximum allowed value (ideally 8, 10 is also possible, however, very Convenient). Data path is logically divided into three main sub-sections, the data path layout Doing the same. In each sub-component, the effective four parallel data streams (those streams not The location is combined with), so that in each sub-section has a number of organizational data streams (thus, Position of all components) method. In each sub-section, the sort of the block, as well as logic Series bus assignments physical bus spacing (pitches), before the start of the layout are small Heart made in order to be able to get a proper connection layout. B.9.12 Inspection ...

Transform data path "t_dp" organization is quite critical, because the data path within The exact ordering of components will affect the internal connections are handled. Reducing the "overs" (not The sub-blocks connected to the vertical line) is the number of very important. This happens in the most crowded spot, Because there is a maximum allowed value (ideally 8, 10 is also possible, however, very Convenient). Data path is logically divided into three main sub-sections, the data path layout Doing the same. In each sub-component, the effective four parallel data streams (those streams not The location is combined with), so that in each sub-section has a number of organizational data streams (thus, Position of all components) method. In each sub-section, the sort of the block, as well as logic Series bus assignments physical bus spacing (pitches), before the start of the layout are small Heart made in order to be able to get a proper connection layout. B.9.12 Inspection ...

Transform the structure of the initial work was done with C. Full accuracy and precision integer model in place Both are developed. Various tests are made ​​on the model precisely in place in order to ensure Consistent with the H.261 accuracy requirements, and the transformation within the structure of the dynamic measurement of the calculated Range.

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The logical approach is to simulate a schematic diagram for each analog stuff, as long as the stuff in Which level analog meet the requirements. Low-level library unit (ie zcells and kdplib) They are mainly used to simulate the performance descriptions, as this get a smaller faster simulation. Other In addition, the performance library unit provides timing calibration feature, which enables certain line configuration issues outstanding. As a reliability test, some simulations using library unit transistors description to complete. All Zero delay logic simulation under the state, so the purpose is to examine functional properties. Real Test performance when using other techniques.

Lsim switch layer simulation (with RC_ timing mode) as part of the inspection timing characteristics Experience to do, but also provides some other potential problems transistor-level test (case If the glitch sensitive line).

The main test timing problems CPA inspection techniques is the use of tools, for "datechk" "Path" option. This is used to identify the longer signal paths (some already known). Hspice is used in certain critical situations validation CPA analysis.

Most Lsim analog source with standard components → → drain (sink) methodology carried out, Because the majority of IDCT characteristics is through the device token stream drill. Other Simulation is necessary. Use these simulations to test the microprocessor interface accessed via special Xing (configuration, event and test logic) and those through JTAG / scan test access Test characteristics.

Encoding and decoding of the entire IDCT simulated by one of ordinary skill in the Bank who are easily Completed. Once again using the standard source → Block → drain and a method of testing for Lsim Many of the same token streams. B.9.13 Testing and Test Support

This section examines some of the techniques for testing and analyzing how to test each block.

Access provided for testing three techniques (mechanisms) are as follows:

· Microprocessor access to RAM

· Microprocessor access Kuice parts

· Access control and data path logic scan path

There are two in the IDCT "peeking" on parts and a "super glimpse into the device" components. Figure 140 shows the location of parts peeking devices and other microprocessor test access.

To test all the main components of the characteristics of the token stream related purposes, with the above components And two RAM blocks, you can isolate each of the main block. Using a microprocessor access, you can Control token input to either a block, and then observing the isolated parts of the token port output. In addition, there are two separate scan paths, which through each block of the control part (several Almost) all of the flip-flops and latches for "oned" transform data path pipeline. They are also some of the data path through the latch. With two scan path "a" and "b" form Shows, the former from "decheck" block runs to "ip_fmt" part and the latter from the first "Oned" block to the "ras" block. ...

To test all the main components of the characteristics of the token stream related purposes, with the above components And two RAM blocks, you can isolate each of the main block. Using a microprocessor access, you can Control token input to either a block, and then observing the isolated parts of the token port output. In addition, there are two separate scan paths, which through each block of the control part (several Almost) all of the flip-flops and latches for "oned" transform data path pipeline. They are also some of the data path through the latch. With two scan path "a" and "b" form Shows, the former from "decheck" block runs to "ip_fmt" part and the latter from the first "Oned" block to the "ras" block. ...

Each component will now be discussed with the problems related to the various tests. B.9.13.1 "Decheck"

Each component will now be discussed with the problems related to the various tests. B.9.13.1 "Decheck"...

This block is a variant of the standard structure, including a two-wire interface latch added RAM blocks parts and control part. Zcells control section is realized, the address sequence generation With a small ROM. All zcells in the scan path "a", through the latch zcell Browser to access the ROM address and data. There is more logic, for example, number generation, Plus the ability to increment or decrement. In addition, there is a seven full adder is used to read the address of raw Percent. RAM microprocessor interface can be accessed through the keyhole registers. Table B.9.1. B.9.13.3 "lp-fmt"

This block is also a standard format. Control logic with some fairly simple logic zcell Series implementation (all in the scan path "a" 1). But the data latch and shift / multiple pass Delivery is no direct access to complete data path, because the logic here is very simple and obvious And simple. B.9.13.4 "oned"

This block is also a standard structure. It is divided into random logic and data path in two parts. zcell relatively simple logic, all zcells are in the scan path "a" on. Transform stream Watermark data path control signal is derived from a long shift register is obtained. This shift Register contains zcell latches. Latches in the scan path. In addition, since the flow Waterline between certain level has considerable logic depth (such as multipliers and adders), the In certain pipeline latch is placed in the scan path. Non-data tokens along a shift register Transfer register, the shift register is used as a data path to the realization of any of the levels are not Test access. B.9.13.5 Tram ...

This block is also a standard structure. It is divided into random logic and data path in two parts. zcell relatively simple logic, all zcells are in the scan path "a" on. Transform stream Watermark data path control signal is derived from a long shift register is obtained. This shift Register contains zcell latches. Latches in the scan path. In addition, since the flow Waterline between certain level has considerable logic depth (such as multipliers and adders), the In certain pipeline latch is placed in the scan path. Non-data tokens along a shift register Transfer register, the shift register is used as a data path to the realization of any of the levels are not Test access. B.9.13.5 Tram ...

This standard structure and fully implemented by the zcells. The most complex logic functions Could be used for 8-bit rounding incrementer. All other logic is quite simple. In all states Scan Path "b" on. B.9.13.7 other top-level block

This standard structure and fully implemented by the zcells. The most complex logic functions Could be used for 8-bit rounding incrementer. All other logic is quite simple. In all states Scan Path "b" on. B.9.13.7 other top-level block...

This standard structure and fully implemented by the zcells. The most complex logic functions Could be used for 8-bit rounding incrementer. All other logic is quite simple. In all states Scan Path "b" on. B.9.13.7 other top-level block...

Core brand All data flow between the blocks (and block a large part of the data stream) With a two-wire interface. (See Technical Reference and detailed chapter). Figure B.10.1 Each of Arrows indicate a two-wire interface. Enter the token flow through the input interface, which put From the phase locked loop (Ph0/Ph1) obtained from the internal clock to the external system clock Data synchronization. Token flow through a top fork into two paths, all the way into the address generation Device, the other way to a 256-word FIFO. From the preceding I or P frame data from the DRAM When removing, FIFO dampening effect on the data. Meanwhile, the previous I or P frame number It is removed from the DRAM, they are predictive adder (Prediction Adder) was added From the spatial decoder (Spatial Decoder) to input the number of errors (incoming err- or data) before the first filter processing in the projections (P and B frames). In MPEG Decoding a, I, and P frames frame reordering data must also be removed in order to make the output frame is Indeed. Reordering the data read pointer (Read Rudder) block is inserted into the stream. ...

Core brand All data flow between the blocks (and block a large part of the data stream) With a two-wire interface. (See Technical Reference and detailed chapter). Figure B.10.1 Each of Arrows indicate a two-wire interface. Enter the token flow through the input interface, which put From the phase locked loop (Ph0/Ph1) obtained from the internal clock to the external system clock Data synchronization. Token flow through a top fork into two paths, all the way into the address generation Device, the other way to a 256-word FIFO. From the preceding I or P frame data from the DRAM When removing, FIFO dampening effect on the data. Meanwhile, the previous I or P frame number It is removed from the DRAM, they are predictive adder (Prediction Adder) was added From the spatial decoder (Spatial Decoder) to input the number of errors (incoming err- or data) before the first filter processing in the projections (P and B frames). In MPEG Decoding a, I, and P frames frame reordering data must also be removed in order to make the output frame is Indeed. Reordering the data read pointer (Read Rudder) block is inserted into the stream. ...

Time decoder block is connected to all the major internal microprocessor interface (UPI) bus. This is from the microprocessor interface components external microprocessor interface (MPI) bus to get The. This component associated with it on a chip address decoder of the components. Event logic Series is also related to the interface with the microprocessor.

Time decoder block is connected to all the major internal microprocessor interface (UPI) bus. This is from the microprocessor interface components external microprocessor interface (MPI) bus to get The. This component associated with it on a chip address decoder of the components. Event logic Series is also related to the interface with the microprocessor....

Time decoder block is connected to all the major internal microprocessor interface (UPI) bus. This is from the microprocessor interface components external microprocessor interface (MPI) bus to get The. This component associated with it on a chip address decoder of the components. Event logic Series is also related to the interface with the microprocessor....

In normal operation, most blocks of the chip and from the phase-locked loop (PLL) block letters No. pllsysclk synchronous operation. DRAM Interface is an exception, its timing depends on the iftime sub-block synchronization. iftime subblock generation DRAM control signal (notwe, notoe, notcas, notras). This block is the core of the two-phase non-overlapping clock clko And clkl timing. They are from the 90 ° phase of the two-phase clock obtained, but these two Clock is generated by PLL cki0, ckil and ckq0, ckq1 independent supply.

Because clko, clk1 DRAM interface clock and with the rest of the chip clock is different Step, the DRAM interface and the rest of the chip at the interface between the steady state may be temporarily (Metastable behavior). Measures have been taken (as far as practicable) to eliminate this may Capable of. Synchronization occurs in two areas: in the address generator output interface (addrgen / predread / psgsync, addrgen/ip_wrtz/sync18 and addrgen/ip_rd2 / sync18) and in some parts. These components control the DRAM interface (see DRAM access The mouth of the relevant chapters) in the alternate buffer (swing-buffer RAMs) of "alternate." In each case, with the three series of transient stability Hard (metastable-hard) triggers the completion Synchronization process. It should be noted that the address generator means clk0/clk1 used in the output Phase. ...

Because clko, clk1 DRAM interface clock and with the rest of the chip clock is different Step, the DRAM interface and the rest of the chip at the interface between the steady state may be temporarily (Metastable behavior). Measures have been taken (as far as practicable) to eliminate this may Capable of. Synchronization occurs in two areas: in the address generator output interface (addrgen / predread / psgsync, addrgen/ip_wrtz/sync18 and addrgen/ip_rd2 / sync18) and in some parts. These components control the DRAM interface (see DRAM access The mouth of the relevant chapters) in the alternate buffer (swing-buffer RAMs) of "alternate." In each case, with the three series of transient stability Hard (metastable-hard) triggers the completion Synchronization process. It should be noted that the address generator means clk0/clk1 used in the output Phase. ...

Boundaries of the transmitted clock mode signal must be re-synchronized because never simultaneously The resulting non-overlapping clock generator clock slight misalignment between the (minor skews) may Means that each interface overlap (underlab). Established in each of the "peeking" on the block (See Section B.11.4) internal circuitry to ensure this does not happen. Kuice block has been All clocks placed on the boundary between the way. However, in front of the address generator is a sample In addition, where the re-synchronization is completed within the token decoding unit. B.11.2 clock control

Each standard clock generator produces many different clocks, they allow in the normal way Type and scan - test (scan-test) mode. Scan - test mode, when Clock control has been described elsewhere. But it is worth noting that a clock generator Several clock (tpho, tph1, tckm, tcks) usually has not been linked to the Graphic Any basic diagram symbols (primitive symbols). This is because the scan path is After the processor by an automatically generated. This post-processor to properly connect these clocks. From a functional point of view, the post-processor is connected with the fact that the icon can be different clock To overlook; effect (behavior) is the same. ...

Each standard clock generator produces many different clocks, they allow in the normal way Type and scan - test (scan-test) mode. Scan - test mode, when Clock control has been described elsewhere. But it is worth noting that a clock generator Several clock (tpho, tph1, tckm, tcks) usually has not been linked to the Graphic Any basic diagram symbols (primitive symbols). This is because the scan path is After the processor by an automatically generated. This post-processor to properly connect these clocks. From a functional point of view, the post-processor is connected with the fact that the icon can be different clock To overlook; effect (behavior) is the same. ...

Table B.11.1 Clock Control

pllselect	override	Manner
				0	0	pllsysclk be directly connected to an external sysclk, The PLL Bypass; DRAM interface clock (cki0, cki1, ckq0, ckq1) and starting straight from the lead ti Access is controlled.
0	1	Override mode-ph0 and ph1 clock from tph0ish and tp1ish leads directly be controlled. DRAM interface clock (cki0, cki1, ckq0, ckq1) leads directly from ti and tq be controlled.
			1	0	Work pllsysclk is generated when the PLL Bell; DRAM interface clock generated by PLL.
1	1	External resistor connected to ti and tq instead of the internal electricity Resistance (only troubleshooting).

B.11.3 two-wire interface

The total two-wire interface functions are described in detail in the Technical Reference. However, the two-wire interface with At the time all the parts inside the decoder to the component communications. Most of the block contains several water Line-level, all of these pipeline stage itself are two-wire interface level. Therefore, in order to clarify Many circuit diagram, two-wire interface to understand the internal implementation is very important. In general, these internal Pipeline stage portion 143 constructed as shown in Fig.

Figure 143 shows a latch - Logic - Latch representation, since it is through The structure often used. However, when put together many levels that the latch - Latch - Logic "class" is also valid (for many engineers it is a more familiar terms Model). Latch - Logic - Latch structure allows the use of all internal block communication The latch to latch, either send or receive in the blocks do not have any insertion logic.

Referring again to Figure 143, by removing the logic block will be able to form a simple two-wire interface FIFO level. Then the data valid signal and a direct connection between the latch is latched in _valid signal is directly connected to the in_accept latch input NOR gate, as out Out_accept _Valid signal and the gate control signal is the case. When the corresponding receiver Signal is high, the data valid signal and the transmission. In this manner, the in_valid and out_accept_reg phase or, if in_valid is low, out_accept_reg the low data Will be received. Whenever the stop (received signal low) occurs, the gap (with a valid bit low Data) is removed from the pipeline.

As shown in Figure 143, the logic block is inserted, in_accep and out_valid also the same number Data or block status. In the illustrated configuration, the master from the setting of the block held by Any standard state, the master device is enabled with Ph1, from equipment Ph0 enabled. B.11.4 Kuice block

Kuice block, via the microprocessor interface, the different points of the chip access data stream. There are two types peeking block. Usually Kuice block can be accessed only in the test mode, where Clock can be directly controlled. "Super peeking" on the clock is running can be accessed. It contains a line that comes from the microprocessor bus asynchronous data with the internal chip clock synchronization. Table B.11.2 lists all the decoder temporarily moved to look for the location and type.

Table B.11.2 time peeking decoder device

Location	Type
		addrgen/vec_pipe/snoopz31	Kuice device
addrgen/cnt_pipe/endsnp	Kuice device
		addrtgen/cnt_pipe/endsnp	Kuice device
addrgen/predread/snoopz44	Kuice device
		addrgen/ip-wrt2/superz10	Super Kuice device
addrgen/ip_rd2/superz10	Super Kuice device
		dramx/dramif/itsnoops/ snoopz15(fsnp)	Kuice device
dramx/dramif/ifsnoops/ snoopz15(bsnp)	Kuice device
		dramx/dramif/ifsnoops/superz9	Super Kuice device
wrudder/superz9	Super Kuice device
		pflts/fwdflt/dimbuff/snoopk13	Kuice device
pfits/bwdflt.dimbuff/snoopk13	Kuice device
		pflts/snoopz9	Kuice device

The use of two kinds of peeking details included in the test section. JTAG interface work Details contained in the JTAG file. B.12 Function Block B.12.1 top fork (Top Fork)

According to the present invention, the top of the fork has two purposes. First, it bifurcation into the data stream Two separate streams: one to the address generator, and the other to the FIFO. Second, it provides Means for starting and stopping the chip, the chip can be configured.

Fork portion of the device looks very simple. The same data both to the address generator, Also added to the FIFO. In an interview before a signal is sent back on, this data must have been Address generator and FIFO receive. Thus, two fork branches are dependent on the effective signal Another branch of the receive signals. If the chip is in the stopped state, added to the two branches of the effective Signals are held low.

In in_accept remains low, the chip start until the configuration bit is set high. This Ensures that the user has configured the chip before, no data is accepted. If the user needs Any other time configuration chip, he must set the configuration bits and wait until finished chips To the current stream. Stop the following steps:

1) If the configuration bit has been set, at the top fork detects a FLUSH token, No longer receive more data.

2) FLUSH token reaches the read pointer, the chip has finished streaming. This allows the signal seq _done high.

3) When seq_done becomes high, set an event bit, this bit can be read microprocessor. Event signal can be masked event block. B.12.2 address generator

In the present invention, the address generator (addrgen) is responsible for a frame block count, And is responsible for the DRAM data transfer sequence to produce the correct address. Address generator input From the token input port (via the top fork) to the token stream. Its output to the DRAM Interfaces, including addresses and other information. This information is a request / acknowledge protocol control.

The main part of the address generator are:

· Token decoding

· Block counting and generation of DRAM block address

· Motion vector data into the address offset

· To predict send a request to the address generator

· Reordering read address generator

· Write address generator B.12.2.1 token decode (tokdec)

The token decoder, with coding standards, frame and block information and a motion vector with The tokens are decoded off. The information extracted from the stream into a set of registers. By upi also You can access these registers. Token header data is detected on the subsequent signal to each of the blocks Can block count and address generation. JPEG nothing happens when you run.

List of tokens is decoded as follows:

  ·CODING_STANDARD

  ·DATA

  ·DEFINE_MAX_SAMPLING

  ·DEFINE_SAMPLING

  ·HORIZONTAL_MBS

  ·MVD_BACKWARDS

  ·MVD_FORWARDS

  ·PICTURE_START

  ·PICTURE_TYPE

  ·PREDICTION_MODE

This block is also a combination of the request from the generator to the information to control the frame pointer conversion (toggling), and stop the input stream. Appear at the input of a new frame (in pictu- re_start token form), the flow is stopped, but the previous frame or the write-back Reordering read has not been completed. B.12.2.2 macroblock counter (mblkcntr)

Macroblock counter of the present invention contains four basic counters which point to the frame macroblock The horizontal and vertical position of the block and the macro block horizontal and vertical position. Open at a time The beginning and every time there PICTURE_START, all counters are reset to zero. In a few According to the token header arrives, the token in the header according to the color component number and the structure of the frame, the total Number is added and reset. The frame structure used in the Token Decoder described sampling register.

For a given color component, as counts. Each new component to a number of the same According to the token, the horizontal block counter is incremented until it reaches the width of the last macro-block is then re- Position. This reset the vertical block count is incremented until it reaches the height of the macro block, so it Reset. When this happens, the next color component look. Thus, each of the macro block Component repeat step click - macro block in the horizontal and vertical dimensions may vary for each component of the Different. If, for any component, the received number of blocks to be less than expected, the count will Not wrong to proceed to the next component.

When the color component data token less than expected, the level of the macro block count increases. (Note Italy, for a given color component, where there is more than the expected value of the number of blocks, it will also This occurs. Because then the counter will expect a higher component of the index (index). When the count reaches the picture width in macroblocks, the horizontal count is reset. This Reset the vertical macroblock count increases.

In the H.261 CIF format, a further ability to count macroblocks. In this Situation between the macroblock and a picture called a block group (group of blocks) of the amount of Outside layers. This block group is 11 macro blocks wide and three deep macroblock, an image is always two Group wide. Token token decoder extracts from PICTURE_TYPE CIF bit. This spread macroblock Counter, the instruction of its block group count. Each component of the number of blocks too much or too little of the situation would lead From the same reaction. B.12.2.3 block calculates (blkcalc)

Block calculates the macro blocks and macro-blocks within the block to the image coordinates into the coordinate position of the block Standard, which it broke level. Of course, this must be different from the color components of the sampling ratio consideration Included. B.12.2.4 base block address (bsblkadr)

Information from blkcalc come together with the color components used to calculate the amount of displacement of the linear DRAM block address within the address space. In essence, for a given color component stresses, The linear block address is the number of blocks in a downward direction (number of blocks dowm) multiplied image Width plus the length direction, the number of blocks (number of blocks long). This is added to the color Color component offset to form the base block address. B.12.2.5 vector displacement (vec_pipe)

Token Decoder motion vector displacement information given by the horizontal and vertical pixel offsets In the form of coordinates. I.e. the forward and backward vectors in each of a (x, y). (x, y) Being formed from a block is given to the other blocks of the predicted displacement. Displacement is Expressed in units of half a pixel. Note that these coordinates may be positive or negative. They First, for each color component and the calibration samples (scaled), and is used to form blocks and New pixel offset coordinates.

In Figure 145, the shaded area represents the block that is being formed. Dashed outline indicates The block being predicted. Large arrow indicates the block offset - the horizontal and vertical DRAM block vector. The DRAM block that contains the prediction block origin - in this case is (1,4). Small arrow indicates a new Pixel offset - the DRAM block in the prediction block origin. Because DRAM blocks are 8 × 8 bytes, the pixel offset count is (7,2).

Multiplier array Vmarr1a then block vector offset into a linear vector Offset. Pixel information as a (x, y) coordinate (pix_info) predicted request is sent Generator. B.12.2.6 forecast request

Frame pointer, base block address and vector offset added together to form a block address. This block Is from the DRAM (Inblkad3) fetch address. If the pixel offset is zero, and generate a Requests. If the dimension in the x dimension or a y offset is generated two requests - the original Block address and immediately to the right or down immediately into both an address. Both in the x and y dimensions Offset, to produce four requests.

Chip clock mode and DRAM interface clock synchronization between the way the first increase occurred in France (Inblkad3) and between the state machine. This state machine generates the appropriate request. So the state Machine (psgstate) with DRAM interface clock timing, it constitutes a DRAM interface sweep scanning element Scan chain. B.12.2.7 reordering read and write requests

Because this does not involve a pixel offset, with the base block address and the frame pointer addition To form a film each address. Reordering read using the same frame memory. Predictions and data are Is written back into another frame memory. Each block includes a short FIFO, for memory address, Because the read and write data transfer is likely to lag behind projections on the corresponding address data transfer Send. (This is because the data stream along the chip, the read / write data more than the predicted data convection Effect). Each block also contains on-chip clock and the DRAM interface clock synchronization between. B.12.2.8 offset

DRAM memory configured with two frames, each containing up to three color components. In each frame Within the frame buffer pointer and offset color components must pass upi programming. B.12.2.9 Kuice device

In the present invention, the device is put peeking following location:

· In blkcalc and bsblkadr between - This interface includes horizontal and vertical block Block Standard, the appropriate displacement and the color components in the picture width in units of blocks (of the pair Component).

· In bsblkadr behind - the base block address.

· In vec_pipe back - linear block offset within the block pixel offsets and forecast Mode information, color component and H.261 operation.

· In Inblkad3 back - the physical block address, such as "prediction Request" above.

Super peeking reordering device in read and write requests generator, the external DRAM in the test Use. Look at all the details DRAM interface section. B.12.2.10 scan

addrgen block has its own scan chain, the timing of its own clock generator with member Generator (adclkgen) control. Note that the rear end of the part attribution DRAM request generator Interface clock range. B.12.3 ** prediction filter

According to the present invention, the general structure of the prediction filter 146 shown in FIG. Forward and backward filter Wave is identical, they are the MPEG forward and backward prediction block filtering. Only forward filtering Used in H.261 mode (after the input to the filter h261_on should always be low because there H.261 stream does not contain backward prediction). Throughout the prediction filter block consists of several two-wire interface level Pipeline components. B.12.3.1 prediction filter

Each of the predictive filter and another unrelated work perfectly valid data appeared in Its input, it will immediately process the data. As can be seen from Fig. 147 a prediction filter bag Including four separate blocks, two of which are the same. Preferably MPEG and H.261 operation alone Describe these blocks work site. H.261 is more complex, it is first described. B.12.3.1.1 H.261 operation

The one-dimensional filter equation used is as follows: $F_i=\frac{x_{i+1}+{2x}_i+x_{i-1}}{4}(1\&le;i\&le;6)$

                 F _i＝x _i(Other)

This formula is used for the prediction filter x 8> 8 for each row, the filter is y projections For each column. The mechanism to implement it are shown in Figure 118. This is basically the re FIG pfltldd Present. Filter consists of three two-wire interface consisting pipeline stages. The first and last line A pixel, registers A and C are reset, data does not change through the register B, D and F (B and D content is added to 0). B × 2 × mux control set, so that the output of register B The left one. This shift in addition to a position other than one in any event, it is always Displacement. Therefore, all the values ​​are 4 x (More about this explanation see below). All Other pixels x ..._i+1This formula is used for the prediction filter x 8> 8 for each row, the filter is y projections For each column. The mechanism to implement it are shown in Figure 118. This is basically the re FIG pfltldd Present. Filter consists of three two-wire interface consisting pipeline stages. The first and last line A pixel, registers A and C are reset, data does not change through the register B, D and F (B and D content is added to 0). B × 2 × mux control set, so that the output of register B The left one. This shift in addition to a position other than one in any event, it is always Displacement. Therefore, all the values ​​are 4 x (More about this explanation see below). All Other pixels x ..._iLoaded into register B, x_i-1Loaded into register A. From Figure 148 As can be seen, H.261 filter equation is then implemented. Because the vertical filtering is performed at three levels Group as a unit to complete, (see below comments on peacekeeping buffer) do not require different Handle the first and last row of pixels. In one line, control and counting pixels With each 1-D filter is the control logic is completed. It should be noted that the result has not been 4 In addition. In the prediction filter adder (B.12.4.2) completed at the input is 16 except (right 4 Bit). This is the horizontal and vertical filtering are completed achieved. Therefore, no calculation accuracy There are losses. Registers DA, DD and DF under the control signals to the line. This includes h261 _on and last_byte. ...

Loaded into register A. From Figure 148 As can be seen, H.261 filter equation is then implemented. Because the vertical filtering is performed at three levels Group as a unit to complete, (see below comments on peacekeeping buffer) do not require different Handle the first and last row of pixels. In one line, control and counting pixels With each 1-D filter is the control logic is completed. It should be noted that the result has not been 4 In addition. In the prediction filter adder (B.12.4.2) completed at the input is 16 except (right 4 Bit). This is the horizontal and vertical filtering are completed achieved. Therefore, no calculation accuracy There are losses. Registers DA, DD and DF under the control signals to the line. This includes h261 _on and last_byte. ...

Between the x and y filters, Victoria cache buffer data, so with three vertical pixels Ground to a set of y-filter. However, these 3 groups of pixels are still processed horizontally, So there is no prediction filter transpose happen. Referring to Figure 149, the output buffer from Victoria The order of the pixels in Table B.12.1 described.

Table B.12.1 H.261-dimensional buffer sequence

Clock	Input pixels	Output pixel	Clock	Input pixels	Output pixel
							1	0	55(a)	17	16	7
2	1	56	18	17	F (0.a.15)(b)
						3	2	57	19	18	F (1.9.17)
4	3	58	20	19	F (2.10.18)
						5	4	59	21	20	F (3.11.19)
6	5	60	22	21	F (4.12.20)
						7	6	61	23	22	F (5.13.21)
8	7	62	24	23	F (6.14.22)
						9	8	63	25	24	F (7.15.23)
10	9	0	26	25	F (8.16.24)
						11	10	1	27	26	F (9.17.25)
12	11	2	28	27	F (10.18.26)
						13	12	3	29	28	F (11.19.27)
14	13	4	30	29	F (12.20.28)
						15	14	5	31	30	F (12 20.29)
16	15	6	32	31	F (14.22.30)

a, before a pixel is the smallest line (least row of pixels from previous block), if there is no previous block (or if there is a long gap between blocks) is a valid number Data.

b, F (x) represents a function in H.261 filter equation. B.12.3.1.2 MPEG operation

In MPEG operation, the prediction filters to complete a simple half-pixel (half pel) Interpolation: $F_i=\frac{x_i+x_{i+1}}{2}(0\&le;i\&le;8,\mathrm{halfpel})$

             F _i＝x _i(0≤i≤7，integerpel)

Unless h261_on input is low, which is the default filtering operation. If the signal into the dim Into a 1-D filter is low, the integer pixel (integer pel) interpolation is performed. Corresponding , If the h261-0n low and xdim and ydim is low, all the pixels directly without filtering Through. This is an obvious requirement that when the dim signal into the 1-D filter is high, Row (or column) will be 8 pixels wide (or high). This is summarized in Table B.12.2 in. Ginseng To Figure 148, "1-D prediction filter." 1-D filter is the operation of the MPEG mid_pixel H.261 line with the first and last pixels in the operation is the same. For half as MPEG Su operations, register A is always reset, the register C output left one (in any Case, the output of register B is always left one). Therefore, after the two clocks, Register F contains (2B +2 C), four times the required result, but this prediction filter plus At the input of adder has been noted that there has been flowing through several filters both x and y, is shifted to the right 4. ...

Unless h261_on input is low, which is the default filtering operation. If the signal into the dim Into a 1-D filter is low, the integer pixel (integer pel) interpolation is performed. Corresponding , If the h261-0n low and xdim and ydim is low, all the pixels directly without filtering Through. This is an obvious requirement that when the dim signal into the 1-D filter is high, Row (or column) will be 8 pixels wide (or high). This is summarized in Table B.12.2 in. Ginseng To Figure 148, "1-D prediction filter." 1-D filter is the operation of the MPEG mid_pixel H.261 line with the first and last pixels in the operation is the same. For half as MPEG Su operations, register A is always reset, the register C output left one (in any Case, the output of register B is always left one). Therefore, after the two clocks, Register F contains (2B +2 C), four times the required result, but this prediction filter plus At the input of adder has been noted that there has been flowing through several filters both x and y, is shifted to the right 4. ...

h261-on	xdim	ydim	Function
				0	0	0	F i＝X i
0	0	1	Being translated ......
				0	1	0	· Run-6 位 .........
0	1	1	MPEG 9 × 9 块
				1	0	0	H.261 Low-pass filter
1	0	1	Illegal
				1	1	0	Illegal
1	1	1	Illegal

In MPEG format and the dimensions of the buffer functions are relatively simple. Formatter will Must first collect two effective pixels, and only then in order for them to make a half-pixel x-filter Interpolation; dimensional buffer cache only one line. It is noteworthy that the data has passed through x-filter After the filter, a line is always only 8 pixels, because the filtering action of the nine pixels The row is converted into 8 rows of pixels. "Lost" pixels in the data stream using the gap instead. When finished after the half-pixel interpolation, X-filter in each line terminal (8 pixels in each of the After) inserting a gap; y-filter inserted at the end of the block 8 gap. This is important , Since the end of the block of eight or nine out of the gap and the set of data in the stream FIFO token header to And between the data token is consistent with other tokens. This makes the chip liquidity in the worst case scenario Minimized. This happens when the 9 × 9 when the block is filtered. B.12.3.2 prediction filter adder ...

In MPEG format and the dimensions of the buffer functions are relatively simple. Formatter will Must first collect two effective pixels, and only then in order for them to make a half-pixel x-filter Interpolation; dimensional buffer cache only one line. It is noteworthy that the data has passed through x-filter After the filter, a line is always only 8 pixels, because the filtering action of the nine pixels The row is converted into 8 rows of pixels. "Lost" pixels in the data stream using the gap instead. When finished after the half-pixel interpolation, X-filter in each line terminal (8 pixels in each of the After) inserting a gap; y-filter inserted at the end of the block 8 gap. This is important , Since the end of the block of eight or nine out of the gap and the set of data in the stream FIFO token header to And between the data token is consistent with other tokens. This makes the chip liquidity in the worst case scenario Minimized. This happens when the 9 × 9 when the block is filtered. B.12.3.2 prediction filter adder ...

Predictive mode can only change between blocks, i.e. at startup (power-up) or at the fwd _1st_byte And / or bwd_1st_byte signal is valid after that is the current prediction block The last byte. If the current block is a forward prediction, only test fwd_1st_byte. If it is a backward prediction, only test bwd_1st_byte. If it is a dual To predict the fwd_1st_byte and bwd_1st_byte both have to test.

Signal fwd-on and bwd-on decide which one predicted value. At any time, these Both signals may be active or inactive both. Startup, or when the input of the block is not Valid (valid) data and the emergence of a gap, the block into two signals are invalid state State.

Using two criteria determine the next block prediction mode: Signal fwd_ima_twin and bwd_ima_twin, they indicate that prior to the block or blocks after the bidirectional prediction pair a Part, and the bus fwd_p_num [1:0] and bwd_p_num [1:0]. The bus contains several Words, these numbers for each new prediction block or the prediction block (pair) by 1. These blocks Is necessary, because, for example, if two forward prediction blocks followed by a bidirectional Prediction block, DRAM interface is far enough to get to the front block backward bidirectional prediction block, So that the second block until the forward prediction, the backward prediction filter reaches the adder block Inputs. Similarly, the other backward and forward prediction series prediction filter in the adder At the input is removed from the sequence. Therefore, the following predictive mode is determined as follows: ...

Using two criteria determine the next block prediction mode: Signal fwd_ima_twin and bwd_ima_twin, they indicate that prior to the block or blocks after the bidirectional prediction pair a Part, and the bus fwd_p_num [1:0] and bwd_p_num [1:0]. The bus contains several Words, these numbers for each new prediction block or the prediction block (pair) by 1. These blocks Is necessary, because, for example, if two forward prediction blocks followed by a bidirectional Prediction block, DRAM interface is far enough to get to the front block backward bidirectional prediction block, So that the second block until the forward prediction, the backward prediction filter reaches the adder block Inputs. Similarly, the other backward and forward prediction series prediction filter in the adder At the input is removed from the sequence. Therefore, the following predictive mode is determined as follows: ...

2) If valid backward data is present, and the bwd_ima_twin is high, the block stop, Until With fwd-ima-twin of the set, the valid forward data arrives, then as above a Sample processing. If the forward and backward data are valid together, does not stop.

3) If valid forward data exist, but fwd_ima_twin not set, then check fwd p_num. If this is equal predicted from the last number plus one (stored in pred_num in) The test mode is set to forward.

4) If the effective reverse data exist, but bwd_ima_twin not set, then check bwd_ p_num. If this is equal predicted from the last number plus one (stored in pred_num middle), The predictive mode is set to backward.

Note that the use of a return from the pipeline to the "early-valid" signal, This is to enable a prediction filter to the adder means of the new first data blocks to arrive Previously set. This ensures that no stop line was introduced.

ima_twin and pred_num signal is not filtered along with the data and prior to the adoption and Reverse prediction filter pipeline. This is because:

1) These signals only in the fwd-1st-byte and / or bwd-1st-byte is valid only when Be examined. In which each of the prediction filter 25 saves almost three pipeline stages.

2) in the block, the signal remains active, so that when fwd_1st_byte and / or bwd_1st_byte adder arrival prediction filter, the signal is valid.

3) before the arrival of the data signal for one clock cycle to be tested. B.12.4 Prediction Adder and FIFO

Predictive adder (padder) with the prediction error data filter data plus (error data) formed by the method of the predicted frame (predicted frame). In order to fill Compensation from the input through the address generator, DRAM interface and prediction filters in delay caused, Padder before reaching the error data, through a 256 word FIFO (sfifo).

CODING_STANDARD, PREDICTION_MODE and the data token is decoded to determine When given a prediction block is formed. In the data token, the eight plus nine projections 2 Complement error data. The results are limited in the range 0 to 255 and sent to the next block. Note Italy, this data limitation also applies to all internal coded data, including in JPEG.

The predictive adder of the present invention also includes a body. It comes from the FIFO is used to detect Data from the prediction filter to a mismatch between the data. Theoretically, from filter The amount of data to be predicted from the FIFO contains data to correspond exactly to the number of tokens. In severe The event of failure, padder will attempt to compensate.

From the FIFO and filters to the end of data blocks, respectively, with in-extn and fl-last input Entry to identify. When the filter end of the data stream in the data token is detected before the end of When the remainder of the token continues to the output unchanged. On the other hand, if the filter block Scores According to the token length, the input is stopped until all the excess filter genetic data has been accepted Abandoned so far.

In the FIFO or predicted no peeking adder unit. Because the chip is configured to be able to make Data from the token input port directly to these blocks, and their output directly to the The token output port. B.12.5 write pointer and the read pointer B.12.5.1 write pointer (wrudder)

Write pointer all tokens from the predictive adder to the read pointer. It also transfers I or P picture in MPEG, all data blocks, and all data blocks in H.261 to the DRAM access Mouth, so that these data address generator block can be written under the control of the external frame memory Makers. All the main functions are included in a two-wire interface level, although the data is written back to the DRAM interface of the way through a glimpse into the device.

Write means for decoding the following tokens:

Table B.12.3 decoded by the write pointer token

Token name	Write pointer function
		CODING_STANDARD	JPEG streams prohibition on write-back
PICTURE_TYPE	I and P frames only in the write back, B frames are not written back
		DATA	Only the data in the token data is written back to the

The data after the token header is detected, all data bytes are output to the DRAM interface. In_extn going low indicates that the data with the end token has been detected. This gives a filled (flu- sh) signal to the DRAM interface alternating buffers. Under normal operating conditions, which both How alternating with alternating moments of the buffer is consistent, but if the data token does not contain 64 Bytes of data, this provides a recovery means (although subsequent pieces of an output image is rarely May not be correct). B.12.5.2 read pointer (rrudder)

The invention of the read pointer has three functions, the two main functions of which relates to the Image sequence in MPEG reordering:

1) from the external frame memory has been read-back data, the token stream at the correct insert.

2) of the I and P pictures in the reordering of the image header information.

3) a method of detecting FLUSH token, detection of the end of the token stream (see Section B.12.1, "Top fork").

The read pointer 150 is shown in Fig. Entire part is based on the standard two-wire interface technology Components. The input interface latches are decoded token, these decoders determine the components Work:

Table B.12.4 decoded by the read pointer token

Token name	Read pointer function
		FLUSH	Signal to the top fork
CODING_STANDARD	If decoding standard is not MPEG, prohibit heavy Sequence
		SEQUENCE_START	Reorder columns on the first image read back The data is invalid
PICTURE_START	Signaled the current output FIFO must Exchange (I or P picture). Picture header of the first token
		PICTURE_END	Image layer above all tokens allow through Cross
TEMPORTAL_REFERENCE	The second picture header tokens
		PICTURE_TYPE	The third picture header tokens
DATA	When reordering, the contents of the data token Was traded to re-sort the data

Reordering function is performed by the microprocessor interface may be, but if not MPEG encoding standards were Disabled, regardless of the state register. With an MPI address generator control register Whether to generate a reordering address. So, reordering is output from this block. To the How to interpret the pointer work, to consider the input and output logic. Remember, the token sequence As shown below:

·CODING_STANDARD

·SEQUENCE_START

·PICTURE_START

·TEMPORAL_REFERENCE

·PICTURE_TYPE

·Picture containing DATA Tokens and other tokens

·PICTURE_END

...

·PICTURE_START

· ... B.12.5.2.1 input control logic

Start the beginning, all tokens into FIFO1 (called the current input FIFO) until Encounter I or P picture first PICTURE_TYPE token so far. Then becomes when FIFO2 Before the input FIFO, all input point to it, until the next I or P picture PICTURE_ TYPE is encountered so far, but FIFO1 turned into the current input FIFO. I and P picture, PICTURE_TYPE and PICTURE_END all tokens between the abandoned, except data token Outside. This is to prevent motion vectors, etc. in the reordering of the stream in contact with the wrong picture Together, the error where the original image does not make sense.

As a token stream into three yards FIFO, to indicate the presence of certain token header. This eliminates the need to complete the respective FIFO output token decoding. B.12.5.2.2 output control logic

Was started from FIFO1 receives the token (called the current output FIFO) until it encounters A picture start code so far. After this, FIFO2 becomes the current output FIFO. Return Referring to B.12.5.2.1 section, it can be seen, at this level, the three picture header tokens, PICTURE_START, TEMPORAL_REFERENCE and PICTURE_START remain in the FIFO 1. I or P frames in each encounter a picture start code, the current output FIFO is exchanged. Accordingly, the three picture header tokens are stored until the next I or P frames so far. Time, They will become re-sort the data with the correct information. B-picture does not re-ordered, and thus not Any token is discarded through. In the first graph, all tokens, including PICTURE_END, be abandoned. ...

Was started from FIFO1 receives the token (called the current output FIFO) until it encounters A picture start code so far. After this, FIFO2 becomes the current output FIFO. Return Referring to B.12.5.2.1 section, it can be seen, at this level, the three picture header tokens, PICTURE_START, TEMPORAL_REFERENCE and PICTURE_START remain in the FIFO 1. I or P frames in each encounter a picture start code, the current output FIFO is exchanged. Accordingly, the three picture header tokens are stored until the next I or P frames so far. Time, They will become re-sort the data with the correct information. B-picture does not re-ordered, and thus not Any token is discarded through. In the first graph, all tokens, including PICTURE_END, be abandoned. ...

In the present invention, the spatial decoder, temporal decoder and the video formatter, each This includes a special chip DRAM interface components. In all three devices, DRAM access The mouth of the function is from the chip to the external DRAM and from the external DRAM into the chip data transfer. Data Transmission is provided by the address generator for the block address.

DRAM interface is typically used clock work. This clock and the address generator and through several Between each block according to the clock is asynchronous, however, is easy to handle this asynchronous, because it These clock operates at about the same frequency.

DRAM interface and the data is typically rest of the chip in blocks of 64 bytes between the transmission (The only exception is the time decoder forecast data). Transmission occurs through a Called "alternate buffer" of the device. This is essentially a pair of double-buffered structure chasing Line pair of RAM. With the DRAM interface filling or emptying one RAM when another part of the chip Empty or fill out another RAM. A portable generator from address to address the independence of total Lines connected with each alternate buffer.

Each chip has four alternate buffer, but in each case, the alternate buffer The functions are different. In the space decoder, an alternate buffer used to transmit coded Data to the DRAM, another to read coded data from the DRAM, the third token of data transmission To DRAM, while the fourth token read from DRAM data. The decoder at the time, one Alternate buffer used to write or predicted based image data to DRAM, the second read from the DRAM Take the base data or forecast data, the other two read forward and backward prediction data. In the video format Type of vessel, an alternate buffer is used to transfer data to the DRAM, the other three used from DRAM read data, i.e., reading light (Luminance) (Y), red and blue color difference data (respectively The Cr and Cb) in each one. ...

Each chip has four alternate buffer, but in each case, the alternate buffer The functions are different. In the space decoder, an alternate buffer used to transmit coded Data to the DRAM, another to read coded data from the DRAM, the third token of data transmission To DRAM, while the fourth token read from DRAM data. The decoder at the time, one Alternate buffer used to write or predicted based image data to DRAM, the second read from the DRAM Take the base data or forecast data, the other two read forward and backward prediction data. In the video format Type of vessel, an alternate buffer is used to transfer data to the DRAM, the other three used from DRAM read data, i.e., reading light (Luminance) (Y), red and blue color difference data (respectively The Cr and Cb) in each one. ...

Such as described in Section B.13.1, time decoder has four alternate buffer: two with To read and write decoded and the predicted base (I and P) picture data. These buffers Operating as described above. The other two used to take forecast data.

Such as described in Section B.13.1, time decoder has four alternate buffer: two with To read and write decoded and the predicted base (I and P) picture data. These buffers Operating as described above. The other two used to take forecast data....

In the address generator, the frame pointer, base block address and vector offset add up to Taken from the DRAM block address. If the pixel offset is zero, only one request generated. If the two dimensions in the x or y has an offset in one, two requests is generated - the original block Address and immediately to the right or down immediately both an address. x and y are both a When the offset is generated four requests. Each block you want to take, calculated from the address generator Start and stop address parameters and these parameters to the DRAM interface. These start and stop to Site using best examples, are summarized as follows:

Consider a pixel offset of (1,1), as shown in the shaded area 152 shown in Figure 26. Ground Address generator resulting in four requests, labeled A in the figure-D. Problem to be solved is how to Quickly provide the required sequence of row address. The solution is to use the "Start / Stop" Technologies. Described as follows:

Consider block A in Figure 152. Must start position (1,1) to start reading to position (7,7) Results Beam. Suppose now that is a read one byte (i.e. an 8-bit DRAM interface). Coordinate The x value of the formation of the three least significant bits of the address, y values ​​to form the three most significant bits. x And the initial value of y is 1, the address given 9. From address read from the data, x value increases. This A process is repeated until the x value reaches its stop value. At this point, y value increases 1, x from Start value is reloaded into a given address 17. Because each byte of data is read, x value Also increases until it reaches its stop value. This process is repeated until the x and y values ​​are Have reached their stop values. Thus, the address sequence 9,10,11,12,13,14, 15, 17, ......, 23, 25, ......, 31, 33, ......, ......, 57, ......, 63 is generated. ...

Consider block A in Figure 152. Must start position (1,1) to start reading to position (7,7) Results Beam. Suppose now that is a read one byte (i.e. an 8-bit DRAM interface). Coordinate The x value of the formation of the three least significant bits of the address, y values ​​to form the three most significant bits. x And the initial value of y is 1, the address given 9. From address read from the data, x value increases. This A process is repeated until the x value reaches its stop value. At this point, y value increases 1, x from Start value is reloaded into a given address 17. Because each byte of data is read, x value Also increases until it reaches its stop value. This process is repeated until the x and y values ​​are Have reached their stop values. Thus, the address sequence 9,10,11,12,13,14, 15, 17, ......, 23, 25, ......, 31, 33, ......, ......, 57, ......, 63 is generated. ...

The next question is where to write the data should be. Obviously, look at the A block read from address 9 The data should be written to take the address of the alternate address 0,0 buffer. Number read from address 10 It should be written to the address buffer 15 alternately, and so on. Similarly, from the B-block address 8 Reading The data should be written to the alternate address buffer 15, from address 16 should be written to read-out data exchange For buffer address 15. This operation finally have a very simple implementation, as outlined below.

The next question is where to write the data should be. Obviously, look at the A block read from address 9 The data should be written to take the address of the alternate address 0,0 buffer. Number read from address 10 It should be written to the address buffer 15 alternately, and so on. Similarly, from the B-block address 8 Reading The data should be written to the alternate address buffer 15, from address 16 should be written to read-out data exchange For buffer address 15. This operation finally have a very simple implementation, as outlined below....

The next question is where to write the data should be. Obviously, look at the A block read from address 9 The data should be written to take the address of the alternate address 0,0 buffer. Number read from address 10 It should be written to the address buffer 15 alternately, and so on. Similarly, from the B-block address 8 Reading The data should be written to the alternate address buffer 15, from address 16 should be written to read-out data exchange For buffer address 15. This operation finally have a very simple implementation, as outlined below....

External DRM access	Swing buffer The address of	External DRAM address (Binary)	Alternately buffer to Address (binary)
				9＝y-start， X-start	0＝y-stop， x-stop	001001	000000
10	1	111110	000001
				11	2	001011	000010
15	6	001111	000110
				17＝y-1， X-start	8＝y+1  x-stop	010001	001000
18	9	010010	001001

So far the discussion has focused on 8-bit DRAM interface. For 16-bit or 32-bit interface, Must make minor modifications. First, the pixel offset vector must be "limited" (clipped), It points to the 16 or 32 edges. In the example we have been using, for block A, Start DRAM read will point to address 0, the addresses 0 to 3 of the data will be read. Now, do the Data must be abandoned. All data is written to the buffer and add alternately offset to read Take, you can do that. (Alternating current than the physical buffer of 8 bits are necessary To be bigger). MPEG as a half-pixel interpolation method, in the x and / or y direction must be connected from the DRAM I read 9 bytes. In this case, the address generator provides the appropriate start and stop addresses, DRAM interface of some additional logic is used. But the DRAM interface works without Fundamental changes. ...

So far the discussion has focused on 8-bit DRAM interface. For 16-bit or 32-bit interface, Must make minor modifications. First, the pixel offset vector must be "limited" (clipped), It points to the 16 or 32 edges. In the example we have been using, for block A, Start DRAM read will point to address 0, the addresses 0 to 3 of the data will be read. Now, do the Data must be abandoned. All data is written to the buffer and add alternately offset to read Take, you can do that. (Alternating current than the physical buffer of 8 bits are necessary To be bigger). MPEG as a half-pixel interpolation method, in the x and / or y direction must be connected from the DRAM I read 9 bytes. In this case, the address generator provides the appropriate start and stop addresses, DRAM interface of some additional logic is used. But the DRAM interface works without Fundamental changes. ...

· A "last byte" signal indicating the last byte of a transmission (64, 72 or 81 bytes)

· An H.261 logo

· A bidirectional prediction flag

· With two specified block size (in the x and y directions are 8 or 9 words)

· Digit indicates the order of each block

The last byte of data from the alternate identity can buffer readout produce. Other signals Obtained from the address generator, DRAM interface through the conveyor, so that they are the correct data Block linked. This is because the data is to use a prediction filter assembly from the alternating readout buffer. B.14 UPI File B.14.1 Introduction

This document intended to give the reader microprocessor interface of the present invention have an understanding of the work. UP interface and the spatial decoder and temporal decoder interface is basically the same, the only difference Do is the number of address lines.

Pure logic described here is a microprocessor internal logic. The circuit is:

  UPI

  UPI101

  UPI102

  DINLOGIC

  DINCELL

  UPIN

  TDET

  NONOVRLP

  WRTGEN

  READGEN

  VREFCKT

Circuit UPI, UPI101, UPI102 difference is that there are seven UPI101 address input, Section 8 of its total ground, while there are eight UPI and UPI102 address input,

Input / output signals

The signal described here is one pairs UPI module list of all inputs and outputs (output Into, the output is defined with respect UPI). Described in detail in the table of the source of these signals Or destination:

NOTRSTINPUT Glolal chip reset, active low, from the temporary (Pad) lose Come into the drive.

E1InputEnable signal 1, active low, from the temporary (Pad) input driver (Schmitt) to.

E2InputEnable signal 2, active low, from the temporary (Pad) input driver (Schmitt) to.

RNOTWInputRead not write signal from the temporary (Pad) input driver (Schmiff) Come.

ADDRIN [7:0] Input address bus signals, from the temporary (Pad) input driver (Schmitt) to.

NOTDIN [7:0] Input1 input data bus from the bi-directional data pin microprocessor (TTLin) of the input buffer (Pad) drives.

INT_RNOTWoutput internal read not write signal to the microprocessor interface to access the Internal wiring (see memory map).

INT_ADDR [7:0] OutPut internal address bus to access the microprocessor interface All the lines (see memory map).

INTDBUS [7:0] Input / output internal data bus, connected to the microprocessor Port access all the lines (see memory map), and the microprocessor data output pads. Internal data bus data transfer, the data on the chip pin opposite (inverse).

READ_STROutputAn is an internal timing signal, which indicates the device memory Figure one unit in a read.

WRITE_STROutputAn is an internal signal that indicates the internal memory graph Write-once one unit.

TRISTATEDPADOutputAn is an internal signal, connected to the microprocessor data Output pad, which indicates that they should be tri-stated.

Total comments:

UPI schematics containing six smaller modules: NONOVRLP, UPIN, DINLOGIC, VREFCKT, READGN, WRTGEN. It should be noted that from the total signal on the table, in addition to the microprocessor Processor bus timing signals, not related to the interface with the microprocessor clock signal. Total Line timing signal to all the other timing signals on the chip is asynchronous. Therefore, in addition Those that can be externally controlled by a timing other than forcing the microprocessor operation and other equipment No timing relationship between the parts. For example, when on a test system to access the microprocessor interface At the same time, stopping the external system clock.

UPI another meaning there is no clock timing of some of their own internal arrangements. On Is to say, some of the signal components of the UPI is internally controlled delay.

The total UPI function fetch address data from the outside world, enable and read / write signal, and The format of these signals, so that they can drive the internal circuits correctly. Define the memory Figure accessing internal signal is INT_RNOTW_INT_ADDR [...], INTDBUS [...] and READ_STR and WRITE_STR. For a read cycle and a write cycle, when these signals Expressed in the following order relation. It should be noted that although the datasheet definition and the following diagram generally form Shows a chip enable cycle, the circuit operation is such that: an enable signal can be kept low, Address can be recycled to do sequential read operation or write operation. Because addresses turn into lines, This function is possible. ...

The total UPI function fetch address data from the outside world, enable and read / write signal, and The format of these signals, so that they can drive the internal circuits correctly. Define the memory Figure accessing internal signal is INT_RNOTW_INT_ADDR [...], INTDBUS [...] and READ_STR and WRITE_STR. For a read cycle and a write cycle, when these signals Expressed in the following order relation. It should be noted that although the datasheet definition and the following diagram generally form Shows a chip enable cycle, the circuit operation is such that: an enable signal can be kept low, Address can be recycled to do sequential read operation or write operation. Because addresses turn into lines, This function is possible. ...

In a read cycle, the internal data bus is pre-charged to high, it also has a pull-up Resistance, so for the extended period, when the internal data bus is not being driven, it will default Is 0 × FF state. Because the internal data bus and the data on the pin is inverted when it Are enabled when this pin to the outside into the 0 × 00. This means that if any External cycle accesses a register or registers of an (This register is a memory graph No signal region), the output data is determined, and is low.

Line Details:

UPIN-

This circuit is the total change detecting part. It contains a sub-circuit called TDET. TDET a single bit change detection circuit. For each address bit and rnotw signals, and each An enable signal, UPIN has a TDET module. UPIN also contains some combinatorial logic, Each of the change detection circuit output gates together. The gate logic signal generated Numbers are as follows:

TRAN-show on the input signal a transition (transition).

UPD-DONE-indicates some change has been completed, a cycle can be performed.

CHIP_EN indicates that the chip has been selected.

TDET-

This is the single bit change detection circuit. It contains two latches and two XOR gates. Used first latch signal SAMPLE timing, the second time with the signal UPDATE. Both Non-overlapping signals are coming from the module NONOVRLP. General operation is such that an input Into the shift causes a CHANGE, in turn causing SAMPLE. When the SAMPLE is high, all Input change is accepted. When the input change is stopped, then CHANGE goes low and SAMPLE Low, which caused UPDATE becomes high. Then transfer data to the output latch and show UPD_ DONE.

NONOVRP-

This line is basically a non-overlapping clock generator, it will TRAN input, and Produce SAMPEL and UPDATE. The UPDATE output, the external control becomes blocked UPDATE High until a write pulse has been completed.

DINLOGIC-

This module contains the eight data input circuit DINCELL case and the drive TRISTAT- EPAD signal some doors. This indicates that the output data port only in the following circumstances before driving, Enable1 is low, ENable2 is low, RnotW is high and the internal read_str is high.

DINCELL-

This line includes a data input latches and a driver internal data bus tristate Drive. When the signal DATAHOLD is high, and both low Enable1 and Enable2 When the data from the input pad to be latched. INT-RNOTW whenever the internal signal is low, Three-state driver to drive the internal data bus. Internal data bus precharge pair of transistors, the total Line pull element (pullup) is also included in this module.

WRTGEN-

This module generates WRITE_STR, and a latch signal DATAHOLD, which is the number According to latch transparencies. Write strobe is a self-timed signal, however, the delay from the scheduled time Determined in the VREFCKT. Timing Line RESETWRITE output is used to terminate WRITE_STR signal. It should be noted that the actual write pulse write register in only one visit Period after the end of production. This is because the data input to the chip is only the trailing edge in the cycle is Sampled. Therefore, only a normal access cycle has ended after the data is valid.

READGEN-

This line, as its name suggests, produces READ_STR signal. It also generates PRECH signal which is used to pre-charge the internal data bus. PRECH signal is a The self-timed signal, which depends on the period of VREFCKT, also take the block to the internal data bus Voltage. READ_STR not a self-timed, but the pre-charge cycle is complete, has been Extended to the end of the cycle so far. A precharge circuit inverter, their conversion characteristics are Offset such that they require an almost inverted phase front 75% of the power supply voltage. This Circuits that in READ_STR before the start of the internal bus is correctly precharged. To To prevent the internal bus has been precharged case PRECH pulse width tends to zero, given When the line through the signal RESETREAD guarantee a minimum width. ...

VREFKCT-

This line, as its name suggests, produces READ_STR signal. It also generates PRECH signal which is used to pre-charge the internal data bus. PRECH signal is a The self-timed signal, which depends on the period of VREFCKT, also take the block to the internal data bus Voltage. READ_STR not a self-timed, but the pre-charge cycle is complete, has been Extended to the end of the cycle so far. A precharge circuit inverter, their conversion characteristics are Offset such that they require an almost inverted phase front 75% of the power supply voltage. This Circuits that in READ_STR before the start of the internal bus is correctly precharged. To To prevent the internal bus has been precharged case PRECH pulse width tends to zero, given When the line through the signal RESETREAD guarantee a minimum width. ...

Image format according to the present invention, the structure shown in Figure 155, there are used for Two write and read address generator, the address generator and provides management of two frame rate conversion of Buffer manager, a data processing pipeline, including both vertical and horizontal oversampling Injector (upsamplers), the color space converter, and gamma correction, as well as an adjustment process The final output line control block. C.1.2 Buffer manager

Image format according to the present invention, the structure shown in Figure 155, there are used for Two write and read address generator, the address generator and provides management of two frame rate conversion of Buffer manager, a data processing pipeline, including both vertical and horizontal oversampling Injector (upsamplers), the color space converter, and gamma correction, as well as an adjustment process The final output line control block. C.1.2 Buffer manager...

Whenever the read address generator system receives from the display VSYNC signals, according to the new display Display buffer means for forming a request to the buffer manager. If a buffer contains the complete The image data and the image that has been prepared for the display, then the buffer pointer Will be sent to the display address generator, otherwise send buffer manager is displayed on the last Buffer pointer. At the beginning of the work, the zero is transmitted as a pointer until the first buffer Is full.

If the image number (calculated for each image input) is greater than or equal to a given coding frame Display (presentation number) when the number of the desired image, an image is ready to display it. The desired number of clock pulses by the count value of the image is determined, the image clock or The clock divider formed outside or generated locally, this technology allows the frame rate conversion (Such as 2-3 pull-down).

External DRAM is used as a buffer, this buffer may be two in number or 3, to achieve frame rate conversion requires three buffers. C.1.3 write address generator

Write address generator receives a token from the buffer manager and detect each new data token To arrive. When each data token arrives, the address generator for the calculation of a new DRAM interface Address storage block arrives, the original data is then transmitted to DRAM interfaces for Miles Data is written to the alternate buffer. Note that DRAM address block address and the DRAM IN Organized by the raster blocks like. However, the input image data is actually organized sequences of macroblocks, So the address generation algorithm for macroblock lower row of blocks must consider the line width (in blocks count) Offsets.

Provided by the buffer manager reaches the buffer pointer is stored in the map for the Like the address offset, and that each component in the specified buffer is stored in a separate area Storage, so also used in the calculation component offsets. C.1.4 read address generator

Read address generator (dispaddr) does not accept or generate tokens, it generates addresses only, Response VSYNC, it can be based field_info, read_start, Sync_mode and lsb _invert request buffer from the buffer manager pointer when receiving a pointer which Three address sets are formed, each corresponding to a component, in order to read out the current raster map Elephant. Allows different set: interlaced / progressive display and / or data, vertical not sampled, and Vertical sync (for interlaced display). At a lower level, the read address generator of the transfer base address Block address into order, and each of the three components of the byte count in the same DRAM page Structure compatible to the address of DRAM interface block start and end of the block with a page count And the row address. C.1.5 output pipeline ...

Read address generator (dispaddr) does not accept or generate tokens, it generates addresses only, Response VSYNC, it can be based field_info, read_start, Sync_mode and lsb _invert request buffer from the buffer manager pointer when receiving a pointer which Three address sets are formed, each corresponding to a component, in order to read out the current raster map Elephant. Allows different set: interlaced / progressive display and / or data, vertical not sampled, and Vertical sync (for interlaced display). At a lower level, the read address generator of the transfer base address Block address into order, and each of the three components of the byte count in the same DRAM page Structure compatible to the address of DRAM interface block start and end of the block with a page count And the row address. C.1.5 output pipeline ...

Basically there are two timing modes formatter associated with the image, the first one is the system Clock, which clock the chip front (address generators and buffer manager, plus the DRAM access The mouth end) provides timing, the second is the pixel clock, which clock is back with all Timing (DRAM interface output and all output lines).

% E4% B8% 8A% E8% BF% B0% E4% B8% A4% E7% A7% 8D% E6% 97% B6% E9% 92% 9F% E5% 9D% 87% E9% A9% B1% E5 % 8A% A8% E4% B8% 80% E4% BA% 9B% E8% 8A% AF% E7% 89% 87% E4% B8% 8A% E7% 9A% 84% E6% 97% B6% E9% 92 % 9F% E5% 8F% 91% E7% 94% 9F% E5% 99% A8% E3% 80% 82FIFO% E3% 80% 81% E7% BC% 93% E5% 86% B2% E5% 99% A8 % 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E7% AE% A1% E7% 90% 86% E5% 99% A8% E5% 8F% 8A % E8% AF% BB% E5% 9C% B0% E5% 9D% 80% E5% 8F% 91% E7% 94% 9F% E5% 99% A8% E7% 94% A8% E5% 90% 8C% E4 % B8% 80% E6% 97% B6% E9% 92% 9F (D% CF% 86)% E5% B7% A5% E4% BD% 9C% EF% BC% 8C% E5% 86% 99% E5% 9C% B0% E5% 9D% 80% E5% 8F% 91% E7% 94% 9F% E5% 99% A8% E7% 94% A8% E5% 90% 8C% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E4% B8% 8A% E7% 9B% B8% E4% BC% BC% E7% 9A% 84% E4% BD% 86% E7% 8B% AC% E7% AB% 8B% E6% 97% B6% E9% 92% 9FW% CF% 86% E3% 80% 82% E6% 95% B0% E6% 8D% AE% E7% 94% A8% E5% 86% 85% E9% 83% A8% E7% 9A% 84DRAM% E6% 8E% A5% E5% 8F% A3% E6% 97% B6% E9% 92% 9F (out% CF% 86)% E8% A2 % AB% E5% 90% 8C% 0A% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% E6% AD% A5% E8% BF% 9B% E5% 85 % A5DRAM% E6% 8E% A5% E5% 8F% A3% E5% 86% 85% EF% BC% 8CD% CF% 86% E3% 80% 81W% CF% 86% E5% 92% 8Cout% CF% 86 % E5% 9D% 87% E7% 94% B1SYSCLK% E7% 94% 9F% E6% 88% 90% E3% 80% 82

Read and write addresses DRAM interface through its own clock within the DRAM interface is clocked.

Data from the DRAM interface bifRφ read out and transmitted to the called "bushy_ ne "portion of the output lines (its physical location in the northeast) by NE when expressed Clock operation, the pipeline from the gamma RAMS forward partly independent but the same clock Rφ Timing. bifRφ, NEφ and Rφ are taken from the pixel clock pixin.

For testing, all of the major interfaces between blocks with super peeking peeking or device. It depends on timing mode and the required access type. Separated from each other but there are the same as for regular There are ways retiming latch block boundary associated with it. C.2 buffer management

According to the present invention, a buffer management block is to provide an address generator, which Address generator with a pointer identifies two or three external buffers are used to image data Read and write. These pointers allocated by three main factors. Each factor represents the workers As in the role of a timing mode. These factors refer to the image data arrives image output formatter Into the end of the velocity (coded data rate), the data display speed (display data rate), and Frame encoded video sequence (presentation rate (presentation rate)). C.2.2 Functional Overview

A three-buffer system allows the presentation rate and the display rate of the type (such as 2-3 pull-down), Therefore, the frame rate by the system timing constraints, when necessary to obtain the best possible sequence of frames, you can By using repeated frames or skipping. Presents certain difficulties in decoding the image also can follow the class Similar solutions. Therefore, when the image decoding takes longer than the display time can be longer When busy, while the other things, the previous frame will be repeated. In the double buffer system , The three timing modes must lock - precisely because it occupies the first three buffers gap (taking up slack) thus providing flexibility.

By keeping the buffer manager associated with each of the external buffer some status information Interest to work. This information includes information indicating whether the buffer is used for a variety of tags, the data Is full, the display is ready, the image of the image sequence number is stored in the current Buffer. No records were also presented. Each time a picture clock pulse is received, this number Is increased, and that number is based on the coding sequence image frame rate to display the current desired Image number.

At the input, each detected PICTURE_START token, to allocate an arrival Buffer (data will be written into a buffer). Then, this buffer is marked Note, in use. In PICTURE_END reached when the buffer is deallocated (set to zero) And based on the image number and the number showing the relationship between the buffer is marked as full (FULL) or prepare Good (READY).

Each VSYNC, via two-wire interface display address generator requests a new display buffer. If buffer tag ready by the buffer manager then assigns this buffer is allocated To show. If there is no READY (ready) buffer, the buffer will be displayed in front of heavy Complex to show.

Whenever the number showing the change is detected, according to the READY_ness right contains the complete image Each of the buffers tested. This test is done by checking the image number and the presentation number The relationship between the. Buffers are considered in turn. When the buffer is considered to any one of Ready (READY), it automatically cancels any previous mark READY buffer READY_ ness. On the flag in front of an empty buffer (EMPTY). This is useful, because the root According to the allocation scheme, followed by the image number is stored in the buffer, which is considered later.

If the input stream to skip the image is indicative of the in H.261 TEMPORAL_ REFERENCE token number of the image within the buffer is modified. Although this feature as we Desired, and the current are not included. Similarly, in MPEG TEMPORAL_REFERENCE Token no effect.

FLUSH token of the input stop until each buffer is empty or used as display buffer Has been allocated. Then, showing the number and the image number is reset and starts a new sequence. C.2.3 Structure C.2.3.1 Interface C.2.3.1.1 Interface to bm_front

All data from the FIFO, bm_front input to the buffer manager. By-wire connection Mouth produces transmission, data width is 8 bits plus an extension. Arrival of the buffer manager The data is guaranteed to be a complete token. If the upper end of the data stream has obvious gaps occur, they need To continue processing presents numbers and display buffer requests. C.2.3.1.2 to waddrgen (write address generator) interface

Token (8-bit data, an extension bit) via two-wire interface is transferred to the write address generator Makers. Also spread to reach the same buffer pointer interface to enable the PICTURE_START Token arrives at the same time as the write address generator generates can get the correct address pointer. C.2.3.1.3 Interface to dispaddr

The interface to the read address generator comprises two separate two-wire interface, they were watching As is from the "request" and "reply" signals of the one-line is not sufficient, because in 2 End are based on two-lane state agency.

In general, the same dispaddr following sequence of events related to the interface. First, dis_ paddr through identified drq_valid, response from the display device to the VSYNC, issued a Request input to the buffer manager. Second, when the buffer manager state machine in its Obtain a suitable point, receives the request and assign a buffer for display. Then, disp_Valid line has been identified, the buffer pointer is transferred and typically immediately dispaddr Received. Moreover, there is a two-wire interface with the last (rst_fld) For additional lines, It indicates the current pointer associated with the field number must be reset, regardless of the number of previous games. C.2.3.1.4 Microprocessor Interface

The buffer manager block uses a 4-bit address space of the microprocessor and the 8-bit data bus And read-write strobe. There are two select signals, one for the user can access unit, and the other Under normal operating conditions, that do not require access to the test unit. C.2.3.1.5 event

Buffer manager can produce two different events: Pointer to find and delayed arrival. Section An event, and when the image reaches its PICTURE_START expansion byte (image pointer) with When set register values ​​written BU_BM_TARGET_IX match is confirmed. The second event Occurs when the display buffer is allocated and it is less than the current number of images showing number, The pipeline in system by the process performed by the buffer manager, without trying to keep significant Display requirements. C.2.3.1.6 image clock

In the present invention, showing the number of image clock counter as a clock signal, which either Is generated from the chip, or from an external source (standard display system). The buffer manager receives These two signals and under Pclk_ext (buffer manager's control register A) Select one of the values ​​of a. This signal can be used as a temporary picutpad enable signal. Therefore, if the image format is generating its own picture clock, this signal can be As the output signal of the chip. C.2.3.2 The main functional blocks

The following section describes the composition of the buffer manager schematic (bmLogic) of individual hardware Function blocks. C.2.3.2.1 Input / Output block (bm input)

This module includes a buffer manager, all the four-wire interface hardware (Input and output data, drq_valid / receiving and disp_valid / Receive). Enter Connected to the data register with some token decoding hardware is displayed. Input to bm_ tokdee signal on vheader, ensure that the decoder output token in the header that only punctuation Valid (ie, not in the middle of the token). rtinmd block as output data register, and the flow Under a waterline in the double (duplicate) adjacent to the input data register. This is for Consider different clock generator cause timing differences. Signal "go" and "ngo" is based on the Receive data valid and non-stop phase (AND), and used elsewhere in the state machine in Table Indicates whether something in the input or output "plug (bunged up)". ...

This module includes a buffer manager, all the four-wire interface hardware (Input and output data, drq_valid / receiving and disp_valid / Receive). Enter Connected to the data register with some token decoding hardware is displayed. Input to bm_ tokdee signal on vheader, ensure that the decoder output token in the header that only punctuation Valid (ie, not in the middle of the token). rtinmd block as output data register, and the flow Under a waterline in the double (duplicate) adjacent to the input data register. This is for Consider different clock generator cause timing differences. Signal "go" and "ngo" is based on the Receive data valid and non-stop phase (AND), and used elsewhere in the state machine in Table Indicates whether something in the input or output "plug (bunged up)". ...

A small amount of additional circuitry, they are associated with the input data register, this register the Now another higher level. This circuit generates a signal which represents the input data Register includes a write BU_BM_TARGIX equal value, and which circuit is also used to generate Health events. C.2.3.2.2 pointer blocks (bm index)

Pointer blocks mainly represent various key buffer pointer two registers. It We are arr_buf, in this buffer reaches the image data written in, disp_buf, From this buffer the read image data to display it, and rdy_buf, that includes the latest A pointer to the image buffer, if the buffer is dispaddr requested, the image is displayed. There is a register that contains buf_ix, it is used as a generic pointer pointing to the buffer. This Registers to give a delta ("D" input to multiplexer), through the buffer cyclically Test their state, that is when the state needs to change, you can get arr_buf, disp_buf or rdy_buf a value. So these registers (Ph0 type) can From the microprocessor as a test portion of the address space is accessed. old_ix just buf_ ix retiming program, which is enabled to indicate the state of the buffer block and the bm_stus The elephant number register. buf_ix and old_ix Both are decoded into three signals (each holding A value of 1 to 3) of these signals output from these blocks. Other output indicates whether buf_ix has Arr_buf or disp_buf with the same values, whether rdy_buf and disp_buf both have Value of zero. Zero is not a reference value for the buffer. It only means currently not allocated to achieve / Explicit Show / ready buffer. ...

Pointer blocks mainly represent various key buffer pointer two registers. It We are arr_buf, in this buffer reaches the image data written in, disp_buf, From this buffer the read image data to display it, and rdy_buf, that includes the latest A pointer to the image buffer, if the buffer is dispaddr requested, the image is displayed. There is a register that contains buf_ix, it is used as a generic pointer pointing to the buffer. This Registers to give a delta ("D" input to multiplexer), through the buffer cyclically Test their state, that is when the state needs to change, you can get arr_buf, disp_buf or rdy_buf a value. So these registers (Ph0 type) can From the microprocessor as a test portion of the address space is accessed. old_ix just buf_ ix retiming program, which is enabled to indicate the state of the buffer block and the bm_stus The elephant number register. buf_ix and old_ix Both are decoded into three signals (each holding A value of 1 to 3) of these signals output from these blocks. Other output indicates whether buf_ix has Arr_buf or disp_buf with the same values, whether rdy_buf and disp_buf both have Value of zero. Zero is not a reference value for the buffer. It only means currently not allocated to achieve / Explicit Show / ready buffer. ...

In bmLogic additional circuitry layer is used to determine whether the current buffer pointer (buf_ix) Equal to the maximum use of the pointer as defined, and its value is written to the control register set The. Control register is "1" indicates triple buffering system, the value "0" indicates that two buffers System. C.2.3.2.3 buffer status

The main part of the buffer state of each buffer status and picture number register. Three groups each group is the master-slave mode arrangements register bank from the register is 3, the main register is Single register, this register is output from the register of a point (through old_ix use Register Enable). A possible to the main register input is the output from the register of Multiplexing of distribution obtained (in the buf_ix bmLogic level index). Buffer state in bmLogic stage is decoded. Preferable to use a state machine logic shown in Table C.2.1 any value Or loop its previous value. In front of the image number value or desirability of increasing the value of the previous one (or a plus δ, if it is normal, and hope time H.261 baseline is different). This value is determined by in Block 8 adder provided. The first input to this adder is this_Pnum, current The image data written number. ...

The main part of the buffer state of each buffer status and picture number register. Three groups each group is the master-slave mode arrangements register bank from the register is 3, the main register is Single register, this register is output from the register of a point (through old_ix use Register Enable). A possible to the main register input is the output from the register of Multiplexing of distribution obtained (in the buf_ix bmLogic level index). Buffer state in bmLogic stage is decoded. Preferable to use a state machine logic shown in Table C.2.1 any value Or loop its previous value. In front of the image number value or desirability of increasing the value of the previous one (or a plus δ, if it is normal, and hope time H.261 baseline is different). This value is determined by in Block 8 adder provided. The first input to this adder is this_Pnum, current The image data written number. ...

Buffer Status	Value
		Air
	00
		Full	01
Ready	10
		In the use of	11

This requires a separately stored (in its own master-slave register arrangement) to enable the three Buffer any picture number register easily adjust the current (or previous) Fig Like a number instead of an image based on their own previous number (this number is almost always out of date) Updated. this_Pnum reset to -1 so that when the first picture arrives it from the adder The outputs are summed, therefore, the input to the first buffer picture number register is zero.

In the current version is worth noting that because of lack of time reference values ​​provided δ Block, δ link to zero. C.2.3.2.4 show number

8 showing the same rendering tag number register combined with that presented in the state machine number In its previous examination has been changed, it is necessary, because the picture clock is essentially Asynchronous and valid for the duration of any state, not limited to those relating to the present number of states. In this The remaining circuit blocks for the detection of the image clock pulse has occurred, and "memory" These facts. This method renders a number can be changed when it is updated. Figure 156 were Represents the sequence of events illustrated. In re_timed image clock rising edge, the signal incr_prn A valid period, and continued until the arrival of the state, in this state number is modified during rendering. This is expressed by the signal en_Prnum. About the only allowed in some states during the present number of modifications The reason is because it is a large number of user-driven logic, including standard cells, the block is not very 8-bit adder, which provides a signal adder rdyst. Therefore, it must be in successive Using this result, the state is not changed during the state. C.2.3.2.5 time basis ...

8 showing the same rendering tag number register combined with that presented in the state machine number In its previous examination has been changed, it is necessary, because the picture clock is essentially Asynchronous and valid for the duration of any state, not limited to those relating to the present number of states. In this The remaining circuit blocks for the detection of the image clock pulse has occurred, and "memory" These facts. This method renders a number can be changed when it is updated. Figure 156 were Represents the sequence of events illustrated. In re_timed image clock rising edge, the signal incr_prn A valid period, and continued until the arrival of the state, in this state number is modified during rendering. This is expressed by the signal en_Prnum. About the only allowed in some states during the present number of modifications The reason is because it is a large number of user-driven logic, including standard cells, the block is not very 8-bit adder, which provides a signal adder rdyst. Therefore, it must be in successive Using this result, the state is not changed during the state. C.2.3.2.5 time basis ...

The role of this is to calculate δ, H.261 data stream that is received in the token Between the reference value with the desired time basis (one plus the previous value) of the difference between. Province allowed in H.261 Skip some frames. Time reference all non-H.261 token stream is ignored. Calculated Is used in the calculation of the status block to buffer image number, the block is omitted from bmLogic its Affect the image at any sequence number is always continuous, even in the H.261 flow indication Some frames should be skipped.

The role of this is to calculate δ, H.261 data stream that is received in the token Between the reference value with the desired time basis (one plus the previous value) of the difference between. Province allowed in H.261 Skip some frames. Time reference all non-H.261 token stream is ignored. Calculated Is used in the calculation of the status block to buffer image number, the block is omitted from bmLogic its Affect the image at any sequence number is always continuous, even in the H.261 flow indication Some frames should be skipped....

As a buffer register, the control register in the presence bm_uregs block. They are Access bit register set register (define the maximum number of external buffers and internal / external Department of the image clock) and destination index registers. Access bit depending on the desired synchronization. Signal stopd_0, stopl_1 and nstopd_1 originated in the access bits and 2 stop bits or events. For all bmLogic the UPi address is decoded by block bm_udec completed, which takes a few UPi The lower 4 bits of the data bus, and the top level of the image format of the address decode select signal 2. C.2.3.2.7 control state machine

The state machine logic begins with its own block bm_state. Due to the formation of reason codes, it is now In the finishing and attributed to bmLogic schematic second.

This is the main part of the logic is the same. It includes a decoder for controlling other bmLog- ic signal generation logic block and the new state encoding, including the state machine used to select Path markers from_ps and from_fl. Each of the independent production block Dm_stns and Dm_index Health mux control signal.

In the state machine in hardware signal has been given names to simplify typing letters and inspection. It They are listed in the table C.2.2. As well as logical expressions representing them, they also make As comments appear in the characteristic M bmLogic description (bmLogic.M).

Table c.2.2 signal names for the state machine

Table c.2.2 signal for the state machine name (cont'd)c.2.3.2.8 δ monitoring operation (bminfo)

In the present invention, including the module bminfo, so the buffer status information, the pointer value and the Presented numbers can be observed during the simulation. It is written in M, and whenever its input Into one of the changes generated output. c.2.3.3 register address translation.

Buffer manager's address space is divided into two areas, the user can access area and test Areas. Therefore, there are two separate enable lines from the top decoded. Table c.2.3 displays user Access registers, Table c.2.4 display test space content.

Table C.2.3 user-accessible registers

Register Name Access Bit Reset State Function
	BU_BM_ACCESS 0x10 [0] 1 access bit buffer manager
BU_BM_CTLO 0x11 [0] 1 Max buf lsb: 1 → 3 buffers.0 → 2 [1] an external image clock selection
	BU_BM_TARGET_IX 0x12 [3:0] 0x0 image reaching the detector
BU_BM_PRES_NUM 0x13 [7:0] 0x00 render No.
	BU_BM_THIS_PNUM 0x14 [7:0] 0xFF Current picture number
BU_BM_PIC_NUM0 0x15 [7:0] none within the image buffer a number
	BU_BM_PIC_NUM1 0x16 [7:0] none buffer within the picture No. 2
BU_BM_PIC_NUM2 0x17 [7:0] none within the image buffer 3 No.
	BU_BM_TEMP_REF 0x18 [4:0] 0x00 time basis from streams

Table C.2.4 Test Register

Register name	Access	Position	Reset state	Function
					BU_BM_PRES_FLAG	0x80	[0]	1	Showing Markup
BU_BM_EXP_TR	0x81	[4∶0]	0xFF	Desired time reference
					BU_BM_TR_DELTA	0x82	[4∶0]	0x00	Incremental
BU_BM_ARR_IX	0x83	[1∶0]	0x0	Indexed bumper reached
					BU_BM_DSP_IX	0x84	[1∶0]	0x0	Display buffer index
BU_BM_ROY_IX	0x85	[1∶0]	0x0	Indexed prepare buffers
					BU_BM_BSTATE3	0x86	[1∶0]	0x0	3 state buffer
BU_BM_BSTATE2	0x87	[1∶0]	0x0	Buffer						2 Status
					BU_BM_BSTATE1	0x88	[1∶0]	0x0	Buffer		1 Status
BU_BM_INDEX	0x89	[1∶0]	0x0	Current buffer index
					BU_BM_STATE	0x8A	[4∶0]	0x00	State buffer manager
BU_BM_FROMPS	0x8B	[0]	0x0	From PICTURE_START To sign
					BU_BM_FROMFL	0x8C	[0]	0x0	Come from FLUSH_TOKEN Logo

C.2.4 state machine work

In the buffer manager state machine has 19 states, see Table C.2.5. The phase Interaction is shown in Figure 157 and described in Feature Description bmLogic.M.

Table C.2.5 Buffer Status

Status	Value
		PRES0	0x00
PRES1	0x10
		ERROR	0x1F
TEMP_REF0	0x04
		TEMP_REF1	0x05
TEMP_REF2	0x06
		TEMP_REF3	0x07
ALLCC	0x03
		NEW_EXP_TR	0x00
SET_ARR_IX	0x0E
		NEW_PIC_NUM	0x0F
FLUSH	0x01
		DRO	0x08
TOKEN	0x0C
		OUTPUT_TAIL	0x08
VACATE_RDY	0x17
		USE_RDY	0x0A
VACATE_DISP	0x09
		PICTURE_END	0x02

C.2.4.1 reset state

Reset state is PRES0, accompanied flag is set to zero, so that in the main loop initial Technology. C.2.4.2 main loop

Circulation path includes a state machine state is shown in FIG 153 (152 in FIG deepened in the main line), State PRES0 and PRES1 involving detection through a signal Presflg image clock. Right involved The test allows two cycles, since they are dependent on the value and rdyst are in C.2.3.2.4 Description adder output signal. If the marker is detected showing that all buffers are considered to be To "Ready", otherwise the state machine advances to state DRQ. Circulating around PRES0 ~ PRES1 Each cycle of the test a different buffer, checking full, and the ready state. If these Conditions are met, the previously prepared buffer (if one exists) is cleared, the distribution New ready buffer and update its status. This process is repeated until all the buffers Be detected (pointer == Max buf) then the state to continue. When any of the following is true When the buffer is considered ready for the show ...

(Pic_num＞Pres_num)&&((pic_num·Pres_num)＞＝128)

Circulation path includes a state machine state is shown in FIG 153 (152 in FIG deepened in the main line), State PRES0 and PRES1 involving detection through a signal Presflg image clock. Right involved The test allows two cycles, since they are dependent on the value and rdyst are in C.2.3.2.4 Description adder output signal. If the marker is detected showing that all buffers are considered to be To "Ready", otherwise the state machine advances to state DRQ. Circulating around PRES0 ~ PRES1 Each cycle of the test a different buffer, checking full, and the ready state. If these Conditions are met, the previously prepared buffer (if one exists) is cleared, the distribution New ready buffer and update its status. This process is repeated until all the buffers Be detected (pointer == Max buf) then the state to continue. When any of the following is true When the buffer is considered ready for the show ...

Or (Pic_num == pres_num.

Check the display buffer state DRQ request (drg_Valid_reg && disp_acc_ reg). If there is no request, the state of the token to the state advance normally - will be described below, whether Then, the display buffer pointer is given as follows, if there is no ready buffer, the previous finger Needle and then give. If there is no front display buffer to give a blank pointer (zero). If the buffer The display for the preparation, and its pointer is given its status is updated. If desired In front of the display buffer is cleared, the state machine as usual manner.

State tokens are typical for the completion of the main loop selection. If no valid input and output Failures, the token as a key value to be tested (described in a later section), otherwise control returns Back to state PRESO.

When certain conditions are met, the control only from the main loop. These instructions in the following sections. C.2.4.3 ready buffer pointer assignment

If the PRES0 ~ PRES1 cycle, a buffer is judged ready, because At any time in the buffer is specified only as a ready, any previous ready Buffer needs to abdicate. Status VACATE = RDY by setting its status VACANT And remove the original prepared buffers, and reset the pointer to a buffer, so that when the control Return to PRES0 state, all buffers will be ready for testing. The reason for this Is the current pointer to point out that the above-prepared buffer (for the purpose of clearing it) and And there is no record that we want to prepare a new buffer pointer. Therefore need to re-test all Buffers. C.2.4.4 display buffer pointer assignment ...

If the PRES0 ~ PRES1 cycle, a buffer is judged ready, because At any time in the buffer is specified only as a ready, any previous ready Buffer needs to abdicate. Status VACATE = RDY by setting its status VACANT And remove the original prepared buffers, and reset the pointer to a buffer, so that when the control Return to PRES0 state, all buffers will be ready for testing. The reason for this Is the current pointer to point out that the above-prepared buffer (for the purpose of clearing it) and And there is no record that we want to prepare a new buffer pointer. Therefore need to re-test all Buffers. C.2.4.4 display buffer pointer assignment ...

When receiving PICTURE_END token, control passes to state from the state TOKEN PICTURE_END. If the pointer does not point to the current arrival buffer is set to point to it State it can be updated. Assume out_acc_reg and en_full both are true, like State can be updated as described below, otherwise the control until it remains at PICTURE_END We both are true. en_full signal provided by the write address generator, which represents alternate buffer Device has been alternately. Preferably one that has been successfully written, so this is a security update buffer State.

When receiving PICTURE_END token, control passes to state from the state TOKEN PICTURE_END. If the pointer does not point to the current arrival buffer is set to point to it State it can be updated. Assume out_acc_reg and en_full both are true, like State can be updated as described below, otherwise the control until it remains at PICTURE_END We both are true. en_full signal provided by the write address generator, which represents alternate buffer Device has been alternately. Preferably one that has been successfully written, so this is a security update buffer State....

When PICTURE_START token in the state reached during TOKEN, marking from_ps be Settings to make changes in the basic state machine cycles to enable access to state ALLOC instead of state TOKEN. Involves the allocation of a state ALLOC arrive buffer (it can reach the image data is written) and The buffer loop until you find the one whose status is VACANT. If out_acc_reg high Level is assigned only a buffer so that it is output on the data two-wire interface. Accordingly, Cycle loop will continue until those conditions identified. Once you find a suitable buffer is reached, Pointer assigned to arr_buf, its status is marked as IN_VSE. Pointer is set to 1, Mark from_ps is reset, and the status is further provided to the NEW_EXP_TR. In Pointer image is formed on the check (included in the back of PICTURE_START immediately behind the words In) to determine whether it is associated with targ_ix same (in the assembly specified target pointer), If the same set_if ...⁺When PICTURE_START token in the state reached during TOKEN, marking from_ps be Settings to make changes in the basic state machine cycles to enable access to state ALLOC instead of state TOKEN. Involves the allocation of a state ALLOC arrive buffer (it can reach the image data is written) and The buffer loop until you find the one whose status is VACANT. If out_acc_reg high Level is assigned only a buffer so that it is output on the data two-wire interface. Accordingly, Cycle loop will continue until those conditions identified. Once you find a suitable buffer is reached, Pointer assigned to arr_buf, its status is marked as IN_VSE. Pointer is set to 1, Mark from_ps is reset, and the status is further provided to the NEW_EXP_TR. In Pointer image is formed on the check (included in the back of PICTURE_START immediately behind the words In) to determine whether it is associated with targ_ix same (in the assembly specified target pointer), If the same set_if ...

Three states NEW_EXP_TR, SET_ARR_IX and NEW_PIC_NUM set a new hope And enter the desired time reference number of the image data. This center of the state is only set pointer arr_buf to make the correct picture number register is updated (also more noteworthy this_pnum New). Control then proceeds to state OUTPUT_TAIL and output data (showing the appropriate Two-wire interface signals) until it encounters a low expansion. At this time the main loop to restart, which Means that all the data blocks (64) output, which renders markup or display a request for any eventuality Again. C.2.4.7 When the operation when receiving FLUSH

Three states NEW_EXP_TR, SET_ARR_IX and NEW_PIC_NUM set a new hope And enter the desired time reference number of the image data. This center of the state is only set pointer arr_buf to make the correct picture number register is updated (also more noteworthy this_pnum New). Control then proceeds to state OUTPUT_TAIL and output data (showing the appropriate Two-wire interface signals) until it encounters a low expansion. At this time the main loop to restart, which Means that all the data blocks (64) output, which renders markup or display a request for any eventuality Again. C.2.4.7 When the operation when receiving FLUSH...

When the FLUSH token TOKEN in the state to check out. Mark from_fl is set, the Changes in the basic state machine loop to make the state FLUSH is accessed instead of state TOKEN. FLUSH turn state inspection of each buffer state, waiting for it to become VACANT or IN_ USE as shown. Simply state machine cycle until the condition is true, then added it The index and the process repeated until all the buffers are accessed. When the last buffer to meet this When pieces, showing number, image number, and the time base registers showing all their reset values rst_fid is set to 1. Mark form_f1 reset, the normal operation of the main loop begins again. C.2.4.8 When the operation when receiving TEMPORAL_REFERENCE ...

When the FLUSH token TOKEN in the state to check out. Mark from_fl is set, the Changes in the basic state machine loop to make the state FLUSH is accessed instead of state TOKEN. FLUSH turn state inspection of each buffer state, waiting for it to become VACANT or IN_ USE as shown. Simply state machine cycle until the condition is true, then added it The index and the process repeated until all the buffers are accessed. When the last buffer to meet this When pieces, showing number, image number, and the time base registers showing all their reset values rst_fid is set to 1. Mark form_f1 reset, the normal operation of the main loop begins again. C.2.4.8 When the operation when receiving TEMPORAL_REFERENCE ...

TEMP_REF0：temp_ref＝in_data_reg；

TEMP_REF1：delta＝temp_ref_exp_tr；index＝arr_buf；

TEMP_REF2：exp_tr＝delta+exp_tr；

TEMP_REF3: pic_num [i] = tnis_pnum delta; in dex = 1. C.2.4.9 Other tokens and end

In addition to the above-mentioned state TOKEN all cases outside the transfer control to the state OUTPUT_TALL, maintain control over this until it encounters a token of the last word (in_ extn_reg is low), and then re-enter the main loop. C.2.5 Application Notes C.2.5.1 state machine stop buffer manager input

This needs to be repeated to the image of the clock asynchronous timed asynchronous event request for inspection, And the display buffer. These checks stop buffer manager input requirements means that when Continuously providing data to the input of the buffer manager, through the number of buffer manager According to the rate will be limited. A typical state series can be PRES0, PRES1, DRQ, TOKEN, OUTPUT_TALL, in addition to outside of each OUTPUT_TALL last for a Cycles. This means that for each block of data item 64 will have three overhead cycles. During transmission Entry is stopped (in the state PRSE0, PRSE1 and DRQ period). Therefore, the write rate reduction Slow 3/64, or 5%. When the state machine of the auxiliary branch is executed in the worst conditions, This number may be increased to 13 cycles of overhead. It should be noted that such a large overhead applies only Once per frame with the situation. C.2.5.2 numbers presented during the visit characteristics ...

This needs to be repeated to the image of the clock asynchronous timed asynchronous event request for inspection, And the display buffer. These checks stop buffer manager input requirements means that when Continuously providing data to the input of the buffer manager, through the number of buffer manager According to the rate will be limited. A typical state series can be PRES0, PRES1, DRQ, TOKEN, OUTPUT_TALL, in addition to outside of each OUTPUT_TALL last for a Cycles. This means that for each block of data item 64 will have three overhead cycles. During transmission Entry is stopped (in the state PRSE0, PRSE1 and DRQ period). Therefore, the write rate reduction Slow 3/64, or 5%. When the state machine of the auxiliary branch is executed in the worst conditions, This number may be increased to 13 cycles of overhead. It should be noted that such a large overhead applies only Once per frame with the situation. C.2.5.2 numbers presented during the visit characteristics ...

Module bm_tref (not shown) should be included in the bmLogic, H.261 time Reference value can be directly input from bmtref to bm_stus module δ being processed correctly. If the frames are always sequential, δ zero input can be maintained. C.3 write address generating C.3.1 Introduction

According to the present invention, a write address generation function of the hardware address for the data generation block write Back buffer. This takes into account the buffer base address of said components in the stream, the macroblock The vertical and horizontal sampling, image size and encoding standard. Macroblock data in the form of reach But it must be stored, so you can easily retrieve the rows for display. C.3.2 Function Overview

Whenever a new block the incoming data stream when said data token, the write address generator to be To generate a new block address, the address does not need immediate, since the actual require address Before DRAM interface can store up to 64 data words (in alternating buffer). This means Means that the various address components can be added to a running total in successive cycles, and therefore, does not require Hardware multiplier. Macroblock counter function key by storing a terminal value and the register file The count value of the middle range. After each block address calculation and comparison of these operands of the Pieces updates.

Taking into account is shown in Figure 161 image format, hope can be taken from the standard address sequence number H.261 data stream and the like in the form of data flow, which as shown below. It should be noted, this format H.261 specification found not true, since these sheets are not wide enough (3 macroblocks rather than 11) In order to facilitate this use of the same "half-picture width", and assuming the sequence Column is "H.261 type." Data reaches a whole macroblock as shown in the example 4:2:0, each Components are stored in the designated buffer in its own area. Standard Address Series: 000,001,00 C, 00D, 100,200;

          002，003，00E，00F，101，201；

          004，005，010，011，102，202；

          006，007，012，013，103，203；

          008，009，014，015，104，105；

          00A，00B，016，017，105，205；

          018，019，024，025，106，107；

          01A，01B，026........

          ……

          080，081，08C，08D，122，222；

          082，083，08E，08F，123，223；

H261 type sequence

        000，001，00C，00D，100，200；

        002，003，00E，00F，101，201；

        004，005，010，011，102，202；

        018，019，024，025，106，107；

        01A，01B，026，027，107，207；

        01C，01D，028，029，108，208；

        030，031，03C，03D，10C，20C，

        032，033，03E，03F，10D，20D；

        034，035，040，041，10E，20E；

        006，007，012，013，103，203；

        008，009，014，015，104，105；

        00A，00B，016，017，105，205；

        01E，01F，02A，02B，109，209；

        020，021，02C，02D，10A，20A；

        022，023，02E，02F，108，20B；

        036，037，042，043，1 0F，20F；

        038，039，044，045，110，210；

        03A，038，046，047，111，211；

        048，049，054，055，112，212；

        04A，04B，056..........

        ……

        06A，06B，076，077，11D，21D；

        07E，07F，08A，08B，121，221；

        080，081，08C，08D，122，222；

082,083,08 E, 08F, 123; 223; C.3.3 Structure C.3.3.1 Interface C.3.3.1.1 Interface to buffer manager

Buffer manager buffer index data and output directly to the write address generator, This is under the control of the two-wire interface implementation. In some methods, in consideration of the write address sent Generator block as the expansion of the buffer manager because the two are very closely linked, and they Consists of two separate (but similar) clock generator work. C.3.3.1.2 Interface to dramif

Write address generator provides data for the DRAM interface and address. Both have their own lane Interface, and at different clock dramif used in this specification for each of them. Particularly, Address Dramit write address using the same clock timing generator clock hair has nothing to do, so the output Out of synchronization. C.3.3.1.3 Microprocessor Interface

Write address generator uses three microprocessor address space plus 8-bit data bus and read Write strobe. There is a single selection bits for register access. C.3.3.1.4 event

A write address generator can form five different events. Two appear in the data stream corresponding to the (hmbs and Vmbs) of the image size information, 3 corresponds to the order DEFINE_SAMPLING Cards (one event for each component). c.3.3.2 basic structure

Write address generator is shown in the waddrgen.sch, which includes a data channel, Some control logic and look into the depths and its synchronization. C.3.3.2.1 Data Channel (bwadpath)

C.5 of this document describes the data path section types, including 18 adder / minus Adder and register file (see C.3.3.4) and is used in the control logic generates zero mark (Based on the adder output). C.3.3.2.2 control logic

The control logic of the present invention, the register file is used to generate all the hardware drivers loaded letter Number. Adder control signals, dual interface signal component also includes a writable control register. C.3.3.2.3 detector and synchronization

Each port on the data and address advanced detectors. The detector is in a data channel to the Since Zcells advanced detector control. Address in the write address generator's clock and dramif "Clk" between the way synchronization. Syncifs used in Zcell, as a two-wire interface signals Simplify the address for the data synchronizer road. C.3.3.3 control logic and state machines C.3.3.3.1 input / output block (wa inout)

This section includes input and two output two-wire interface, as well as the input data with (on the order Decoder card) and arrival buffer index latch (4 decoding method). C.3.3.3.2 two-cycle control block (wa fc)

Mark fc (first cycle) and remain in this state machine indicates whether a two-cycle operation The middle row (i.e., the operation exc.) C.3.3.3.3 component count (wa comp)

For each component of the data block requires a separate address, this receives the input stream The data header types consider keeping the current component. C.3.3.3.4 Control Module 0-3 (wa_nod 3)

H.261 data stream is generated when the address sequence is required along the screen (see C.3.2) with In half the number of the macro block method 3 lines. This is subject to keep the module counter of 0-3, and each Visit a new macroblock row it increases. C.3.3.3.5 Control Register (Wa uregs)

Module wa_uregs including setting registers and coding standard registers, the latter from the data Flow loading, setting register with 3: QCIF (1sb), and in the data stream to the desired maximum of Capacity (bits 1 and 2). Access bit also resides in this block (as it normally would be synchronized), Stop bit has been taken from the top of the next one (waLogic), it is the access bit and stop bit event 'Or'. Decoded by a microprocessor address block wa_udec complete this block read and write access Strobe, select line and the address bus, the lower two. C.3.3.3.6 control state machine (wa state)

The logic in this one is divided into several distinct areas. State decoding, the new state series Code, the solution intermediate logic signal, the data path control signals (drive a, drive b, loading Set, the adder control and selection signals), multi-channel switch control, control, and 5-wire interface An event signal. C.3.3.3.7 event is generated

Since the input token received some results to five event bits. Importantly, In each case the entire token is received before any events generated because the event service Service routine according to the received new value calculation is performed. For this reason, each of the input Prior to the event for the entire cycle latency hardware. C.3.3.4 register address translation

The write address generator member has two register set, which are located in the standard cell Set the top part of the keyhole type register and data path registers. These registers points Do not listed in Table C.3.1 and C.3.2.

Table C.3.1 top register

Register name	Address bits	Reset state	Function
				BU_WADDR_COD_STD	0x4
2	0	From the data stream encoded in the standard
			BU_WADDR_ACCESS	0x5
1	0	Access Bit
			BU_WADDR_CTL1	0x6
3	0	Maximum component [2:1] and QCIF [0]
			BU_WA_ADDR_SNP2	0xB0	8		Kuice on the write address generator Implement Address C / p
BU_WA_ADDR_SNP1	0xB1
		8
BU_WA_ADDR_SNP0	0xB2
		8
BU_WA_DATA_SNP1	0xB4
		8		Write a glimpse on the output address data Detector WA
BU_WA_DATA_SNP0	0xB5
		8

Table C.3.2 image formatter address generator keyhole

Keyhole register name	Keyhole Address	Position	Note
				BU_WADDR_BUFFER0_BASE_MSB	0x35
	2	Must Load
			BU_WADDR_BUFFER0_BASE_MID	0x36
	8
			BU_WADDR_BUFFER0_BASE_LSB	0x97		8
BU_WADDR_BUFFER1_BASE_MSB	0x39						2	Must Load
			BU_WADDR_BUFFER1_BASE_MID	0x3a
	8
		BU_WADDR_BUFFER1_BASE_LSB	0x3b	8
BU_WADDR_BUFFER2_BASE_MSB	0x8d					2	Must Load
		BU_WADDR_BUFFER2_BASE_MID	0x8e
	8
		BU_WADDR_BUFFER2_BASE_LSB	0x81		8
BU_WADDR_COMP0_HMBADDR_MSB	0x91						2	Test only
		BU_WADDR_COMP0_HMBADDR_MID	0x92
	8
		BU_WADDR_COMP0_HMBADDR_LSB	0x93		8
BU_WADDR_COMP1_HMBADDR_MSB	0x95						2	Test only
		BU_WADDR_COMP1_HMBADDR_MID	0x96
	8
		BU_WADDR_CCMP1_HMBADDR_LSB	0x97		8
BU_WADDR_COMP2_HMBADDR_MSB	0x99						2	Test only
		BU_WADDR_CCMP2_HMBADDR_MID	0x9a	8
BU_WADDR_COMP2_HMBADDR_LSB	0x9b				8
		BU_WADDR_COMP0_VMBADDR_MSB	0x9d			2	Test only
BU_WADDR_COMP0_VMBADDR_MID	0x9e				8
		BU_WADDR_COMP0_VMBADDR_LSB	0x9f			8
BU_WADDR_COMP1_VMBADDR_MSB	0xa1							2	Test only
		BU_WADDR_COMP1_VMBADDR_MID	0xa2			8
BU_WADDR_COMP1_VMBADDR_LSB	0xa3						8
		BU_WADDR_COMP2_VMBADDR_MSB	0xa5			2		Test only
BU_WADDR_COMP2_VMBADDR_MID	0xa6						8
		BU_WADDR_COMP2_VMBADDR_LSB	0xa7			8
BU_WADDR_VBADDR_MSB	0xa9						2		Test only
		BU_WADDR_VBADDR_MID	0xaa	8
BU_WADDR_VBADDR_LSB	0xab					8

Table C.3.2 image formatter address generator keyhole (continued)

Keyhole register name	Keyhole Address	Position	Note
				BU_WADDR_COMP0_HALF_WIDTH_IN_BLOCKS_MSB	0xad
	2	Must Load
			BU_WADDR_CCMP0_HALF_WIDTH_IN_BLOCKS_MID	0xae
	8
			BU_WADDR_COMP0_HALF_WIDTH_IN_BLOCKS_LSB	0xa1		8
BU_WADDR_COMP1_HALF_WIDTH_IN_BLCCKS_MSB	0xb1						2	Must Load
			BU_WADDR_COMP1_HALF_WODTH_IN_BLOCKS_MID	0xb2
	8
		BU_WADDR_COMP1_HALF_WIDTH_IN_BLOCKS_LSB	0xb3	8
BU_WADDR_COMP2_HALF_WIDTH_IN_BLOCKS_MSB	0xb5					2	Must Load
		BU_WADDR_COMP2_HALF_WIDTH_IN_BLOCKS_MID	0xb6
	8
		BU_WADDR_COMP2_HALF_WIDTH_IN_BLCCKS_LSB	0xb7	8
BU_WADDB_HB_MSB	0xb9					2	Test only
		BU_WADDR_HB_MID	0xba	8
BU_WADDR_HB_LSB	0xbb				8
		BU_ADDR_COMP0_OFFSET_MSB	0xbd			2		Must Load
BU_WADDR_COMP0_OFFSET_MID	0xbe
			8
BU WADDR_COMP0_OFFSET_LSB	0xbf				8
		BU_WADDR_COMP1_OFFSET_MSB	0xc1				2	Must Load
BU_WADDR_COMP1_OFFSET_MID	0xc2
			8
BU_WADDR_COMP1_OFFSET_LSB	0xc3			8
		BU_WADDR_COMP2_OFFSET_MSB	0xc5			2	Must Load
BU_WADDR_COMP2_OFFSET_MID	0xc6
			8
BU_WADDR_COMP2_OFFSET_LSB	0xc7			8
		BU_WADDR_SCRATCH_MSB	0xc9			2	Test only
BU_WADDR_SCRATCH_MID	0xca							8
		BU_WADDR_SCRATCH_LSB	0xcb		8
BU_WADDR_MBS_WIDE_MSB	0xcd					2		Must Load
		BU_WADDR_MBS_WIDE_MID	0xce
	8
		BU_WADDR_MBS_WIDE_LSB	0xc1	8
BU_WADDR_MBS_HIGH_MSB	0xd1					2	Must Load
		BU_WADDR_MBS_HIGH_MID	0xd2
	8
		BU_WADDR_MBS_HIGH_LSB	0x03		8

Keyhole register name	Keyhole Address	Position	Note
				BU_WADDR_COMP0_LAST_MB_ROW_MSB	0x105	2	Must Load
BU_WADDR_COMP0_LAST_MB_ROW_MID	0x106
			8
BU_WADDR_COMP0_LAST_MB_ROW_LSB	0x107				8
		BU_WADDR_COMP1_LAST_MB_ROW_MSB	0x109				2	Must Load
BU_WADDR_COMP1_AST_MB ROWMID	0x10a				8
		BU_ADDR_COMP1_LAST_MB_ROW_LSB	0x10b			8
BU_WADDR_COMP2_LAST_MB_ROW_MSB	0x10d				2		Must Load
		BU_ADDR_COMP2_LAST_MB_ROW_MID	0x10e
	8
		BU_WAOOR_COMP2_LAST_MB_ROW_LSB	0x10f	8
BU_WADDF_COMP0_HBS_MSB	0x111					2	Must Load
		BU_WADDR_COMP0_HBS_MID	0x112
	8
		BU_WADDR_COMP0_HBS_LSB	0x113		8
BU_WADDR_COMP1_HBS_MSB	0x115						2	Must Load
		BU_WADDR_COMP1_HBS_MID	0x116
	8
		BU_WADDR_COMP1_HBS_LSB	0x117		8
BU_WADDR_COMP2_HBS_MSB	0x119						2	Must Load
		BU_WADDR_COMP2_HBS_MID	0x11a
	8
		BU_WADDR_COMP2_HBS_LSB	0x11b	8
BU_WADDR_COMPO_MAXHB	0x111					2	Must Load
		BU_WADDR_COMP1_MAXHB	0x123					2
BU_WADDR_COMP2_MAXHB	0x127					2
		BU_WADDR_COMP0_MAXVB	0x12b					2	Must Load
BU_WADDR_COMP1_MAXVB	0x121				2
		BU_WADDR_COMP2_MAXVB	0x133	2

Table C.3.2 image formatter address generator keyhole (continued)

Table C.3.2 image formatter address generator keyhole (continued)...

Table C.3.2 image formatter address generator keyhole (continued)...

1, WADDR_HALF_WIDTH_IN_BLOCKS: It defines the block into the image Half-width.

2, WADDR_MBS_WIDE: It defines a macro block into the width of the image.

3, WADDR_MBS_HIGH: It defines a macro block into the image height.

4, WADDR_LAST_MB_IN_ROW: it defines a single macroblock full width OK, the last one left macroblock block number. From the upper left corner of the leftmost macroblock open from zero Starting block number, along with each block of frames increases, but also with the subsequent macroblock row to the next row of blocks Increases.

5, WADDR_LAST_MB_IN_HALF_ROW: This is similar to the previous item, it is determined Righteous liberal block line in the last half of a macro block block number of the upper left corner.

6, WADDR_LAST_ROW_INMB: it defines the macro block line in the last row block The leftmost block number.

7, WADDR_BLOCKS_PER_MB_ROW: it defines included in a single, full width Degree of macro-block line the total number of blocks.

8, WADDR_LAST_MB_ROW: it defines the image of the last macroblock in the leftmost Macro block left block address.

9, WADDR_HBS: It defines the block to enter the width of the image.

10, WADDR_MAXHB: it defines the macro blocks in a single row in the rightmost block Block number.

11, WADDR_MAXVB: It block defines a single macro-block -1.

Also, define the DRAM organization registers must be programmed, which are three buffer Is an n-component base register offset register. Where n is the desired data stream number of components (It can be defined in the data flow, the minimum is 1 and the maximum is 3).

Note that many parameter specifies the block number or block address. This is because hope is a final address A block address, and the calculation is based on the cumulative algorithms.

Figure 162 illustrate the layout structure, resulting in the following register values​​:

        1)WADDR_HALF_WIDTH_IN_BLOCKS＝0x16

        2)WADDR_MBS_WIDE＝0x16

        3)WADDR_MBS_HIGH＝0x12

        4)WADDR_LAST_MB_IN_ROW＝0x2A

        5)WADDR_LAST_MB_IN_HALF_ROW＝0x14

        6)WADDR_LAST_ROW_IN_MB＝0x2C

        7WADDR_BLOCKS_PER_MB_ROW＝0x58

        8)WADDR_LAST_MB_ROW＝0x5D8

        9)WADDR_HBS＝0x2C

        10)WADDR_MAXVB＝1

11) WADDR_MAXHB = 1 C.3.5 state machine operation

In the buffer manager state machine in 19 states, as detailed in Table C.3.3. Its Linkages shown in Figure 164 and also in the Feature Description bmlogic.M for illustration.

Table C.3.3 write address generator status

Status	Value
		IDLE	0x00
DATA	0x10
		CODING_STANDARD	0x0C
HORZ_MBS0	0x07
		HORZ_MBS1	0x06
VERT_MBS0	0x0B
		VERT_MBS1	0x0A
OUTPUT_TAIL	0x08
		HB	0x11
MB0	0x1D
		MB1	0x12
MB2	0x1E
		MB3	0x13
MB4	0x0E
		MB5	0x14
MB6	0x15
		MB4A	0x18
MB4B	0x09
		MB4C	0x17
MB4D	0x16
		ADDR1	0x19
ADDR2	0x1A
		ADDR3	0x1B
ADDR4	0xIC
		ADDR5	0x03
HSAMP	0x05
		VSAMP	0x04
PIC_ST1	0x01
		PIC_ST2	0x01
PIC_ST3	0x02

C.3.5.1 address calculation

A write address generator state machine main part 164 on the left bottom of Fig instructions. When connected Receive data token, the state machine moves from state IDLE state ADDR1. Then to the state ADDR5, 18-bit block address from the state with two-wire interface control ADDR5 be output. By the state ADDR1 calculation performed until ADDR5 are:

          BU_WADDR_SCRATCH＝BU_BUFFERn_BASE

          +BU_COMPm_OFFSET；

          BU_WADDR_SCRATCH＝BU_WADDR_SCRATCH

          +BU_WADDR_VMBADDR；

          BU_WADDR_SCRATCH＝BU_WADDR-SCRATCH

          +BU_WADDR_HMBADDR；

          BU_WADDR_SCRATCH＝BU+WADDR_SCRATCH

          +BU_WADDR_VBADDR；

          out_addr＝BU_WADDR_SCRATCH+BU_WADDR_HB；

Used registers are defined as follows:

1, BU_WADDR_VMBADDR: the leftmost macroblock is a macroblock row block address (top left Block) included in the macroblock address is in a block is calculated.

2, BU_WADDR_HMBADDR: the top macroblock macroblock row block address (top left Block) included in the macroblock address is in a block is calculated.

3, BU_WADDR_VBADDR: line in the macro block, the block row of the left block address of the block, In these blocks, including its address is in a block is calculated.

4, BU_WADDR_HB: the address of the macro block is the block being the horizontal block Number.

5, BU_WADDR_SCRATCH: used to temporarily store intermediate results of the temporary register.

Consider Figure 163, for example, take the address 0x62 block calculation, the following sequence of calculations Will occur:

SCRATCH＝BUFFERn BASE+COMPm OFFSET；(assume 0)

SCRATCH＝0+0x5D8；

SCRATCH＝0x5D8+0x28 ；

SCRATCH＝0x600+0x2C；

Block Address = 0x62C +1 = 0x62D;

Contents of the various registers are illustrated in Fig. C.3.5.2 new screen location parameter calculation

When the address is output, the state machine in order to update the positional parameters described above even the various screens Continued to perform calculations. States HB and MBO until MB6 calculated at some point transfer control to State DATA, the data token is output from this state tips.

These states in pairs, the first count and the calculation of the current between its final value Poor, then generates zero mark. Reset register or add a second pair of fixed (according to the screen size Inch derived through setting register values​​) bias. In each case, if the calculation has reached To its final value (ie set zero mark), control continues down to the state "MB" sequence, Otherwise, think of all the order to calculate the correct (ready for the next address calculation) and transfer control To state DATA.

Note that all involve addition and subtraction of the state of charge two cycles to complete (allows standard Quasi ripple-carry adder), this by marking fc (first cycle) of use, This flag adder state changes between 1 and 0.

All addresses and screen position calculation state calculation assumes case suitable wire interface Allows data output. C.3.5.2.1 of the standard (MPEG-type) sequence of calculations

Work in the following order (including zero mark under adder output):

States HB and MBO:

    scratch＝hb-maxhb；
    if (z)
      hb＝0；
    else
    (

      hb＝hb+1

      new_state＝DATA；

    )
    states MB1 and MB2：
    scratch＝vb_addr-last_row_in_mb；
    if  (z)

      vb_addr＝0；
    else
    (

      vb_addr＝vb_addr+width_in_blocks；

      new_state＝DATA；
    )
    states MB3 and MB4：
    scratch＝hmb_addr-last_mb_in_row；
    if (z)

      hmb_addr＝0 ；
    else
    (

      hmb_addr＝hmb_addr+maxhb；

      new_state＝DATA；
    )
    states MB5 and MB6：
    scratch＝vmb_addr-last_mb_row；
    if  (！z)

      vmb_addr＝vmb_addr+blocks_per_mb_row；

(In PICTURE_START token is detected after reset V_mb_addr, not when Image calculated from the end of the launch) C.3.5.2.2 calculation of H.261 sequence

Calculated sequence of H.261 standard sequence with state MB4 different:

States HB and MBO: - as above

State MB1 and MB2: - above

States MB3 and MB4:

scratch＝hmb addr-last_mb_in_row；
if(z&(mod3＝＝2))/*end of slice on right of screen*/
(
  hmb addr-0；
  new state-MB5；
)
else if(z)/*end of row on right of screen*/
(
  hmb_addr＝half_width_in_blocks；
  new_state＝MB4A；
)
else
(

  scratch＝hmb addr-last mb_in half row；

  new-state＝MB4B；
}
				<!-- SIPO <DP n="577"> -->
				<dp n="d577"/>
    state MB4A：
    vmb_addr＝vmb_addr+blocks_per_mb_row；
    new_state＝DATA；
    state(MB4)and MB4B：
    (scratch＝hmb_addr-last_mb_in_half_row；)
    if (z&amp;(mod3＝＝2))/*end of slice on left of screen*/
    {

       hmb_addr＝hmb_addr+maxhb；

       new_state＝MB4C；
     }
     else if(z)/*end of row on left of screen*/
     {

       hmb_addr＝0；

       new_state＝MB4A；
     }
     else
     {

       hmb_addr＝hmb_addr+maxhb；
       new_state＝DATA；
     }
     states MB4C and MB4D：
     vmb_addr＝vmb_addr-blocks_per_mb_row；
     vmb_addr＝vmb_addr-blocks_per_mb_row；
     new_state＝DATA；
     states MB5and MB6：-as above

C.3.5.3 token operation according PICTURE_START

When a PICTURE_START token is received, the control passes to state PIC_ST1, in that Lane Vb_addr register (BU_WADDR_VBADDR) resets to zero. State PIC_ST2 and PIC_ST3 each is accessed once for each component, respectively, and reset hmb_addr Vmb_ addr. Controlled by the state OUTPUT_TAIL then returned to IDLE. C.3.5.4 token operation under DEFINE_SAMPLING

DEFINE_SAMPLING When receiving the token, the component with the input data register Effectiveness of the worst two loading. Also by state HSAMP and VSAMP, maxhb and maxvb Register for component loading. Moreover, the definition of appropriate sampling event bit is triggered (via a All cycle delay to allow a write token). C.3.5.5 HORIZONTAL_MBS and VERTICAL_MBS operation

When each HORIZONTAL_MBS and VERTICAL_MBS arrived, contained in the token 14-bit value written to the two cycles in the appropriate register. Related event bit is triggered Hair, delayed by one cycle. C.3.5.6 Other Tokens

CODING_STANDARD token is detected and the input data to the top BU_WADDR_ COD_STD registers, this data is decoded, nh261 mark (not H.261) by hardware Of the buffer management block. All other tokens of the control over the status OUTPUT_TAIL, Where the received data until the end of the token. It should be noted, it actually does not output any number of Data. C.4 read address generator C.4.1 Overview

The read address generator of the present invention consists of four state machine / datapath blocks, the first "Dline" generates a row address and these addresses are assigned to the other three (each component a) The same page / block address generators, "dramctls". All blocks connected via two-wire interface Knot, mode of operation, including all interlaced / progressive combination of the first above / below in conjunction with and In the above / below / on the following frame starter combined. Table C.3.4 shows dispaddr control System registers the names, addresses, and Reset state and C.13 section gives two address generation Device programming examples. C.4.2 row address generator (dline)

Calculated for each component of this row start address. Table C.3.4 shows dline, 18 Bit data path registers.

Note, DISP_register_name with ADDR_register_name, DISD_ name only difference is dispaddr between registers, the means that register will be targeted at Read the display area of DRAM. ADDR_name means registers describe certain about the external Buffer structure things.

Operating

dline basic operations are: (ignoring all manner of duplication)

    if(vsync_start)/*first active cycle of vsync*/
    (
    comp＝0
    DISP_VB_CNT_COMp[comp]＝0；
    LINE[comp]＝BUFFER_BASE[comp]+0；
    LINE[comp]＝LINE[comp]+DISP_COMP_OFFSET[comp]；
    while(VB_CNT_COMP[comp]＜DISP_VBS_COMP[comp]
    (
    while(line_count[comp]＜8)
    (
     (
     while(comp＜3)
     (     -OUTPUT LINE[comp]to dramctl[comp]
     line[comp]＝LINE[comp]+ADDR_HBS_COMP[comp]；
     comp＝comp+1；
     )
     line_count[comp]＝line_count[comp]+1；
     )
     VB_CNT_COMP[comp]＝VB_CNT_COMP[comp]+1；
     line_count[comp]＝＝0；
     )
     )

Table C.3.4 Dispaddr datapath register

Register name	Bus	Keyhole Address	Explanation	Note
					BUFFER_BASE0	A	0x00，01， 02，03	Each buffer The starting block Site	These registers Start of the operation Ago by UPI Load
BUFFER_BASE1	A	0x04，05， 06，07
			BUFFER_BASE2	A	0x08，09， 0a，0b
DISP_COMP_ OFFSET0	B	0x24，25， 26，27，				From the buffer base Address to read the beginning of Address offset
			DISP_COMP_ OFFSET1	B	0x28，29， 2a，2b
DISP_COMP_ OFFSET2	B	0x2c，2d， 2e，2f
			DISP VBS_COMP0	B	0x30，31， 32，33		The vertical block read Number
DISP_VBS_COMP1	B	0x34，35， 36，37
			DISP_VBS_COMP2	B	0x38，39， 3a，3b
ADDR_HBS_COMP0	B	0x3C，3d， 3e，3f				Water in the data Flat block number

Table C.3.4 Dispaddr data path registers (continued)

Register name	Bus	Keyhole address	Explanation	Note
					ADDR_HBS_COMP1	B	0x40，41， 42，43
ADDR_HBS_COMP2	B	0x44，45， 46，47
			LINE0	A	0x0C，0d， 0e，0f	Current row address	This register is By dispddr Positioning for the time Note: All Register from Microprocessor connected Port R / W
LINE1	A	0x10，11， 12，13
			LINE2	A	0x14，15， 16，17
DISP_VB_ CNT_COMP0	A	0x18，19， 1a，1b						Vertical to be read Straight block number
			DISP_VB_ CNT_COMP1	A	0x1c，1d， 1e，1f
DISP_VB_ CNT_COMP2	A	0x20，21， 22，23

C.4.3 Dline control register

The above operation is controlled by dispaddr control register changes. These registers are displayed in the In Table C.4.3.

Table C.4.3 Control Register

Register name	Address	Position	Reset state	Function
					LINES_IN_ LAST_ROW0	0x08	[2∶0]	0x07	These three registers determine readout The last block is the number of rows (8 Outside)
LINES_IN_ LAST_ROW1	0x09	[2∶0]	0x07
				LINES_IN_ LAST_ROW2	0x0a	[2∶0]	0x07
DISPADDR_ ACCESS	0x0b	[0]	0x00					Access bit on dispaddr
				DISPADDR _CTLO See the following Control bits are set Detailed instructions	0x0c	[1∶0]	0x0		SYNC_MDDE
[2]	0x0	READ_START
			[3]			0x1	INTERLACED/PROG
[4]	0x0	LSB_INVERT
			[7∶5]			0x0	LINE_RPT
DISPADDR _CTL1	0x0d	[0]						0x1	COMPOHOLD

Dispaddr control register C.4.3.1 LINES_IN_LAST_ROW [component]

These three registers for each component of the final block is read to determine the number of rows, so read Height of the window can be any number of rows. This is a back-up feature since the top of the window, left And right along the boundary of the block, and the output controller can cut (discarded) over the line. C.4.3.2 DISPADDR_ACCESS

This is the access bit for the whole dispaddr, in this position, writing "1", the dispaddr synchronized with the clock stopped. Read back from the access bit value will remain at "0" until dispaddr has safely stopped. To achieve this state, all the dispaddr registers executive Line asynchronous upi accesses are safe. It should be noted upi data path registers are actually locked Until the access bit is "1." In order not to interrupt the current display or datapath operation situation Case complete dispaddr access only released in the following circumstances access access.

Stop: Only datapath has completed its current two year operation (if it is done A) from the output controller "safety signal" is high to allow access. This Signal representative of the screen area of the display window, the controller is programmed at the output (Non dispaddr). Note: So in an attempt to gain access on dispaddr you need To output controller programming.

Start access only "safe" is high or released during vsync. This ensures significantly Shows not too close to the active window at the start.

This program enables the control software to request access to, until asked to end the modified dispaddr and release access. If the software is too slow, until after the release of vsync access bit, dispaddr will be safe until the next cycle was initiated. Border color in this "lost (by Discard) "image displayed during (not spam). C.4.3.3 DISPADDR_CTL0 [7:0]

When reading the following description, the understanding of interlaced and interlaced displays the difference between the data is important.

There are two kinds of forms interlaced data. Top registers support field - images (each buffer Including a farm) and frame images (each including a full frame buffer - interlaced or non-interlaced).

DISPADDR_CTL0 [7:0] control bits include the following:

SYNC_MODE[1∶0]

An interlaced display, the top and bottom fields involving the field_info pin area VSYNS Points. On this point, field_info = HIGH means the top field. This two control bits determine which A Vsyncs dispaddr from the buffer manager requests a new display buffer. Because Here, the damper mass (if the data is interlaced) and the display of the field sync.

0: In the top field of the new display buffer

1: bottom field

2: two

3: two

At startup, dispaddr to the buffer manager on every vsync to request a buffer Makers. dispaddr receives a zero (no display) buffer until the buffer is ready. When it finally got a valid buffer pointer, dispaddr did not know it at the display What place. Therefore, the display starts with the correct vsync synchronization.

READ_START

In interlaced display startup, the display will actually determine from which Vsync begins. The display in the receive buffer pointer, dispaddr may "sitout" Current vsync, to align the display field with buffer midfielder.

INTERLACED/PROGRESSIVE

0: Progressive

1: Interlaced

In the progressive mode, the read-out buffer display area all rows. In interlaced mode , Only the reading interval row start reading the first line or second line determined by the field_info, Note Intended for (interlaced) field image, the system wants all rows from each buffer read, so this The setting position is progressive. field_info and the first / second line can start mapping between Through lsb_invert inverted (the name is due to historical reasons).

LSB_INVERT

When set, the inverted signal from the line counter to see field_info. Accordingly, Reading can be a start on the right line and monitor adjustment. Regardless of the encoder used in Practices, monitor, or top-level registers.

LINE_RPT[2∶0]

When set, each component so that the corresponding lines are read twice (bit 0 affecting component 0 etc.), This is a vertical oversampling (upsampling) the first part. It is used to convert the QFIF Into 601 eight times the desired color through sampling (upsampling).

COMP0HOLD

The component of 0 is used to read the number of rows 1 and 2 with the component ratio of the number line reading program (With display opposite).

0: same number of rows, i.e. the data in the buffer 4:4:4

1:2 times the number of rows in the component 0, ie 4:2:0

Page block address generator (dramctls)

When passing a row address, these blocks produce a series of pages / row address and blocks to be Read line by line. Typically, if the minimum width of the page 8, and the output includes a page address, A 3-bit number of lines, a 3-bit block start, and a 3-bit block stop address (row number from the dline computing and unchanged through dramctls). Therefore, in order from the left of the first three Starting the read-out from the sheet 5 rows 0xaa 48 pixels (any point along any line), The address will be passed to the DRAM interface:

    Page＝0xaa
    Tine＝5
    Block start＝2
    Block stop＝7

These three devices each having five data path registers. These are shown in Table C.3.4 Medium. Each dramctl basic features are:

    Block start＝2
    Block stop＝7
    while(true)
    {
    CNT_LEFT＝0；
    GET_A_NEW_LINE_ADDRESS from dline；
    BLOCK_ADDR＝input_block_addr+0；
    PAGE_ADDR＝input_page_addr+0；
    CNT_LEFT＝DISP_HBS+0；
    while(CNT_LEFT＞BLOCKS_LEFT)
    {
    BLOCKS_LEFT＝8-BLOCK_ADDR；
    --＞output PAGE_ADDR，start＝BLOCK_ADDR，stop＝7.
    PAGE_ADDR＝PAGE_ADDR+1；
    BLOCK_ADDR＝0；
    CNT_LEFT＝CNT LEFT-BLOCKS_LEFT；
    }
    ΓLast Page of line*/
    CNT_LEFT＝CNT_LEFT+BLOCK ADDR；
    CNF_LEFT＝CNT_LEFT-1；
    -＞output PAGE_ADDR，start＝BLOCK_ADDR，stop＝CNT_LEFT
    }

Table C.3.5 Dramctl (0,2, & 2) data path register

Register name	Bus	Keyhole Address	Explanation	Note
					DISP_COMP0 _HBS	A	0x48，49， 4a，4b	The level of the number of blocks to be read c.f. ADDR-HBS	Before the start of the operation Register must be loaded Register
DISP_COMP1 _HBS	A	0x4c，4d， 4e，4f
			DISP_COMP2 _HBS	A	0x50，51， 52，53
CNT_left0	A	0x54，55， 56，57，				The remaining blocks to be read Number	These registers By dispa- ddr, with time Room Positioning Note: All registers Register R / W to Since upi
			CNT_left1	A	0x58，59， 5a，5b
CNT_left2	A	0x5c，5d 5e，5f
			PAGE_ADDR0	A	0x60，61， 62，63			The address of this page
PAGE_ADDR1	A	0x64，65， 66，67
			PAGE_ADDR2	A	0x68，69， 6a，6b
BLOCK_ADDR0	B	0x6c，6d， 6e，6f				Current block address

Table C.3.5 Dramctl (0,2, & 2) data path registers (continued)

Register name	Bus	Keyhole Address	Explanation	Note
					BLOCK_ADDR1	B	0x70，71， 72，73
BLOCK_ADDR2	B	0x74，75， 76，77
			BLOCK_left0	B	0x78，79， 7a，7b	Residual current page Block
BLOCK_left1	B	0x7c，7d， 7e，7f
			BLOCK_left2	B	0x80，81， 82，83

Program

Below 15 dispaddr register must be programmed before the start of the operation.

           BUFFER_BASE0，1，2

           DISP_COMP_OFFSET0，1，2

           DISP_VBS_COMP0，1，2

           ADDR_HBS_COMP0，1，2

           DISP_COMP0，1，2_HBS

Use dispaddr control registers reset state will give an unusual walk duplicate 4:2 n interlaced display, and in the entry field begins (field_info = HIGH). Figure 159 "includes SIF (22 × 18 macroblocks) picture buffer 0 "shows a typical image in the SIF Buffer settings. (C.13 section more particularly in this example). Note that, in this example, DISP_HBS_COMPn equal ADDR_HBS_COMPn. Similarly, the vertical register DISP_ VBS_COMPn and considerable write address generator registers are equal, ie the area is read All buffers.

Window is formed with a read address generator.

Address assignment can be programmed to enable it to read only part of the buffer (window). Window The size of the mouth through the register DISP_HBS, DISP-VBS, COMPONENT_OFFSET and LINES_IN_LAST_ROW for each component of the program. Figure 160, "SIF having a display window, Weight 0. "Shows how this is done. (Only component 0).

In this example, the registers are set to:

          BUFFER_BASEO＝0×00

          DISP_COMP_OFFSET0＝0×2D

          DISP_VBS_COMP0＝0×22

          ADDR_HBS_COMP0＝0×2C

          DISP_HBS_COMO＝0×2A

Note:

· Window can only begin and end at the block boundaries.

In this case we make LINES_IN_LAST_ROW equal to 7 (meaning all 8).

· In addition to 4:4:4 data outside of the case is unrealistic. In order to correspond to the other two Ingredients edge of the window can not block boundary.

· If the received data is not 4:4:4 color space converter will not, which means that These read window approach with non-sampler (up samplers) must be programmed together in order to complete it. C.5 address generation data path

In dispaddr and waddrgen data path used in the structure and width (18 Bits) are the same, only the number of registers, some shielding and the state machine returns to the standard Remember different. Figure 165 shows a portion of the circuit (the circuit of one slice) "data path portion (Slice of Datapath)". Register is independent Assignment, to drive the A or B bus, and the controller, their use (assignment) is the most Optimized. All registers can be loaded from the C bus. However, not all the "loading" the letter Numbers are being driven. All operations involving the adder contains two cycles to allow the adder Having ordinary ripple carry. Figure 166, "two cycle operation of the datapath," shows the Loaded back into the "A" bus registers two registers two cycles and timing. In a few According to the passage of various markers are "Ph0" technology in order to generate C code. Same reason, data communication Road structure of the program is slightly exceptions, all registers (A and B buses) are in a single Block, this eliminates the need for a combination of pathways in the cell, thus allowing C code can better health Percent. Upi for the data path to get access, you must set the access bit because without this visit Because if this access will be locked except bit upi. Unlike upi read and write access: ...

In dispaddr and waddrgen data path used in the structure and width (18 Bits) are the same, only the number of registers, some shielding and the state machine returns to the standard Remember different. Figure 165 shows a portion of the circuit (the circuit of one slice) "data path portion (Slice of Datapath)". Register is independent Assignment, to drive the A or B bus, and the controller, their use (assignment) is the most Optimized. All registers can be loaded from the C bus. However, not all the "loading" the letter Numbers are being driven. All operations involving the adder contains two cycles to allow the adder Having ordinary ripple carry. Figure 166, "two cycle operation of the datapath," shows the Loaded back into the "A" bus registers two registers two cycles and timing. In a few According to the passage of various markers are "Ph0" technology in order to generate C code. Same reason, data communication Road structure of the program is slightly exceptions, all registers (A and B buses) are in a single Block, this eliminates the need for a combination of pathways in the cell, thus allowing C code can better health Percent. Upi for the data path to get access, you must set the access bit because without this visit Because if this access will be locked except bit upi. Unlike upi read and write access: ...

· R: This is done using the A and B bus. Once again, the access bit must be set. Already Addressable registers are driven to the A or B bus, and the bus upi byte select one from the relevant Bytes, and drive it to the upi bus.

Because two-cycle datapath operation requires A and B bus hold their value (and upi Visit interrupt these), access must only before the start of any data access operation by controlling Given system state machine.

Address generator in the two data paths through a 9-bit wide registers lock Eye in the top address is addressed, 0 × 28 (msb) and 0 × 29 (lsb) of the key hole, and 0 × 2A to Data. This keyhole address given in Table C.11.2.

Note:

1) All the address generator (dispaddr and waddrgen) in the address register Includes a block address, pixel address never used, including the row address of the register and only three LINES_IN_LAST_ROW register.

2) Some registers are copied between the address generator, for example, BUFFER_BASEO the Now dispaddr and waddrgen address space. These are two separate registers, They all need to be loaded, which can display the window (display portion of the memory read-only), And ease of display formats other than 3 component video. C.6 DRAM Interface C.6.1 Overview

In the present invention, the spatial decoder, temporal decoder and the video formatter contains a Special chip DRAM interface block. In all these three devices, DRAM interface function is Provided by the address generator block of the data from the chip address to the external DRAM and from External DRAM into the chip.

Typically, DRAM interface consists of clock operation, this clock with two address generators Is asynchronous, the various blocks of the data transfer clock is asynchronous, however, this tolerance induction is Easy to manage, because the clock is roughly at the same frequency.

DRAM interface and the data is typically in 64 byte blocks transferred between the rest of the chip (At time of forecast data decoder is the only exception). Send generation relies on known "Alternate buffer" of the device. This is essentially a double buffer configuration in working RAMS, and the DRAM interface enables a RAM filled or empty, and then another part of the chip enable Another RAM is empty or filled. Carries an address from the address generator with independent bus Each alternate buffer linked.

Each chip has four alternate buffer, the function of these alternate buffer in each situation State is different. The spatial decoder, a buffer is used to alternately pass DRAM Send coded data, and the other encoded data read from the DRAM, the first three to send a token of DRAM Data, the first four are read from the DRAM token data. Decoding time, a turn DRAM buffer is used to write to the internal or the predictive image data, a second read from the DRAM internal Ministry or predicted image data is read before the other two and the next forecast data. In Video formatter, one alternate buffer is used to transfer data to DRAM, the other three are Is used to read data from the DRAM, for each of the luminance (Y), red color difference data and blue color difference data (Respectively, Cr and Cb) alternating with a buffer. ...

Each chip has four alternate buffer, the function of these alternate buffer in each situation State is different. The spatial decoder, a buffer is used to alternately pass DRAM Send coded data, and the other encoded data read from the DRAM, the first three to send a token of DRAM Data, the first four are read from the DRAM token data. Decoding time, a turn DRAM buffer is used to write to the internal or the predictive image data, a second read from the DRAM internal Ministry or predicted image data is read before the other two and the next forecast data. In Video formatter, one alternate buffer is used to transfer data to DRAM, the other three are Is used to read data from the DRAM, for each of the luminance (Y), red color difference data and blue color difference data (Respectively, Cr and Cb) alternating with a buffer. ...

In the video formatter, data is written to the external DRAM in blocks, but is read in raster order Out. To write, the space has been described with exactly the same decoder, and read a little about the complex Miscellaneous more.

Formatter external DRAM in the video data is organized in a well to at least eight data Blocks are arranged into one. The eight blocks are 8 consecutive horizontal blocks. When rasterized, the need from The eight successive blocks in each of the 8 bytes read, and written in the alternate buffer (i.e., Eight blocks in the same line each).

Consider the top row (assuming a byte-wide interface), x address (3 LSBS) is set Set to zero, the same Y address (3MSBS) is also set to zero. Then, whenever you start 8 bytes Each address is read out when x is increased. In this case, the top address (bit 6 and above_ Lsb = bito) is increased, and the x address (3LSBS) is set to zero. This process is repeated, Until 64 bytes read. For access to the external DRAM with 16 or 32 bit wide interface, x Address just add two or four, rather than one.

Address generator can signal the DRAM interface is less than 64 bytes should be read (this In the beginning and end of the line raster may be required), although typically read a multiple of 8. This By using the start and stop worth to. Starting values ​​are used for the address at the top ( bit 6 and 6 Above), while the stop value is compared with the start value and generates an indication when to stop Read signals. C.7 vertical oversampling C.7.1 Introduction

At its input to a pixel of a color component of the raster scan, according to the present The vertical over-sampler specified to provide a high level of output scan twice. Options allow A variety of ways to form the output pixel value. C.7.2 port

Enter the two-wire interface:

  ·in_valid

  ·in_accept

  ·in_data[7：0]

  ·in_lastpel

  ·in_lastiine

Output wire interface:

  ·out_valid

  ·out_accept

  ·out_data[9：0]

  ·out_last

  mode[2：0]

  nupdata[7：0]，upaddr，upsel[3：0]，uprstr，upwstr   ramtest

  tdin，tdout，tphO，tckm，tcks

phO, ph1, notrstO C.7.3 Wan formula

By entering the bus mode [2:0] select mode

Mode register values ​​1 and 7 are not used

Each of the above manner, the output pixel is 10-bit values ​​instead of bytes. This does not occur in rounding and truncation. To use the same range, where needed, the value Is to the left. C.7.3.1 mode 0: Fifo

Fifo this block only as a memory. Exactly the same number of pixels in the output with the output. This value is to the left 2. C.7.3.2 Mode 2: Repeat

Each line in the input scan is repeated to produce an output scan twice as high. Pixel Value is again to the left 2.

A-> ABACBDBCCDD C.7.3.3 Mode 4: The following (Lower)

Each input line produces two output lines, and in this "Lower" mode, these two rows The second line (the following line in the display) with the same input line. The first line of the pair of Is the current input line into the line and in front of the average. If it is the first input line, without a preceding The lines can be used, the input line is repeated.

When chroma sampling and reduce the brightness of the sample is in the same position, they should choose this mode Style.

A-> ABAC (A + B) / 2DB (B + C) / 2C (C + D) / 2D C.7.3.4 Mode 5: top (upper)

Like "below (Lower) way", but in this case the input line to form the output The rows of the above, and the following lines are adjacent to the average of the input line. The last line of output is Repeat the last input line.

When chroma sampling with upper luminance sample in the same position, you should choose this mode.

A-> AB (A + B) / 2CBD (B + C) / 2C (C + D) / 2DD C.7.3.5 Mode 6: Central (Central)

The "Central" mode corresponding to the luminance sample chroma sampling is located midway between Situation. To make the output color pixel in the same position and the brightness of the pixel. Using weights Average to form the output line.

A-> AB (3A + B) / 4C (A +3 B) / 4D (3B + C) / 4 (B +3 C) / 4 (3C + D) / 4 (C +3 D) / 4D C.7.4 How It Works

There are two rows storage, imagine they are designated as "a" and "b". In the "FIFO" And "duplicate" mode, only the memory row "a". Each memory can hold up to The line 512 pixels (vertical upsampling should be done on the level before sampling), the "FIFO" Mode, the line length is not limited.

Input signal in_Lastpel and in_LastLine used to indicate the end of the input line and Image in the end. In_Lastpel last pixels of each line there should be high. In _LastLine Becomes higher should work with the image of the last pixel of the last line of consistent appearance.

Out_Last output signal at the end of each output line is high when the pixel appears.

In "repeat" mode, each line is written to memory "a". Then this line is read Out two times. When the second time it is read out, the next line may start to be written.

In "lower", "upper" and "central" mode, lines are alternately written into the memory "A" or "b". The first line of the image is always written to the memory "a". 2 small state Machine, each memory one remember what the content of each store, and which output line is Is formed. Generated from these states to go to the line memory RAM read and write requirements, and Determine when to write the next line can be stacked on top of current data signal.

When writing in-Lastpel is high, the register (Lastaddr) memory write address, So as to output line for the formation of the line length. C.7.5 UPI

This includes two 512 × 8 bit RAM arrays, which can be used by the microprocessor interface, A typical method is accessed. Does not exist a microprocessor accessible registers. C.8 horizontal upsampler C.8.1 Overview

In the present invention, the top register includes three of the same one for each color component Horizontal over-sampler. Three independently controlled so that a description of this need. From User point of view, the only difference is that each horizontal upsampler is converted to the memory map Table, a different set of addresses.

Level of implementation of joint copy oversampling and filtering operations. There are four kinds of work:

Table C.7.1 level oversample mode

Mode	Function

	0	Straight (not processed), the reset state
1			Non-cross-use, with the 3-tap FIR filter
	2	x 2Oversampling and filtering
3			x 4Oversampling and filtering

C.8.2 The use of horizontal upsampler

Each horizontal over-sampler address transition diagram of 25 units, corresponding to the 12 13 coefficient register and a 2 way register. Determined number of write mode register Set the working methods, as described in Table C.7.1. Mode can be used according to some or all of Ministry coefficient register. Corresponding FIR filter described below.

According to the work mode, the input X_nIn one, two or four clock cycles remain constant. Mode is programmed for each real coefficient as follows:

Table C.7.2 coefficient of Embodiment 1

Coefficient	All clock cycle
		k0	c00
k1	c10
		k2	c20

Table C.7.3 way a factor of 2

Coefficient	All clock cycle	Second clock cycle
			k0	c00	c01
k1	c10	c11
			k2	c20	c21

Table C.7.4 factor of three ways

Coefficient	Section 1:00 Clock cycle	Section 2:00 Clock cycle	Section 3:00 Clock cycle	Section 4:00 Clock cycle
					k0	c00	c01	c02	c03
k1	c10	c11	c12	c13
					k2	c20	c21	c22	c23

In a particular mode, the coefficients are not being used in that mode is not required to Programming.

For uniform filter, each line of the first and last pixels in the filter before being Repeat. For example, after two times over-sampling after each line of the first and last pixels in a weight Complex 4 times instead of 2 times. Because the remaining data in the filter at the end of each line is discarded, the output The pixels of the input is still always exactly double the number of the data stream, two or four times.

According coefficient values​​, output sampling or sampling together with input from the input taken place or Sample removed. Here are some of the sampling mode in some examples coefficient values. "-" Indicates Coefficient value is "irrelevant." All values ​​are in hexadecimal.

Table C.7.5 sampling coefficient

Coefficient	X 2Oversampling output pixel Consistent with the input pixel	X 2Oversampling output pixel Between the input pixel	x 4Oversampling output pixel Between the input image
				c00	0000	01BD	00E9
c01	0000	010B	00B6
				c02	-	-	012A
c03	-	-	0102
				c10	0800	0538	0661
c11	0400	0538	0661
				c12	-	-	0446
c13	-	-	029F
				c20	0000	010B	OOB6
c21	0400	01BD	00E9
				c22	-	-	0290
c23	-	-	045F

C.8.3 Description of the level of oversampling

Level oversampled data path 168 illustrated in FIG.

The X₄Oversampling case, the job profile is as follows. In addition, X₂Oversampling and X₁Filtering (Mode 2 and 1) of this degenerate bypass (mode 0) throughout the filter, the data from the The final input latches demux straight to the output latch as described below.

1) When valid data is latched in the input latch ("L"), it is maintained for 4 clocks Cycles.

2) each coefficient register (expressed as "COEFF") by a clock cycle is cis Multiplexing sequence to the multiplier, and four pipeline registers (expressed as "PIPE") 2 A device is timing. Therefore, the input data X_n, The first pipeline with a value c00.X_n，c01.X _n， c02.X _n，c03.X _nFill.

3) Similarly, the second multiplier in order to use it by a coefficient X_n, The first three multiplications Used for all its coefficients were multiplied.

You can see the output will be as shown in Table C.7.6 form.

Table C.7.6 output sequence for mode 3

Clock cycle	Export
			0	c20.x n+c10.x n-1+c00.x n-2
1	c21.x n+c11.x n-1+c01.x n-2
		2	c22.x n+c12.x n-1+c02.x n-2
3	c23.x n+c13.x n-1+c03.x n-2

From the output perspective, each clock cycle to form a single pixel. Since each Output pixel 12 is to determine the weights of the input pixel value (although only three different values​​), This can be seen in the x₄Oversampling is performed on the input pixel 12 tap filter. (12 tap filter).

The X₂Oversampling, in addition to the input data is only held for 2 clock cycles, the substance of their work with Same. Furthermore, only two coefficients are used, and "PIPE" blocks described by multiplexer Off selector is shortened. The X₁Filters, input only one clock cycle. If Greece As desired, using a coefficient and a "PIPE" stage.

We now discuss some features of the present invention to achieve some note translation.

1) The datapath width and coefficient width (13 bit 2's complement) can be selected. Thus, When the color space converter can be designed using the same multiplier. The width of the water The purpose of oversampling level is more than adequate.

2) The coefficient of the composite to the multiplier on the multiplexer selector and the data is read back of UPI Enjoy. This leads to some complex graph structure (mainly due to the C code is difficult to form), but the actual Circuit small.

3) as that of the color space converter, carry-save multipliers are used, the results If only in the final solution.

For all levels of the control over-sampling can be regarded as a single two-wire interface level, This interface is formed at its output can be 2 or 4 times its input data. By UPI this method of programming of the programmable shift register (bob) length. The selected Means every clock cycle, every two clock cycles or every four clock cycles, generates an output pulse Overshoot. This in turn controls the main state machine, the main state machine also passed in_valid, out_accept (for two-wire interface) and the signal "in_Last" OK. The signals from the Vertical transmission over sampler, and the last pixel of each line is high. This makes each The first and last pixels of the line repeated twice (twice_over), and the line between the pipeline is cleared In addition to (clearning down). (On one line is completed, the pipeline including the part is processed, Redundant data). C.9 color space converter C.9.1 Overview ...

For all levels of the control over-sampling can be regarded as a single two-wire interface level, This interface is formed at its output can be 2 or 4 times its input data. By UPI this method of programming of the programmable shift register (bob) length. The selected Means every clock cycle, every two clock cycles or every four clock cycles, generates an output pulse Overshoot. This in turn controls the main state machine, the main state machine also passed in_valid, out_accept (for two-wire interface) and the signal "in_Last" OK. The signals from the Vertical transmission over sampler, and the last pixel of each line is high. This makes each The first and last pixels of the line repeated twice (twice_over), and the line between the pipeline is cleared In addition to (clearning down). (On one line is completed, the pipeline including the part is processed, Redundant data). C.9 color space converter C.9.1 Overview ... $\left[\begin{array}{c}y0\\ y1\\ \mathrm{<figure-callout\; id="2"\; label="y"\; filenames="A95103213.506511.png,A95103213.506531.png"\; state="\{\{state\}\}">y</figure-callout>}2\end{array}\right]=\left[\begin{array}{ccc}c01& c02& c03\\ c11& c12& c13\\ c12& c22& \mathrm{<figure-callout\; id="23"\; label="c"\; filenames="A95103213.506921.png,A95103213.507151.png"\; state="\{\{state\}\}">c</figure-callout>}23\end{array}\right]\&times;\left[\begin{array}{c}x0\\ x1\\ x2\end{array}\right]+\left[\begin{array}{c}c04\\ c14\\ \mathrm{<figure-callout\; id="24"\; label="c"\; filenames="A95103213.506591.png,A95103213.506921.png"\; state="\{\{state\}\}">c</figure-callout>}24\end{array}\right]$

Where X_0-2The input data, Y_0-2C is the output data_nmAre coefficients. On the matrix coefficients Not deliberately used traditional names, because these names correspond to signal names in the figure.

CSC can implement a number of different color space conversion, even if only the top register Using a limited set of these conversions. Design color space conversion is as follows:

        E _R，E _G，E _B→Y，C _R，C _B

        R，G，B→Y，C _R，C _B

        Y，C _R，C _B→E _R，E _G，E _B

        Y，C _R，C _B→R，G，B

Where R, G and B (0 ...... 511) range, all other quantities are in the (32 ...... 470) scope. Because the input to the top register CSC is Y, C_R，C _BOnly The first of these equations 3 and 4 are relevant.

In the CSC design, the precision of coefficients can be selected to enable the 9-bit data, all inputs The value of the full floating point simulation of the algorithm, the value A of the positive and negative range. (Which The best accuracy is obtained). This CX₀～CX ₃Gives 13 two's complement factor, and for CX ₄14 shows the coefficients of the two's complement. Conversion coefficients for all design decimal and hexadecimal Band is given as follows:

Table C.8.1 various conversion factor

	E R-＞Y		R-＞Y		Y-＞E R		Y-＞R
									CoeM	Dec	Hex	Dec	Hex	Dec	Hex	Dec	Hax
c0I	O.299	0132	0.256		1.O	04C0	1.159	C4AD
									c02	0.587	0259	0.502		1.402	059C	1.539	C6BE
c03	0.114	0075	0.098		0.0	0000	0.0	0000
									c04	0.0	0000	16		-179.456	F4C8	-223.47a	F15B
c11	0.5	0200	0.428		1.0	0400	1.159	C4AD
									c12	-0.419	FE53	-0.358		-0.714	FD25	-0.335	FCAB
c13	-0.081	FFAD	-0.070		-0.344	FEAO	-0.402	FE54
									c14	128.0	0800	128		135.5	0878	139.7	CEBA
c21	-0.169	FF53	-0.144		1.0	0400	1.159	04AD
									c22	-0.331	FEAD	-0.283		0.0	0000	0.0	00C0
c23	0.5	0200	0.427		1.772	0717	2.071	0849
									c24	128	0800	128		-226.816	FID2	-233.34	EE42

All of these numbers can be calculated from the basic equation:

       Y＝0.299E _R+0.587E _G+0.0114E _BThe color and the following equation:

                 C _R＝E _R－Y

                 C _B＝E _B－Y

R, G and B of the equation is to consider all of these quantities obtained after scaling range. C.9.2 The use of color space converter

At reset, C₀₁，C ₁₂And C₂₃Is set to 1, all other coefficients set to 0. Because This, Y₀＝X ₀，Y ₁＝X ₁，Y ₂＝X ₂And all data pass through unchanged. To select the Color space conversion, simply the appropriate factor (for example, from Table C.8.1) is written to the Address conversion table in a special unit.

Referring to FIG., X_0……2Corresponds to in_data_0……2And Y_0……2Corresponds out_data_0……2. Users should remember that input data to the CSC must be sampled to 4:4:4. If so, not only meaningless color space conversion, and the chip will be locked.

It should be noted that each output from the coefficient input any of the allowed combinations of (Or minus) a constant which is formed. Therefore, for any given color space conversion, the output By switching the order of rows in the matrix converter (i.e. coefficient write address) is changed.

Table C.8.1 CSC ​​can ensure that all the conversion work. If other conversions, the user Must keep in mind the following:

1) If any intermediate result in the calculation requires greater than 10 bits of accuracy (including symbols Bit), the hardware will not work.

2) CSC's output is saturated from 0 to 511. That is, any number less than 0 with 0 generations For, and any number greater than 511, use 511 instead. Saturation logic implementation is only hypothetical results Slightly larger than 511 or slightly less than 0. If the CSC is incorrectly programmed, then the public will sign Is the output of all (or most) time saturation. C.9.3 CSC description

CSC structure 169 illustrated in FIG, due to space limitations, there is only shows three The two components. In the figure, "register" or "R" refers to the main from the register, "latch "Or a" L "refers to a transparent latch.

All coefficients are loaded not significantly represented in the figure write UPI registers. To understand the Its work, the reference leftmost component (which produces output out_data0) Consider the following sequence:

1) the input data reaches X_0-2(in_data0-2). This represents the input color space In a single pixel. This is latched.

2)X ₀Is multiplied by C₀₁And latched into the first pipeline register. X₁And X₂Continue to move A register.

3)X ₁Is multiplied by C₀₂, Is added to the X₁·C ₀₁Go, and latched on to the next pipeline registers Register. X₂Continue moving a register.

4) X is multiplied by C₀₃And (3) adding the results, formation of (X₁·C ₀₁＋X ₂·C ₀₂＋X ₃·C ₀₃). This result is latched into the next pipeline register.

5) (4) results with C₀₄Addition. Because the data retained by the multiplier in the form of binary Hold, which is also used to solve the adder data from the multiplier chain. As a result, latched on to the next Stage pipeline registers.

6) The final operation is the saturation data. Partial results are transmitted from the solution to the full adder And the block in order to achieve this step.

Can be seen as the beginning of this part of the matrix equation result is referred to as Y₀. Similarly, using the same method to form the Y₁And Y₂。

Use of three multipliers, the coefficients as the multiplicand data as a coefficient. This can be obtained A valid solution, and the downward part of the results along the data path, the same input data through the 3 And the same parallel data paths, one for each output.

In order to achieve the said section C.9.2 reset state, three components must be used for each Different methods reset. In order to avoid having three set program (Schematics) and three kinds of slightly With the wiring diagram (Layout), right at the top forced into a high or low output UPI register Into.

CSC almost no control associated with it. Nevertheless, each pipeline stage is a Wire interface level, it is effective to receive a latch chains and their associated Control (in_accept = out_accept_r + Lin_Valid-r). Therefore, CSC is an A five deep-wire interface, when stopped to retain 10 data layers.

CSC output includes resync latch, because the output of the next line Feature does not consider a different clock generator. C.10 Output Controller C.10.1 Foreword

Output controller according to the present invention has the following features:

· It is in one of three ways a way to provide data

· 24-bit 4:4:4

· 16-bit 4:2:2

· 8-bit 4:2:2

· It alignment data to the video display window that pulse through vsync and hsync And programmable time register definitions.

• If necessary, add a border it around the video window. C.10.2 port

Enter the two-wire interface:

·in_Valid

·in_accept

·in_data[23：0]

Output wire interface:

·out_Valid

·out_accept

·out_data[23：0]

·out_active

·out_window

·out_comp[1：0]

in_vsync，in_hsync

nupdata [7:0], upaddr [4:0], upsel, rstr, wstr, tdin, tdout, tph0, tckm, tcks, chiptest, Ph0, Ph1, notrst0, notrstl. C.10.3 output

The format of the output register by writing to the choice of working methods C.10.3.1 way 0

This approach is 24 4:4:4 RGB or YCrCB. Input data is passed directly to the output. C.10.3.2 Modes 1 and 2

These methods provide 4:2:2 YCrCb, assuming in_data [23:16] is Y, in_ data [15:8] is Cr, and in_data [7:0] are Cb. C.10.3.2.1 way a

In 16-bit YCrCb, Y is presented in out_data [15:8] on. Cr and Cb multiplexed To out_data [7:0] on-time, Cb first. out_data [23:16] are not used. C.10.3.2.2 Mode 2

In an 8-bit YCrCb, Y, Cr and Cb are in accordance with the Cb, Y, Cr, Y multiplexing order of Bonded to out_data [7:0] on the time. out_data [23:8] are not used. C.10.3.3 Output Timing

In the video display window, the following registers are used to put the data.

· Vdelay-in video or border before the first row, after the pulse with the vsync The number of hsync pulses.

· Hdelay-hsync and video or borders in the first clock cycle between pixels Number

· Height-video window height, in number of lines as a unit.

· Width-video window width, in number of pixels as a unit.

· North, south-respectively above and below the video window frame height, The number of lines as a unit.

· West, east-namely the video window on the left and right border width, Pixels.

Minimum vdelay zero. The first hsync is the first active line. Can be programmed into the hdelay the minimum is 2. It should be noted, however, from in_hsync to an effective output The actual pixel delay hdelay +1 cycles.

Any side edge may have a value of zero. By writing to the register border-r, border-g And border-b Select the border color. By writing to the register bank-r, bank-g and bank-b Select the border color of the outer region. Note that in the output mode 1 and 2 perform multiplexed Will also affect the border and blank components. That is, the values ​​in these registers correspond to in_ data [23:16], in_data [15:8] and in_data [7:0]. C.10.4 output tag

· Out_activo indicates the output data is valid part of the window, that video data Or borders.

· Out_window that the output data is part of the video window.

· Out_comp [1:0] indicates the color components present in the output mode 1 and 2 out_ data [7:0] on. In mode 1, 0 = Cb, 1 = Cr. In mode 2, 0 = Y, 1 = Cr, 2 = Cb. C.10.5 two-way

In the present invention, through the double register to write a two-way to select. It is not in Reset after being selected. In the two-mode, the output timing registers and sync signals are Is ignored, and the block control data flow from the out_accept. Note that, in normal operation In, out_accept should be maintained at the high level. C10.6 Kuice device

Are placed in a super glimpse into the output of the block, this includes access to the output labeled Asked. C.10.7 How it works

Two identical down counter records the current position of the display. "Vcount" Right hsyncs counting down, and from the appropriate timing registers for Vsync loaded or in its final Count when loaded. "Hcount" counts down for each pixel, and hsync loaded or in It ultimately count loaded. Note that in the output mode 2, a pixel is quite two Clock cycle. C.11 clock divider C.11.1 Overview

The top layer in the present invention includes two identical register clock divider, a production process Health PICTURE_CLK, another generation AUDIO_CLK. Clock divider is the same and is independent Vertical control. Therefore, in this one just described. From the user point of view, two clock divider The only difference is the divisor register is mapped into the memory address in a different location map.

Clock divider is to provide a 4X SYSCIK is divided clock frequency, And for equality duty (mark-space) is not required.

Divisor required range from 0 to 16,000,000, 24 so it can be used to represent. And limit the minimum divisor of 16. This is because by using a half divisor, the clock frequency Device will be close to one and the same duty cycle (in one SYSCLK cycle) because most available Big clock frequency is SYSCLK, the maximum available crossover rate SYSCLK / 2. Furthermore, Because in cascade using four counters, the divisor / 2 must never less than 8, or lose The divided clock is driven to the positive supply. C.11.2 use the clock divider

Each clock divider address translation by the four units, which correspond to three 8 except Number of registers and a 1 Access Register. Clock divider is inactive when power is initially, when the Its divisor registers are accessed by the active.

C.10.1 divisor register in accordance with the address conversion table in any order written. Clock Divider in its position by the detected synchronization 0 to 1 transition is activated. Open Began detecting a conversion, clock divider will leave the reset state, and generates a divide by Minutes. Subsequent conversion (assuming the divisor has changed) only the clock divider is locked to a new The frequency of "on-the-fly". Once activated, in addition to the chip reset, but can not be stopped Clock divider.

Table C.10.1 clock divider register

Address	Register
		00b	Access Bit
01b	Divisor highest bit (MSB)
		10b	Divisor
11b	Divisor lowest bit (LSB)

In addition to values ​​available range from 14 to 16,77,216. C.11.3 clock divider description

Clock divider are available 4 22 counter implementation. These counters are connected together into a class, So that when a counter carry bit, which in turn activate the next counter. One count Before the carry device, the counter by 1/4 divider divisor values​​. Therefore, each counter will turn Receives it, to form the frequency divided clock pulses.

Carry later, the counter will divisor / 8 reload, and was divided produce roughly the same The duty cycle of the clock frequency. Since each counter is pre-counter activated it from the Divisor register before loading them. On_thd_fly divided clock frequency can be changed. These Changed simply by changing the contents of the divisor and implementation.

Each counter with its own independent clock generator timing to precisely control Clock alignment between the counters and make each counter clock devices by different timings.

A state machine controls the divisor / 4 and divisor / 8 values ​​is formed. While also correct source Clock from the PLL (PLL) clock generator multiplexed to go. According to the value of the divisor, namely, Number of devices by different clock timing. This is because different values ​​formed in addition to the divided clock whose Edge with PLL provides different combinations depending on the clock. C.11.4 test clock divider

Clock divider can be used CHIPTEST power to the chip is high on the test. So The effect is oblige all clocks within the clock divider logic with SYSCIK time, with phase The clock generated by the PLL.

Clock divider has a full scan design, so the next step can use the standard JTAG test access, as long as the chip is powered up.

If the device is running in order to work properly, CHIPTEST remains high, then the clock Divider function can not be guaranteed. C.12 address translation C.12.1 top level address translation

Note:

1) the top-level address translation registers in Table C.11.1 set, is set Name to be used for accounting periods. These names do not need to appear in the data table.

2) Since this is a full address transformation unit comprises a number listed here only for measurement Try to use the unit.

Table C.11.1 top register A top-level address translation

Register name	Address	Position	Note
				BU_EVENT	0x0	8	Write a Reset
BU_MASK	0x1	8	R/W
				BU_EN_INTERRUPTS	0x2	1	R/W
BU_WADDR_COD_STD	0x4	2	R/W
				BU_WADDR_ACCESS	0x5	1	R / W access
BU_WADDR_CTL1	0x6	3	R/W
				BU_DISPADDR_LINES_IN_LAST_ROW0	0x8	3	R/W
BU_DISPADDR_LINES_IN LAST_ROW1	0x9	3	R/W
				BU_DISPADDR_UNES_IN_LAST_ROW2	0xa	3	R/W
BU_DISPADDR_ACCESS	0xb	1	R / W access
				BU_DISPADDR_CTL0	0xc	8	R/W
BU_DISPADDR_CTL1	0xd	1	R/W
				BU_BM_ACCESS	0x10	1	R/W-access
BU_BM_CTL0	0x11	2	R/W
				BU_BM_TARGET_IX	0x12	4	R/W
BU_BM_PRES_NUM	0x13	8	R / W asynchronous
				BU_BM_THIS_PNUM	0x14	8	R/W
BU_BM_PIC_NUM0	0x15	8	R/W
				BU_BM_PIC_NUM1	0x16	8	R/W
BU_BM_PIC_NUM2	0x17	8	R/W
				BU_BM_TEMP_REF	0x18	5	RO

Register name	Address	Position	Note
				BU_ADDRGEN_KEYHOLE_ADDR_MSB	0x29	1	R / W address generator Kuice device Table C.11.2 content
BU_ADDRGEN_KEYHOLE_ADDR_LSB	0x29	8
			BU_ADDRGEN_KEYHOLE_ODATA	0x2a	a
BU_IT_PAGE_START	0x00	5				R/W
			BU_IT_READ_CYCLE	0x31	4		R/W
BU_IT_WRITE_CYCLE	0x32	4				R/W
			BU_IT_REFRESH_CYCLE	0x33	4		R/W
BU_IT_RAS_FALUNG	0x34	4				R/W
			BU_IT_CAS_FALLING	0x35	4		R/W
BU_IT_CONFIG	0x36	1				R/W
			BU_OC_ACCESS	0x40	1		R / W access
BU_OC_MODE	0x41	2				R/W
			BU_OC_2WIRE	0x42	1		R/W
BU_OC_BOROER_R	0x49	8				R/W
			BU_OC_BORDER_G	0x4a	8		R/W
BU_OC_BORDER_B	0x4b	8				R/W
			BU_OC_BLANK_R	0x4d	8		R/W
BU_OC_BLANK_G	0x4e	8				R/W
			BU_OC_BLANK_9	0x4f	8		R/W
BU_OC_MDELAY_1	0x50	3				R/W
			BU_OC_HDELAY_0	0x51	8		R/W
BU_OC_WEST_1	0x52	3				R/W
			BU_OC_WEST_0	0x53	8		R/W
BU_OC_EAST_1	0x54	3				R/W
			BU_CC_EAST_0	0x55	8		R/W
BU_OC_WIDTH_0	0x56	3				R/W
			BU_OC_WIDTH_0	0x57	8		R/W
BU_OC_VDELAY_1	0x5a	3				R/W
			BU_OC_VDELAY_0	0x59	8		R/W
BU_OC_NORTH_1	0x5a	3				R/W
			BU_OC NORTH_0	0x5b	8		R/W
BU_OC_SOUTH_1	0x5c	3				R/W
			BU_OC_SOUTH_0	0x5d	8		R/W
BU_OC_HEIGHT_1	0x5e	3				R/W
			BU_OC_HEIGHT_0	0x5f	8		R/W

Table C.11.1 top register A top-level address translation (continued)

Register name	Address	Position	Note
				BU_IF_CONFIGURE	0x60	5	R/W
BU_UV_MDDE	0x61	6	R/W-xnnnxnnn
				BU_COEFF_KEYADDR	0x62	7	R/W-See TabieO11.3 forconterts
BU_COEFF_KEYDATA	0x63	8
			BU_GA_ACCESS	0x68	1	R/W
BU_GA_BYPASS	0x69	1					R/W
			BU_GA_RAM0_ADDR	0x6a	8	R/W
BU_GA_RAM0_DATA	0x6b	8					R/W
			BU_GA_RAM1_ADDR	0x6c	8	R/W
BU_GA_RAM1_DATA	0x6d	8					R/W
			BU_GA_RAM2_ADDR	0x6e	8	R/W
BU_GA_RAM2_DATA	0x6f	8					R/W
			BU_DIVA_3	0x70	1	R/W
BU_DIVA_2	0x71	8					R/W
			BU_DIVA_1	0x72	8	R/W
BU_DIVA_0	0x73	8					R/W
			BU_DIVA_3	0x74	1	R/W
BU_DIVA_2	0x75	8					R/W
			BU_DIVA_1	0x76	8	R/W
BU_DIVA_0	0x77	8					R/W
			BU_PAD_CONFIG_1	0x78	7	R/W
BU_PAD_CONFIG_0	0x79	8					R/W
			BU_PLL_RESISTORS	0x7a	8	R/W
BU_REF_INTERVAL	0x7b	8					R/W
			BU_REVISION	0xff
	8	RO-revision
			The following registers in the test space They differ in the data table
BU_BM_PRES_FLAG	0x80	1					R/W
			BU_BM_EXP_TR	0x81
	2	These registers are missing on revA
			BU_BM_TR_DELTA	0x82
	2
		BU_BM_ARR_IX	0x83	2	R/W
BU_SM_DSP_IX	0x84					2	R/W
		BU_BM_RDY_IX	0x85	2	R/W
BU_BM_BSTATE3	0x86					2	R/W
		BU_BM_BSTATE2	0x87	2	R/W

Table C.11.1 top register A top-level address translation (continued)

Register name	Address	Position	Note
				BU_BM_BSTATE1	0x88	2	R/W
BU_BM_INDEX	0x89	2	R/W
				BU_B_STATE	0x8a	5	R/W
BU_BM_FROMPS	0x8b	1	R/W
				BU_BM_FROMFL	0x8c	1	R/W
BU_DA_COMP0_SNP3	0x90	8	R / W in the display address Address generator output Kuice on the device
				BU_DA_COMP0_SNP2	0x91
	8
		BU_DA_COMP0_SNP1		0x92		8
BU_DA_COMP0_SNP0	0x93							8
		BU_DA_COMP1_SNP3		0x94		8
BU_DA_COMP1_SNP2	0x95							9
		BU_DA_COMP1_SNP1		0x96		8
BU_DA_COMP1_SNP0	0x97							8
		BU_DA_COMP2_SNP3		0x98		8
EU_DA_COMP2_SNP2	0x99							8
		BU_DA_COMP2_SNP1		0x9a	8
BU_DA_CCMP2_SNP0	0x9b					8
		BU_UV_RAM1A_ADDR_1	0xa0	8	R / W on the vertical oversampling The test sample RAM upi Test Access
BU_UV_RAM1A_ADDR_0	0xa1
			8
BU_UV_RAM1A_DATA	0xa2					9
		BU_UV_RAM1B_ADDR_1	0xa4					8
BU_UV_RAM1B_ADDR_0	0xa5					8
		BU_UV_RAM1B_OATA	0xa6					8
BU_UV_RAM2A_ADDR_1	0xa9					8
		BU_UV_RAM2A_ADDR_0	0xa9					8
BU_UV_RAM2A_DATA	0xaa					8
		BU_UV_RAM2B_ADDR_1	0xac					8
BU_UV_RAM2B_ADDR_0	0xad					8
		BU_UV_RAM2B_DATA	0xae					8
BU_WA_ADDR_SNP2	0xb0			8	R / W in the write address sent Address output of the generator Kuice on the management device
		BU_WA_ADDR_SNP1	0xb1
	8
		BU_WA_ADDR_SNP0	0xb2	8
EU_WA_DATA_SNP1	0xb4				8	R / W WA Data output Kuice on device
		BU_WA_DATA_SNP0	0xb5
	8

Table C.11.1 top register A top-level address translation (continued)

Table C.11.1 top register A top-level address translation (continued)

Register name	Address	Position	Note
				BU_IF_SNP0_1	0xb8	8	R / W, the number dramif According to the output of the three Kuice device
BU_IF_SNP0_0	0xb9
			8
BU_IF_SNP1_1	0xba				8
		BU_IF_SNP1_0	0xbb			8
BU_IF_SNP2_1	0xbc			8
		BU_IF_SNP2_0	0xbd		8
BU_IFRAM_ADDR_1	0xc0			1		R / W if RAM UPI Accessed
		BU_IFRAM_ADDR_0	0xc1				8
BU_IFRAM_DATA	0xc2			8
		BU_OC_SNP_3	0xc4		8		R / W chip outputs Kuice on the device
BU_OC_SNP_2	0xc5
			8
BU_OC_SNP_1	0xc6			8
		BU_OC_SNP_0	0xc7		8
BU_YAPLL_CONFIG	0xc8			8		R/W
		BU_BM_FRONT_BYPASS	0xca		1		R/W

Table C.11.2 Top-Level Registers A address generator keyhole

Keyhole register name	Keyhole Address	Position	Note
				BU_DISPADDR_BUFFER0_BASE_MSB	0x01
	2	8 Register Must Load
			BU_DISPADDR_BUFFEA0_BASE_MID	0x02		3
BU_DISPADDR_BUFFER0_BASW_LSB	0x03							3
			BU_DISPADDR_BUFFER1_BASE_MSB	0x05		2			Must Load
BU_DISPADDR_BUFFER1_3ASE_MID	0x06
			3
BU_DISPADDR_BUFFER1_BASE_LSB	0x07				8
		BU_DISPADDR_BUFFER2_BASE_MSB	0x09				2	Must Load
BU_DISPADDR_BUFFER2_BASE_MID	0x0a
			8
BU_DISPADDR_BUFFER2_BASE_LSB	0x0b			3
		BU_DLDPATH_LINE0_MSB	0x0d			2	Only for Test
BU_DLDPATH_LINE0_MID	0x0e
			3
BU_DLDPATH_UNE0_LSB	0x0f				8
		BU_DLDPATH_UNE1_MSB	0x11				2	Only for Test
BU_DLDPATH_UNE1_MID	0x12
			3
BU_DLDPATH_LINE1_LSB	0x13				3
		BU_DLDPATH_LINE2_MSB	0x15				2	Only for Test
BU_DLDPATH_UNE2_MID	0x16
			3
BU_DLDPATH_UNE2_LSB	0x17				3
		BU_DLDPATH_VBCNT0_MSB	0x19				2	Only for Test
BU_DLDPATH_VBCNT0_MID	0x1a
			3
BU_DLDPATH_VBCNT0_LSB	0x1b			3
		BU_DLDPATH_VBCNT1_MSB	0x1d			2	Only for Test
BU_DLDPATH_VBCNT1_MID	0x1e
			3
BU_DLDPATH_VBCNT1_LSB	0x1f				3
		BU_DLCPATH_VBCNT2_MSB	0x21				2	Only for Test
BU_DLCPATH_VBCNT2_MID	0x22
			3
BU_DLDPATH_VBCNT2_LSB	0x23				3

Table C.11.2 Top-Level Registers A address generator keyhole (continued)

Keyhole register name	Keyhole Address	Position	Note
				BU_DISPADDR_COMP0_OFFSET_MSB	0x25
	2	Must Load
			BU_DISPADDR_COMP0_OFFSET_MID	0x25
	3
			BU_DISPADDR_COMP0_OFFSET_LSB	0x27		8
BU_DISPADDR_COMP1_OFFSET_MSB	0x29						2	Must Load
			BU_DISPADDR_COMP1_OFFSET_MID	0x2a
	8
		BU_DISPADDR_COMP1_OFFSET_LSB	0x2b	8
BU_DISPADDR_COMP2_OFFSET_MSB	0x2d					2	Must Load
		BU_DISPADDR_COMP2_OFFSET_MID	0x2e
	8
		BU_DISPADDR_COMP2_OFFSET_LSB	0x2f		2
BU_DISPADDR_COMP0_VBS_MSB	0x31						2	Must Load
		BU_DISPADDR_COMP0_VBS_MID	0x32
	8
		BU_DISPADDR_COMP0_VBS_LSB	0x33		8
BU_DISPADDR_COMP1_VBS_MSB	0x35						2	Must Load
		BU_DISPADDR_COMP1_VBS_LSB	0x36
	8
		BU_DISPADDR_COMP2_VBS_MID	0x37		2
BU_DISPADDR_COMP2_VBS_MSB	0x39						2	Must Load
		BU_DISPADDR_COMP2_VBS_MID	0x3a
	8
		BU_DISPADDR_COMP2_VBS_LSB	0x3b	3
BU_ADDR_COMP0_HBS_MSB	0x3d					2	Must Load
		BU_ADDR_COMP0_HBS_MID	0x3e
	8
		BU_ADDR_COMP0_HBS_LSR	0x31		8
BU_ADDR_COMP1_HBS_MSB	0x41						2	Must Load
		BBU_ADDR_COMP1_HBS_MID	0x42
	9
		BU_ADDR_COMP1_HBS_LSB	0x43		8
BU_ADDR_COMP2_HBS_MSB	0x45						2	Must Load
		BU_ADDR_COMP2_HBS_MID	0x46
	9
		BU_ADDR_COMP2_HBS_LSB	0x47		3
BU_DISPADDR_COMP0_HBS_MSB	0x49						2	Must Load
		BU_DISPADDR_COMP0_HBS_MID	0x4a
	9
		BU_DISPADDR_COMP0_HBS_LSB	0x4b	8
BU_DISPADDR_COMP1_HBS_MSB	0x4d					2	Must Load
		BU_DISPADDR_COMP1_HBS_MID	0x4e
	3
		BU_DISPADDR_COMP1_HBS_LSB	0x4f		8

Table C.11.2 Top-Level Registers A address generator keyhole (continued)

Keyhole register name	Keyhole Address	Position	Note
				BU_DISPADDR_COMP2_HBS_MSB	0x51
	2	Must Load
			BU_DISPADDR_COMR2_HBS_MID	0x52
	3
			BU_DISPADDR_COMP2_HBS_LSB	0x53		3
BU_DISPADDR CNT_left0_MSB	0x55						2	Only for Test
			BU_DISPADDR_CNT_left0_MID	0x55
	3
		BU_DISPADDR_CNT_left0_LSB	0x57		3
BU_DISPADDR_CNT_left1_MSB	0x59						2	Only for Test
		BU_DISPADDR_CNT_left1_MID	0x5a
	8
		BU_DISPADDR_CNT_left1_LSB	0x5b		8
BU_DISPADDR_CNT_left2_MSB	0x5d						2	Only for Test
		BU_DISPADDR_CNT_left2_MID	0x5e
	3
		BU_DISPADDR_CNT_left2_LSB	0x5f		8
BU_DISPADDR_PAGE_ADDR0_MSB	0x61						2	Only for Test
		BU_DISPADDR_PAGE_ADDR0_MID	0x62
	8
		BU_DISPADDR_PAGE_ADDR0_LSB	0x53		3
BU_DISPADDR_PAGE ADDR1_MSB	0x55						2	Only for Test
		BU_DISPADDR_PAGE_ADDR1_MID	0x66
	3
		BU_DISPADDR_PAGE_ADDR1_LSB	0x67		8
BU_DISPADDR_PAGE_ADDR2_MSB	0x69						2	Only for Test
		BU_DISPADDR_PAGE_ADDR2_LSB	0x6a
	8
		BU_DISPADDR_PAGE_ADDR2_MID	0x5b		2
BU_DISPADDR_BLOCK_ADDR0_MSB	0x6d						2	Only for Test
		BU_DISPADDR_BLOCK_ADDR0_MID	0x5e
	3
		BU_DISPADDR_BLOCK_ADDR0_LSB	0x6f		3
BU_DISPADDR_BLOCK_ADDR1_MSB	0x71						2	Only for Test
		BU_DISPADDR_BLOCK_ADDR1_MID	0x72
	8
		BU_DISPADDR_BLOCK_ADDR1_LSB	0x73		8
BU_DISPADDR_sLOCK_ADDR2_MSB	0x75						2	Only for Test
		BU_DISPADDR_SLOCK_ADDR2_MID	0x76
	3
		BU_DISPADDR_BLOCK_ADDR2_LSB	0x77		8
BU_DISPADDR_BLOCKS_left0_MSB	0x79						2	Only for Test
		BU_DISPADDR_BLOCKS_left0_MID	0x7a
	8
		BU_DISPADDR_BLOCKS_left0_LSB	0x7b		3

Table C.11.2 Top-Level Registers A address generator keyhole (continued)

Keyhole register name	Keyhole Address	Position	Note
				BU_DISPADDR_BLOCKS_left1_MSB	0x7d
	2	Only for Test
			BU_DISPADDR_BLOCKS_left1_MID	0x7e
	8
			BU_DISPADDR_BLOCKS_left1_LSB	0x7f		3
BU_DISPADDR_BLOCKS_left2_MSB	0x81						2	Only for Test
			BU_DISPADDR_BLOCKS_left2_MID	0x82
	3
		BU_DISPADDR_BLOCKS_left2_LSB	0x83		2
BU_WADDR_BUFFER0_BASE_MSB	0x85						2	Must Load
		BU_WADDR_BUFFER0_BASE_LSB	0x86
	8
		BU_WADDR_BUFFER1_BASE_MSB	0x87		3
BU_WADDR_BUFFER1__BASE_MSB	0x89						2	Must Load
		BU_WADDR_BUFFER1_BASE_MID	0x8a
	8
		BU_WADDR_BUFFER1_BASE_LSB	0x8b	8
BU_WADDR_BUFFER2_BASE_MSB	0x8d					2	Must Load
		BU_WADDR_BUFFER2_BSE_MID	0x8e
	8
		BU_WADDR_BUFFER2_BASE_LSB	0x8f		8
BU_WADDR_COMP0_HMBADDR_MSB	0x91						2	Only for Test
		BU_WADDR_COMP0_HMSADDR_MID	0x92
	8
		BU_WADDR_COMP0_HMBADDR_LSB	0x93		8
BU_WAODR_COMP1_HMBAOOR_MSB	0x95						2	Only for Test
		BU_WADDR_COMP1_HMBADDR_MID	0x96
	3
		BU_WADDR_COMP1_HMBADDR_LSB	0x97		3
BU_WADDR_COMP2_HMBADDR_MSB	0x99						2	Only for Test
		BU_WADDR_COMP2_HMBADDR_MID	0x9a
	3
		BU_WADDR_COMP2_HMBADDR_LSB	0x9b	3
BU_WADDR_COMP0_VMBADDR_MSB	0x9d					2	Only for Test
		BU_WADDR_COMP0_VMBADDR_MID	0x9e
	3
		BU_WADDR_COMP0_VMBADDR_LSB	0x9f		8
BU_WADDR_COMP1_VMBADDR_MSB	0xa1						2	Only for Test
		BU_WADDR_COMP1_VMBADDR_MID	0xa2
	8
		BU_WADDR_COMP1_VMBADDR_LSB	0xa3		8
BU_WADDR_C0MP2_VMBADDR_MSB	0xa5						2	Only for Test
		BU_WADDR_COMP2_VMBADDR_MID	0xa6
	8
		BU_WADDR_COMP2_VMBADDR_LSB	0xa7		3

Table C.11.2 Top-Level Registers A address generator keyhole (continued)

Keyhole register name	Keyhole Address	Position	Note
				BU_WADDR_VBADDR_MSB	0xa9
	2	Only for Test
			BU_WADDR_VBADDR_MID	0xaa
	9
			BU_WADDR_VBADDR_LSB	0xab	3
BU_WADDR_COMP0_HALF_WIDTH_IN_BLOCKS_MSB	0xad					2	Must Load
			BU_WADDRR_COMP0_HALF_WIDTH_IN_BLCCKS_MID	0xae
	3
		BU_WADDR_COMP0_HALF_WIDTH_IN_BLCCKS_LSB	0xaf	8
BU_WADDR_COMP1_HALF_WIDTH_IN_BLCCKS_MSB	0xb1					2	Must Load
		BU_WADDRR_COMP1_HALF_WIDTH_IN_BLOCKS_MID	0xb2
	8
		BU_WADDR_COMP1_HALF_WIDTH_IN_BLOCKS_LSB	0xb3	8
BU_WADDR_COMP2_HALF_WIDTH_IN_BLOCKS_MSB	0xb5					2	Must Load
		BU_WADDR_COMP2_HALF_WIDTH_IN_BLOCKS_MID	0xb6
	8
		BU_WADDR_COMP2_HALF_WIDTH_IN_BLOCKS_LSB	0xb7	8
BU_WADDR_HB_MSB	0xb9					2	Only for Test
		BU_WADDR_HB_MID	0xba
	8
		BU_WADDR_HB_LSB	0xbb	8
BU_WADDR_COMP0_OFFSET_MSB	0xbd					2	Must Load
		BU_WADDR_COMP0_OFFSET_MID	0xbe
	8
		BU_WADDR_COMP0_OFFSET_LSB	0xbf	8
BU_WADDR_COMP1_OFFSET_MSB	0xc1					2	Must Load
		BU_WADDR_COMP1_OFFSET_MID	0xc2
	8
		BU_WADDR_COMP1_OFFSET_LSB	0xc3	8
BU_WADDR_COMP2_OFFSET_MSB	0xc5					2	Must Load
		BU_WADDR_COMP2_OFFSET_MID	0xc6
	3
		BU_WADDR_COMP2_OFFSET_LSB	0xc7	3
BU_WADDR_SCRATCH_MSB	0xc9					2	Only for Test
		BU_WADDRR_SCRATCH_MID	0xca
	9
		BU_WADDR_SCRATCH_LSB	0xcb	8
BU_WADDR_MBS_WIDE_MSB	0xcd					2	Must Load
		BU_WADDR_MBS_WIDE_MID	0xce
	8
		BU_WACDR_MBS_WIDE_LSB	0xcf	8
BU_WADDR_MSS_HIGH_MSB	0xd1					2	Must Load
		BU_WADDR_MBS_HIGH_MID	0xd2
	3
		BU_WADDR_MBS_HIGH_LSB	0xd3		3

Table C.11.2 Top-Level Registers A address generator keyhole (continued)

Keyhole register name	Keyhole Address	Position	Note
				BU_WADDR_COMP0_LAST_MB_IN_ROW_MSB	0xd5
	2	Must Load
			BU_WADDR_COMP0_LAST_MB_IN_ROW_MID	0xd6
	8
			BU_WADDR_COMP0_LAST_MB_IN_ROW_LSB	0xd7	8
BU_WADDR_COMP1_LAST_MB_IN_ROW_MSB	0xd9					2	Must Load
			BU_WADDR_COMP1_LAST_MB_IN_ROW_MID	0xda
	8
		BU_WADDR_COMP1_LAST_MB_IN_ROW_LSB	0xdb	8
BU_WADDR_C0MP2_LAST_MB_IN_ROW_MSB	0xdd					2	Must Load
		BU_WADDR_COMP2_LAST_MB_IN_ROW_MID	0xde
	8
		BU_WADDR_COMP2_LAST_MB_IN_ROW_LSB	0xdf		8
BU_WADDR_COMP0_LAST_MB_IN_HALF_ROW_MSB	0xe1						2	Must Load
		BU_WADDR_COMP0_LAST_MB_IN_HALF_ROW_MID	0xe2
	8
		BU_WADDR_COMP0_LAST_MB_IN_HALF_ROW_LSB	0xe3	8
BU_WADDR_C0MP1_LAST_MB_IN_HALF_ROW_MSB	0xe5					2	Must Load
		BU_WADDR_COMP1_LAST_MB_IN_HALF_ROW_MID	0xe5
	8
		BU_WADDR_COMP1_LAST_MB_IN_HALF_ROW_LSB	0xe7	8
BU_WADDR_COMP2_LAST_MB_IN_HALF_ROW_MSB	0xe9					2	Must Load
		BU_WADDR_COMP2_LAST_MB_IN_HALF_ROW_MID	0xea
	8
		BU_WADDR_COMP2_LAST_MB_IN_HALF_ROW_LSB	0xeb		8
BU_WADDR_COMP0_LAST_ROW_IN_MB_MSB	0xed						2	Must Load
		BU_WADDR_COMP0_LAST_ROW_IN_MB_MID	0xee
	8
		BU_WADDR_COMP0_LAST_ROW_IN_MB_LSB	0xef	8
BU_WADDR_COMP1_LAST_ROW_IN_MB_MSB	0xf1					2	Must Load
		BU_WADOR_COMP1_LAST_ROW_IN_MB_MID	0xf2
	8
		BU_WADDR_COMP1_LAST_ROW_IN_MB_LSB	0xf3	8
BU_WADDR_COMP2_LAST_ROW_IN_MB_MSB	0xf5					2	Must Load
		BU_WADDR_COMP2_LAST_ROW_IN_MB_MID	0xf6
	8
		BU_WADDR_COMP2_LAST_ROW_IN_MB_LSB	0xf7	8
BU_WADDR_COMP0_BLOCKS_PER_MB_ROW_MSB	0xf9					2	Must Load
		BU_WADDR_COMP0_BLOCKS_PER_MB_ROW_MID	0xfa
	8
		BU_WADDR_COMP0_BLOCKS_PER_MB_ROW_LSB	0xfb	8
BU_WADDR_COMP1_BLOCKS_PER_MB_ROW_MSB	0xfd					2	Must Load
		BU_WADDR_COMP1_BLOCKS_PER_MB_ROW_MID	0xfe
	8
		BU_WADDR_COMP1_BLOCKS_PER_MB_ROW_LSB	0xff		9

Table C.11.2 Top-Level Registers A address generator keyhole (continued)

Keyhole register name	Keyhole Address	Position	Note
				BU_WADDR_COMP2_BLOCXS_PER_MB_ROW_MSB	0x101
	2	Must Load
			BU_WADDR_COMP2_BLOCKS_PER_MB_ROW_MID	0x102
	8
			BU_WADDR_COMP2_BLOCKS_PER_MB_ROW_LSB	0x103		8
BU_WADDR_COMP0_LAST_MB_ROW_MSB	0x105						2	Must Load
			BU_WADDR_COMP0_LAST_MB_ROW_MID	0x106
	8
		BU_WADDR_COMP0_LAST_MB_ROW_LSB	0x107		8
BU_WADDR COMP_LAST_MB_ROW_MSB	0x109						2	Must Load
		BU_WADDR_COMP1_LAST_MB_ROW_MID	0x10a
	8
		BU_WADDR_COMP1_LAST_MB_ROW_LSB	0x10b	8
BU_WADDR_COMP2_LAST_MB_ROW_MSR	0x10d					2	Must Load
		BU_WADDR_CCMP2_LAST_MB_ROW_MID	0x10e
	8
		BU_WADDR_COMP2_LAST_MB_ROW_LSB	0x10f	8
BU_WADDR_COMP0_HBS_MSB	0x111					2	Must Load
		BU_WADDR_COMP0_HBS_MID	0x112
	8
		BU_WADDR_COMP0_HBS_LSB	0x113		8
BU_WADDR_COMP1_HBS_MSB	0x115						2	Must Load
		BU_WADDR_COMP1_HBS_MID	0x115
	8
		BU_WADDR_COMP1_HBS_LSB	0x117		8
BU_WADDR_COMP2_HBS_MSB	0x119						2	Must Load
		BU_WADDR_COMP2_HBS_MID	0x11a
	8
		BU_WADDR_COMP2_HBS_LSB	0x11b	8
BU_WADDR_COMP0_MAXHB	0x11f					2	Must Load
		BU_WADDR_COMP1_MAXHB	0x123					2
BU_WADDR_COMP2_MAXHB	0x127					2
		BU_WADDR_COMP0_MAXVB	0x125					2	Must Load
BU_WADDR_COMP1_MAXVB	0x121
			2
BU_WADDR_COMP2_MAXVB	0x133				2

Table c.11.3. Horizontal spatial oversampling and C keyhole address conversion table

Keyhole Storage Server name	Keyhole Address	Position	Note
				BU_UH0_A00_1	0x0	5	R/W-Coeff0.0
BU_UH0_A00_0	0x1		8
				BU_UH0_A01_1	0x2	5		R/W-Coeff0.1
BU_UH0_A01_0	0x3		8
				BU_UH0_A02_1	0x4	5	R/W-Coeff0.2
BU_UH0_A02_0	0x5		8
				BU_UH0_A03_1	0x6	5		R/W-Coeff0.0
BU_UH0_A03_0	0x7		8
				BU_UH0_A10_1	0x8	5	R/W-Coeff1.0
BU_UH0_A10_0	0x9		8
				BU_UH0_A11_1	0xa	5		R/W-Coeff1.1
BU_UH0_A11_0	0xb	8
			BU_UH0_A12_1	0xc	5	R/W-Coeff1.2
BU_UH0_A12_0	0xd	8
			BU_UH0_A13_1	0xe	5		R/W-Coeff1.3
BU_UH0_A13_0	0xf	8
			BU_UH0_A20_1	0x10	5	R/W-Coeff2.0
BU_UH0_A20_0	0x11						8
			BU_UH0_A21_1	0x12	5			R/W-C0eff2.1
BU_UH0_A21_0	0x13					8
			BU_UH0_A22_1	0xl4	5		R/W-Coeff2.2
BU_UH0_A22_0	0x15					8
			BU_UH0_A23_1	0x16	5			R/W-Coeff2.3
BU UH0_A23_0	0x17					8
			BU_UH0_MODE	0x18	2		R/W
BU_UH1_A00_1	0x20	5				R/W-Coeff0.0
			BU_UH1_A00_0	0x21			8
BU_UH1_A01_1	0x22	5						R/W-Coeff0.1
			BU_UH1_A01_0	0x23		8
BU_UH1_A02_1	0x24	5					R/W-Coeff0.2
			BU_UH1_A02_0	0x25		8
BU_UH1_A03_1	0x26	5						R/W-Coeff0.0
			BU_UH1_A03_0	0x27		8

Table C.11.3. Horizontal spatial oversampling and C keyhole address translation table (continued)

Keyhole Storage Server name	Keyhole Address	Position	Note
				BBU_UH1_A10_1	0x28	5	R/W-Coeff1.0
BU_UH1_A10_0	0x29		8
				BU_UH1_A11_1	0x2a	5		R/W-Coeff1.1
BU_UH1_A11_0	0x2b	8
			BU_UH1_A12_1	0x2c	5	R/W-Coeff1.2
BU_UH1_A12_0	0x2d	8
			BU_UH1_A13_1	0x2e	5		R/W-Coeff1.3
BU_UH1_A13_0	0x2f					8
			BU_UH1_A20_1	0x30	5			R/W-Coeff2.0
BU_UH1_A20_0	0x31					8
			BU_UH1_A21_1	0x32	5		R/W-Coeff2.1
BU_UH1_A21_0	0x33					8
			BU_UH1_A22_1	0x34	5			R/W-Coeff2.2
BU_UH1_A22_0	0x35					8
			BU_UH1_A23_1	0x36	5		R/W-Coeff2.3
BU_UH1_A23_0	0x37					8
			BU_UH1_MODE	0x38	2			R/W
BU_UH2_A00_1	0x40	5				R/W-Coef0.0
			BU_UH2_A00_0	0x41			8
BU_UH2_A01_1	0x42	5						R/W-Coeff0.1
			BU_UH2_A01_0	0x43		8
BU_UH2_A02_1	0x44	5					R/W-Coeff0.2
			BU_UH2_A02_0	0x45		8
BU_UH2_A03_1	0x46	5						R/W-Coeff0.0
			BU_UH2_A03_0	0x47		8
8U_UH2_A10_1	0x48	5					R/W-Coeff1.0
			BU_UH2_A10_0	0x49		8
BU_UH2_A11_1	0x4a	5						R/W-Coeff1.1
			BU_UH2_A11_0	0x4b	8
BU_UH2_A12_1	0x4c	5				R/W-Coeff1.2
			BU_UH2_A12_0	0x4d	8
BU_UH2_A13_1	0x4e	5					R/W-Coeff1.3
			BU_UH2_A13_0	0x4f		8

Table C.11.3. Horizontal spatial oversampling and C keyhole address translation table (continued)

Keyhole Storage Server name	Keyhole Address	Position	Note
				BU_UH2_A20_1	0x50	5	R/W-Coeff2.0
BU_UH2_A20_0	0x51		8
				BU UH2_A21_1	0x52	5		R/W-Coeff2.1
BU_UH2_A21_0	0x53		8
				BU_UH2_A22_1	0x54	5	R/W-Coeff2.2
BU_UH2_A22_0	0x55		8
				BU_UH2_A23_1	0x56	5		R/W-Coeff2.3
BU_UH2_A23_0	0x57		8
				BU_UH2_MODE	0x58	2	R/W
BU_CS_A00_1	0x60	5	R/W
				BU_CS_A00_0	0x61
	8
		BU_CS_A10_1	0x62	5	R/W
BU_CS_A10_0	0x63
			8
BU_CS_A20_1	0x64			5	R/W
		BU_CS_A20_0	0x65
	8
		BU_CS_B0_1	0x66	6	R/W
BU_CS_B0_0	0x67
			8
BU_CS_A01_1	0x68			5	R/W
		BU_CS_A01_0	0x69
	8
		BU_CS_A11_1	0x6a	5	R/W
BU_CS_A11_0	0x6b
			8
BU_CS_A21_1	0x6c			5	R/W
		BU_CS_A21_0	0x6d
	8
		BU_CS_B1_1	0x6e	6	R/W
BU_CS_B1_0	0x61
			8
BU_CS_A02_1	0x70			5	R/W
		BU_CS_A02_0	0x71
	8
		BU_CS_A12_1	0x72		5	RW
BU_CS_A12_0	0x73
			8
BU_CS_A22_1	0x74			5	R/W
		BU_CS_A22_0	0x75
	8
		BU_CS_B2_1	0x76	6	R/W
BU_CS_B2_0	0x77
			8

Table C.11.3. Horizontal spatial oversampling and C keyhole address translation table (continued)

Keyhole Storage Server name	Keyhole Address	Position	Note
				BU_UH2_A20_1	0x50	5	R/W-Coeff2.0
BU_UH2_A20_0	0x51		8
				BU_UH2_A21_1	0x52	5		R/W-Coeff2.1
BU_UH2_A21_0	0x53		8
				BU_UH2_A22_1	0x54	5	R/W-Coeff2.2
BU_UH2_A22_0	0x55		8
				BU_UH2_A23_1	0x56	5		R/W-Coeff2.3
BU_UH2_A23_0	0x57		8
				BU_UH2_MODE	0x58	2	R/W
BU_CS_A00_1	0x60	5	R/W
				BU_CS_A00_0	0x61
	8
		BU_CS_A10_1	0x62	5	R/W
BU_CS_A10_0	0x63
			8
BU_CS_A20_1	0x64			5	R/W
		BU_CS_A20_0	0x65
	8
		BU_CS_B0_1	0x66	6	R/W
BU_CS_B0_0	0x67
			8
BU_CS_A01_1	0x68			5	R/W
		BU_CS_A01_0	0x69
	8

Table C.11.3. Horizontal spatial oversampling and C keyhole address translation table (continued)

BU_CS_A11_1	0x6a	5	R/W
				BU_CS_A11_0	0x6b
	8
		BU_CS_A21_1	0x6c	5	R/W
BU_CS_A21_0	0x6d
			8
BU_CS_B1_1	0x6e			6	R/W
		BU_CS_B1_0	0x6f
	8
		BU_CS_A02_1	0x70	5	R/W
BU_CS_A02_0	0x71
			8
BU_CS_A12_1	0x72			5	R/W
		BU_CS_A12_0	0x73
	8
		BU_CS_A22_1	0x74	5	R/W
RU_CS_A22_0	0x75
			8
BU_CS_B2_1	0x76			6	R/W
		BU_CS_B2_0	0x77
	8

C.13 image size parameters C.13.1 Foreword

The following detailed description of fragments encoding format corresponding to the image from the write address generator Size interrupt processing requirements needed. Note that the picture size parameters can be sent HORIZ ONTAL_MBS, VERTICAL_MBS and DEFINE-SAMPLING (for each component) tokens Changing the combination of "on-the-fly", the result a write address generator interrupts. These Tokens arrive in any order, and usually, any one of the dimensions of the image are required Parameters recalculated. However, the set time, before performing any calculations to detect all things Member of arrival will be more effective.

On setting, image size parameter register to write a specific value is possible, therefore Can not rely on interrupt processing corresponding to the token. For this reason, also gives the SIF register values ​​appropriate image. C.13.2 Interrupt Processing image size parameter

There are five kinds of frame sizes events, each event initial response given by:

     if {hmbs_avent}

      load {mbs_wide}；

     else if {vmbs_event}

      load{mbs_high}；

     else if {def_samp0_event}

     {

      load {mexhb[O]}；

      load {mbxvb[O]}；

     }

     else if {def_samp1_event}

     {

      load {maxhb[1]}；

      load {maxvb[1]}；

     }

     else if {def_samp2_event}

     {

      load {maxhb[2]}；

      load {maxvb[2]}；

     }

In addition, to maintain a consistent picture size parameters, the following calculation to:

   if {hmbs_event||vmbs_event||

       def_samp0_event||def_samp1_event||def_samp2_event}
   {
     for {i＝0；icmex_componet；i++}
     {
      hbs[i]＝addr_hbs[i]＝(maxhb[i]+1)·mbs_wide；
      half_width_in_blocks[i]＝{{maxhb[i]+1}·mbs_wide}/2；
      last_mb_in_row[i]＝hbs(i]-(maxhb[i]+1)；
      last_mb_in_half_row[i]＝half_width_in_blocks[i]-
   (maxhb[i]+1)；
      last_row_in_mb[i]＝hbs[i]·maxvb[i]；
      blocks_per_mb_row[i]＝last_row_in_mb[i]+hbs[i]；
      last_mb_row[i]＝blocks_per_mb_row[i]·{mbs_high-l}；

Although not strictly required to modify the interrupt based on the image size dispaddr register Value (such as the display window size). Depending on the application requirements may want this Do it. C.13.3 register values ​​for SIF image

SIF be displayed on interrupt processing after the image size included in all registers The value of the 4:2:0 stream is as follows: C.13.3.1 initial value

  BU_WADDR_MBS_WIDE＝0×16

  BU_WADDR_MBS_HIGH＝0×12

  BU_WADDR_COMP0_MAXHB＝0×01

  BU_WADDR_COMP1_MAXHB＝0×00

  BU_WADDR_COMP2_MAXHB＝0×00

  BU_WADDR_COMP0_MAXVB＝0×01

  BU_WADDR_COMP1_MAXVB＝0×00

BU_WADDR_COMP2_MAXVB = 0 × 00 C.13.3.2 second value - calculated after

  BU_WADDR_COMP0_HBS＝0×2C

  BU_WADDR_COMP1_HBS＝0×16

  BU_WADDR_COMP2_HBS＝0×16

  BU_ADDR_COMP0_HBS＝0×2C

  BU_ADDR_COMP1_HBS＝0×16

  BU_ADDR_COMP2_HBS＝0×16

  BU_WADDR_COMP0_HALF_WIDTH_IN_BLOCKS＝0×15

  BU_WADDR_COMP1_HALF_WIDTH_IN_BLOCKS＝0×0B

  BU_WADDR_COMP2_HALF_WIDTH_IN_BLOCKS＝0×0B

  BU_WADDR_COMP0_LAST_MB_IN_ROW＝0×2A

  BU_WADDR_COMP1_LAST_MB_IN_ROW＝0×15

  BU_WADDR_COMP2_LAST_MB_IN_ROW＝0×15

  BU_WADDR_COMP0_LAST_MB_IN_HALF_ROW＝0×14

  BU_WADDR_COMP1_LAST_MB_IN_HALF_ROW＝0×0A

  BU_WADDR_COMP2_LAST_MB_IN_HALF_ROW＝0×0A

  BU_WADDR_COMP0_LAST_ROW_IN_MB＝0×2C

  BU_WADDR_COMP1_LAST_ROW_IN_MB＝0×0

  BU_WADDR_COMP2_LAST_ROW_IN_MB＝0×0

  BU_WADDR_COMP0_BLOCKS_PER_MB_ROW＝0×58

  BU_WADDR_COMP1_BLOCKS_PER_MB_ROW＝0×16

  BU_WADDR_COMP2_BLOCKS_PER_MB_ROW＝0×16

  BU_WADDR_COMP0_LAST_MB_ROW＝0×5D8

  BU_WADDR_COMP1_LAST_MB_ROW＝0×176

  BU_WADDR_COMO2_LAST_MB_ROW＝0×176

Note that if these values ​​are explicitly written in the set, it must be considered most Characteristics of multi-byte units.

Note that additional diagrams that for those with a thing like the art technology to make people understand Release, they include this application in order to further understanding of the present invention, the detailed structure and the outside Operation effect.

The present invention described above, a pipeline system to meet the needs of a long term presence, in order to change the Into the system. The invention relates to an improved pipeline system having an input, an output And a lot of processing between input and output level. This is a lot of processing stage consists of two-wire interface of the internal Link up along the transmission line token, and the control and / or data tokens in general accommodate Unit form, in the pipeline processing stage to interface with all, in the pipeline with the selected The level interact to complete the control data in the processing stage and / or joint control - Data Power Can, therefore, the processing stage in the pipeline, the configuration and the process is provided in high spirits Activity. According to the present invention, the treatment stage can be identified according to at least one token which can be equipped Position. A processing stage can start code detector, the detector receives an input and generates Students and / or conversion token. ...

The present invention may also include a token in the form of PICTURE_START token code to indicate Following the start of the image data after the token, a token table PICTURE-END Shows the end of a separate image, a FLUSH token is used to remove the buffer and resetting the Systems, while CODING_STANDARD token is used to determine the system environment, choose a lot of image compression Shrink / decompression standard one for processing. The invention also relates to an improved water Wire system to decode the video data, and has a Huffman decoder, a number of points According to Index (ITOD) level, an arithmetic logic unit (ALU) and one directly with the system Face data buffer means, and thus the sizes of various data time-expanded video image may Is controlled. According to the present invention, there is a processing stage receives the input data stream, which includes the identification stage Do apparatus specified bit flow model, whereby the processing stage random access and error recovery easy. The invention also includes a means to achieve after the cessation of the operation of the image to obtain the map Clear image data decoding end to indicate the end of the image, and clear lines. ...

Improved pipeline system also comprises a fixed size, fixed width buffer And a device that fills the buffer and transmitted through the buffer of an arbitrary number of bits. The present invention Also relates to a run-length coding including the data stream, and a reverse mode of the device. The device according to the data flow is valid token, this token is used to extend the run-level encoding a number of zero According to the run followed by a stage, and thus, each token number to represent the specified value. The present invention It also includes a reverse pattern of the stage, an inverse discrete cosine transform stage and a processing stage, This processing stage in the reverse mode of the inverse discrete cosine transform stage and the intermediate stage, the processed According to the token table work. ...

Furthermore, the present invention relates to an improved pipeline system, which has a Huffman decoder, which according to H.261, JPEG or MPEG standards required Huffman Encoding, decoding encoded data word click. This data word includes an identifier, which identifies Huffman code standards, under this standard, the data word to be coded. Means for receiving Huff- man encoded data word, means for reading out the identifier to identify the kind of standards to control the connected Huffman code of the received data word. If necessary, based on the read identifier, identifier Huff- man code data word is such as H.261 Huffman code or MPEG Huffman code. Device may Huffman code word is connected to the data receiving device operated to generate an index number, which An index number with each JPEG Huffman code data word, whereas the data word from Huffman code word data receiving device. This device is used to operate a lookup table in which packet Comprises a Huffman code table, the table has used the format of the JPEG standard, to transmit JPEG Huffman table information includes a receiver input index, which index number from Index generation means, further comprising an output, which is the index number corresponding to the decoded data Words. ...

Improved system includes a multi-standard video decompression apparatus, the device has a number of stages, These stages are arranged in a pipelined processor as two-wire interface are connected internally. Control token and Data token through a single-wire interface to transmit control data token format. A token Decoding circuit is placed within a certain level in order to identify some of the token is associated with the class as a control System token and passes along the line of control token do not know. Reconfigurable processing circuits Is located within the selected intermediate, and an identification of the control token to respond to reconfigure Such level to deal with a recognizable data token. To implement this system, many Kind of unique support subsystem circuitry and processing techniques have been disclosed. ...

Improved system includes a multi-standard video decompression apparatus, the device has a number of stages, These stages are arranged in a pipelined processor as two-wire interface are connected internally. Control token and Data token through a single-wire interface to transmit control data token format. A token Decoding circuit is placed within a certain level in order to identify some of the token is associated with the class as a control System token and passes along the line of control token do not know. Reconfigurable processing circuits Is located within the selected intermediate, and an identification of the control token to respond to reconfigure Such level to deal with a recognizable data token. To implement this system, many Kind of unique support subsystem circuitry and processing techniques have been disclosed. ...

Claims (27)

1, a system having an input, an output and between input and output Plurality of processing stages, characterized in that:

An interactive interface to the token, it means adapted to define a common stage in the processing The control and / or data functions; and

One of said stage, which receives said input, and for generating and / or conversion Said token.

2, in a process number of separate machines bit stream encoded in the bit stream with a Series of digital bits arranged in a series of bit stream, and a start code and coded independently from the series bits Code pairs carry the data string, characterized in that: a housing having first, second and third storage The start code detector, these registers are connected in series, and each of said register Registers are stored bit stream from the different number of bits; storing a value of said first Register, said second register and a start code to identify a first decoding means Position, are contained in said first register with the said values ​​associated; for the Transferred to the register value to a predetermined end of said third circuit means; and in order from the top Data of the third register receives the second decoding means arranged in parallel. ...

2, in a process number of separate machines bit stream encoded in the bit stream with a Series of digital bits arranged in a series of bit stream, and a start code and coded independently from the series bits Code pairs carry the data string, characterized in that: a housing having first, second and third storage The start code detector, these registers are connected in series, and each of said register Registers are stored bit stream from the different number of bits; storing a value of said first Register, said second register and a start code to identify a first decoding means Position, are contained in said first register with the said values ​​associated; for the Transferred to the register value to a predetermined end of said third circuit means; and in order from the top Data of the third register receives the second decoding means arranged in parallel. ...

An interactive interface token in the form of universal adaptation unit in said at Managerial be controlled and / or complete data functions,

The token is a PICTURE_START token code for indicating an image of Starting will follow later in the DATA tokens being.

4, a system having an input, an output and a large number of input and output in Between the processing stage, characterized in that:

Deformation an interactive interface to the token, it defines a global adaptation unit so the above Processing stages to complete the control and / or execution of data functions,

The token is a PICTURE_START token code for indicating an image of Starting will follow in later DATA token.

5, with a plurality of processing stages having use with the system, characterized in that:

A universal adaptation unit, which take the form of interactive interface token to said Processing stage to be controlled and / or complete data functions,

The token is a PICTURE_END token is used to represent an independent picture End.

6, a system having an input, output, and between input and output at a large Management level, characterized in that:

Deformation an interactive interface token, it defines a common unit adapted to the above Processing stage to be controlled and / or complete data functions,

PICTURE _END the token is a token, independent of the image to indicate a End.

7, for a large number of processing stages with a use with the system, characterized in that:

A generic form of interactive interface token adaptation unit, as in the above processing stage In the control and / or data functions,

Wherein said token is a FLUSH token, which is used to remove the buffer and resetting the Systems.

8, a system having an input, an output and input, and outputs There are many processing stages, characterized in that:

An interactive interface deformation token element defines a common adaptation to the Stage in the process control and / and data functions,

The token is a FLUSH token is used to clear the buffer and reset the system, To keep the system from input to output stopped.

9, and having a plurality of processing for use with the system level, characterized in that:

A generic form of an interactive interface token adaptation unit in said process Stage control and / or data functions,

The CODING_STANDARD token is a token, the determination condition of said system, Many of the selected image compression / decompression of a standard for processing.

10, a system having an input, an output and input to the output A plurality of processing stages, characterized in that:

An interactive interface deformation token defines a common adaptive unit, in the The processing stage for said control and / or complete data functions,

The CODING_STANDARD token is a token, the determination condition of said system, Many of the selected image compression / decompression of a standard for processing.

11, to the decoded video data, and a Huffman decoder systemo Used together, characterized in that:

A pointer to the data (ITOD) level of the index;

An arithmetic logic unit (ALU); and

A data buffer means to follow the said system directly,

Thus, the size of data to the various time video images to be controlled.

12, a space in the video data decoding system having a Huffman decoder, A pointer to the data index and an arithmetic logic unit, characterized in that:

A two-wire interface is connected to the internal processing level, said data using the serial interface Treatment, to control the use of parallel processing.

13, a space in the video data decoding system having a Huffman decoder, A pointer to the data index and an arithmetic logic unit, characterized in that:

It is independent of a ROM storing a program standard for many images of each standard, Selecting the program by the token,

Thus, facilitates the standard for many image processing.

14, a space in the video data decoding system having a Huffman decoder, A pointer index to the data and an arithmetic logic unit, characterized in that:

Token format is used to format the token,

Resulting data token.

15, a space in the video data decoding system having a Huffman decoder, A pointer to the data index and an arithmetic logic unit, characterized in that:

An internal link processing stage two-wire interface, said data into a serial interface Processing, control of parallel processing;

A microcode ROM, which has a separate program memory, for many images of each standard A, the procedure described by the token optional,

A token formatter, format it tokens, making it easy to handle a large number of images marked Standards and data token generation.

16, a video data decoding system, characterized by: a Huffman decoder pack Includes a decoding stage and data index level; a parser stage to said data index Unit to send an instruction to select the criteria for a particular identification code required table, said sub- Level analyzer to indicate whether the arriving data inverted.

17, in the pipeline system has an input data stream, characterized in that:

A processing stage for receiving said input data stream, and said stage comprises To identify specific bit-stream model of the device.

Thus, the level to facilitate random access and error recovery.

18, a pipeline, characterized in that: one looking for ways to apparatus for searching Different codes encoded data stream, such data streams into a single serial data stream arrangement, can be randomly Access and enhanced error recovery.

19, in the pipeline machine, characterized in that: one for an image after stopping (Stop- After-Picture) operation means for decoding the image data to obtain the clear end in order to Indicates the end of the image and cleared lines.

20, in the pipeline machine, characterized in that: a fixed size, fixed width Buffers, and a device; it fills the buffer cache is transmitted through an arbitrary number of bits.

21, the system having a data stream, including run-level code, characterized in that:

Inverse modeling device in said data stream is valid, this data stream from a command Signs on said run-level code spread out to become a zero-run-length data followed behind in class, Thus, each token using the specified number of values ​​expressed.

22, a device for processing data, characterized in that:

An expansion circuit for receiving a data token, said data token with couples Cheng-level code, and can decode the run level of the code;

A padding circuit for communication with said expansion of the circuit to check said data Length with a predicted token, so the token if said data length is less than predicted length Degree of filling of the circuit of the token plus data to said data unit, until a prediction Length; and

A bypass circuit for bypassing addition to any outside data token token.

23, as an effective treatment of the data buffer is filled, characterized in that:

Provided having a first width of the first form predicted token, having at least A surface format:

Format A-EXXXXXXLLLLLLLLLLL

Format B-FRRRRRRLLLLLLLLLLL

Format C-EOOOOOOLLLLLLLLLLL Where E = extension bits; F = specified format; R = Run-bit; L = length of the bit or data Token; X = "uncertain (don't care) bit";

A separate token the form oa format token, the token in the form oa format ELLLLLLLLLLL;

Separation Form B format a token and a token format oa data token, a token format In the form of FRRRRRROOOOO;

Isolated Form C O token token the format, the format of the form O token FLLLLLLLLLLL;

Combined format 0, format Format 1 0a and tokens into a buffer, said buffer Chong has a second prediction width.

24, A method for providing a set of time delay compressed image apparatus to which the image Should on one video compression / non-compression standard, characterized in that:

The data word contains compressed image;

A counter circuit suitable for data word count;

A microprocessor communication with said counter circuit and adapted to receive a start signal Interest rates, which start information with video decompression standards;

Said microprocessor of said information communication start a counter circuit;

Reverse pattern of a circuit for receiving said data word and has a delay of said Capacity data word;

A control circuit in the middle, with said counter circuit and said reverse mode Type of circuit communication;

The counter circuit, the count of the initial information with said data word for comparison Over and send a signal to said control circuit; and

Said control circuit based on said data signal to said word line, the number of According to the starting criteria have been met, and controls the delay characteristic of the reverse mode.

25, in the pipeline system has a reverse pattern is inverse cosine transform stage and grade, Characterized in that: a processing stage, which is located in the reverse mode of said device and the inverse discrete level than Chord conversion stage between the token table function to process the data.

26 A Huffman decoder, wherein:

Means capable of decoding the data word;

Corresponding to the H.261, JPEG or MPEG standards are encoded Huffman coding, Data word includes a recognizer, which identifies the data words of the Huffman coding standard used, Decoder is further characterized in that:

Having a receiving apparatus Huffman coding of the data word, including reading identifier to determine The received data is Huffman code word by which the standard control device, and When necessary the data word into a JPEG Huffman encoded data word means, such transfer Carried out for the read identifier corresponding to the Huffman coding to identify the data word is H.261 or MPEG standard encoding;

Huffman encoded data word with the operation of the device relative to the link receiver means for producing Generates a JPEG Huffman code corresponding to each data word index number, index number from the production Receiving an index number generating device, and includes an output, this output corresponding to the index number is A decoded data word.

27 A method of decoding the data word, the decoder corresponding to the H.261, JPEG or MPEG Huffman coding standards are encoded data word, said data word comprises a recognizer, The data word recognizer standard Huffman code in which is encoded, characterized in that:

Huffman coding receives the encoded data word comprises:

Huffman coding receives the encoded data words, including reading recognizer to determine what Huffman coding standard control data of the received code word and the number needed to According to the word into a JPEG Huffman encoded data word, the conversion is implemented in response to the Read recognizer recognizes Huffman coding data is H.261 or MPEG Huffman encoding Code;

Generating an index number, the index corresponding to the received compiled for each JPEG Huffman Code data word; and

Operating a lookup table that includes a Huffman code table, with the JPEG standard JPEG Huffman table information for transmission format, this operation includes receiving an index Number, and generates a corresponding index number to the received decoded data word.

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