CN111208867A - DDR (double data Rate) read data integer clock cycle-based synchronization circuit and synchronization method - Google Patents

DDR (double data Rate) read data integer clock cycle-based synchronization circuit and synchronization method Download PDF

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CN111208867A
CN111208867A CN201911375233.9A CN201911375233A CN111208867A CN 111208867 A CN111208867 A CN 111208867A CN 201911375233 A CN201911375233 A CN 201911375233A CN 111208867 A CN111208867 A CN 111208867A
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ddr
read data
register reg
data
integer
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CN111208867B (en
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王亮
吴汉明
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Elownipmicroelectronics Beijing Co ltd
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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Abstract

The invention discloses a DDR (double data Rate) read data integer clock cycle-based synchronous circuit and a synchronous method, wherein the synchronous circuit comprises: the device comprises a physical layer calibration circuit and a read data valid enable generation circuit which are connected with each other; the physical layer calibration circuit is used for carrying out delay multi-beat enabling comparison on DDR read data and reference data to obtain a comparison result; the read data effective enabling generation circuit is used for determining the integer clock period of DDR read data reaching the DDR physical layer according to the comparison result, delaying the effective enabling of the DDR read data by the determined integer clock period, and achieving integer clock period synchronization of the DDR read data. The invention adopts a mode of delaying multi-beat enable comparison signals to determine the integer clock period of DDR read data reaching a DDR physical layer, and effectively enables the data to delay the corresponding integer clock period, thereby realizing the integer clock period synchronization of the DDR read data.

Description

DDR (double data Rate) read data integer clock cycle-based synchronization circuit and synchronization method
Technical Field
The invention relates to the technical field of DDR (double data rate), in particular to a DDR-read-data-integer-clock-period-based synchronization circuit and a DDR-read-data-integer-clock-period-based synchronization method.
Background
According to a DDR protocol, after a DDR controller sends a read command, through a plurality of DDR clock cycles, DDR particles can return DQS and DQ, what a physical layer of the controller needs to process is to send received Data (DQ) to an internal clock domain of the controller, the data is dfi _ rddata on a physical layer interface, and corresponding effective control is dfi _ rddata _ valid. Because of the uncertainty of the connection delay between the IO (input/output port) and the board level, the phase of the internal clock and the data received by the DDR physical layer is difficult to determine, and the phase includes an integer clock period phase and a fractional clock period.
The processing method in the prior art is to calculate the integer clock delay of the read data loop by delaying multiple beats of read data, because the read data is a signal with a large bit width, the corresponding comparison logic is greatly increased, and the speed loss is also brought.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a DDR (double data Rate) read data integer clock cycle-based synchronization circuit and a DDR read data integer clock cycle-based synchronization method.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a DDR-read data integer clock cycle based synchronization circuit, said synchronization circuit comprising: the device comprises a physical layer calibration circuit and a read data valid enable generation circuit which are connected with each other;
the physical layer calibration circuit is used for carrying out delayed multi-beat enabling comparison on DDR read data and reference data to obtain a comparison result;
the read data effective enabling generation circuit is used for determining the integer clock period of DDR read data reaching a DDR physical layer according to the comparison result, delaying the effective enabling of the DDR read data by the determined integer clock period, and achieving the integer clock period synchronization of the DDR read data.
Further, as to the above-mentioned DDR-read-data integer clock cycle-based synchronization circuit, the physical layer calibration circuit is specifically configured to:
generating N pulse signals sequentially delayed by 1 beat, wherein N is a positive integer;
and comparing the DDR read data with the reference data according to the pulse signal to obtain a comparison result.
Further, a DDR-read-data integer clock cycle based synchronization circuit as described above, said physical layer calibration circuit comprising: the system comprises N registers reg and N comparators which are sequentially connected in series, wherein one register reg corresponds to one comparator;
the first input end of each comparator is connected with the DDR read data, the second input end of each comparator is connected with reference data, the third input end of each comparator is connected with a comparator enabling signal output by the corresponding register reg, and the output end of each comparator is connected with the read data effective enabling generation circuit;
the D end of the first register reg is connected with an externally input pulse, and the Q end of the first register reg is connected with the third input end of the corresponding comparator and the D end of the next register reg; the D end of each register reg between the first register reg and the last register reg is connected with the Q end of the last register reg, and the Q ends are connected with the third input end of the corresponding comparator and the D end of the next register reg; the D end of the last register reg is connected with the Q end of the last register reg, and the Q end is connected with the third input end of the corresponding comparator;
the N registers reg are used for generating N pulse signals which are sequentially delayed by 1 beat and used as enabling signals of the corresponding comparators;
and the comparator is used for comparing the input DDR read data and the reference data according to a comparator enable signal input by the corresponding register reg and outputting a comparison result.
Further, as to the DDR-read-data integer clock cycle-based synchronization circuit, the read-data-valid-enable generation circuit is specifically configured to:
and determining the integer clock period of the DDR read data reaching the DDR physical layer according to the comparison result corresponding to each pulse signal.
Further, as to the DDR-read-data integer clock cycle-based synchronization circuit, the read-data-valid-enable generation circuit is specifically configured to:
and when the comparison result corresponding to the Mth pulse signal is that the DDR read data is the same as the reference data, determining that the integer clock period of the DDR read data reaching the DDR physical layer is M clock periods, wherein M is a positive integer and is less than or equal to N.
Further, a DDR-read-data-integer-clock-cycle-based synchronization circuit as described above, said read-data-valid-enable generation circuit comprising: the input end of the phase selector is connected with the output ends of the N comparators;
the D end of the first register reg _ is connected with an externally input delay signal, and the Q end is connected with the input end of the phase selector and the D end of the next register reg _; the D end of each register reg between the first register reg _ and the last register reg _ is connected with the Q end of the last register reg _ and the Q end is connected with the input end of the phase selector and the D end of the next register reg _ respectively; the D end of the last register reg _ is connected with the Q end of the last register reg _ and the Q end is connected with the input end of the phase selector;
the N registers reg _ are used for generating N delay signals sequentially delayed by 1 beat;
the phase selector is used for selecting a corresponding delay signal according to the determined integer clock period, generating effective enabling of the DDR read data after delay, and achieving integer clock period synchronization of the DDR read data.
Further, as to the DDR-read-data integer clock cycle-based synchronization circuit, the phase selector is specifically configured to:
when the integer clock cycle of the DDR read data reaching the DDR physical layer is determined to be M clock cycles, selecting to receive a delay signal output by an Mth register reg _;
and delaying the effective enabling of the DDR read data by M clock cycles through the delay signal to generate the delayed effective enabling of the DDR read data, so that integer clock cycle synchronization of the DDR read data is realized.
The embodiment of the invention also provides a DDR (double data Rate) read data integer clock cycle-based synchronization method, which comprises the following steps:
(1) performing delayed multi-beat enabling comparison on DDR read data and reference data to obtain a comparison result;
(2) and determining the integer clock cycle of the DDR read data reaching the DDR physical layer according to the comparison result, and delaying the effective enabling of the DDR read data by the determined integer clock cycle to realize the integer clock cycle synchronization of the DDR read data.
Further, as described above, in a DDR-based read data integer clock cycle synchronization method, step (1) includes:
generating N pulse signals sequentially delayed by 1 beat, wherein N is a positive integer;
and comparing the DDR read data with the reference data according to the pulse signal to obtain a comparison result.
Further, as described above, in a DDR-based read data integer clock cycle synchronization method, step (2) includes:
and when the comparison result corresponding to the Mth pulse signal is that the DDR read data is the same as the reference data, determining that the integer clock period of the DDR read data reaching the DDR physical layer is M clock periods, wherein M is a positive integer and is less than or equal to N.
The invention has the beneficial effects that: the invention adopts the mode of delaying the multi-beat enable comparison signal to determine the integer clock period of DDR read data reaching the DDR physical layer, reduces the complexity of logic, also reduces the comparison logic, has higher speed, effectively enables the data to delay the corresponding integer clock period, and realizes the integer clock period synchronization of the DDR read data.
Drawings
Fig. 1 is a circuit diagram of a physical layer calibration circuit provided in an embodiment of the present invention;
fig. 2 is a circuit diagram of a read data valid enable generation circuit provided in an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
The invention provides a DDR (double data Rate) data reading integer clock cycle-based synchronous circuit, which comprises: the device comprises a physical layer calibration circuit and a read data valid enable generation circuit which are connected with each other;
the physical layer calibration circuit is used for carrying out delay multi-beat enabling comparison on DDR read data and reference data to obtain a comparison result;
the read data effective enabling generation circuit is used for determining the integer clock period of DDR read data reaching the DDR physical layer according to the comparison result, delaying the effective enabling of the DDR read data by the determined integer clock period, and achieving integer clock period synchronization of the DDR read data.
The physical layer calibration circuit is specifically configured to:
generating N pulse signals sequentially delayed by 1 beat, wherein N is a positive integer;
and comparing the DDR read data with the reference data according to the pulse signals to obtain a comparison result.
The physical layer calibration circuit includes: the system comprises N registers reg and N comparators which are sequentially connected in series, wherein one register reg corresponds to one comparator;
the first input end of each comparator is connected with DDR read data, the second input end of each comparator is connected with reference data, the third input end of each comparator is connected with a comparator enabling signal output by the corresponding register reg, and the output end of each comparator is connected with a read data effective enabling generation circuit;
the D end of the first register reg is connected with an externally input pulse, and the Q end of the first register reg is connected with the third input end of the corresponding comparator and the D end of the next register reg; the D end of each register reg between the first register reg and the last register reg is connected with the Q end of the last register reg, and the Q ends are connected with the third input end of the corresponding comparator and the D end of the next register reg; the D end of the last register reg is connected with the Q end of the last register reg, and the Q end is connected with the third input end of the corresponding comparator;
the N registers reg are used for generating N pulse signals which are sequentially delayed by 1 beat and used as enabling signals of the corresponding comparators;
the comparator is used for comparing the input DDR read data and the reference data according to the comparator enable signal input by the corresponding register reg and outputting a comparison result.
The read data valid enable generation circuit is specifically configured to:
and determining the integer clock period of the DDR read data reaching the DDR physical layer according to the comparison result corresponding to each pulse signal.
The read data valid enable generation circuit is specifically configured to:
and when the comparison result corresponding to the Mth pulse signal is that the DDR read data is the same as the reference data, determining that the integer clock period of the DDR read data reaching the DDR physical layer is M clock periods, wherein M is a positive integer and is less than or equal to N.
The read data valid enable generation circuit includes: the input end of the phase selector is connected with the output ends of the N comparators;
the D end of the first register reg _ is connected with an externally input delay signal, and the Q end is connected with the input end of the phase selector and the D end of the next register reg _; the D end of each register reg between the first register reg _ and the last register reg _ is connected with the Q end of the last register reg _ and the Q end is connected with the input end of the phase selector and the D end of the next register reg _ respectively; the D end of the last register reg _ is connected with the Q end of the last register reg _ and the Q end is connected with the input end of the phase selector;
the N registers reg _ are used for generating N delay signals which are sequentially delayed by 1 beat;
the phase selector is used for selecting corresponding delay signals according to the determined integer clock period, generating effective enabling of the delayed DDR read data, and achieving integer clock period synchronization of the DDR read data.
The phase selector is specifically configured to:
when the integer clock period of DDR read data reaching the DDR physical layer is determined to be M clock periods, selecting to receive a delay signal output by an Mth register reg _;
the effective enabling of DDR read data is delayed for M clock cycles through the delay signal, the delayed effective enabling of the DDR read data is generated, and integer clock cycle synchronization of the DDR read data is achieved.
It should be noted that the register reg and the register reg _ are the same type of register.
The invention also provides a DDR (double data Rate) read data based integer clock cycle synchronization method, which comprises the following steps:
s100, performing delayed multi-beat enabling comparison on DDR read data and reference data to obtain a comparison result;
s200, determining the integer clock period of DDR read data reaching the DDR physical layer according to the comparison result, and delaying the effective enabling of the DDR read data by the determined integer clock period to achieve integer clock period synchronization of the DDR read data.
The step S100 includes:
generating N pulse signals sequentially delayed by 1 beat, wherein N is a positive integer;
and comparing the DDR read data with the reference data according to the pulse signals to obtain a comparison result.
The step S200 includes:
and when the comparison result corresponding to the Mth pulse signal is that the DDR read data is the same as the reference data, determining that the integer clock period of the DDR read data reaching the DDR physical layer is M clock periods, wherein M is a positive integer and is less than or equal to N.
The invention compares the DDR read data and the reference data in which cycle of N clock cycles, the data of the DDR read data and the reference data are the same, namely, the integer clock cycle of the DDR read data reaching the DDR physical layer is determined, and then the effective enabling of the DDR read data is delayed by the corresponding integer clock cycle, so that the effective enabling consistent with the data time sequence is obtained. The integer clock period of the data reading circuit is calculated by delaying the multi-beat enable comparison signal, so that the complexity of logic is reduced, the comparison logic is reduced, and the speed is higher.
Example one
As shown in fig. 1, reg 0-reg 12 are 13 registers (register reg), 1cycle pulse is a pulse of 1 clock cycle, and the comparator logic, i.e. comparator, has 3 inputs, one is gold _ data (reference data), one is read _ data (data read from IO by physical layer, i.e. above DDR read data), and one is enable.
As shown in fig. 2, reg _0 to reg _12 are 13 registers (register reg _). This circuit is read data enable active select logic, the select signal being the compare _ result comparator output.
The 13 registers of reg 0-reg 12 are connected in series and used for generating pulses which are delayed by 13 beats in sequence and used as enable signals of the comparator, wherein reg0 corresponds to enable [0], reg1 corresponds to enable [1], the registers are pushed inwards in sequence, and reg12 corresponds to enable [12 ]. The gold _ data and the read _ data are both 32-bit data, the 1-cycle pulse is generated by a signal of 1 clock cycle generated by a physical layer under the condition that no delay exists in an acceptance loop, the signal is used for enabling a comparator, the read _ data and the reference data are compared 13 times when the data is read once, only one comparator in the 13 comparators is equal in result, if the result output by an Mth comparator is correct, namely the value of compare _ result [ M ] is 1, the delay of the whole read data loop can be judged to be M clock cycles, then the corresponding dfi _ rddata _ en delay signal is selected by using a compare _ result [ M ], after phase selector selection, the generated signal is the dfi _ rddata _ valid, and finally integer clock cycle synchronization is realized, namely the data reading data and the dfi _ rddata _ valid signals are synchronized.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.

Claims (10)

1. A DDR-read data integer clock cycle based synchronization circuit, said synchronization circuit comprising: the device comprises a physical layer calibration circuit and a read data valid enable generation circuit which are connected with each other;
the physical layer calibration circuit is used for carrying out delayed multi-beat enabling comparison on DDR read data and reference data to obtain a comparison result;
the read data effective enabling generation circuit is used for determining the integer clock period of DDR read data reaching a DDR physical layer according to the comparison result, delaying the effective enabling of the DDR read data by the determined integer clock period, and achieving the integer clock period synchronization of the DDR read data.
2. The DDR-read-data integer clock cycle-based synchronization circuit of claim 1, wherein the physical layer calibration circuit is specifically configured to:
generating N pulse signals sequentially delayed by 1 beat, wherein N is a positive integer;
and comparing the DDR read data with the reference data according to the pulse signal to obtain a comparison result.
3. The DDR read data integer clock cycle based synchronization circuit of claim 2, wherein the physical layer calibration circuit comprises: the system comprises N registers reg and N comparators which are sequentially connected in series, wherein one register reg corresponds to one comparator;
the first input end of each comparator is connected with the DDR read data, the second input end of each comparator is connected with reference data, the third input end of each comparator is connected with a comparator enabling signal output by the corresponding register reg, and the output end of each comparator is connected with the read data effective enabling generation circuit;
the D end of the first register reg is connected with an externally input pulse, and the Q end of the first register reg is connected with the third input end of the corresponding comparator and the D end of the next register reg; the D end of each register reg between the first register reg and the last register reg is connected with the Q end of the last register reg, and the Q ends are connected with the third input end of the corresponding comparator and the D end of the next register reg; the D end of the last register reg is connected with the Q end of the last register reg, and the Q end is connected with the third input end of the corresponding comparator;
the N registers reg are used for generating N pulse signals which are sequentially delayed by 1 beat and used as enabling signals of the corresponding comparators;
and the comparator is used for comparing the input DDR read data and the reference data according to a comparator enable signal input by the corresponding register reg and outputting a comparison result.
4. The DDR-read-data-integer-clock-cycle-based synchronization circuit of claim 2, wherein the read-data-valid-enable generation circuit is specifically configured to:
and determining the integer clock period of the DDR read data reaching the DDR physical layer according to the comparison result corresponding to each pulse signal.
5. The DDR read data integer clock cycle-based synchronization circuit of claim 4, wherein the read data valid enable generation circuit is specifically configured to:
and when the comparison result corresponding to the Mth pulse signal is that the DDR read data is the same as the reference data, determining that the integer clock period of the DDR read data reaching the DDR physical layer is M clock periods, wherein M is a positive integer and is less than or equal to N.
6. The DDR read data integer clock cycle based synchronization circuit of claim 5, wherein the read data valid enable generation circuit comprises: the input end of the phase selector is connected with the output ends of the N comparators;
the D end of the first register reg _ is connected with an externally input delay signal, and the Q end is connected with the input end of the phase selector and the D end of the next register reg _; the D end of each register reg between the first register reg _ and the last register reg _ is connected with the Q end of the last register reg _ and the Q end is connected with the input end of the phase selector and the D end of the next register reg _ respectively; the D end of the last register reg _ is connected with the Q end of the last register reg _ and the Q end is connected with the input end of the phase selector;
the N registers reg _ are used for generating N delay signals sequentially delayed by 1 beat;
the phase selector is used for selecting a corresponding delay signal according to the determined integer clock period, generating effective enabling of the DDR read data after delay, and achieving integer clock period synchronization of the DDR read data.
7. The DDR read data integer clock cycle based synchronization circuit of claim 6, wherein the phase selector is specifically configured to:
when the integer clock cycle of the DDR read data reaching the DDR physical layer is determined to be M clock cycles, selecting to receive a delay signal output by an Mth register reg _;
and delaying the effective enabling of the DDR read data by M clock cycles through the delay signal to generate the delayed effective enabling of the DDR read data, so that integer clock cycle synchronization of the DDR read data is realized.
8. A DDR (double data Rate) read data integer clock cycle-based synchronization method is characterized by comprising the following steps:
(1) performing delayed multi-beat enabling comparison on DDR read data and reference data to obtain a comparison result;
(2) and determining the integer clock cycle of the DDR read data reaching the DDR physical layer according to the comparison result, and delaying the effective enabling of the DDR read data by the determined integer clock cycle to realize the integer clock cycle synchronization of the DDR read data.
9. The DDR read data integer clock cycle-based synchronization method as claimed in claim 8, wherein the step (1) comprises:
generating N pulse signals sequentially delayed by 1 beat, wherein N is a positive integer;
and comparing the DDR read data with the reference data according to the pulse signal to obtain a comparison result.
10. The DDR-read-data integer clock cycle based synchronization method according to claim 9, wherein the step (2) comprises:
and when the comparison result corresponding to the Mth pulse signal is that the DDR read data is the same as the reference data, determining that the integer clock period of the DDR read data reaching the DDR physical layer is M clock periods, wherein M is a positive integer and is less than or equal to N.
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