JP3408486B2 - Synchronous circuit between devices - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to transfer control of data between devices using clocks of the same frequency, and more particularly to improvement when clock skew between devices becomes a problem.

When data is transferred between devices, circuit boards, or LSIs at a clock frequency of hundreds of megahertz to several hundreds of megahertz, the wavelength of the clock is about 1 meter to several meters, so that data transfer of several meters is performed. In this case, a delay of one clock to several clock cycles occurs, and several cycles of data are loaded on the data transmission path. In this frequency band, it is difficult to design the delay time to be an integral multiple of the clock cycle so that the capture edge of the receiver clock does not coincide with the change point of the received data.

The present invention relates to a technique for enabling data to be transferred to a clock of a receiver even when such a delay time is difficult to predict.

[0004]

2. Description of the Related Art FIG. 10 is a principle diagram for explaining conventional transfer control between devices. The data transmitted from the transmission device 1 to the reception device 2 may not be simply captured by the clock of the reception device side because the clock skew between the devices becomes a problem. It is a mechanism that takes in at the clock and selects either one.

For example, as disclosed in Japanese Unexamined Patent Application Publication No. 11-46182, the received data is converted into a receiver clock,
Each of the inverted clocks is taken into a flip-flop, and the vertical parity check result of the taken-in data is used to determine which is to be the target of the synchronized data.

Further, as disclosed in Japanese Patent Laid-Open No. 63-95518, the phase relationship between the clock on the transmitting device side and the clock on the receiving device side is compared, and the receiving device side clock or the receiving device clock is compared. It is determined which of the inverted clocks should be used.

[0007]

However, in the technique using the above vertical parity check result, when an error occurs even number of times in each bit of the n received data, the clock of the receiving device side or its inverted clock is changed. There is a problem that it is not possible to determine which of the data systems taken in is to be the synchronized reception data.

Even if the horizontal parity check result is used,
If you mistakenly capture even number of received data of a book,
A parity error is not detected and a proper judgment cannot be made.

If all the n pieces of data are "0" and there is no temporal change, an error may not be detected by the parity check.

Further, the distance between the transmitter and the receiver is increased,
If the transmitted waveform is distorted, correct data may not be received even if the clock on the receiver side or its inverted clock is taken in.

Such an example will be described with reference to FIG. The output waveform of the transmitter 1 arrives at the receiver 2 with a delay of about one clock cycle. However, due to waveform distortion due to attenuation, time t5 of the rising edge of the clock of the receiving device
Then, the correct value cannot be sampled at any time t6 of the rising edge of the inverted clock of the receiver.

Further, in the case of the technique of transmitting the clock on the transmitter side to the receiver and comparing the phase relationship with the clock of the receiver, the clock waveform is attenuated according to the distance between the transmitter and the receiver. When the distance becomes long, it may not be possible to accurately capture the edge of the clock, and it may not be possible to accurately compare the phase difference between the devices.

The main object of the present invention is to determine whether to use the clock on the side of the receiver or its inverted clock,
By using a pattern that can be reliably determined, and by determining the phase relationship between the clocks of the transmitter and receiver even if the transmitted signal is subject to delay and waveform distortion in the data transmission path. The purpose of the present invention is to provide a circuit that can reliably transfer data to the clock on the receiving device side.

[0014]

According to a first aspect of the present invention, there is provided a synchronizing circuit between devices, which generates a test signal of a constant cycle using a clock of the transmitting device in response to a test instruction and sends the signal to a data transmission line. A circuit for generating a test signal having the same cycle and pattern as the test signal in response to a test instruction using the clock of the receiving device in the receiving device, and its output and the receiving output of the test signal of the transmitting device. Means for classifying the phase difference and storing the result, first data holding means for receiving the received data with the inverted clock of the receiving device, second data holding means for taking the output of the first data holding means with the clock of the receiving device And a third data holding means for receiving the received data at the clock of the receiving device, and based on the stored determination result, the output of the second data holding means and the third data holding means. Either the output of the holding means, characterized in that the synchronizing received data.

According to a second aspect of the present invention, there is provided a synchronization circuit between devices, wherein in the first inter-device synchronization circuit, a transmitting device which transmits data to the input section of the receiving device from the transmitting device through a transmission line equivalent to data. It is characterized by further comprising a fourth data holding means for fetching the transmitted data by the inverted signal of the clock and making it the received data.

A third inter-device synchronization circuit of the present invention is the first or second inter-device synchronization circuit, which receives the reception output of the transmission device test signal and slightly reduces the pulse width of the output. A timing compensation circuit for passing the phase difference between the test signals to the classification determination circuit is provided, and the determination circuit performs the determination in consideration of the timing margin.

The fourth inter-device synchronization circuit of the present invention is the third inter-device synchronization circuit, wherein when the data width is n (n is a natural number) bits, only one bit out of n bits is transmitted. A means for determining a phase difference section between a test signal from the apparatus and a test signal inside the receiving apparatus, and based on the result of the 1-bit phase difference section determination, holds the second data for n-bit data. Means output and said third
It is characterized in that either one of the data holding means outputs is selected and used as the synchronized reception data.

According to a fifth aspect of the present invention, there is provided a synchronization circuit between devices, wherein in the fourth aspect of the synchronization circuit, when the transmitter and the receiver are simultaneously supplied with power, a predetermined power supply confirmation signal from the transmitter is used. A first timer that defines the period up to time A, a predetermined time B (B <B <
A second timer for defining the period up to A) is provided in each of the transmitting device and the receiving device, and each device turns on the test instruction for a period defined by the timer of the own device.

According to a sixth aspect of the present invention, there is provided a synchronization circuit between devices, wherein in the fourth aspect of the synchronization circuit between devices, when the transmitter and the receiver are simultaneously supplied with power, the transmitter determines the power supply of the transmitter. A first timer that defines a period from the signal to the predetermined time A is provided, the test instruction of the transmission device is turned on for the specified period, and the reception device counts the pulses of the reception test signal on the synchronized reception data line, Counter means for detecting that the count has reached a predetermined number corresponding to a time sufficiently shorter than the predetermined time A is provided, and the test instruction of the receiving device is turned on during the period from the power confirmation of the receiving device to the detection, and at the time of the detection. The determination result of the phase difference classification is set in the storage means.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION To clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an entire first embodiment of a synchronizing circuit between devices according to the present invention. This figure shows
It comprises a transmitter 1 and a receiver 2.

The transmitter 1 is composed of a selection circuit 11 for switching the operation according to the test instruction signal 5, a flip-flop (hereinafter abbreviated as FF) 21, and inverters 12 and 13. D, Q, and CK of FF indicate a data input terminal, an output terminal, and a clock input terminal, respectively.

The receiving device 2 has a fourth FF 31 as a fourth data holding means for temporarily storing the data from the transmitting device 1, an inverter 85 for generating an inverted clock of the receiving device, and a first data. First F as holding means
F41, second FF5 as second data holding means
1, a third FF 61 as third data holding means, a selection circuit 71, a timing compensation circuit 81, a timing test circuit 82, a timing determination circuit 83, and a hold circuit 84 as determination result storage means.

The timing test circuit 82 includes FFs 824 to FF827 for generating four types of timings and FFs 820 to FF82 for testing the timings of received data.
3 and inverters 828 and 829.

Next, the operation of this embodiment will be described.
When the test instruction signal 5 is “1”, the selection circuit 11 outputs F
A signal obtained by inverting the output signal of F21 by the inverter 12 is selected and output. At this time, the output signal of the selection circuit 11 forms a loop because it is input to the FF 21 again, and its value is inverted every clock cycle to oscillate a signal that repeats "0101". Whether the initial value is "0" or "1" is indefinite. On the other hand, when the test instruction signal 5 is "0", the selection circuit 11 selects the input data 3 to be transmitted. FF2
1 outputs any input data inside the transmitter 1 in synchronization with the rising edge of the transmitter clock 4. The inverter 13 inverts the transmitter clock 4 and outputs it to the receiver 2.

The test instruction signal 5 is directly received by the receiving device 2
Is output to. The fourth FF 31 of the receiver 2 captures the output signal of the FF 21 of the transmitter 1 at the rising edge of the signal output by the inverter 13. FF21 and the fourth
Transmission line between the FF31, the inverter 13 and the fourth F
If the distances of the transmission lines between the F31s are equal, the delay amount between them can be made equal to each other, and the fourth FF 31 takes in the data regardless of the length of the transmission line within a range in which the waveform distortion is allowable. You can At this time, it is assumed that the duty ratio of the transmitter clock 4 is 50%.

The first FF 41 takes in the output signal of the fourth FF 31 at the rising edge of the signal obtained by inverting the receiver clock 7 by the inverter 85. Second F
F51 outputs the output of the first FF41 to the receiver clock 7
Capture on the rising edge of. The third FF 61 simply takes in the output of the fourth FF 31 at the rising edge of the receiver clock 7.

Transmitter clock 4 and receiver clock 7
Are signals having the same period but not necessarily the same phase. When the output signal of the fourth FF 31 is fetched into the first FF 41 or the third FF 61 at the timing when the output signal of the fourth FF 31 changes, the value may be in an unstable state called metastable. However, if the waveform distortion inside the receiving device 2 can be ignored, the output signal of the fourth FF 31 is stably taken in by either the third FF 61 or the first FF, and there is no error. Should be.

Therefore, in order to transfer the output signal of the FF 31 to the receiver clock 7, it is necessary to determine whether to take in the rising edge of the receiver clock 7 or the rising edge of its inverted signal.

The determination method will be described below. The timing compensation circuit 81 delays the timing of the rising edge of the output signal of the FF 31 by a predetermined time so that the timing close to the change point of the output signal of the fourth FF 31 is not used for the determination.

For example, it is realized by a circuit as shown in FIG. The input signal is divided into two, one of which is passed through the delay element 810 and the other is directly input to the AND circuit 811. The delay time of the delay element 810 is, for example, 1/10 to 1 of one clock cycle of the receiver clock 7.
/ 4 is desirable. Because, if it is extremely small, it is determined that the margin is not included when a signal having a timing close to the change point of the output signal of the fourth FF 31 is input to the timing determination circuit 83. 1 /
This is because if the number is 2 or more, the timing determination described below will not be performed correctly.

Returning to FIG. 1, the timing test circuit 82
Tests whether the phase of the output signal of the fourth FF 31 is closer to one of the four types of repeating patterns of "0101" generated from the receiver clock 7. FF824 is
By returning the output signal to the input through the inverter 828, the value is inverted every clock cycle, and a signal that repeats "0101" is oscillated. Although the phases are not necessarily the same, the same test pattern as that of the FF 21 is generated.

This signal is FF8 at the rising edge of the signal obtained by inverting the receiver clock 7 by the inverter 829.
25. If the duty ratio of the receiver clock 7 is 50%, the output of the FF 825 is F
This means that the phase is 180 degrees behind the output of F824.

The FF 826 takes in the output signal of the FF 825 at the timing of the rising edge of the receiver clock 7, and generates a signal whose phase is delayed by 360 degrees with respect to the output of the FF 824. Further, the FF 827 takes in the output signal of the FF 826 at the rising edge of the signal inverted by the inverter 829, and generates a signal whose phase is delayed by 540 degrees from the output of the FF 824.

The FF 820 takes in the output signal of the timing compensation circuit 81 at the rising edge of the output signal of the FF 824. Similarly, FF821, FF822, FF8
23 are FF825, FF826, and FF827, respectively.
The output signal of the timing compensation circuit 81 is taken in at the rising edge of the output signal of.

FIG. 3 shows an example of the timing of the signals of FF820 to FF827. The output of the timing compensation circuit 81 is
It rises at time t1 and falls at time t2.
Since the FF 825 outputs the rising edge between the times t1 and t2, the output of the FF 821 is always "1".
become. At time t3 of the rising edge of FF825,
Since it is equal to the time of the falling edge of the receiver clock 7, it can be seen that the receiver 2 should capture data at the time of the falling edge of the receiver clock 7.

Although not shown, similarly, if the output signal of the FF 824 rises between the times t1 and t2, the output of the FF 820 is always "1", and the receiver 2 receives the receiver clock. It can be seen that the data should be captured at the time of the rising edge of 7.

Similarly, when the output of the FF822 is "1", it is the rising edge of the receiver clock 7, and when the output of the FF823 is "1", it is the falling edge of the receiver clock 7. You can see that you need to import the data.

On the other hand, as shown in FIG. 4, from time t1 to t2
There is a rising edge of the output of the FF 825 at the time t3 between the time t1 and the time t4 between the times t1 and t2.
There may be 6 rising edges. Here, the time t4 is the same as T1, but is shown on the right side of T1 in FIG. 4 for convenience. The outputs of both FF821 and FF822 are always "1". In this case, it is shown that the receiving device 2 can receive data using either the rising edge or the falling edge of the receiving device clock 7.

The relationship between the outputs of FF820 to FF823 and the edge of the receiver clock 7 to be used by the receiver 2 is as shown in FIG. At this time, the timing determination circuit 8
If the output signal of 3 is defined as shown in FIG. 5, it is convenient for the receiving device 2 to select the edge of the receiving device clock 7 to be used. Then, the output of the timing determination circuit 83 is "
In the case of "1", the receiving apparatus 2 may use the rising edge of the receiving apparatus clock 7, and in the case of "0", the falling edge. The combination of the outputs of the FF820 to FF823 is any one of FIG.

When the output of the timing judgment circuit 83 is R, R = (# FF823 / FF820) + (# FF82
1 · FF822) (# FF823: inverted output of FF823, ·: logical product,
+: Logical sum).

Returning to FIG. 1, description will be made. The output of the timing determination circuit 83 is input to the hold circuit 84, and the value is held when the test instruction signal 5 changes from "1" to "0". When the test instruction signal 5 is "0", the input data 3 is sent to the receiving device 2 and the phase cannot be determined. Therefore, the hold circuit 84 is necessary. The hold circuit 84 uses, for example, an FF with a hold input, the set input is the output of the determination circuit 83 gated by the test instruction signal 5, and the hold input is the test instruction signal 5.

The output signal of the hold circuit 84 is input to the selection circuit 71. The selection circuit 71 selects the output of the third FF 61 when the output of the hold circuit 84 is “1”, selects the output of the second FF 51 when the output of the hold circuit 84 is “0”, and synchronizes the received data. 6 is supplied to the inside of the receiving device.

By the series of these operations, the fourth FF 31
The output signal of can be transferred to the timing using the receiver clock 7. The third FF 31 is
If the distance between the transmitter 1 and the receiver 2 is short and the attenuation and distortion of the transmitted signal are small, it is not necessary to provide the transmitter 1 (transmitter 1
In the form of a driver for sending out the output of the FF21, and a receiver for receiving it at the receiving device 2).

Next, a second embodiment of the synchronizing circuit between devices according to the present invention will be described. In the first embodiment, the input data 3 has been treated as a 1-bit signal, but it can be expanded to a plurality of bits. FIG. 6 is a block diagram showing the whole of this embodiment.

The FF 22 is provided for the second to nth bits of the input data 3 and outputs the input data 3 to the receiving device 2. The fourth FF 32 is an FF that receives the data of the FF 22 with the clock signal of the inverter 13. The first FF 42 captures the output signal of the fourth FF 32 at the rising edge of the signal obtained by inverting the receiver clock 7 by the inverter 85. Second FF 52
Captures the output of the first FF 42 at the rising edge of the receiver clock 7. The third FF 62 is the fourth F
The output of F32 is simply captured at the rising edge of the receiver clock 7.

The selection circuit 72 selects the output of the FF 62 when the output of the hold circuit 84 is "1", and selects the output of the FF 52 when the output of the hold circuit 84 is "0", and selects the output of the synchronized reception data 6. Output from the second bit to the nth bit.

FF32, FF42, FF52, FF6
2. The selection circuit 72 is provided corresponding to the 2nd to nth bits of data.

The determination of the phase relationship between the transmitting device 1 and the receiving device 2 based on the test instruction signal 5 is performed using the first bit data line output from the FF 21. The fluctuation range of the delay characteristic between the first bit and each bit is the timing compensation circuit 8
Within the delay time of 1, the data lines can be transferred without making the bit skew by making the lengths of the data lines for each bit equal.

Next, a third embodiment of the synchronizing circuit between devices according to the present invention will be described. In this embodiment, the test instruction signal 5
It is related to the alternative method of.

In FIG. 1, the test instruction signal 5 controls the selection circuit 11 to select the input data 3 or the inverted output of the FF 21. It also controls the hold circuit 84 and holds the output of the timing determination circuit 83. Since the test instruction signal 5 is used by the transmission device 1 and the reception device 2, it is necessary to send the test instruction signal 5 from the transmission device 1 to the reception device 2. In the present embodiment, this is solved.

FIG. 7 shows the overall configuration of this embodiment, which is the first because the transmitter 1 generates a test instruction signal.
The timer circuit 901 is provided. Similarly, a second timer circuit 902 is provided to generate a test instruction signal for the receiver 2.

The operation will be described with reference to FIG. , The timer circuit 901 is reset for a predetermined number of cycles by the rise of the transmitter power supply confirmation signal 8 and starts counting from the next cycle (if there is no reset instruction, the transmitter power supply confirmation signal 8 is on and the count is less than the time A). As a starting condition). Then, the timer circuit 901 sets the predetermined time A
FF2 as an input of the selection circuit 11 for the period until reaching
The inverted signal of 1 is selected, and the FF 21 is controlled to output the test signal. After a predetermined time A has passed, the selection circuit 1
1 selects the input data 3.

On the other hand, the second timer circuit 902 inside the receiver 2 is reset for a predetermined number of cycles by the rise of the receiver power supply confirmation signal 9, starts counting from the next cycle, and a predetermined time B has passed. After that, a hold instruction is given to the hold circuit 84.

If the transmitter power supply confirmation signal 8 and the receiver power supply confirmation signal 9 have the same timing and the predetermined time A is longer than the predetermined time B, it is obtained by the repeating pattern output from the transmission device 1. The timing determination result can be held in the hold circuit 84, and the number of signal lines connecting the transmitter 1 and the receiver 2 can be reduced by one.

Next, a fourth embodiment of the inter-device synchronization circuit according to the present invention will be described. In this embodiment, the second timer circuit 902 on the receiving device side of the third embodiment is changed to a counter circuit 903.

The overall structure of this embodiment is shown in FIG. The operation will be described below. The first timer circuit 901 operates similarly to the third embodiment shown in FIG. The counter circuit 903 counts the rising / falling edge of the output signal of the selection circuit 71, and gives a hold instruction to the hold circuit 84 after reaching a predetermined number of times.

If the count number of the counter circuit 903 is set to reach the predetermined number before the measured time of the timer circuit 901 reaches the predetermined time A, the transmission is performed as in the third embodiment of FIG. The number of signal lines connecting the device 1 and the receiving device 2 can be reduced by one.

In the above description, the FF with hold input is shown as an example of the hold circuit 84, but this may be used as one bit of the nonvolatile flash ROM and its writing means.

In this case, the transmitter 1 or the transmitter 1 and the receiver 2 is used as the mode signal for generating the test signal.
Switch or jumper pin is provided on both of them, and the test mode is designated by the switch or jumper pin only when the device is used for the first time and when the cable between the transmitter 1, the receiver 2 and the device is replaced for repair. It may be an inter-device synchronization circuit that determines the phase difference classification between clocks and updates the corresponding bit of the flash ROM. This is particularly effective when it is required to start up the device for a short time.

Further, the hold circuit 84 is an R-SFF (set-reset FF) with a shift path, and the judgment value (output of the judgment circuit 83) which has been tested once and stored (the output of the judgment circuit 83) is shifted in at the initialization of the receiving device 2 at the time of startup. Therefore, it may be set every time.

Further, it has an interface with both the transmitting device 1 and the receiving device 2, and is capable of collectively controlling ON / OFF of these shift modes, shift in / out, and operation / stop of the clock of these devices. If a console device exists, the following inter-device synchronization circuit may be used.

That is, each test instruction signal of the transmitter 1 and the receiver 2 is set as an FF that can be set only by shift-in in the shift mode, and the host device or console device is in the shift mode in the transmitter 1 and the receiver 2. The test instruction FF of 1 is shifted on. After that, the shift mode is released, the normal clock is output, the clock is stopped, the mode is returned to the shift mode, the value of the R-SFF with the shift path as the hold circuit 84 is read, and this is set at every initialization.

[0064]

As described above, according to the present invention, a circuit for generating a test pattern using a transmitter clock for a transmitter and a test pattern for a receiver having the same cycle as the transmitter are generated using a clock of the receiver. And a circuit for discriminating the phase difference between the test signals, or the phase difference between the transmitter test signal and the receiver test signal, which are sampled and relayed by the inverted clock of the transmitter clock.

Therefore, the phase difference of the clocks of the transmitter and the receiver can be determined regardless of the phase relationship, and which of the receiver clock and its inverted output is appropriate as the data acquisition timing can be determined. Since the data system having the proper timing is selected as the synchronized reception data, there is an effect that the data transmission between the devices having the different clock phases can always be performed accurately.

Further, since the phase difference of the clock between the transmitter and the receiver is determined by using the data transmission line for actually transmitting the data, the phase difference reflects the delay and the waveform distortion of the data transmission line. However, it is not necessary to subtract these influences when determining the phase difference, and there is an effect that the determination circuit can be simplified.

Further, according to the present invention, an FF for taking in data at the timing of the inverted signal of the clock of the transmitter is attached to the input unit of the receiver to shape the waveform distortion at the time of reception and enhance the accuracy of the phase difference determination. be able to.

Further, the timing compensation circuit used in the present invention does not select an unstable acquisition data system (a sample value is not constant every time) which occurs when data is transferred from the transmission device to the reception device. So the transmitter,
If the clock cycle of the receiving device is the same, it is not necessary to change the delay time of the delay element depending on the clock frequency, and it is possible to achieve synchronized transmission with a margin for a wide range of clocks periodically. Have

Further, according to the present invention, a test signal is automatically generated at the time of turning on the power of the apparatus, and a signal for selecting the received data system of the fetched one is automatically set and held at a proper timing, so that the synchronization is performed immediately after the start-up is completed. It has the effect of transmitting the converted data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing details of a timing compensation circuit 81 in FIG.

3 is a time chart of the timing test circuit 82 of FIG. 1 (case 1).

4 is a time chart of the timing test circuit 82 of FIG. 1 (case 2).

5 is a truth table of the timing judgment circuit 83 of FIG.

FIG. 6 is a block diagram showing the overall configuration of a second embodiment of the present invention.

FIG. 7 is a block diagram showing an overall configuration of a third embodiment of the present invention.

FIG. 8 is a block diagram showing the overall configuration of a fourth embodiment of the present invention.

FIG. 9 is a time chart showing the operation of the third embodiment of the present invention.

FIG. 10 is a principle diagram of a conventional method for realizing data transfer between devices.

FIG. 11 is a diagram showing an example in which a received waveform is distorted in conventional data transmission between devices.

[Explanation of symbols]

1 transmitter 2 receiver 3 input data 4 transmitter clock 5 test instruction signal 6 synchronized received data 7 receiver clock 8 transmitter power supply confirmation signal 9 receiver power supply confirmation signal 11, 71, 72 selection circuits 12, 13, 85 , 828, 829 Inverters 21, 22, 31, 32, 41, 42, 51, 52, 6
1, 62 FF 81 Timing compensation circuit 82 Timing test circuit 83 Timing determination circuit 84 Hold circuit 820-827 FF 901 First timer circuit 902 Second timer circuit 903 Counter circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H04L 25/40 G06F 1/04 340D 29/00 H04L 13/00 T (58) Fields investigated (Int.Cl. ⁷ , DB name) ) H04L 7/00 G06F 1/10 G06F 1/12 G06F 13/42 350 H04L 25/02 301 H04L 25/40 H04L 29/00

Claims (6)

(57) [Claims] 1. A transmitter is provided with a circuit for generating a test signal of a constant cycle using a clock of the transmitter in response to a test instruction and transmitting the test signal to a data transmission path, and a receiver is provided with the test signal in response to the test instruction. A circuit for generating a test signal of the same cycle and the same pattern by using a clock of the receiving device, means for discriminating the phase difference between the output of the receiving device and the receiving output of the test signal of the transmitting device, and storing the result, receiving data for the receiving device First data holding means for fetching with the inverted clock of
The second data holding means for fetching the output of the data holding means at the clock of the receiving device and the third data holding means for fetching the received data at the clock of the receiving device, and the second data holding means according to the stored determination result. 2. A synchronizing circuit between devices, characterized in that either one of the output of the data holding means and the output of the third data holding means is selected as the synchronized reception data. 2. In the inter-device synchronization circuit, the transmitted data is taken into an input section of the receiving device by an inverted signal of a transmitting device clock transmitted from the transmitting device through a transmission line equivalent to the data, 2. The inter-device synchronization circuit according to claim 1, further comprising a fourth data holding unit for storing the received data. 3. A timing compensation circuit is provided, which receives a received output of the transmitter test signal, slightly reduces the pulse width of the output, and passes the pulse width to the test signal phase difference classification determination circuit, wherein the determination circuit is a timing margin. 3. The inter-device synchronization circuit according to claim 1, wherein the determination is performed in consideration of. 4. In the inter-device synchronization circuit, if the data width is n (n is a natural number) bits, 1 out of n bits is set.
Only for bits, there is a means for determining the phase difference classification of the test signal from the transmitter and the test signal inside the receiver, and based on the judgment result of the 1-bit phase difference classification,
4. The apparatus according to claim 3, wherein for n-bit data, either one of the output of the second data holding means and the output of the third data holding means is selected and used as the synchronized reception data. Synchronous circuit. 5. A first timer that defines a period from a power supply confirmation signal of the transmission device to a predetermined time A when the transmission device and the reception device are simultaneously supplied with power, and a predetermined timer from a power supply confirmation signal of the reception device. A second timer that defines a period up to time B (B <A) is provided in each of the transmission device and the reception device, and each device turns on the test instruction for a period defined by the timer of its own device. The synchronous circuit between the devices according to claim 4. 6. When the transmitter and the receiver are supplied with power at the same time, the transmitter is provided with a first timer for defining a period from a power supply confirmation signal of the transmitter to a predetermined time A, and the prescribed period. The test instruction of the transmission device is turned on, the reception device counts the pulses of the reception test signal on the synchronized reception data line, and it is detected that the count has reached a predetermined number corresponding to a time sufficiently shorter than the predetermined time A. 7. A counter means for controlling the receiver is turned on, a test instruction of the receiving device is turned on during a period from the power supply confirmation of the receiving device to the detection, and the phase difference classification determination result is set in the storage device at the time of the detection. 4. A synchronization circuit between the devices described in 4.