CN106936531B - A kind of synchronous method of multi-disc based on JESD204B agreements ADC - Google Patents
A kind of synchronous method of multi-disc based on JESD204B agreements ADC Download PDFInfo
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- CN106936531B CN106936531B CN201710305625.2A CN201710305625A CN106936531B CN 106936531 B CN106936531 B CN 106936531B CN 201710305625 A CN201710305625 A CN 201710305625A CN 106936531 B CN106936531 B CN 106936531B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
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Abstract
The invention discloses a kind of synchronous method of multi-disc based on JESD204B agreements ADC, by the adjustment to SYSREF (system reference) signal, ensure SYSREF signals and the sampling clock DCLK_ of ADC firstADCMeet best settling time and retention time, then adjust the time interval T of local multiframe cycle delay, that is, SYSREF signals to LMFC (local multiframe clock) rising edge of receiving terminalRXLMFC, accomplish that the worst link can realize deterministic delays, ensure that synchronization of the multi-disc based on JESD204B agreements ADC, and then ensure that multi-disc ADC is synchronous when repeating to power on or re-establish link.
Description
Technical field
The invention belongs to technical field of signal sampling, more specifically, are related to a kind of multi-disc and are based on JESD204B agreements
The synchronous method of ADC.
Background technology
JESD204B serial transmission protocols (abbreviation JESD204B agreements) are important interface standards in ADC transmission, it
Compared to traditional parallel LVDS interface standard, have many advantages, such as that speed is fast, it is few to occupy I/O pin, just gradually by major institute of ADC factories
Favor.
Transmitting terminal, that is, the ADC and receiving terminal of JESD204B agreements are divided into transport layer, data link layer and physical layer.It is highest
Link rate is 12.5Gb/s.It sees on the whole, sampled data (such as 12bit, 8bit) is encoded in transmitting terminal by 8B/10B
It is packaged into serial data later, unstrings, decode and then restore original sampling after serial transmission to receiving terminal through receiving terminal
Data.
Although JESD204B agreements have, speed is fast, the huge advantages such as few that occupy I/O pin, present in link not
Deterministic delays greatly hinder synchronization of the multi-disc based on JESD204B agreements ADC, to forming the time of JESD204B agreements
The application scenarios such as alternating sampling system (TIADC systems) bring obstacle.Link is embodied in without deterministic delays to re-establish
Receiving terminal cannot determine at the time of point or determining local multiframe under JESD204B agreements during either re-powering
The edge of clock cycle receives data, makes the delay of link have nonrepeatability.
Invention content
It is an object of the invention to overcome the deficiencies in the prior art, propose a kind of multi-disc based on JESD204B agreements ADC's
Synchronous method, to realize deterministic delays.
For achieving the above object, synchronous method of the multi-disc of the present invention based on JESD204B agreements ADC, feature exist
In including the following steps：
(1), in ADC of the multi-disc based on JESD204B agreements, as the FPGA of sampled data receiving terminal and with can
In the data collecting system for generating the Clock management module construction of SYSREF (system reference) signal, the production of Clock management module is adjusted
The raw ADC sampling clocks DCLK_ met the requirementsADCIt is separately input in each ADC, generates the FPGA reference clocks met the requirements
DCLK_FPGABe input in each FPGA, meanwhile, the SYSREF signals that Clock management module is generated be input to each ADC with
And in each FPGA；
(2), the register of good each ADC is configured, and makes to receive SYSREF signals relative to sampling clock DCLK_ADC's
Settling time window is more than time threshold T1, and retention time window is more than time threshold T2, time threshold T1, time threshold T2 roots
It is determined according to specific ADC chips；
(3), the internal register of Clock management module is adjusted by serial SPI protocol, the initial of SYSREF signals is set
Analogue delay value is 0, generates the SYSREF signals of single；
(4), the settling time error flag register of each ADC and the value of retention time error flag register are read；
(5), for arbitrary a piece of ADC, if settling time error flag register and the deposit of retention time error flag
At least one in device is not " 0 " (i.e. " 1 "), then reset accordingly by ADC method to settling time error flag register and
Retention time error flag register is reset, and then increases SYSREF signal imitation length of delays, and adjust by serial SPI protocol
The internal register of Clock management module resets the analogue delay value of SYSREF signals, regenerates the SYSREF of single
Signal, return to step (4)；
If the value of settling time error flag register and retention time error flag register is all " 0 ", at this time table
Bright SYSREF signals and ADC sampling clocks DCLK_ADCSettling time and the retention time be full foot, then jump to step (6)；
(6), it is obtained in receiving terminal i.e. FPGA, the time interval of SYSREF signals to LMFC (local multiframe clock) rising edge
TRXLMFCSo that there are a N value, while meet the following formula：
(TTXOUT+TWIRE(max)+TRXIN(max)) ＜ ((N+1) × TLMFC-TTXLMFC+TRXLMFC)
(TTXOUT+TWIRE(min)+TRXIN(min)) ＞ (N × TLMFC-TTXLMFC+TRXLMFC)
Wherein, TTXOUTFor the time interval that LMFC rising edges in transmitting terminal, that is, ADC are exported to serial data, TWIRE(max)、
TWIRE(min)The line delay maximum value and minimum value of respectively transmitting terminal, that is, ADC to receiving terminal, that is, FPGA, TRXIN(max)、
TRXIN(min)Respectively receiving terminal, that is, FPGA receives serial data to the time interval maximum and minimum value of LMFC rising edges,
TLMFCFor the period of local multiframe clock, TTXLMFCFor SYSREF signals in transmitting terminal, that is, ADC to the time between LMFC rising edges
Interval；
(7), the time interval T for obtaining step (6)RXLMFCLMFC delay time registers in receiving terminal FPGA are sent to, in this way
It ensures that the deterministic delays of link, and then realizes synchronization of the multi-disc based on JESD204B agreements ADC.
The object of the present invention is achieved like this.
Synchronous method of the multi-disc of the present invention based on JESD204B agreements ADC, by SYSREF (system reference) signal
Adjustment, ensures SYSREF signals and the sampling clock DCLK_ of ADC firstADCMeet best settling time and retention time,
Then the time of local multiframe cycle delay, that is, SYSREF signals to LMFC (local multiframe clock) rising edge of receiving terminal is adjusted
It is spaced TRXLMFC, accomplish that the worst link can realize deterministic delays, ensure that multi-disc based on JESD204B agreements ADC's
It is synchronous, and then ensure that multi-disc ADC is synchronous when repeating to power on or re-establish link.
Description of the drawings
Fig. 1 is the data collecting system functional block diagram that multi-disc is built based on JESD204B agreements ADC in the present invention；
Fig. 2 is the diagram of receiving terminal uncertainty delay；
Fig. 3 is the sampled data split oscillogram of ADC sync validities verification, wherein, (a) is sampled data split mistake
Oscillogram, (b) be the correct oscillogram of sampled data split.
Specific embodiment
The specific embodiment of the present invention is described below in conjunction with the accompanying drawings, so as to those skilled in the art preferably
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate the main contents of the present invention, these descriptions will be ignored herein.
Fig. 1 is the data collecting system functional block diagram that multi-disc is built based on JESD204B agreements ADC in the present invention.
In the present embodiment, as shown in Figure 1, the data acquisition that multi-disc is built based on JESD204B agreements ADC in the present invention
System is by multi-disc based on JESD204B agreements ADC, as the FPGA of sampled data receiving terminal and with can generate SYSREF
The Clock management module construction of (system reference) signal.
In the present embodiment, as shown in Figure 1, by the ADC of two panels model AD9625, two panels model kintex-7
The phase-locked loop chip of FPGA and a piece of model LMK04828 build a data collecting system, wherein, ADC is adopted as data
The transmitting terminal of collecting system, receiving terminals of the FPGA as data collecting system, phase-locked loop chip are a piece of as Clock management module
FPGA corresponds to a piece of ADC.
In the present embodiment, synchronous method of the multi-disc of the present invention based on JESD204B agreements ADC includes the following steps：
Step S1：Adjust the ADC sampling clocks DCLK_ that the generation of Clock management module is met the requirementsADCIt is separately input to each
In ADC, the FPGA reference clocks DCLK_ met the requirements is generatedFPGAIt is input in each FPGA, meanwhile, Clock management module will
Its SYSREF signal generated is input in each ADC and each FPGA；
Step S2, the register of good each ADC is configured, and makes to receive SYSREF signals relative to sampling clock
DCLK_ADCSettling time window be more than time threshold T1, retention time window be more than time threshold T2, in the present embodiment,
Time threshold T1 is 150ps, time threshold T2 is 100ps；
In the present embodiment, AD9625, settling time window registers and retention time have been configured by SPI protocol first
Window registers are 0x13C [7 respectively:5] and 0x13B [7:5] register.Their stepping is 35ps, then sends 5 to 0x13C
[7:5] register sends 3 to 0x13B [7:5] register.
Step S3：The internal register of phase-locked loop chip is adjusted by serial SPI protocol, the initial of SYSREF signals is set
Analogue delay value is 0, generates the SYSREF signals of single；
In the present embodiment, the primary simulation delay of the SYSREF signals of ADC1 and ADC2 is adjusted to be 0, is then adjusted
The register of phase-locked loop chip makes it generate the SYSREF signals of single.
The value of S4, the settling time error flag register for the ADC that reads back and retention time error flag register, see whether
For " 0 ".
In the present embodiment, settling time error flag register and retention time error flag register are respectively
0x100 [3] and 0x100 [2], it characterize whether the sampling clock DCLK_ of SYSREF signals and ADCADCSettling time window and
Retention time window is more than the value set in step S2, is the storage 0x100 [3] and 0x100 that reads back respectively when reading for the first time
[2] value is found to be " 1 ".
Step S5：For arbitrary a piece of ADC, if settling time error flag register and retention time error flag are posted
At least one in storage is not " 0 " (i.e. " 1 "), reset accordingly by ADC method to settling time error flag register and
Retention time error flag register is reset, and then increases SYSREF signal imitation length of delays, and adjust by serial SPI protocol
The internal register of Clock management module resets the analogue delay value of SYSREF signals, regenerates the SYSREF of single
Signal, return to step S4；
If the value of settling time error flag register and retention time error flag register is all " 0 ", at this time table
Bright SYSREF signals and ADC sampling clocks DCLK_ADCSettling time and the retention time be full foot, then jump to step S6.
In the present embodiment, " 0 " is set to again to register 0x03A [6] reset set to reset 0x100 [3] and 0x100
[2]。
In the present embodiment, the length of delay for adjusting SYSREF signals is 180ps, regenerates the SYSREF signals of single.
It was found that the value of 0x100 [3] and 0x100 [2] all stabilize to " 0 ", show SYSREF signals and ADC sampling clocks DCLK_ADCBuild
Between immediately and the retention time is full foot.
Step S6：It is obtained in receiving terminal i.e. FPGA, the time of SYSREF signals to LMFC (local multiframe clock) rising edge
It is spaced TRXLMFCSo that there are a N value, while meet the following formula：
(TTXOUT+TWIRE(max)+TRXIN(max)) ＜ ((N+1) × TLMFC-TTXLMFC+TRXLMFC)
(TTXOUT+TWIRE(min)+TRXIN(min)) ＞ (N × TLMFC-TTXLMFC+TRXLMFC)
Wherein, TTXOUTFor the time interval that LMFC rising edges in transmitting terminal, that is, ADC are exported to serial data, TWIRE(max)、
TWIRE(min)The line delay maximum value and minimum value of respectively transmitting terminal, that is, ADC to receiving terminal, that is, FPGA, TRXIN(max)、
TRXIN(min)Respectively receiving terminal, that is, FPGA receives serial data to the time interval maximum and minimum value of LMFC rising edges,
TLMFCFor the period of local multiframe clock, TTXLMFCFor SYSREF signals in transmitting terminal, that is, ADC to the time between LMFC rising edges
Interval.
In the present embodiment, TTXOUTFor 6 frame periods, TWIRE(min)For 0 frame period, TWIRE(max)For 0 frame period,
TRXIN(max)、TRXIN(min)Respectively 92 frame periods and 84 frame periods, TLMFCFor 32 frame periods, TTXLMFCFor 0 frame week
Phase, TRXLMFCIncrement size selected as 0 first, then TRXLMFCJust it is 28 frame periods (T in the present embodimentRXLMFCValue added be
TRXLMFC4 times of increment size, and TRXLMFCIt is increased on the basis of 28), it cannot get one while the N values met at this time.
By TRXLMFCCorresponding increment size increases to 5, then TRXLMFCBecome 28+5*4=48 frame period, again by numerical tape
It can be 1 in the hope of N values to enter, and met the requirements.
Step S7：The time interval T that step S6 is obtainedRXLMFCCorresponding increment size is sent to LMFC in receiving terminal FPGA
Delay time register, ensures that the deterministic delays of link in this way, and then realizes multi-disc based on the same of JESD204B agreements ADC
Step.
In the present embodiment, TRXLMFCIncrement size be 5 (corresponding TRXLMFCValue be 48 frame periods), send 5 to two
LMFC delay time registers 0x010 [11 in piece FPGA:8], the deterministic delays of link are ensured that in this way, and then realize two panels
Synchronization based on JESD204B agreements ADC.
Emulation
1st, receiving terminal deterministic delays are verified
Value proves that the present invention realizes deterministic delays at the time of receiving sampled data by receiving terminal.Do not make
Before this method, receiving terminal, that is, FPGA, which is received at the time of sampled data starts, to be one of two things in Fig. 2, that is, is received
Be at the time of sampled data starts with power on be not both it is uncertain, sometimes early sometimes late, the delay of link is not true
It is fixed.
It after the present invention is used, is powered on by constantly repeating, continuous retest, obtained result is Fig. 2 always
In a kind of situation, this demonstrate that the present invention realizes deterministic delays.
2nd, the validity that verification ADC is synchronized.
Adjust phase-locked loop chip so that the sampling clock 200ps of the sampling clock lag ADC1 front ends of ADC2 front ends, if
Two panels ADC accomplishes to stablize synchronization, then two panels ADC may be constructed the time-interleaved system that sample rate is 5GSPS.By to two
Can the data of piece ADC stablize split to prove the validity of ADC synchronizations.
When SYSREF signals are not using the present invention, the sampled data of split two panels ADC can obtain Fig. 3 (a) or Fig. 3
(b) situation, and as the generation of different both of these case powered on is random.Its basic reason is SYSREF signals
Metastable state region in ADC sampling clocks, be directed toward that the previous ADC sampling periods have at the time of SYSREF signals is caused to have when
It carves and is directed toward the latter sampling period, there is uncertainty.
After the present invention is used, it is ensured that the settling time and retention time of SYSREF, all there are one time windows, did not went out
Existing metastable state repeats to power on and test into excessively continuous, and the data of two panels ADC, which can be stablized, pieces together Fig. 3 (b) forms.Fig. 3
(b) form is also that front end two panels ADC sampling clocks have the reason of certain phase difference, the time-interleaved system of obtained stabilization
Demonstrate the validity of two panels ADC synchronizations.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change appended claim limit and determining the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (2)
1. synchronous method of a kind of multi-disc based on JESD204B agreements ADC, which is characterized in that include the following steps：
(1), in ADC of the multi-disc based on JESD204B agreements, as the FPGA of sampled data receiving terminal and with can generate
In the data collecting system of the Clock management module construction of SYSREF, that is, system reference signal, adjust Clock management module and generate completely
The ADC sampling clocks DCLK_ required enoughADCIt is separately input in each ADC, generates the FPGA reference clocks met the requirements
DCLK_FPGABe input in each FPGA, meanwhile, the SYSREF signals that Clock management module is generated be input to each ADC with
And in each FPGA；
(2), the register of good each ADC is configured, and makes to receive SYSREF signals relative to sampling clock DCLK_ADCFoundation
Time window is more than time threshold T1, and retention time window is more than time threshold T2, and time threshold T1, time threshold T2 are according to tool
The ADC chips of body determine；
(3), the internal register of Clock management module is adjusted by serial SPI protocol, the primary simulation of SYSREF signals is set
Length of delay is 0, generates the SYSREF signals of single；
(4), the settling time error flag register of each ADC and the value of retention time error flag register are read；
(5), for arbitrary a piece of ADC, if in settling time error flag register and retention time error flag register
At least one is not " 0 " i.e. " 1 ", then when resetting method accordingly by ADC to settling time error flag register and holding
Between error flag register reset, then increase SYSREF signal imitation length of delays, and pass through serial SPI protocol adjust clock pipe
The internal register of module is managed, the analogue delay value of SYSREF signals is reset, regenerates the SYSREF signals of single, return
Return step (4)；
If the value of settling time error flag register and retention time error flag register is all " 0 ", show at this time
SYSREF signals and ADC sampling clocks DCLK_ADCSettling time and the retention time be full foot, then jump to step (6)；
(6), it is obtained in receiving terminal i.e. FPGA, SYSREF signals to LMFC are the time interval of local multiframe rising edge clock
TRXLMFCCorresponding increment size：Time interval TRXLMFCCorresponding increment size selected as 0 first cannot get one while meet following
During the N values of formula, increase time interval TRXLMFCCorresponding increment size, until obtaining one while meeting the N values of the following formula；
Described the following formula is：
(TTXOUT+TWIRE(max)+TRXIN(max)) ＜ ((N+1) × TLMFC-TTXLMFC+TRXLMFC)
(TTXOUT+TWIRE(min)+TRXIN(min)) ＞ (N × TLMFC-TTXLMFC+TRXLMFC)
Wherein, TTXOUTFor the time interval that LMFC rising edges in transmitting terminal, that is, ADC are exported to serial data, TWIRE(max)、
TWIRE(min)The line delay maximum value and minimum value of respectively transmitting terminal, that is, ADC to receiving terminal, that is, FPGA, TRXIN(max)、
TRXIN(min)Respectively receiving terminal, that is, FPGA receives serial data to the time interval maximum and minimum value of LMFC rising edges,
TLMFCFor the period of local multiframe clock, TTXLMFCFor SYSREF signals in transmitting terminal, that is, ADC to the time between LMFC rising edges
Interval；
(7), the time interval T for obtaining step (6)RXLMFCCorresponding increment size is sent to LMFC delays in receiving terminal FPGA and posts
Storage, ensures that the deterministic delays of link in this way, and then realizes synchronization of the multi-disc based on JESD204B agreements ADC.
2. synchronous method of the multi-disc according to claim 1 based on JESD204B agreements ADC, which is characterized in that step (2)
In time threshold T1=150ps, time threshold T2=100ps.
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Families Citing this family (7)
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| CN109495090B (en) * | 2018-09-30 | 2022-04-12 | 中国人民解放军海军工程大学 | Digital precise time delay matching circuit |
| CN109542162A (en) * | 2018-11-15 | 2019-03-29 | 南京长峰航天电子科技有限公司 | A kind of clock system of 3Gsps signal processing platform |
| CN112436915B (en) * | 2020-11-05 | 2022-04-22 | 苏州云芯微电子科技有限公司 | SYSREF establishment time and retention time detection system |
| CN113535620B (en) * | 2021-06-29 | 2023-03-07 | 电子科技大学 | Multichannel synchronous high-speed data acquisition device |
| CN114090497A (en) * | 2021-11-17 | 2022-02-25 | 南京理工大学 | Synchronization scheme of high-speed data acquisition clock |
| CN116665730A (en) * | 2022-02-18 | 2023-08-29 | 长鑫存储技术有限公司 | Delay parameter determination method and device, storage medium and electronic equipment |
| CN115604809B (en) * | 2022-09-14 | 2023-11-14 | 哈尔滨工业大学 | Data synchronization method and data acquisition device among multi-wireless synchronization data acquisition modules |
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