CN1385967A - Quickly-locked double-track digital delay phase-locking circuit - Google Patents
Quickly-locked double-track digital delay phase-locking circuit Download PDFInfo
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- CN1385967A CN1385967A CN 01117693 CN01117693A CN1385967A CN 1385967 A CN1385967 A CN 1385967A CN 01117693 CN01117693 CN 01117693 CN 01117693 A CN01117693 A CN 01117693A CN 1385967 A CN1385967 A CN 1385967A
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Abstract
This invention discloses a circuit of generating a delay signal, circuit containing a first delay circuit generating first delay signal, secondary delay circuit generating a second delay signal, a delay unit generating internal delay signal, a first phase detector generating first control signals and a second phase detector generating a second control signal. This invention has got a delay circuit monitor to generate the said first and second delay control signals and a DTC delay unit to generate the said delay signal.
Description
The present invention is about a kind of Design of Digital Circuit, particularly about a kind of Design of Digital Circuit with phase-correcting circuit (phase alignment circuit).
Reference data U.S. patent documents: U.S. Patent number 6,060,928; U.S. Patent number 6,144,713; U.S. Patent number 6,166,572; And U.S. Patent number 6,125,157.
Postpone phase lock circuitry (delayed locked loop) and be used in high-speed phase correcting circuit, for example double data rate Synchronous Dynamic Random Access Memory DDR SDRAM usually.In using the system of DDR SDRAM as memory storage device, the reading of data that needs a data strobe pulse phase control (data strobe phasecontrol) to be sent back to by DDR SDRAM (hereinafter referred to as DDR) with locking (latch).DDR sends data pulse and data at each clock pulse edge, therefore is called " edge calibration " (edgealigned); And write data pulse and data when DDR carries out in each clock pulse central authorities, therefore be called " central authorities' calibration " (center-aligned).This respectively at the method that reads and write with the different clock location triggered, be for simplified design when DDR makes with obtain better acceptance rate.Therefore, when DDR carried out write cycle, system must produce four minutes accurately one postpone to be used for central calibration pulse and data.
Fig. 1 represents typical double rail type digital delay phase lock circuitry (DLL) circuit.Phase detectors 130 compare ext_clk signal and the delay_clk signal that is produced by T/4 delay circuit 115.Delay circuit watch-dog 140 response is from the increment_or_decrement of phase detectors 130 (increase progressively _ or _ successively decrease) signal, output delay_control_number (delays _ control _ number) signal to delay circuit 115 and 116 with the adjustment retardation.Final system convergence and acquisition T/4 delayed clock (delay clock) 150.Yet, drift about because of variation of temperature from the possibility of result of phase detectors 130, cause delay circuit watch-dog 140 to provide improper information to T/4 delay circuit 115 and 116.And process changes the result that also may influence phase detectors 130.Therefore, the present invention proposes one and has twin-lock and decide the digital delay phase lock circuitry circuit of mechanism and dynamic deferred control to solve the above problems.It should be noted that the present invention can produce the inhibit signal of any hope.So the present invention can use in the circuit of any use DLL mechanism.
The invention provides the correct time delay generator of a use double rail type digital delay phase lock circuitry (DLL).This double rail type digital dll comprises first delay circuit, second delay circuit, delay cell, first phase detectors, second phase detectors, delay circuit watch-dog, transducer digit time (DTC) delay cell.
First delay circuit receives the external timing signal and first delayed control signal, to produce first inhibit signal.And second delay circuit receives second delayed control signal and external timing signal, to produce second inhibit signal.Delay cell is used external timing signal, first inhibit signal and second inhibit signal, to produce the internal latency signal.First phase detectors receive the internal latency signal and first inhibit signal, to produce first control signal; And second phase detectors use the internal latency signal and second inhibit signal, to produce second control signal.Delay circuit watch-dog response first and second control signal, and produce first delayed control signal and second delayed control signal.Inhibit signal is produced by DTC delay cell, and wherein DTC delay cell is input as the external timing signal and first delayed control signal.
The invention provides a double rail type and postpone phase lock circuitry, to produce the inhibit signal of wishing.Double rail type DLL design consideration voltage described herein and variation of temperature and dynamically change the delay of DTC delay cell.Can be applicable in any high-speed phase corrective system at this circuit that provides, and retardation can be through introducing N DTC delay cell to delay circuit, and be expanded time into the 1/N cycle.
Fig. 1 represents a known DLL circuit, can produce a T/4 delayed clock.
Fig. 2 represents the double rail type DLL circuit of a design according to the present invention, and it can produce a T/N delayed clock.
Fig. 3 represents the specific embodiment as the DTC delay cell among Fig. 2.
Fig. 4 represents the double rail type DLL circuit of a design according to the present invention, and it can produce a T/4 delayed clock.
Fig. 5 represents the locking example of double rail type DLL circuit.
Fig. 6 represents the leading example of double rail type DLL circuit.
Fig. 7 represents the backward example of double rail type DLL circuit.
Fig. 8 represents that a DTC delay cell changes the nonlinear characteristic that is produced because of process.
Fig. 9 represents that one has the delay circuit of 4 DTC delay cells, changes the nonlinear characteristic that is produced because of process.
Consult Fig. 2, the double rail type DLL circuit of its expression one design according to the present invention can produce a T/N delayed clock, and wherein T is that clock cycle time (clock cycle time) and N are predetermined numbers.Double rail type DLL circuit of the present invention comprises: first delay circuit 200, second delay circuit 220, delay cell are preferably a half-resolution (half-resolution) delay cell 235, first phase detectors 245, second phase detectors 255, delay circuit watch-dog 265 and DTC delay cell 270.
Fig. 3 represents that how DTC delay cell transforms 4 delay control figures input 305 is inhibit signal output 310.DTC delay cell comprises a digital delay number coding device 320.Digital delay number coding device 320 receives 4 to postpone control figure input 305 and produces D0, D1... to D15 signal, always has 16 and postpone scale (Tscale) in DTC delay cell, as D (n)=1, represents that the delay of a correspondence exists.Therefore, DTC delay cell is imported 305 receiving inputted signals 315 and output delay signal output 310 according to 4 delay control figures.
Please refer to Fig. 4.In preferred embodiment of the present invention, the number of the DTC delay cell in first delay circuit 400 and second delay circuit 420 equals 4 respectively.That is N=4.400 responses of first delay circuit have first delayed control signal (delay_control_count) and the ext_clk signal of k value, and produce first inhibit signal (delay_clk (k)), and it is at least the function of k.420 responses of second delay circuit have second delayed control signal (delay_control_count_1) and the ext_clk signal of k+1 value, and produce second inhibit signal (delay_clk (k+1)), and it is at least the function of (k+1).The time difference of delay_clk (k) and delay_clk (k+1) is defined as the resolution Tres of a minimum, and it also is the minimum resolution of first delay circuit 400 and second delay circuit 420.So delay_clk (k) is than the leading Tres of delay_clk (k+1).
Moreover the internal latency signal (int_clk) that is produced by half-resolution delay cell 435 postpones one 1/2 Tres than ext_clk.First phase detectors 445 are int_clk and delay_clk (k) relatively, and exports first control signal (successively decreasing); Second phase detectors 455 are int_clk and delay_clk k+1 relatively, and exports second control signal (increasing progressively).In preferred embodiment, first phase detectors 445 and second phase detectors 455 are respectively d type flip flop (D-flip-flop).
In order to make first phase detectors 445 and second phase detectors 455 correctly lock delay_clk (k) and delay_clk (k+1), int_clk should drop between delay_clk (k) and the delay_clk (k+1).The time that is provided with (Tsetup) that is necessary to provide enough is to first phase detectors 445, and enough holding time (Thold) is to second phase detectors 455.Therefore, Tres should be big than the summation of Tsetup and Thold.That is, Tres 〉=(Tsetup+Thold).Yet known in most example, Tsetup is bigger than Thold.So, in preferred embodiment, set:
Tres 〉=2
*Tsetup ... equation (1).
In a preferred embodiment of the present invention, all DTC delay cells in first delay circuit 400 and second delay circuit 420 all are the same.The resolution Tres of the minimum of DTC delay cell is defined by the twice Tsetup of above-mentioned d type flip flop.If the Tsetup of d type flip flop is 0.2ns (nanosecond), then can select Tres is 0.5ns, and it is greater than 2
*Tsetup, and the delay that is produced by half-resolution delay cell is 0.25ns.
With reference to figure 5.When delay_clk (k) and ext_clk calibration, promptly meet the situation of locking.Delay_clk (k) is just caing be compared to ext_clk clock cycle of evening, and delay_clk (k+1) adds Tres than a late clock cycle of ext_clk.Under the situation of locking, it is 0 that first phase detectors 445 are set the reduction signal, and second phase detectors, 455 setting recruitment signals are 0.Then delay circuit watch-dog 465 can not change the value of delay_control_count and delay_control_count_1.
DTC delay cell 470 response ext_clk and delay_control_count produce inhibit signal 475.Therefore, in the example of N=4, can from DTC delay cell 470, obtain an one-period delay clock signals 475 of four minutes.
In the leading example as shown in Figure 6, the leading ext_clk of delay_clk (k) is less than the amount of a clock cycle.In leading example, it is 0 that first phase detectors 445 are set the reduction signal, and second phase detectors, 455 setting recruitment signals are 1.Then delay circuit watch-dog 465 is an increment with 1, increases the value of delay_control_count and delay_control_count_1 respectively.First delay circuit, 400 response ext_clk and delay_control_count produce delay_clk (k).Second delay circuit, 420 response ext_clk and delay_control_count_1 produce delay_clk (k+1).Therefore the delay of first delay circuit 400 and second delay circuit 420 increases.If the still leading ext_clk of delay_clk (k) is less than the amount of a clock cycle, then double rail type DLL circuit continues above-mentioned step, till the locking example that reaches as shown in Figure 5.
For falling behind example as shown in Figure 7, delay_clk (k) falls behind the amount that ext_ clk is less than a clock cycle.In the example that falls behind, it is 1 that first phase detectors 445 are set the reduction signal, and second phase detectors, 455 setting recruitment signals are 0.Then delay circuit watch-dog 465 is a reduction with 1, reduces the value of delay_control_count and delay_control_count_1.First delay circuit, 400 response ext_clk and delay_control_count produce delay_clk (k).Second delay circuit, 420 response ext_clk and delay_control_count_1 produce delay_clk (k+1).Therefore, the delay of first delay circuit 400 and second delay circuit 420 reduces.If delay_clk (k) still falls behind the amount that ext_clk is less than a clock cycle, then double rail type DLL circuit continues above-mentioned step, till the locking example that reaches as shown in Figure 5.
In addition, if in the circuit part of DTC delay cell, nonlinear characteristic is arranged, can't influence the convergence of system.Because two delay circuits 400 and 420 are symmetric circuit structures, both along with process, temperature, and the change of supply power voltage and in the same way and percentage change.Fig. 8 represents that one occurs in the nonlinear characteristic of 8 (promptly 1000) that the postpone control figure input 305 delay scale (Tscale) of the single DTC unit of (promptly 1001) scope to 9.The value of Tscale changes to 0.25ns from 0.125ns, causes a nonlinear situation.In view of the above, the minimum resolution of first delay circuit 400 and second delay circuit 420 (being Tres) is changed to 1ns from 0.5ns as shown in Figure 9.Int_clk has the drift of a 0.25ns with respect to ext_clk.Therefore int_clk still drops between delay_clk (k) and the delay_clk (k+1), and double rail type DLL circuit can allow PVT (process, voltage, temperature) to change.
In addition, the design of double rail type digital dll can easily produce the T/N time delay, and wherein N is respectively the number of DTC delay cell in first delay circuit 400 and second delay circuit 420, and T is time clock cycle.With reference to the embodiment of figure 3, suppose in single DTC delay cell of the present invention it is not to have 16 to postpone scale, but have L Tscales.The then following equation that pushes away satisfies the situation of locking, shown in equation (2).
T=Tscale
*L
*N ... equation (2).
Then, Tres=delay_clk (K+1)-delay_clk (K)=Tscale
*(K+1)
*N-Tscale
*L
*N=Tscale
*N ... equation (3).
From above-mentioned equation (1), (2) and (3), when lock condition takes place, T=L
*Tres 〉=2L
*Tsetup ... equation (4).
From equation (2), Tscale 〉=(2/N)
*Tsetup ... equation (5).
In a preferred embodiment, suppose Tsetup=0.2ns, then can select Tres from equation (1) is 0.5ns, if the target period time (T) is 7.5ns (being real-time clock (RTC) frequency 133MHz), can select L=15 from equation (4).
In another preferred embodiment, suppose N=4 in equation (5), if selection Tsetup is 0.2ns, Tscale 〉=0.5 then
*Tsetup=0.1ns.Therefore Tscale should change to allow PVT greater than 0.1ns.
Though the present invention with preferred embodiment openly as above; right its is not that any those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention in order to qualification the present invention; when can changing and revise, so protection scope of the present invention is as the criterion with the accompanying Claim restricted portion.
Claims (20)
1. circuit that produces inhibit signal comprises:
First delay circuit responds an external timing signal and first delayed control signal, to produce first inhibit signal;
Second delay circuit responds second delayed control signal and this external timing signal, to produce second inhibit signal;
Delay cell responds this external timing signal, to produce the internal latency signal;
First phase detectors respond this internal latency signal and this first inhibit signal, to produce first control signal;
Second phase detectors respond this internal latency signal and this second inhibit signal, to produce second control signal;
The delay circuit watch-dog, respond this first and this second control signal, to produce this first delayed control signal and this second delayed control signal; And
Digit time, transducer DTC delay cell responded this external timing signal and this first delayed control signal, to produce this inhibit signal.
2. circuit as claimed in claim 1, wherein this first delay circuit and this second delay circuit have N DTC delay cell respectively, and N is a predetermined number.
3. circuit as claimed in claim 2, wherein N equals 4.
4. circuit as claimed in claim 1, wherein this internal latency signal that is produced by this delay cell is than these one 1/2 Tres times of delayed external clock signal, and wherein Tres is the time difference of this first inhibit signal and this second inhibit signal.
5. circuit as claimed in claim 1, wherein this delay cell further responds this first inhibit signal and this second inhibit signal.
6. circuit as claimed in claim 1, wherein this first delayed control signal and this second delayed control signal have an initial value k and a k+1 respectively, k is a number, this delay circuit watch-dog through following steps produce this first and this second delayed control signal:
If this first control signal be 1 and this second control signal be 0, be the value that reduction reduces this first delayed control signal (k) and this second delayed control signal (k+1) then with 1; And
If this first control signal be 0 and this second control signal be 1, be the value that increment increases this first delayed control signal (k) and this second delayed control signal (k+1) then with 1.
7. circuit as claimed in claim 2, wherein this inhibit signal that is produced by this DTC delay cell is than this one T/N time of delayed external clock signal, and T is time one-period of this external timing signal, and N is a predetermined number.
8. circuit as claimed in claim 3, wherein this inhibit signal that is produced by this DTC delay cell is than this one T/4 time of delayed external clock signal.
9. circuit as claimed in claim 1, wherein these first phase detectors are d type flip flops.
10. circuit as claimed in claim 1, wherein these second phase detectors are d type flip flops.
11. a method that produces an inhibit signal comprises following steps:
First delay circuit is provided, and response external clock signal and this first delayed control signal are to produce first inhibit signal;
Second delay circuit is provided, responds second delayed control signal, to produce second inhibit signal;
Delay cell is provided, responds this external timing signal, to produce the internal latency signal;
First phase detectors are provided, and response internal latency signal and this first inhibit signal are to produce first control signal;
Second phase detectors are provided, respond this internal latency signal and this second inhibit signal, to produce second control signal;
The delay circuit watch-dog is provided, respond this first and this second control signal, to produce this first delayed control signal and this second delayed control signal; And
Provide digit time transducer DTC delay cell, respond this external timing signal and this first delayed control signal, to produce this inhibit signal.
12. method as claimed in claim 11, wherein this first delay circuit and this second delay circuit have N DTC delay cell respectively, and N is a predetermined number.
13. method as claimed in claim 12, wherein N equals 4.
14. method as claimed in claim 11, wherein this internal latency signal that is produced by this delay cell is than these one 1/2 Tres times of delayed external clock signal, and wherein Tres is a time difference of this first inhibit signal and this second inhibit signal.
15. method as claimed in claim 11, wherein this delay cell further responds this first inhibit signal and this second inhibit signal.
16. method as claimed in claim 11, wherein this first delayed control signal and this second delayed control signal have an initial value k and a k+1 respectively, k is a number, this delay circuit watch-dog through following steps produce this first and this second delayed control signal:
If this first control signal be 1 and this second control signal be 0, be the value that reduction reduces this first delayed control signal k and this second delayed control signal k+1 then with 1; And
If this first control signal be 0 and this second control signal be 1, be the value that increment increases this first delayed control signal k and this second delayed control signal k+1 then with 1.
17. method as claimed in claim 11, wherein this inhibit signal that is produced by this DTC delay cell is than this one T/N time of delayed external clock signal, and T is time one-period of this external timing signal, and N is a predetermined number.
18. method as claimed in claim 11, wherein this inhibit signal that is produced by this DTC delay cell is than this one T/4 time of delayed external clock signal.
19. method as claimed in claim 11, wherein these first phase detectors are d type flip flops.
20. method as claimed in claim 11, wherein these second phase detectors are d type flip flops.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011176938A CN1148876C (en) | 2001-05-16 | 2001-05-16 | Quickly-locked double-track digital delay phase-locking circuit |
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| CNB011176938A CN1148876C (en) | 2001-05-16 | 2001-05-16 | Quickly-locked double-track digital delay phase-locking circuit |
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| CN1148876C CN1148876C (en) | 2004-05-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102035542A (en) * | 2010-10-19 | 2011-04-27 | 钰创科技股份有限公司 | Delay-locked-loop circuit with dynamic accelerating phase-hunting function and method thereof |
| CN102930836A (en) * | 2011-08-09 | 2013-02-13 | 瑞鼎科技股份有限公司 | Source electrode driving device capable of automatically adjusting signal offset |
| CN111208867A (en) * | 2019-12-27 | 2020-05-29 | 芯创智（北京）微电子有限公司 | DDR (double data Rate) read data integer clock cycle-based synchronization circuit and synchronization method |
-
2001
- 2001-05-16 CN CNB011176938A patent/CN1148876C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102035542A (en) * | 2010-10-19 | 2011-04-27 | 钰创科技股份有限公司 | Delay-locked-loop circuit with dynamic accelerating phase-hunting function and method thereof |
| CN102035542B (en) * | 2010-10-19 | 2012-08-01 | 钰创科技股份有限公司 | Delay-locked-loop circuit with dynamic accelerating phase-hunting function and method thereof |
| CN102930836A (en) * | 2011-08-09 | 2013-02-13 | 瑞鼎科技股份有限公司 | Source electrode driving device capable of automatically adjusting signal offset |
| CN102930836B (en) * | 2011-08-09 | 2014-11-19 | 瑞鼎科技股份有限公司 | Source electrode driving device capable of automatically adjusting signal offset |
| CN111208867A (en) * | 2019-12-27 | 2020-05-29 | 芯创智（北京）微电子有限公司 | DDR (double data Rate) read data integer clock cycle-based synchronization circuit and synchronization method |
| CN111208867B (en) * | 2019-12-27 | 2021-08-24 | 芯创智（北京）微电子有限公司 | DDR (double data Rate) read data integer clock cycle-based synchronization circuit and synchronization method |
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| CN1148876C (en) | 2004-05-05 |
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