CN102035542A - Delay-locked-loop circuit with dynamic accelerating phase-hunting function and method thereof - Google Patents
Delay-locked-loop circuit with dynamic accelerating phase-hunting function and method thereof Download PDFInfo
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Abstract
The invention discloses a delay-locked-loop circuit with a dynamic accelerating phase-hunting function and a method thereof, wherein the method comprises the following steps: detecting a total loop delay of an input period signal in the delay-locked-loop circuit; setting an optimum divisor according to the total loop delay; and in a locked phase stage of the delay-locked-phase loop circuit, carrying out frequency elimination on the input period signal and a feedback period signal corresponding to the input period signal by the optimum divisor.
Description
Technical field
(more particularly, relevant a kind of tool dynamically quickens to chase after the delay locked loop circuit of phase function to the relevant a kind of delay locked loop of the present invention for Delay Locked Loop, DLL) circuit.
Background technology
In prior art, in order to increase the stability of delay locked loop circuit, can in delay locked loop circuit, add frequency eliminator, to avoid when the frequency of input periodic signal is too high, producing unsettled situation.Yet the phase velocity that chases after that adds the delay locked loop circuit of frequency eliminator can be because periodic signal be reduced by frequency elimination.Thus, the time that delay locked loop circuit will be locked into the phase place of input periodic signal just can increase, and reduces the usefulness of delay locked loop circuit.In other words, if the divisor of frequency eliminator is low excessively, the stability of delay locked loop circuit also can be lower; If the divisor of frequency eliminator is too high, the efficient of delay locked loop circuit also can reduce.Therefore, in the prior art, the frequency eliminator of fixed divisor must allow the efficient of delay locked loop circuit reduce or stability reduces, and causes user's inconvenience.
Summary of the invention
The invention provides the delay locked loop circuit that a kind of tool dynamically quickens to chase after the phase function.This delay locked loop circuit comprises a voltage controlled delay line circuit, is used for receiving an input periodic signal and a control voltage, and exports periodic signal according to this input periodic signal of this control voltage delay to produce one; One predetermined delay circuit is used for this output periodic signal of a scheduled time length delay, to produce a feedback cycle signal; One adjustable divisor frequency eliminating circuit is used for respectively to this input periodic signal and this feedback cycle signal frequency elimination, to produce a frequency elimination input periodic signal and a frequency elimination feedback cycle signal respectively; One phase/frequency detector is used for relatively the phase place of this frequency elimination input periodic signal and this frequency elimination feedback cycle signal, to produce a rising signals or a decline signal according to this; And a charge pump, be used for adjusting this control voltage according to this rising signals and this dropping signal; Wherein this adjustable divisor frequency eliminating circuit detects the total loop delay of this input periodic signal in this delay locked loop circuit, to produce a best divisor according to this, comes respectively this input periodic signal and this feedback cycle signal to be carried out frequency elimination.
The present invention provides a kind of method of phase velocity with the performance that promotes this delay locked loop circuit that chase after of dynamic adjustment one delay locked loop circuit in addition.This method comprises the total loop of detection one input periodic signal in this delay locked loop circuit and postpones; Postpone according to this total loop, set a best divisor; And in the phase-locked stage of this delay locked loop circuit, this an input periodic signal and a feedback cycle signal that corresponds to this input periodic signal are carried out frequency elimination with this best divisor.
Description of drawings
Fig. 1 is the schematic diagram that dynamic acceleration chases after the delay locked loop circuit of phase function that has of the present invention;
Fig. 2 is the schematic diagram of delay locked loop circuit when running that dynamic acceleration chases after the phase function that have of the present invention;
Fig. 3 is the schematic diagram of adjustable divisor frequency eliminating circuit of the present invention;
Fig. 4 is the schematic diagram of the circuit embodiments of adjustable divisor frequency eliminating circuit of the present invention;
Fig. 5 is the sequential chart of delay locked loop circuit of the present invention internal signal when using the adjustable divisor frequency eliminating circuit.
Wherein, Reference numeral:
100 delay locked loop circuits
110 adjustable divisor frequency eliminating circuits
120 phase/frequency detectors
130 charge pumps
140 voltage controlled delay line circuit
150 predetermined delay circuit
The SUP rising signals
The SDN dropping signal
CLKIN, CLKFB, CLKOUT, CLKIN_DV, CLKFB_DV periodic signal
VX controls voltage
TA, TB time span
111,410 timers
112,420 best divisor testing circuits
113,430 frequency eliminators
421 best divisor detectors
422 best divisor buffers
423 logical operation circuits
4221 delay circuits
INV1～INV10 inverter
F1～F8 trigger
G1～G10 gate
The LT bolt lock device
ID1～ID4 divisor input
DV1～DV4 divisor
SRST1 divisor reset signal
SRST2 detects reset signal
The SST commencing signal
The anti-phase commencing signal of SSTB
The MUX multiplexer
Embodiment
In view of this, the present invention proposes a kind of delay locked loop circuit that dynamic acceleration chases after the phase function that has, and comes frequency elimination with the frequency eliminator of adjustable aliquot, with stability and the efficient that improves delay locked loop circuit simultaneously.
Please refer to Fig. 1.Fig. 1 is the schematic diagram that dynamic acceleration chases after the delay locked loop circuit 100 of phase function that has of the present invention.As shown in Figure 1, delay locked loop circuit 100 comprises an adjustable divisor frequency eliminating circuit 110, a phase/frequency detector (Phase/Frequency Detector, PFD) 120, one charge pump 130, a voltage controlled delay line (Voltage Control Delay Line, VCDL) circuit 140, and a predetermined delay circuit 150.
Adjustable divisor frequency eliminating circuit 110 receives input periodic signal CLK
INWith feedback cycle signal CLK
FB, and will import periodic signal CLK respectively
INWith feedback cycle signal CLK
FBFrequency elimination is to export frequency elimination input periodic signal CLK respectively
IN_DVWith frequency elimination feedback cycle signal CLK
FB_DV
Phase/frequency detector 120 receives frequency elimination input periodic signal CLK
IN_DVWith frequency elimination feedback cycle signal CLK
FB_DV, and relatively frequency elimination is imported periodic signal CLK
IN_DVWith frequency elimination feedback cycle signal CLK
FB_DV, to export rising signals S according to this
UPOr dropping signal S
DNAs frequency elimination input periodic signal CLK
IN_DVPhase-lead in frequency elimination feedback cycle signal CLK
FB_DVThe time, phase/frequency detector 120 output rising signals S
UPAs frequency elimination input periodic signal CLK
IN_DVPhase lag in frequency elimination feedback cycle signal CLK
FB_DVThe time, phase/frequency detector 120 output dropping signal S
DN
Voltage controlled delay line circuit 140 receives input periodic signal CLK
IN, and according to control voltage V
X, postpone input periodic signal CLK
IN, to produce output periodic signal CLK
OUTAs control voltage V
XDuring rising, 140 pairs of inputs of voltage controlled delay line circuit periodic signal CLK
INDelay descend; As control voltage V
XDuring decline, 140 pairs of inputs of voltage controlled delay line circuit periodic signal CLK
INDelay rise.
Predetermined delay circuit 150 receives output periodic signal CLK
OUT, and postpone to export periodic signal CLK with a scheduled delay
OUT, to produce feedback cycle signal CLK according to this
FB
Please refer to Fig. 2.Fig. 2 has the schematic diagram of delay locked loop circuit 100 when running that dynamic acceleration chases after the phase function for explanation is of the present invention.As shown in Figure 2, after delay locked loop circuit 100 of the present invention is activated, can be introduced into detection-phase, enter the phase stage that chases after then, enter the phase-locked stage at last.Postpone phase lock circuitry 100 and be activated the back, then can after park mode finishes, enter once again and chase after the phase stage, and then enter the phase-locked stage if enter park mode.The time span in stage is fixed as time span T all respectively with chasing after mutually to it should be noted that detection-phase
AWith T
B, and the time span in above-mentioned stage can be finished by a timer.In detection-phase, adjustable divisor frequency eliminating circuit 110 can't carry out frequency elimination (meaning is that divisor is " 1 "); The total loop that adjustable divisor frequency eliminating circuit 110 can detect delay locked loop circuit 100 postpones, divisor can be set to a best divisor to judge when phase-locked stage, so allow the stability of delay locked loop circuit 100 when phase-locked stage can be the highest and efficient also can not reduce.More particularly, when detection-phase, delay locked loop circuit 100 can discharge input periodic signal CLK
INA pulse signal to delay locked loop circuit 100, again according to feedback cycle signal CLK
FBCorresponding to the pulse signal that this pulse signal produced, judge that the total loop in delay locked loop circuit 100 postpones, so just can learn the optimum value (best divisor) of the divisor of adjustable divisor frequency eliminating circuit 110.Chasing after phase during the stage, adjustable divisor frequency eliminating circuit 110 equally also can not carry out frequency elimination, so just can allow the phase velocity that chases after of delay locked loop circuit 100 need the phase-locked time for the fastest can the shortening.Therefore, when phase-locked stage, adjustable divisor frequency eliminating circuit 110 just can be according to best divisor, to input periodic signal CLK
INWith feedback cycle signal CLK
FBCarry out frequency elimination.In addition, when phase-locked stage, the mode of adjustable divisor frequency eliminating circuit 110 frequency eliminations can be directly divisor to be set at best divisor to come input periodic signal CLK
INWith feedback cycle signal CLK
FBCarry out frequency elimination, perhaps, divisor set from " 1 " beginning increase to best divisor gradually, so just can not cause divisor moment great variety to be arranged and allow delay locked loop circuit 100 produce unsettled situation.
Please refer to Fig. 3.Fig. 3 is the schematic diagram of explanation adjustable divisor frequency eliminating circuit 110 of the present invention.As shown in Figure 3, adjustable divisor frequency eliminating circuit 110 comprises a timer 111, one best divisor testing circuit 112, and a frequency eliminator 113.
112 input periodic signal CLK that discharged in the detection-phase detection of best divisor testing circuit
INThe total loop of pulse signal in delay locked loop circuit 100 postpone, drawing a best divisor, and export one and specify divisor.Best divisor testing circuit 112 is chasing after the appointment divisor lower (equaling " 1 " as specifying divisor) that phase was exported during the stage, then the numerical value of the appointment divisor exported can be promoted to best divisor gradually when phase-locked stage.
113 of frequency eliminators receive the appointment divisor that best divisor testing circuit 112 is exported, and will import periodic signal CLK according to this
INWith feedback cycle signal CLK
FBFrequency elimination is to produce frequency elimination input periodic signal CLK
IN_DVWith frequency elimination feedback cycle signal CLK
FB_DV
Please refer to Fig. 4.Fig. 4 is the schematic diagram of the circuit embodiments of explanation adjustable divisor frequency eliminating circuit 400 of the present invention.Adjustable divisor frequency eliminating circuit 400 designs for " 4 " with maximum divisor.As shown in Figure 4, adjustable divisor frequency eliminating circuit 400 comprises timer 410, best divisor testing circuit 420 and frequency eliminator 430.
Best divisor testing circuit 420 comprises best divisor detector 421, one a best divisor buffer 422, and a logical operation circuit 423.Best divisor detector 421 comprises inverter INV
1, bolt lock device LT, gate G
3With G
4, multiplexer MUX, and trigger F
1～F
5Bolt lock device LT comprises gate G
1With G
2 Best divisor buffer 422 comprises delay circuit 4221 and trigger F
6～F
8Delay circuit 4221 comprises INV
2～INV
4 Logical operation circuit 423 comprises gate G
5～G
10And inverter INV
5～INV
10Gate G
1With G
2Be NOR gate (NOR gate), gate G
3～G
10Be NAND gate (NANDgate).Trigger F
1～F
8For D flip-flop and for rising edge triggers, and trigger F
1～F
8All comprise a data input pin D, a data output end Q, and a frequency input CK.Delay circuit 4221 be configured such that trigger F
6～F
8Frequency input the CK frequency signal and the trigger F that are received
1～f
5The frequency signal that received of frequency input CK synchronous, therefore the quantity of inverter wherein can change according to the actual requirements.
Inverter INV
1Receive commencing signal S
STAnd anti-phase according to this, and produce anti-phase commencing signal S
STBTwo inputs of bolt lock device LT receive feedback cycle signal CLK respectively
FBAnd anti-phase commencing signal S
STB, its output is coupled to gate G
4An input.The control end C of multiplexer MUX receives commencing signal S
STAs commencing signal S
STDuring expression beginning (logical one), multiplexer MUX is with its input I
1Be coupled to its output O; Otherwise multiplexer MUX is with its input I
2Be coupled to its output O.In addition, the input I of multiplexer MUX
1Be coupled to gate G
4The input I of multiplexer MUX
2Receive switching signal S
SWThe output O of multiplexer MUX is coupled to trigger F
1～F
5Frequency input CK.Frequency eliminator 430 comprises four divisor input I
D1～I
D4, two input I
1With I
2, and two output O
1With O
2Four divisor input I of frequency eliminator 430
D1～I
D4Be respectively coupled to the inverter INV of logical operation circuit 423
7～INV
10Output; The input I of frequency eliminator 430
1Receive input periodic signal CLK
IN, frequency eliminator 430 input I
2Receive feedback cycle signal CLK
FBThe output O of frequency eliminator 430
1Output frequency elimination input periodic signal CL
KI_DV, frequency eliminator 430 output O
2Output frequency elimination feedback cycle signal CLK
FB_DVFrequency eliminator 430 is according to divisor input I
D1～I
D4On the logic of signal decide divisor.More particularly, as divisor input I
D1On the logic of signal be 1 o'clock, the divisor of frequency eliminator 430 is 1; As divisor input I
D2On the logic of signal be 1 o'clock, the divisor of frequency eliminator 430 is 2; As divisor input I
D3On the logic of signal be 1 o'clock, the divisor of frequency eliminator 430 is 3; As divisor input I
D4On the logic of signal be 1 o'clock, the divisor of frequency eliminator 430 is 4.For instance, as divisor input I
D3On the logic of signal be 1 o'clock, then frequency eliminator 430 will be imported periodic signal CLK respectively
INWith feedback cycle signal CLK
FBFrequency remove 3 to draw frequency elimination input periodic signal CLK
IN_DV(its frequency equals to import periodic signal CLK
INFrequency 1/3rd) with frequency elimination feedback cycle signal CLK
FB_DV(its frequency equals feedback cycle signal CLK
FBFrequency 1/3rd).In addition, it should be noted that trigger F
1Data input pin D receive logic 1; Gate G
8An input receive logic 1.
As commencing signal S
STDuring expression " beginning " (logical one), meaning is anti-phase commencing signal S
STBBe logical zero, expression delay locked loop circuit 100 is in detection-phase, at this moment the input I of multiplexer MUX
1Be coupled to its output O, and input periodic signal CLK
INCan pass through gate G
3With G
4Be sent to the input I of multiplexer MUX
1, so the trigger F in the best divisor detector 421
1～F
5Can be transfused to periodic signal CLK
INRising edge give to trigger with trigger F
1The data (logical one) that received of data input pin D transmit and offer trigger F in the best divisor buffer 422 in regular turn
6～F
8The input periodic signal CLK that is discharged when delay locked loop circuit 100
INThe pairing feedback cycle signal of a pulse signal CLK
FBWhen producing rising edge accordingly, then bolt lock device LT output logic 1 is to gate G
4And feasible input periodic signal CLK
INCan't pass through gate G again
4Be sent to trigger F
1～F
5That is to say the input periodic signal CLK that is discharged when delay locked loop circuit 100
INPulse signal when getting back to adjustable divisor frequency eliminating circuit 400 through the whole loop of delay locked loop circuit 100, trigger F
1～F
5The action of Data transmission (logical one) promptly stops.Therefore logical operation circuit 430 just can be according to the trigger F in the best divisor buffer 422
6～F
8State carry out logical operation with in inverter INV
7～INV
10Export divisor DV respectively
1～DV
4Divisor input I to frequency eliminator 430
D1～I
D4Frequency eliminator 430 is again according to divisor DV
1～DV
4Logic state select the divisor that will use, and this moment, selected divisor was best divisor.
As commencing signal S
STDuring expression " closing " (logical zero), the expression detection-phase finishes, and enter the phase stage that chases after.At this moment, the input I of multiplexer MUX
2Be coupled to its output O, meaning is trigger F
1～F
5Frequency input CK can receive switching signal S
SW, and this moment, timer 410 can send the divisor reset signal S of logical one
RST1Trigger F to best divisor detector 421
1～F
5The divisor of frequency eliminator 430 is set at 1 (meaning promptly has only divisor DV under this state to remove all data
1Be logical one).And chasing after phase in the stage, switching signal S
SWBe failure to actuate and be maintained 1 with the divisor that keeps frequency eliminator 430.When chasing after the phase stage when finishing to enter phase-locked stage, switching signal S
SWBegin to carry out transition and trigger trigger F in the best divisor detector 421 to produce rising edge
1～F
5Transmit data, in regular turn divisor is increased progressively.More particularly, when delay locked loop circuit 100 had just entered phase-locked stage, frequency eliminator 430 employed divisors still were that 1 (meaning is divisor DV
1Logic be 1), this moment switching signal S
SW(meaning is divisor DV to allow frequency eliminator 430 employed divisors become 2 to produce first rising edge to carry out the transition first time
2Logic be 1) ... by that analogy, till frequency eliminator 430 employed divisors are best divisor.
In addition, if will detect best divisor again, then detect reset signal S
RST2Expression " replacement " (as logical one) is to remove trigger F in the best divisor buffer 422
6～F
8Data, so just can detect best divisor again.
Please refer to Fig. 5.The sequential chart of internal signal when Fig. 5 uses adjustable divisor frequency eliminating circuit 400 for explanation delay locked loop circuit of the present invention.As shown in Figure 5, in detection-phase, corresponding to input periodic signal CLK
INThe pulse signal that is discharged, feedback cycle signal CLK
FBIn input periodic signal CLK
INProduce corresponding pulse signal before the 4th rising edge after the pulse signal that is discharged, therefore can judge according to this that best divisor is 3 (DV
3Be logical one).After detection-phase finishes, when delay locked loop circuit 100 1 enters the phase stage that chases after, divisor reset signal S
RST1Table " replacement " (logical one) so can quicken the speed that delay locked loop circuit 100 chases after phase the employed divisor of frequency eliminator is made as 1 (not frequency elimination).After chasing after the end of phase stage, when delay locked loop circuit 100 1 enters phase-locked stage, switching signal S
SWBegin to carry out transition to produce rising edge.So so that the employed divisor of frequency eliminator is increased gradually, to improve the stability of delay locked loop circuit.
In sum, delay locked loop circuit provided by the present invention, has the function that dynamic acceleration chases after phase, the total loop that can detect delay locked loop circuit at detection-phase postpones to determine best divisor, can come the periodic signal frequency elimination to reach the fastest phase velocity that chases after with minimum divisor chasing after the phase stage, and improve the stability of delay locked loop circuit at the divisor that the phase-locked stage can be adjusted frequency eliminator gradually, so can offer the bigger convenience of user.
The above only is preferred embodiment of the present invention, and all equalizations of being made according to the present patent application scope of patent protection change and revise, and all should belong to covering scope of the present invention.
Claims (10)
1. the dynamic delay locked loop circuit that quickens to chase after the phase function of tool is characterized in that, comprises:
One voltage controlled delay line circuit is used for receiving an input periodic signal and a control voltage, and exports periodic signal according to this input periodic signal of this control voltage delay to produce one;
One predetermined delay circuit is used for this output periodic signal of a scheduled time length delay, to produce a feedback cycle signal;
One adjustable divisor frequency eliminating circuit is used for respectively to this input periodic signal and this feedback cycle signal frequency elimination, to produce a frequency elimination input periodic signal and a frequency elimination feedback cycle signal respectively;
One phase/frequency detector is used for relatively the phase place of this frequency elimination input periodic signal and this frequency elimination feedback cycle signal, to produce a rising signals or a decline signal according to this; And
One charge pump is used for adjusting this control voltage according to this rising signals and this dropping signal;
Wherein this adjustable divisor frequency eliminating circuit detects the total loop delay of this input periodic signal in this delay locked loop circuit, to produce a best divisor according to this, comes respectively this input periodic signal and this feedback cycle signal to be carried out frequency elimination.
2. delay locked loop circuit as claimed in claim 1 is characterized in that, this adjustable divisor frequency eliminating circuit comprises:
One timer is used for timing to chase after the phase stage to point out a detection-phase,, and a phase-locked stage;
Wherein this delay locked loop circuit discharges a pulse signal of this input periodic signal in this detection-phase;
One best divisor testing circuit, be used in this detection-phase detect this feedback cycle signal to time of should pulse signal producing to produce this best divisor and to export one and specify divisor; And
One frequency eliminator is used for according to this appointment divisor, respectively this input periodic signal and this feedback cycle signal frequency elimination is imported periodic signal and this frequency elimination feedback cycle signal to produce this frequency elimination.
3. delay locked loop circuit as claimed in claim 2, it is characterized in that, chase after phase during the stage in this, this appointment divisor of this best divisor testing circuit output is one so that this frequency eliminator does not chase after mutually speed to this input periodic signal and this feedback cycle signal frequency elimination to quicken this delay locked loop circuit.
4. delay locked loop circuit as claimed in claim 3, it is characterized in that, when this phase-locked stage, this appointments divisor of this best divisor testing circuit output is for being adjusted to this best divisor gradually so that this delay locked loop circuit is stablized from one in the phase-locked stage.
5. delay locked loop circuit as claimed in claim 1 is characterized in that, when the phase-lead of this frequency elimination input periodic signal during in this frequency elimination feedback cycle signal, this phase/frequency detector produces this rising signals; When the phase lag of this frequency elimination input periodic signal during in this frequency elimination feedback cycle signal, this phase/frequency detector produces this dropping signal.
6. delay locked loop circuit as claimed in claim 5 is characterized in that, when this phase/frequency detector produced this rising signals, this charge pump promoted this control voltage; When this phase/frequency detector produced this dropping signal, this charge pump reduced this control voltage.
7. delay locked loop circuit as claimed in claim 6 is characterized in that, when this control voltage rose, this voltage controlled delay line circuit descended to the delay of this input periodic signal; When this control voltage descended, this voltage controlled delay line circuit rose to the delay of this input periodic signal.
8. the method for phase velocity with the performance that promotes this delay locked loop circuit that chase after of dynamically adjusting a delay locked loop circuit is characterized in that, comprises:
Detecting the total loop of an input periodic signal in this delay locked loop circuit postpones;
Postpone according to this total loop, set a best divisor; And
In the phase-locked stage of this delay locked loop circuit, this an input periodic signal and a feedback cycle signal that corresponds to this input periodic signal are carried out frequency elimination with this best divisor.
9. method as claimed in claim 8 is characterized in that, also comprises:
In this delay locked loop circuit chase after phase in the stage, this input periodic signal and this feedback cycle signal frequency elimination are not chased after phase velocity with increase.
10. method as claimed in claim 9 is characterized in that, in the phase-locked stage of this delay locked loop circuit, with this best divisor this input periodic signal is carried out frequency elimination with this feedback cycle signal that corresponds to this input periodic signal and comprises:
With divisor is that a mode that is adjusted to this best divisor gradually comes this input periodic signal and this feedback cycle signal are carried out frequency elimination.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105273168A CN102035542B (en) | 2010-10-19 | 2010-10-19 | Delay-locked-loop circuit with dynamic accelerating phase-hunting function and method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105273168A CN102035542B (en) | 2010-10-19 | 2010-10-19 | Delay-locked-loop circuit with dynamic accelerating phase-hunting function and method thereof |
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|---|---|
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| CN102035542B CN102035542B (en) | 2012-08-01 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196924A (en) * | 2000-01-17 | 2001-07-19 | Nec Corp | Digital dll circuit and its method |
| CN1385967A (en) * | 2001-05-16 | 2002-12-18 | 矽统科技股份有限公司 | Quickly-locked double-track digital delay phase-locking circuit |
| CN1983815A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Time-delay locking loop |
| US20090295442A1 (en) * | 2008-05-28 | 2009-12-03 | Micron Technology, Inc. | Apparatus and method for multi-phase clock generation |
-
2010
- 2010-10-19 CN CN2010105273168A patent/CN102035542B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001196924A (en) * | 2000-01-17 | 2001-07-19 | Nec Corp | Digital dll circuit and its method |
| CN1385967A (en) * | 2001-05-16 | 2002-12-18 | 矽统科技股份有限公司 | Quickly-locked double-track digital delay phase-locking circuit |
| CN1983815A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Time-delay locking loop |
| US20090295442A1 (en) * | 2008-05-28 | 2009-12-03 | Micron Technology, Inc. | Apparatus and method for multi-phase clock generation |
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| CN102035542B (en) | 2012-08-01 |
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