JP3302538B2 - Start code detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decompression method and apparatus system that functions to decode and / or decompress a plurality of different encoded input signals. The embodiments described below have been selected as illustrative and relate to encoding a plurality of encoded video standards. In particular, this embodiment relates to the decoding of one of the known standards known as JPEG, MPEG and H.261.

[0002] The serial pipeline processing scheme of the present invention employs a plurality of adaptive decompression systems that position unique and special interface tokens in the form of control and data tokens as reconfigurable pipeline processors. It consists of one 2-wire bus used to implement the circuit and the like.

[0003]

2. Description of the Related Art One of the prior arts is disclosed in U.S. Pat.
There is one described in US Pat. No. 6,724. The apparatus comprises a plurality of calculation modules, in a preferred embodiment a total of four calculation modules are connected in parallel. Each calculation module is composed of a processing unit, a dual port memory, a scratch pad memory, and an arbitration mechanism. A first bus connects these computing modules and the host processor. The apparatus has a shared memory connected to the host processor and the computing module via a second bus.

US Pat. No. 4,785,349 discloses a complete format for transmission recorded on a compact disk medium and decoded at conventional video frame rates. During compression, regions of the frame are individually analyzed to select the optimal fill coding method specific to each region. Estimate the region decoding time and optimize the compression threshold. Area description codes indicating the size and position of the area are grouped in a first segment of the data stream.
The area fill codes indicating the pixel amplitude of the area are grouped by the type of fill code and placed in other segments of the data stream. Each data stream segment has a variable length encoded according to its respective statistical distribution and is formatted for data frame formation. The number of bytes in the frame is reduced by the addition of ancillary data as determined by the inverse frame sequence analysis, providing an average number selected to minimize pauses during playback of the compact disc. This avoids the unpredictable seek mode waiting time characteristics of the compact disc. The decoder includes a variable length decoder responsive to codestream statistical information for separately variable length coding each segment of the data stream. The area position data is obtained from the area description data, and is supplied together with the area fill code to a plurality of area specifying decoders selected by detecting the type (eg, relative value, absolute value, binomial, and DPCM) of the fill code. . The decoded area pixels are stored in a bitmap format for later display.

US Pat. No. 4,922,341 discloses a method for reducing image data for a digital TV signal using a scene model. Here, the sequentially supplied image signals are encoded, and the time t-1
The previous frame from the scene which has already been encoded in the above exists in the image storage unit as a reference, and the information of the frame from frame to frame consists of an amplification coefficient, a movement coefficient, and an adaptively obtained quad (four) tree division structure. . When the system is initialized, a uniform, predetermined tone value or a halftone representation image as a specified luminance value is stored in the image storage unit of the coder on the transmitter side and the image storage unit of the decoder on the receiver side. Writing is similarly performed for all pixels. Both the image storage of the coder and the image storage of the decoder are fed back to each other, so that the contents of the image storage in the coder and the decoder are read out in blocks of variable size, and the coefficients are greater than or less than one luminance value. It is amplified and operates so that it can be written to another address of this image storage unit. Thereby, blocks of variable size are organized according to a known quadtree structure.

US Pat. No. 5,122,875 discloses an apparatus for encoding / decoding an HDTV signal. The apparatus comprises a high-quality video source signal for providing a hierarchically structured coded word CW representing compressed video data and a corresponding coded word T defining the type of data represented by the coded word CW. And a compression circuit responsive to the A priority selection circuit responsive to the coded words CW and T decomposes the coded word CW into a high priority and a low priority coded word sequence, so that the high and low priority coded word sequences are respectively used for image reproduction. On the other hand, it will correspond to compressed video data of relatively high and low importance. Transfer processors responsive to the high priority and low priority coded word strings form high priority and low priority transfer blocks of high priority and low priority coded words, respectively. Each transfer block includes a header, a coded word CW, and an error detection check bit. Each transfer block feeds a forward error check circuit which supplies additional error check data. The high-priority and low-priority data are then provided to the modem to quadrature amplitude modulate the corresponding transmission carrier.

In US Pat. No. 5,146,325, odd and even field video signals are sequentially and independently compressed in an intra-frame compression mode and an inter-frame compression mode, and then interleaved for transmission. A video decoding system for decoding compressed image data is disclosed.
Odd and even fields are decoded independently. During periods when there is no valid decoded odd / even field data, the even / odd field data is substituted for the unavailable odd / even field data. Decoding the data in the even / odd fields independently and substituting the data in the opposite field for the unavailable data can be effectively used to reduce the image display waiting time at system startup and during channel changes. obtain.

[0008] US Patent No. 5,168,356 discloses a video signal encoding system that divides encoded video data into transfer blocks for signal transmission. Its transport block format improves signal recovery at the receiver, thanks to the provision of header data that allows the receiver to determine the point of re-entry into the data stream when transmitted data is lost or corrupted. The re-entry point is maximized by providing a secondary transport header inserted in the encoded video data in the corresponding transport block.

US Pat. No. 5,168,375 processes a field of image data samples to provide one or more of the decimation, interpolation and shaping functions. A method is disclosed. This is realized by an array conversion processor or the like used in the JPEG compression system. The block of data samples is transformed by a discrete even cosine transform (DECT) in both the decimation and interpolation processes,
Thereafter, the number of frequency terms is changed. In the case of decimation, the number of frequency terms is reduced, after which an inverse transform is performed to produce a reduced size matrix of sample points representing the original data block. In the case of the interpolation process, zero additional frequency components are inserted into the frequency component array, and the subsequent inverse transformation produces a series of enlarged data samples without increasing the spectral bandwidth. In the case of a shaping process implemented by convolution or filtering with a multiplication of the transform of the data and the filter kernel in the frequency domain, an inverse transform is provided which produces a series of blocks of processed data samples. The spatial symbol of the kernel is modified by reducing the number of components for the linear phase filter and zero inserted to equal the number of samples in the data block. This is followed by the formation of a discrete odd cosine transform (DOCT) of the zero-inserted kernel matrix.

US Pat. No. 5,175,617 discloses a system and method for transmitting log map video images over a telephone line band limited analog channel. The pixel configuration in the log map image is adapted to match the geometric arrangement of the human eye sensor where the pixels are more concentrated in the center. The transmitter divides the frequency band into channels and assigns one or two pixels to each channel. For example, a 3KHz voice quality telephone line is divided into 768 channels, each with an interval of 3.9Hz. Since each channel consists of two carriers in quadrature, each channel can carry two pixels. Some channels are reserved for special calibration signals that allow the receiver to detect both the phase and magnitude of the received signal. If the sensor and pixel are directly connected to a group of oscillators and the receiver can continuously receive each channel, the receiver does not need to synchronize with the transmitter. F
The FT algorithm performs a fast discrete approximation for the case of continuous operation in which the receiver synchronizes with the first frame and then obtains subsequent frames every frame period. Since the frame period is relatively low compared to the sampling period, it is unlikely that the receiver will lose frame synchronization once the first frame is detected. In a pilot video call,
Four frames are transmitted per second, and orthogonal coding is performed on 1440 pixel log map images, and a speed of 40,000 per second is obtained.
An effective data transfer rate of 0 bits or more was obtained.

US Pat. No. 5,185,819 discloses an odd and even field video signal in which odd and even field video signals are sequentially and independently compressed in an intra-frame compression mode and an inter-frame compression mode. Are disclosed. The odd and even fields of the independently compressed data are interleaved for transmission such that the compressed data of the even fields in the frame occurs halfway between successive fields of the compressed odd fields in the frame. . For the receiver, the interleaved sequence of fields doubles the number of entry points into the signal for encoding without increasing the amount of transmitted data.

US Pat. No. 5,212,742 discloses an apparatus and method for processing video data for compression / decoding in real time. The apparatus comprises a plurality of calculation modules, in a preferred embodiment a total of four calculation modules are connected in parallel. Each calculation module is composed of a processing unit, a dual port memory, a scratch pad memory, and an arbitration mechanism. A first bus connects these computing modules and the host processor. Finally, the device has a shared memory connected to the host processor and the computing module via a second bus. In this method, each processing unit performs partial allocation of an image for processing.

US Pat. No. 5,231,484 discloses a suitable use of the proposed ISO / IEC MPEG standard. This includes three components or subsystems that work together. The three components or subsystems pre-process the incoming digital video sequence in a variable adaptive manner to provide the optimal visual quality taking into account the number of bits allocated to the image, , And the transform coefficients are adaptively quantized to different regions of the image in video order.

US Pat. No. 5,267,334 discloses a method for removing frame redundancy of a moving image sequence in a computer system. The method comprises the steps of detecting a first scene change in a video sequence and generating a first key frame containing complete scene information for the first image. In the preferred embodiment, this first keyframe is known as a "forward" keyframe or intraframe and is typically present in CCITT compliant compressed video data. The process includes the step of generating at least one intermediate compressed frame, wherein the at least one intermediate compressed frame is a second temporally compressed image of the at least one image subsequent to the first image in the video sequence. It contains difference information from one image. This at least one image is known as an interframe. Finally, there is a step of detecting a second scene change in the moving image sequence and a step of generating a second key frame including complete scene information for an image displayed immediately before the second scene change. This second keyframe is known as a "backward" keyframe. The first key frame and at least one intermediate compressed frame are connected for forward reproduction, and the second key frame and the intermediate compressed frame are connected for reverse reproduction. When an image is played forward, the intra-frame may be used to generate complete scene information. When this scene is played back, a backward keyframe is used to play back the complete scene information.

US Pat. No. 5,276,513 discloses that a first circuit device comprising a predetermined number of known image / pyramid stages is replaced by a second circuit device comprising the same number of novel moving image / vector stages. It is disclosed with the device. These devices are cost-effective hierarchical video analysis (H
MA) in real time with minimal system processing delay and / or
Or with minimal system processing delay and / or with minimal hardware structure. In particular, the first and second circuit arrangements are responsive to relatively high resolution image data from a continuous input sequence of continuous predetermined pixel density image data frames occurring at a relatively high frame rate (eg, 30 frames per second). Obtains a continuous output sequence of continuous predetermined pixel density vector data occurring at the same frame rate after some processing system delay. Each vector data frame indicates image motion that occurs between each pair of consecutive image frames.

US Pat. No. 5,283,646 teaches a real-time video encoding system to precisely encode a picture once while accurately transmitting the desired number of bits per frame, eg, via a communication channel. A method and apparatus for updating a quantization step size used to quantize coefficients representing a transmitted image is disclosed.
This data is divided into sectors having a plurality of blocks. This block is coded using, for example, DCT coding, and generates a coefficient sequence for each block. This coefficient is quantized, and the number of bits required to describe the data varies considerably depending on the quantization step. At the end of transmission of each sector of data, for a selected number of sectors associated with this particular group of data, the actual accumulated number of bits used is compared to the desired accumulated number of bits used. . The system re-adjusts the quantization step size, for example, to obtain the final desired number of data bits for the sectors representing the image. Various methods have been disclosed for renewing the quantization step size to determine the desired bit allocation.

Wescon Technical Pa
pers) No. 2, October / November 1984, Yong M.
A paper by Chong, Yong M, “Data Flow Architecture for Digital Image Processing” (A Data-Flow Archi
(Tecture for Digital Image Processing) discloses a real-time signal processing system specifically designed for image processing. Specifically, a data flow architecture based on a fixed one word long token having a fixed length address field is disclosed. The token is composed of a data field, a control field, and a tag. The tag field of the token is further divided into a processor address field and an identifier field. The processor address feed is used to correctly send the token to the data processor, and the identifier field is used to label the data to inform the data processor what to do. In this way, the identifier field acts as an indication to the data processor. The system sends each token to a specific data flow processor using a module number (MN). If this MN matches the special stage MN, an appropriate operation is performed on the data. If not, the token is sent to the output data bus.

An IEEE J solid circuit (Solid-St)
ate Circuits), Vol. 23, no.
1, February 1988, Kimori et al., "Elastic Pipeline Mechanism with Self-Adjusting Circuit" (An
Elastic Pipeline Mechani
sm by Self-Timed Circuit
In s), an elastic pipeline with a self-regulating circuit is disclosed. An asynchronous pipeline has multiple pipeline stages. Each pipeline stage is
It is provided following a combinational logic circuit that performs a logical operation unique to the pipeline stage. It is composed of input data latch groups. A trigger signal generated from a data transfer control circuit associated with the pipeline stage is simultaneously supplied to the data latch. The data transfer control circuits are connected to each other to form a chain, and control the data transfer between the subsequent pipelines to the handshake mode via the transmission signal line and the acknowledgment signal line. A normal decoder is provided at each stage to select an operation to be performed on the operand of the current pipeline stage. Furthermore, a decoder can be arranged at the preceding stage in order to code a complicated decoding process in advance and to reduce a problem of one path which is important for a logic circuit. Interactions between sub-modules are determined based on completely localized decisions, and each sub-module has its own data buffering and self-adjusting data.
Since data transfer can occur simultaneously, the flexibility of the pipeline eliminates any centralized control. Finally, to increase pipeline flexibility, empty pipeline stages are provided between occupied pipeline stages,
Reliable data transfer between each stage is ensured.

US Pat. No. 5,278,646 allows the number of coefficients contained in each sub-block to be selected,
Disclosed is an improved decoding technique in which a code indicating the number of coefficients in each layer has been inserted into the bitstream at the beginning of each encoded video sequence. According to this technique, by forming a sub-block for each scale along a continuous scan from a selected number of coefficients,
The original run of zero coefficients in the highest resolution layer can be unchanged. These subblocks are decoded in standard form by applying an inverse discrete cosine transform to the square subblocks obtained by appropriate zero padding or by discarding extra coefficients from each scale. . This technique further improves decoding efficiency by providing a distinct end-of-block signal to the separation block and, in most cases, eliminating the need to decode the distinct end-of-block signal.

US Pat. No. 4,903,018 discloses a method for compressing / decompressing structurally related multiple data sequences and a data processing system. An analysis is specific to a data set whose structure has been analyzed to exhibit properties common to a predetermined number of consecutive data elements in a data sequence. Instead of a data element, a code that is decoded again during the extension is used. Common properties are determined by analyzing data elements having the same order in the number of data sequences. During the expansion, the data elements obtained by decoding the code are ranked in the data series based on the order of these data series based on the order of these data elements. A data processing system for performing this method comprises a storage matrix 26 and an index store 28 having the line address of the storage matrix 26 in the associated line sequence.

US Pat. No. 4,334,246 discloses a circuit and method for compressing video following pre-compression for transmission and storage. Here, the original video generated by the raster input scanner is operated by a two-line one-shot predictor, encoded using run-length encoding into a 4, 8, or 12-bit codeword, and a 1-bit data word. Packed in.
Then, the decompressor combines the 16-bit data words, unpacks the data, separates each code word, converts the code words into a number of 4-bit nibbles, all of which are zero, and forms one or more of the decoded data. To terminate the nibble with bit 1 of the current line and examine the actual video of the line currently being scanned and the previous video bits of the current line to generate a depredictor bit to produce the final actual video The decoded data is compared with the predictor bit.

US Pat. No. 5,060,242 DPCM encodes a signal to produce a tightly packed variable length codeword without any data loss and to increase transmission efficiency without gaps. An image signal processing apparatus for performing Huffman and run-length encoding on a signal is disclosed. The robust packed word processing device has a barrel shifter, the shift modulus of which is controlled by the accumulator receive codeword length information. The OR gate is connected to the shifter, and the register is connected to the gate. An apparatus for processing this strongly packed and decorrelated digital signal comprises a barrel shifter for unpacking, an accumulator, a Huffman decoder, a run length decoder, and a coder with inverse DCPM.

US Pat. No. 5,168,375 describes one or more of the decimation, interpolation, and sharpening functions achieved using an array conversion processor such as that employed in the JPEG compression system. Discloses a method of processing fields of an image data sample to provide Blocks of data samples are transformed by a discrete even cosine transform (DECT) in both the decimation and interpolation processes. Thereafter, the number of frequency terms is changed. In the case of decimation, the number of frequency terms is reduced and then inversely transformed to produce reduced size sample points representing the original data block. In the case of interpolation, additional frequency components with zero values are inserted into the array of frequency components. Subsequent inverse transforms produce an expanded data sampling set without increasing the spectrum bandwidth.
In the case of convolution involving data transformation and multiplication with a filter kernel in the frequency domain, or in the case of sharpening realized by a filtering operation, it involves an inverse transformation process resulting in a block set of processed data samples. The blocks are duplicated, saving designated samples and discarding extra samples from the overlap. The spatial representation of the kernel for a linear phase filter is modified by reducing the number of components. Zeros are padded to equalize the number of samples in the data block. Thereafter, a discrete odd cosine transform of the embedded kernel matrix is performed.

US Pat. No. 5,231,486 discloses a high resolution video system for processing a bit stream containing high level, low level priority variable length encoded data words. The code data is separated into a high priority data pack and a low priority data pack by respective data packing units. Code data is continuously supplied to both packing units. The high priority length data and the low priority length data representing the high priority component length and the low priority component length of the code data are supplied to the high priority data packer and the low priority data packer, respectively. When the high priority data is packed for output via the first output path, the low priority data is zeroed. When the low priority data is packed for output via the second output path, the high priority data is zeroed.

US Pat. No. 5,287,178 discloses a video signal encoding system including a signal processing unit for dividing encoded video data into transport blocks having a header part and a data pack part. The system also includes a reset control circuit that releases the reset of system components after a global reset in the described non-concurrent phase sequence to enable signal processing to begin the described sequence. The phase reset release sequence starts when it is detected that valid data is being transmitted on the data line.

No. 5,124,790 (Nakayam
a) The specification discloses an inverse quantizer for use with an image memory. The inverse quantizer performs differential prediction coding (DPC
M) Used in normal usage to decode coded data.

No. 5,136,371 (Savatie
r et al.) The specification relates to an inverse quantizer having an adjustable quantization level that is determined by the full state of the buffer and is variable. A feature of this prior art is that a maximum adjustable data rate can be achieved. Buffer overflow or underflow can be avoided by adapting the quantization step size of the quantizer 152 and the inverse quantizer 156 using the quantization level recalculated after each block is encoded. The quantization level is calculated as a function of the amount of data already encoded for the frame for the total buffer size. In this way, the quantization levels are preferably recalculated by the decoder and are not transmitted.

No. 5,142,380 (Sakagam
i et al.) discloses an image compression apparatus for a still image as captured by an electronic still camera using a solid-state imaging device. Here, the quantizer used is connected to storage means for storing the threshold value of the quantization matrix for the luminance signal Y and ROM 15 for storing the threshold value of the quantization matrix for the chrominance signals I and Q.

No. 5,193,002 (Guichar)
d et al.) The specification is based on CCITT standard H. 261, an apparatus for encoding / decoding an image signal in real time is disclosed. The digital signal processor performs direct quantization and inverse quantization.

No. 5,241,383 (Chen et.
al.) The specification discloses a pseudo-constant bit-rate video encoding device implemented by adjusting the quantization parameter. The quantization parameters used in the quantizer 32 are adjusted periodically to increase or decrease the amount of code bits generated by the encoding circuit. The amount of change in the quantization parameter for encoding the next picture group is measured between the actual number of code bits generated by the encoding circuit for the previous picture group in the estimated number of code bits of the previous picture group. Determined by the deviations made. The number of code bits generated by the encoding circuit is controlled by controlling the quantization step size. In general, a small quantization step size results in a large number of code bits, and a large quantization step size results in a small number of code bits.

No. 5,113,255 (N
agata et al.), U.S. Patent No. 5,126,842 (Andrews et al.), U.S. Patent No. 5,253,058 (Gharavi), U.S. Patent No. 5,260,782. (Hui), US Pat. No. 5,212,742 (No.
rmile et al.) are cited for background and general technical description.

[0032]

SUMMARY OF THE INVENTION The present invention is directed to a pipeline system having an input, an output, and a plurality of processing stages between the input and the output, wherein the plurality of processing stages are tokenized along the pipeline. The control token and the data token are interconnected by a two-wire interface that transmits all the processing stages in the pipeline and interact with the selected processing stages in the pipeline. Embodiments relate to an improved pipeline system, characterized in that the processing stages of the pipeline are provided with increased flexibility in construction and processing. According to the invention, the processing stage is configured to respond to recognition of at least one token. One processing stage is a start code detector that receives input and generates / converts a token.

The token of the present invention includes a picture start code token indicating that a picture starts after a next data token, a picture end token indicating the end of an individual picture, and a flash for clearing a buffer and resetting a system. Token, a coding standard token that adjusts the system to perform processing according to a selected one of a plurality of picture compression / decompression standards. Further, the invention comprises a Huffman decoder, an index / data (ITOD) stage, an arithmetic logic unit (ALU), and data buffer means immediately following the system, for video pictures of varying data size. The present invention relates to a pipeline system for decoding video data, wherein a time interval is controllable. According to the invention, the processing stage comprises means for receiving an input data stream and recognizing a particular bit stream pattern, the processing stage facilitating random access and error recovery. Further, the present invention comprises means for achieving a clear end to picture data decoding, indicating the end of a picture, and performing a picture stop after operation to clear the pipeline. The improved pipeline system comprises a fixed size and fixed width buffer and means for padding the buffer to pass any number of bits through the buffer. The invention further has a data stream comprising a run length code, and is activated by the data stream from the token to extend the run level code to one run of zero data followed by one level. It has an inverse modeler, and each token is represented by a specified number of values. Further, the present invention comprises an inverse modeler stage, an inverse discrete cosine transform stage, and a processing stage located between the inverse modeler stage and the inverse discrete cosine transform stage and responsive to a token table for data processing.

Further, the present invention relates to an improved pipeline system, comprising: 261, JPEG or MPE
Huffman decoding means for decoding a data word coded based on any of the Huffman coding conditions of the G standard, wherein the data word has an identifier for identifying a Huffman code standard in which the data word is coded based on the Huffman decoding means. Means for receiving a Huffman coded data word; means for reading an identifier to determine which standard governed the Huffman coding of the received data word; and optionally, a Huffman coded data word. To H. In response to reading an H.261 or MPEG Huffman coded identifier, the Huffman coded data word is operatively connected to the Huffman coded data word receiving means for receiving an exponent from the exponent generation means, Means for generating an associated index, and a JPE to convey JPEG Huffman table information
Means for operating a look-up table including a Huffman code table having a format used in accordance with the G standard and outputting a decoded data word corresponding to the received exponent.

[0035]

SUMMARY OF THE INVENTION Briefly and generally, a book
The invention resides between an input, an output, and the input and the output.
Multiple stages of processing, along the pipeline
Two-wire interface to transmit the
Multiple interconnected processing stages and universal
Control tokens and / or data in the form of adaptation units
Data tokens and all processing steps in the pipeline.
In the pipeline for interacting with and controlling
A control token that interacts with the selected processing stage; and
Data machine between data token and / or processing stage
Provides the ability and / or a combination control data function, which
With the processing stages in the pipeline, the configuration and
Provides increased flexibility in processing.

Each processing stage in the pipeline is the first
Next, both secondary storage means may be provided. The processing stage is reconfigured upon recognition of the selected token. The tokens in the pipeline are dynamically adaptive and are located depending on the processing stage that performs the function or independent of the processing stage that performs the function.

In the pipeline of the present invention, tokens may be changed by interfacing with stages. Tokens may interact with all stages of the pipeline, or may interact with less than all specific stages.
Tokens in the pipeline may interact with adjacent stages or with non-adjacent stages. The token reconfigures the processing stage. Such a token may be located dependent on one function, or independent of another.

The token may further include an extension bit that indicates that there are additional words in the token and identifies the last word in the token. Address field of the token may be a variable length, typically being hard fumarate <br/> down coding.

The token is generated by a processing stage. The pipeline token may include data to be transferred to the processing stage, and the token may have no data. Certain tokens are identified as data tokens and provide data to the processing stages of the pipeline. Other tokens are identified as control tokens and coordinate processing stages. This adjustment involves a reconfiguration of the processing stage. In addition, other tokens both provide and coordinate data to the processing stage. Either of the tokens identifies an encoding standard for the processing stage of the pipeline. Other tokens operate between processing stages independent of any coding standards. Tokens can also be changed continuously by processing stage.

The flexibility of the interaction of the tokens in cooperation with the processing stages facilitates a large distribution of functions of the processing stages to the internal structure, and the flexibility of the tokens facilitates system expansion and / or modification. In this regard, tokens may also facilitate multiple functions within a processing stage. The token may be based on hardware or software. The token makes data and control available to the processing stage at the same time.

According to the present invention, a plurality of encoded bits as a serial bit stream of digital bits, each having a pair of control codes and corresponding data conveyed in a single bit stream. In a pipeline system in which a plurality of processing stages are interconnected by a two-wire interface for handling a stream, a control token and a data token are generated in response to a single serial bit stream, and start code detection to be provided to the two-wire interface Means and token decoding means provided at a predetermined processing stage for recognizing a token as a control token specific to the stage and passing an unrecognized control token along the pipeline; and for handling the identified data token. Responds to the recognized control token Characterized by comprising a reconstruction decoding parser processing means for reconstructing the stages.

According to the present invention, one stage is a start code detector configured to receive input and generate / convert a token, wherein the start code detector is responsive to data and generates a token; A start code is searched and detected, a token is generated in response to the result, a duplicate start token can be detected, the first start code is ignored, and the second start code is used for generating the start code token. Used for

In the search mode, the start code detector stage searches the input data to find the selected start code. The detector searches for interruptions in the input data stream, and the search is performed on data from external data sources. The start code detector stage generates a start code token, a picture start token, a slice start token, a picture end token, a sequence start token, a sequence end token, and / or a group start token. The start code detector stage performs a padding function that embeds bits in the last word of the token.

The start code detector treats a plurality of separately coded bit streams arranged as a serial bit stream of digital bits, and carries a separately coded start code pair and the serial bit stream. A start code detector subsystem having first, second, and third stages connected in series, each of the registers storing a different number of bits from a bit stream; The register stores a value, first decoding means for identifying a start code associated with the second register and the value contained in the first register, and shifts the value to a predetermined end of the third register. Circuit means and a second array arranged to receive data from the third register in parallel. It includes a decode unit.

A memory is provided for outputting one or a plurality of control tokens stored as a result of decoding the value associated with the start code in response to the second decoding means. Multiple tags shift register to handle the tag indicating the effectiveness of the register or these data are provided. The system further comprises means for accessing the input data stream of the microprocessor interface or al, means for formatting / organizing data stream.

According to the invention, the start code detector identifies a variable width start code associated with a differently decoded bit stream. The detector generates a plurality of data tokens from the input data stream. The system is a pipeline system and the start code detector is located as the first stage of the pipeline system.

The invention comprises a plurality of processing stages and a universal adaptation unit in the form of an interaction interface token for control and / or data functions between the processing stages, wherein the token is the next data start of the picture. Provide a system that is a picture start code token that indicates what follows in the token.

The token is a picture end token indicating the end of each picture.

[0049] token clears the buffer, a flash token to reset the system brought in traveling through the system downstream from the input to the output. The flush token variably resets the stage as it proceeds down the pipeline. The token is a coding standard token that coordinates the system to perform processing according to a selected one of a number of picture compression / decompression standards.

The coding standard token indicates JPEG as a picture standard and / or other suitable standards. At least some processing stages are reconfigured in response to the coding standard token.

One of the processing stages of the system is a Huffman decoder parser, which, in response to the coding standard token, resets the parser to an address location corresponding to the location of the program that handles the picture standard specified by the coding standard token. You. The reset address is selectable by a coding standard control token corresponding to the memory location used to test the Huffman decoder parser.

The Huffman decoder has a decoding stage,
An index / data stage, wherein the parser stage sends instructions to the index / data stage to select the tables required for the specially identified coding standard, indicating whether the incoming data has been inverted. .

The token described above may be an interacting metamorphic interface token.

The present invention comprises a Huffman decoder, an index / data unit, an arithmetic logic unit, and data buffer means immediately following the system, wherein the time interval for video pictures of varying data size is controllable. Provide a data decoding system.

The present invention provides a method for interconnecting processing stages.
It has a line interface, which provides a spatial decoder that enables serial processing for data and parallel processing for control.

As described above, the system of the present invention comprises a ROM having a separate program stored for each of a plurality of picture standards, the programs being selectable by tokens and processing for a plurality of picture standards. Facilitates the implementation of

The spatial decoder system of the present invention comprises a token formatter for formatting the token, so that a data token is created.

The system of the present invention comprises a decode stage and a parser stage that sends instructions to the index / data unit to select the required table for the particular coding standard identified, the parser stage being the incoming. Indicates whether the data to be inverted is inverted. The tables are arranged in a memory that allows multiple use of the appropriate tables.

The invention comprises an input data stream,
The present invention includes a processing stage for receiving an input data stream, the processing stage including means for recognizing a designated bit stream pattern, and provides a pipeline system that facilitates random access and error recovery.
According to the invention, the processing stage is a start code detector and the bit stream pattern comprises a start code. Therefore, the present invention comprises a search mode means for searching for different encoded data streams arranged as a single serial data stream for random access and enhanced error recovery.

The present invention comprises means for performing a picture after stop operation to indicate a clear end to picture data decoding, indicating a picture end, and clearing the pipeline. Provide a pipeline machine that generates a combination of a token and a flash token.

The pipeline machine of the present invention comprises a buffer of fixed size and fixed width, and means for padding the buffer to pass an arbitrary number of bits through the buffer, wherein the padding means comprises a start code detector. It is.

The padding is performed on the last word of the token, and the padding ensures word size uniformity. According to the invention, the reconstruction stage is provided as a spatial decoder, and the padding means adds enough to the picture data being processed by the spatial decoder that each decompressed picture has the same bit length at the output of the spatial decoder. Add a bit.

The present invention, in a system having a data stream containing a run length code, is activated by the data stream from the token, and the run level code is replaced by one level of zero data followed by one level.
A system is provided that includes an inverse modeler means that extends to one run, and each token is represented by a specified number of values.

The inverse modeler means blocks tokens that lack a predetermined number of values, and in the preferred embodiment the predetermined number is 64 coefficients.

An apparatus embodying the present invention includes an extension circuit that accepts a data token having a run length code and decodes the run length code. The padder circuit communicates with the extension circuit to determine whether or not the data token has a predetermined length. If the data token is shorter than the predetermined length, the data unit is written in the data token until the data token reaches the predetermined length. Add. The bypass circuit allows tokens other than data tokens to bypass the expansion circuit and padder circuit.

According to the present invention, in a method for processing data to efficiently fill a buffer, a first type of token having a first predetermined width and having at least one of the following formats: Provide: Format A-ExxxxxxxLLLLLLLLLLLL Format B-ERRRRRRLLLLLLLLLLLL Format C-E00000000LLLLLLLLLLLL where E = extended bit, F = specific format, R =
Run bit, L = length bit or non-data token, x = “don't care” bit.

Format A token is set to ELLLLLL
Divided into format 0a tokens in the form of LLLLLL,
The format B token is divided into a format 1 token and a format 0a data token in the form of FRRRRRRR00000 and the format C token is FL
Divide into format 0 tokens in the form LLLLLLLLLL and pack the format 0, format 0a, format 1 tokens into a buffer having a second predetermined width.

Further, the present invention is directed to an apparatus for providing a delay time to a group of compressed pictures corresponding to a video compression / decompression standard, wherein a data word including the compressed picture is counted by a counting circuit. A microprocessor communicates with the circuitry, receives start-up information in accordance with standards for video decompression, and communicates the start-up information to a counting circuit.

An inverse modeler circuit for accepting and delaying the data word communicates with a control circuit intermediate the counting circuit and the inverse modeler circuit, the control circuit compares the start information with the counted words of the data, and Signal the circuit. The control circuit queues signals corresponding to data words that meet the start criteria and controls the inverse modeler delay function.

The present invention relates to a process which is arranged between an inverse modeler stage and an inverse discrete cosine transform stage in a pipeline system having an inverse modeler stage and an inverse discrete cosine transform stage and responds to a token table for data processing. Features a stage.

The token of the present invention is a quantization table token for generating a quantization table from the processing stage.

The present invention relates to 261, JPEG or M
Means for decoding a data word coded based on a Huffman coding condition of any of the PEG standards, the data word including an identifier identifying the Huffman code standard on which the data word was coded based thereon; Further comprising means for receiving a Huffman coded data word, the receiving means comprising means for reading an identifier which determines which standard governed the Huffman coding of the received data word, optionally a Huffman coded data word. To H. Means for converting a data word to a JPEG Huffman coded data word in response to reading an identifier identifying the H.261 or MPEG Huffman coded, and operably connected to the Huffman coded data word receiving means. Means for generating an index associated with each JPEG Huffman coded data word receiving the index from the index generating means, and a Huffman code table having a format used in accordance with the JPEG standard to convey JPEG Huffman table information. Means for manipulating the look-up table containing the data and outputting a decoded data word corresponding to the received exponent.

Further, the present invention relates to H.264. 261, JPEG,
Alternatively, in the method for decoding a data word coded based on any of the Huffman coding conditions of the MPEG standard, the data word includes an identifier identifying the Huffman code standard coded based thereon. Receiving a coded data word, comprising the steps of: reading an identifier that determines which standard governed the Huffman coding of the received data word; 261 or each JPEG Huffman coded data word received, including converting the data word to a JPEG Huffman coded data word in response to reading an identifier that identifies the Huffman coded data word as MPEG Huffman coded. Generating an index associated with the index, receiving the index, and generating a data word decoded according to the received index.
And operating a look-up table including a Huffman code table having a format used in accordance with the JPEG standard to transmit the EG Huffman table information.

In the following description of the embodiments of the present invention, the following terms are frequently used, and a general description of the terms will be given below.

Terminology block: matrix of 8 rows and 8 columns of pixels, or 64D
CT coefficients (source, quantization or inverse quantization).

Chrominance (component): One of two color difference signals related to three primary colors as defined by a bit stream.
One matrix, block, or one pixel representing an individual. The codes used for the color difference signals are Cr and Cb.

Coding notation: A data element represented in coding form.

Coded video bitstream: A coded representation of a series of one or more images, as defined herein.

Coding order: The order in which images are transmitted and coded. This order does not necessarily have to be the same as the display order.

Component: One pixel from one of the three matrices (luminance and two chrominance) that make up a matrix, block, or image.

Compression: reducing the number of bits used to represent one item of data.

Decoder: An embodiment of the decoding process.

Decoding (processing): According to the definition in this specification,
A process of reading an input encoded bit stream and generating decoded image or audio samples.

Display order: The order in which the decoded images are displayed.
Generally, this is the same order in which the images were input to the encoder.

Coding (Processing): A process of reading an input image sequence or audio sample, which is not specified in this specification, and generating a valid coded bit stream defined in this specification.

Intra coding: coding of a macroblock or picture using only information from the macroblock or picture.

Luminance (component): One matrix, block, or one pixel representing the black and white of a signal, relating to the three primary colors as defined by the bit stream. The sign used for the luminance signal is Y.

Macroblocks: Four 8 × 8 blocks of luminance data and two of 16 × 16 parts of the luminance component of the image (for 4: 2: 0 chroma format), four (4: 2: 2) Chroma format) or 8 (4:
Corresponding 8.times.8 block of chrominance data for 4: 4 chroma format). A macroblock may also refer to pixel data, and may refer to an encoded version of a pixel value and other data elements defined in a macroblock header of the syntax defined herein. There is also. For a person skilled in the art, its use is also clear from the context.

Moving image compression: Improving the efficiency of predicting pixel values using moving image vectors. This prediction uses a motion vector to provide an offset to a past and / or future reference image that contains previously decoded pixel values used to create a prediction error signal. Video Vector: A two-dimensional vector used for video compensation that provides an offset from the current image coordinate position to the reference image coordinates.

Non-intra coding: coding of a macroblock or picture that also uses information from the macroblock or picture itself and macroblocks and pictures generated at different times.

Pixel: picture unit Picture: source, coded or reconstructed picture data The source or reconstructed image has an 8-bit number representing the luminance and two chrominance signals, respectively.
It consists of square matrices. In advanced video, an image is the same as a frame; in interlaced video, an image refers to a frame, or the first or last field of the frame, depending on the context.

Prediction: Predicting the currently decoded pixel value or data element using a predictor.

Reconfigurable processing stage (RPS): A stage for reconfiguring itself and performing various operations in response to a recognized token.

Slice: A series of macroblocks.

Token: A universal adaptation unit in the form of a package of interaction interface messengers for control and / or data functions.

Start Code (System and Video): A 32-bit code inserted into the unique encoded bit stream. These codes are used for several purposes, including identifying some of the structures in the encoding syntax.

Variable Length Coding (VLC): An inverse process for coding that assigns shorter code words to frequent events or assigns longer code words to less frequent events.

Video sequence: a series of one or more images.

[0099]

According to the present invention, there are provided a plurality of processing stages and a universal adaptation unit in the form of an interaction interface control token for performing control and data functions in the processing stages. A pipeline system is provided that has been given increased flexibility.

[0100]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a pipeline system according to the present invention will be described below with reference to the drawings.

As an overview of the most common functions used in the pipeline system used in the preferred embodiment of the present invention, FIG. 1 is a greatly simplified illustration of six cycles of a six stage pipeline. (As will be described in further detail below, the preferred embodiment of the pipeline includes some advantageous features not shown in FIG. 1.) Referring now to the drawings, wherein: Throughout the figures, the same reference numbers indicate the same or corresponding elements, and, more particularly, FIG. 1 is a six-cycle block diagram for implementing the present invention. Each row of the box represents one cycle, and each of the different stages is categorized as A to F, respectively.
Each hatched box indicates that the corresponding stage holds valid data, that is, data to be processed in one of the pipeline stages. After processing (which may include nothing but a simple transfer without manipulation of the data), the valid data is transferred from the pipeline as valid output data.

Note that an actual pipeline application may include more or less than six pipeline stages. As will be appreciated, the invention can be used with any number of pipeline stages. Further, the data may be processed in more than one stage, and different stages may have different processing times.

In addition to the clock and data signals (described below), the pipeline has two transfer control signals, a "VALID" (valid) signal and an "ACCE" signal.
PT "(permissible) signal. These signals are used to control data transfer in the pipeline. The VALID signal, shown as the upper line of the two lines connecting adjacent stages, is supplied in a forward or downstream direction from each pipeline stage to the nearest adjacent device. The device can be another pipeline stage, or some other system. For example, the last pipeline stage may supply its data to the next processing circuitry. The ACCEPT signal, shown as the lower line of the two lines connecting the adjacent stages, supplies the other device in the upstream direction to the previous device.

A data pipeline system of the type used to implement the present invention, as shown in the preferred embodiment, has one or more of the following characteristics:

1. A pipeline is "elastic", that is, the disturbance caused to other pipeline stages due to delays introduced in a particular pipeline stage is as small as possible. Successive pipeline stages can continue processing, thus implying a gap in the flow of data following the delayed stage. Similarly, the preceding pipeline stage can be continued as long as possible. In this case, gaps in the data stream are removed from the data stream as much as possible.

2. The control signals that arbitrate the pipeline are:
These signals are organized to propagate only to the nearest adjacent pipeline stage. In the case of a signal flowing in the same direction as the data flow, said stage is the one immediately following. In the case of a signal flowing in the opposite direction to the data flow, said stage is the immediately preceding stage.

3. The data in the pipeline is coded such that many different types of data are processed in the pipeline. This encoding accommodates data packets of variable size, and the size of the packets need not be known in advance.

4. The overhead associated with data type descriptions is as small as possible.

5. It is possible for each pipeline stage to recognize only the minimum number of data types required for the functions required of the pipeline stages.
However, the pipeline stage must be able to supply all these data types to successive stages, even if they do not recognize the data types. If this is possible, it allows communication between non-adjacent pipeline stages.

Although not shown in FIG. 1, there is a data line, and a data bus to be introduced or led out to each pipeline stage is formed regardless of whether it is a plurality of single lines or several parallel lines. I do. As described and illustrated in greater detail below, data is transferred into and out of the pipeline stages through data lines.
And between stages.

It should be noted that the first pipeline stage can receive data and control signals from any form of preceding device. The preceding device in this case means, for example, a receiving circuit, another pipeline, or the like of the digital image transmission system. On the other hand, the first pipeline stage can generate all or part of the data processed in the pipeline. In practice, as explained in more detail below,
A "stage" may include any processing circuitry, including a system that does nothing (just supplies data) or an entire system (eg, another pipeline or multiple systems or multiple pipelines), and , "Stages" can create, modify, and delete data as needed. If a pipeline stage contains valid data that is transferred down through the pipeline, the VALID signal indicating data validity need not be transferred further than the next immediately following pipeline stage. Thus, a two-wire interface is included between all pipeline stages that make up the system pair. That is, so-called other devices are included, and if data is transferred between such a device and the pipeline, the preceding device and the first stage, and the succeeding device and the last stage, A two-wire interface is included. Each of the signals, ie, AC
CEPT and VALID have values of HIGH and LOW. These values are abbreviated as "H" and "L", respectively. When implementing the present invention, the most common applications of pipelines are typically digital. When implemented as this kind of digital, for example, H
The IGH value is a logical "1", and the LOW value can be a logical "0". However, the system is not limited to being implemented as digital; when implemented as analog, a HIGH value may be an amount above a certain voltage, or other similar set threshold, and may be a LOW value. May be indicated by corresponding signals below (or above) the same or other thresholds. For digital applications, the invention can be implemented using any known technology, for example, CMOS, bipolar, etc.

It is not necessary to use separate storage channels and wires to provide storage for the VALID signal.
This is true in digital embodiments. An indication of the "validity" of the data is all that is required only to be stored with the data. By way of example only, in a digital television image represented by a digital value,
Certain values are not allowed, as specified in International Standard CCIR601. In this system, an 8-bit binary number is used to represent a sample of the image, and values of zero and 255 must not be used.

If this type of image needs to be processed in a pipeline incorporated in an embodiment of the present invention, one of these values (eg, zero) will It will be used to indicate that the data in the stage is not valid. Therefore, any non-zero data should be considered valid. In this example, no particular latch is identifiable and can be said to be storing the "validity" of the associated data. Nevertheless,
The validity of the data is stored with the data.

As shown in FIG. 1, VAL to each stage
The state of the ID signal is indicated as “H” or “L” on the upper right arrow. Therefore, the VALID signal from stage A to stage B is LOW, and the VALID signal from stage D to stage E
The signal is HIGH. The state of the ACCEPT signal to each stage is indicated as "H" or "L" on the lower left arrow. Thus, the ACCEPT signal from stage E to stage D is HIGH, while the ACCEPT signal from a device connected downstream of the pipeline to stage F is LOW.

Whenever the ACCEPT signal from an upstream adjacent stage to a downstream stage is HIGH, data is transferred from one stage to another during one cycle (described below). . The ACCEPT signal between the two stages is L
If OW, no data is transferred between these stages.

Referring again to FIG. 1, if one box is shaded, the corresponding pipeline stage is assumed to contain, for example, valid output data. Similarly, the VALID signal supplied from this stage to the next stage is HIGH. Stage B,
The pipeline when D and E contain valid data is shown in FIG. Stages A, C, and F do not contain valid data. At the start, the VALID signal to pipeline stage A is HIGH, meaning that the data on the transmission line to the pipeline is valid.

Similarly, at this point, the ACCEPT signal to pipeline stage F is LOW, so that regardless of whether it is valid,
No data is transferred from. Note that valid and invalid data is transferred between pipeline stages. Invalid data that stores invaluable data is overwritten, thereby removing invalid data from the pipeline. However, valid data is for processing or for example,
Valid data must not be overwritten because it must be stored for use in a downstream stage, such as a pipeline stage, a device or system connected to the pipeline that receives data from the pipeline.

In the pipeline shown in FIG. 1, stage E contains valid data D1, stage D contains valid data D2, stage B contains valid data D3, and is connected to the upstream pipeline. A device (not shown) contains the data D4 to be transferred to the pipeline and processed. In addition to the upstream devices, stages B, D, and E contain valid data, so the VALID signal from each of these stages or devices to the subsequent device is HIGH. However, VALI from stages A, C, and F
The D signal is LOW because these stages do not contain valid data.

Assume that a device connected downstream from the pipeline is not ready to accept data from the pipeline. The device has a corresponding ACC
This state is transmitted to stage F by setting the EPT signal to LOW. However, stage F itself does not contain valid data and can therefore accept data from preceding stage E. Therefore, the ACCEPT signal from stage F to stage E is set HIGH.

Similarly, stage E contains valid data, and stage F is ready to accept this data. Thus, stage E can accept new data as long as valid data D1 is first transferred to stage F. In other words, stage F cannot transfer data downstream, but all other stages can transfer downstream without overwriting or losing any valid data. Thus, at the end of cycle 1, the data can be "shifted" one step to the right. This state is shown in cycle 2.

In the example shown in the figure, the downstream devices are:
The ACCEPT signal to stage F is still LOW because it is not yet ready to accept new data in cycle two. Therefore, stage F cannot accept new data. The reason is that the valid data D1 is overwritten and lost. Therefore, since stage E also contains valid data D2, the AC from stage F to stage E, as in the case of the ACCEPT signal from stage E to stage D,
The CEPT signal goes LOW. However, all stages from A to D can accept new data (either these stages do not contain valid data or these data shift their valid data downstream) , And can accept new data), and these stages transmit this condition immediately before to the immediately preceding adjacent stage by setting the corresponding ACCEPT signal to HIGH.

FIG. 1 shows the state of the pipeline after the cycle 2 during the period in which the row is classified as the cycle 3. As an example, assume that a downstream device is not yet ready to accept new data from Stage F (the ACCPT signal to Stage F is LOW). Thus, stages E and F are still "blocked", but in cycle 3, stage D has received valid data D3 and the overwriting of invalid data previously at this stage is complete. ing. Since in stage 3 stage D cannot supply data D3, this stage cannot accept new data, and therefore the ACCEPT signal to stage C goes low.
Set to OW. However, stages AC are ready to accept new data, and transmit this by setting the corresponding ACCEPT signal to HIGH. Note that data D4 has been shifted from stage A to stage B.

It is now assumed that the downstream device is ready in cycle 4 to accept new data. This downstream device sends this to the pipeline by setting the FACCEPT signal to the stage HIGH. Although stages CF contain valid data, these stages can shift data downstream in this state and thus accept new data. Thus, each stage sets the corresponding ACCEPT signal outside HIGH, as each stage can step data one step downstream.

As long as the ACCEPT signal to the final pipeline stage (stage F in this example) is HIGH, the pipeline shown in FIG. 1 operates as a rigid pipeline, and steps data one step each cycle. Only shift. Therefore, data D1 included in stage F in cycle 4 is shifted from the pipeline to the next device in cycle 5,
And all other data is shifted downstream by one step.

Now, assume that the ACCEPT signal to stage F goes LOW in cycle 5. This means, again, that stages DF cannot accept new data, and that the ACCEPT signal from these stages to the immediately preceding adjacent stage is low.
W. Thus, data D2, D3, and D4 cannot be shifted downstream, but data D5 is. Thus, the corresponding state of the pipeline after cycle 5 is shown in FIG.

According to a preferred embodiment of the present invention, the ability of the pipeline to "fill up" empty processing stages is highly advantageous. This is because this capability frees the processing stages of the pipeline from each other. In other words, even when the pipeline stage is not ready to accept data, the entire pipeline does not have to stop or wait for a delay stage. Not only that, when one stage cannot accept valid data, it merely forms a temporal "wall" in the pipeline. Even in this state,
The downstream stage of the "wall" is capable of continuing to advance valid data to the pipeline connected circuit, and the stage to the left of the "wall" is still
Valid data can be accepted and transferred downstream. If some pipeline stages cannot temporarily accept new data, other stages can continue to operate normally. In particular, the pipeline continues to accept data into its first stage A unless stage A already contains valid data that cannot be advanced because the next stage is not ready to accept new data. It is possible. As shown in this example, even with one or more processing stages blocked, data can be transferred between pipelines and stages.

In the embodiment shown in FIG. 1, it is assumed that the various pipeline stages do not store the ACCEPT signal received from the immediately succeeding stage. Instead, when the ACCEPT signal to the downstream stage goes LOW, the LOW signal is propagated up the closest pipeline stage that does not contain valid data. For example, referring to FIG. 1, assume that the ACCEPT signal to stage F goes LOW in cycle one. In cycle 2, the LOW signal propagates back from stage F to stage D.

In cycle 3, if data D3 is latched in stage D, the ACCEPT signal propagates up the four stages to stage C in the direction going back. ACCE to stage F in cycle 4
If the PT signal goes high, it propagates against the flow to stage C. In other words, AC
Changes in the CEPT signal must propagate backward through four stages. However, in the embodiment shown in FIG. 1, if there is an intermediate stage that can accept new data, the ACCEPT signal need not propagate all the way back to the beginning of the pipeline.

In the embodiment shown in FIG. 1, each pipeline stage must be able to transfer data between stages without performing unintentional overwriting.
Still, it requires separate input and output data latches. In addition, the pipeline shown in FIG. 1 can be "compressed", but if the downstream pipeline stages are blocked, i.e., if they cannot supply the data they contain, the pipeline will be enabled. It does not "bloat" to provide stages that do not contain valid data between stages that contain data. Rather, the ability to compress relies on cycles corresponding to periods when no valid data is present in the first pipeline stage.

For example, in cycle 4, stage F
The ACCEPT signal to remains LOW, and
If pipeline stages A and 3 are filled with valid data, the pipeline is no longer compressible as long as valid data remains at stage A, and valid input data is lost. There is.
Nevertheless, the pipeline shown in FIG. 1 reduces the risk of data loss. The reason is that as long as there are pipeline stages that do not contain valid data, the pipeline is compressible.

Another embodiment of a pipeline is shown in FIGS. 2 and 3 that is capable of both compression and expansion in a logical manner and has circuitry to limit the propagation of the ACCEPT signal to the nearest preceding stage. . The circuitry for implementing this embodiment is described and illustrated in detail below, and FIGS. 2 and 3 serve to illustrate the operating principle of this embodiment.

For ease of comparison, the input data and ACCEPT to the pipeline embodiment shown in FIGS.
The signals are the same as in the pipeline embodiment shown in FIG. Thus, stages E, D, and B, respectively,
It has valid data D1, D2, and D3. The ACCEPT signal to the stage F is LOW, and the data D4
Are supplied to the start pipeline stage A. FIG.
FIG. 3 shows three lines connecting each adjacent paired stage of each neighboring pair of pipeline stages. The uppermost line that can be a bus is a data line. The middle line is the line through which the VALID signal is transferred, and the bottom line is the line through which the ACCEPT signal is transferred. Further, as before, the ACCEPT signal to stage F remains LOW except during cycle 4. Furthermore,
In cycle 4, additional data D5 is provided to the pipeline.

2 and 3, each pipeline stage is divided into two halves to illustrate that each stage in this embodiment of the pipeline includes a primary and a second data storage element. Represented as one block. 2 and 3, the primary data storage is shown as the right half of each stage. It should be understood, however, that this description is for illustrative purposes only and is not intended to be so limited.

As shown in FIGS. 2 and 3, A
As long as the CCEPT signal is HIGH, data is transferred from the primary storage element of that stage to the secondary storage element of the next stage during any given cycle. Therefore, ACCEPT to stage F
Signal is LOW, but ACC to all other stages
The EPT signal is HIGH, resulting in data D1,
D2 and D3 are shifted one stage forward in cycle 2, and data D4 is shifted to the first stage A.

Up to this point, the pipeline embodiment shown in FIGS. 2 and 3 operates in a manner similar to the pipeline embodiment shown in FIG. However, ACC to Stage F
Even if the EPT signal is LOW, the ACCEPT signal from stage F to stage E is HIGH. As explained below, due to the secondary storage element,
It is not necessary for the LOW ACCEPT signal to propagate beyond stage F and upstream. Further, by leaving the ACCEPT signal to Stage E HIGH, the Stage F signal signals that it is ready to accept new data. Stage F cannot transfer data D1 in its primary storage element downstream in cycle 3 (the ACCEPT signal to stage F is LOW), so stage E transfers data D2 to stage F to the secondary storage element. Since both the primary and secondary storage elements of stage F contain valid data that cannot be supplied in this state, the A from stage F to stage E
The CCEPT signal is set LOW. Thus, this indicates that the LOW ACCEPT signal propagates back only one stage relative to cycle 2, in which case the ACCEPT signal travels backwards through stage C in the embodiment shown in FIG. Must be propagated to Stages A-E can supply their data, so the ACCEPT signal from that stage to the immediately preceding stage is set HIGH. Therefore, data D3 and D4 are shifted right by one stage. As a result, in cycle 4, the data is:
Stage E and stage C are loaded into the primary data storage elements, respectively. Stage E now contains valid data D3 in its primary storage element, but its secondary storage element stores other data without the danger of overwriting any valid data. Can still be used to

Here, as in the previous case, the ACCEPT signal to stage F goes high in cycle 4
Assume IGH. This indicates that downstream devices to which the pipeline supplies data are ready to accept data from the pipeline. However, since the ACCEPT signal of stage F is set to LOW, it indicates to stage E that stage F is not ready to accept new data. The ACCEPT signal in each cycle period indicates what happens in the next cycle, ie, what data is supplied (AC
CEPT HIGH) or whether data must remain in place (ACCEPT LO
W) Please consider showing Thus, between cycle 4 and cycle 5, data D1 is provided from stage F to the next device, and data D2 is shifted from the secondary storage of stage F to the primary storage, but at stage E. Is not transferred to the stage F. ACCE of the next stage
Since the PT signal is HIGH, data D4 and D5 can be transferred to the next pipeline stage as usual.

By equipping the secondary storage elements by comparing the state of the pipeline in cycles 4 and 5, the pipeline embodiment shown in FIGS. 2 and 3 can be expanded; That is, it can be seen that the data storage element is released so that valid data can be advanced therein. For example, the data of these data blocks cannot be transferred until the ACCEPT signal to the stage F becomes HIGH.
In, the data blocks D1, D2 and D3 form a "solid wall". However, once this signal is HIGH
, The data D1 is shifted out of the pipeline,
Data D2 is shifted into the primary storage element of stage F, and if the next device cannot receive data D2 and the pipeline must also once "compress", the second stage of stage F The next storage element is free to accept new data. This is shown in cycle 6. During this cycle, data D3 is shifted into the secondary storage element of stage F, and data D4 is provided from stage D to stage E as usual.

FIGS. 4, 5, 6 and 7 generally show a preferred embodiment of the pipeline. This preferred embodiment implements the structure shown in FIGS. 2 and 3 using two-phase non-overlapping clocks with phases φ0 and φ1. Although a two-phase clock is preferred, it should be understood that various embodiments of the present invention can be driven with more than one phase clock.

As shown in FIGS. 4, 5, 6, and 7, each pipeline stage is illustrated as having two separate boxes representing primary and secondary storage elements. In addition, the VALID signal and data lines connect the various pipeline stages as before, but for ease of explanation, FIGS.
FIG. 7 shows only the ACCEPT signal. An ACCEP
The change of state during one clock phase of the T signal is:
The change from LOW to HICH is shown in FIGS. 4, 5, 6, and 7 using an upward arrow. Similarly, a change from HIGH to LOW is indicated by a down arrow. The transfer of data from one storage element to another storage element is indicated by a large open arrow. The VALID signal from the primary or secondary storage element at any given stage is assumed to be HIGH whenever the storage element contains valid data.

In FIGS. 4, 5, 6 and 7, each cycle is shown as comprising one full cycle of non-overlapping clock phases φ0 and φ1. As will be described in more detail below, data is transferred from the secondary storage elements (shown as left boxes in each stage) to the primary storage elements (shown as right boxes in each stage) during clock cycle φ1. Transferred to
On the other hand, data is transferred from the secondary storage element of one stage to the primary storage element of the next stage during the clock cycle φ0. Similarly, FIGS. 4, 5, 6, and 7 illustrate that the primary and secondary storage elements at each stage are stored in the same manner as the ACCEPT signal is provided from stage to stage.
Indicates that it is further connected via an internal receiving line to provide a CCEPT signal. In this way, the secondary storage element will know when it can supply its data to the primary storage element.

FIGS. 4, 5, 6, and 7 show the φ1 phase of cycle 1. FIG. During this cycle, data D1, D2, and D3, which have already been shifted to the secondary storage elements of stages E, D, and B, respectively, are shifted to the primary storage elements of each stage. Therefore, the configuration of the pipeline during the φ0 phase of cycle 1 is the same as that of cycle 1 in FIG. As before, the ACCEPT signal to stage F is assumed to be LOW. However, FIGS. 4, 5,
As shown in FIGS. 6 and 7, the ACCEPT signal to the primary storage element of stage F is LOW, but since this storage element does not contain valid data, this storage element replaces the ACCEPT signal with its secondary storage element. Is set to HIGH.

Since the secondary storage element of stage F does not contain valid data, the ACCEPT signal is also set HIGH from the secondary storage element of stage F to the primary storage element of stage E. As before, the primary storage elements of stage F can accept data, so that the data in all upstream primary and secondary storage elements can be shifted downstream without any data being overwritten. is there. 1
The shift of data from one stage to the next stage occurs during the next φ0 phase in cycle 2. For example, valid data D1 contained in the primary storage element of stage E is shifted to the secondary storage element of stage F, and data D4 is in the pipeline, ie
Shifted into the secondary storage element of stage A, and so on.

The primary storage element of stage F does not yet contain valid data during the φ0 phase in cycle 2, so the ACCEPT signal from the primary storage element to the secondary storage element of stage F remains HIGH. is there. Thus, during the φ0 phase period in cycle 2, data can be shifted one step further to the right, ie, from the secondary storage element to the primary storage element in each stage. However, once the valid data is
Loaded to the primary storage element of stage F, ACCEPT from downstream device to stage F is still LOW
, The data cannot be shifted from the secondary storage element of stage F without overwriting and destroying the valid data D1. Thus, the ACCEPT signal from the primary storage element to the stage F secondary storage element will be low. However, the secondary storage does not contain valid data and its ACCEPT
Since the signal output was HIGH, the data D2 can still be shifted to the secondary storage of stage F.

During the φ1 phase of cycle 3, data can be shifted in all earlier stages, but data D2 cannot be shifted into the primary storage element of stage F. However, once valid data has been loaded into the secondary storage element, stage F cannot provide this data. Stage F sends this event to its ACCEPT signal
Transmit by setting outside W.

When the ACCEPT signal to stage F is LOW
Assuming that the data remains upstream, the data upstream of the F stage is shifted between stages and within each clock phase stage until the next valid data block D3 reaches the primary storage element of stage E. It is possible to As shown in FIG.
This state is reached during one phase period.

During the φ phase period of cycle 5, data D3
Of the stage E to the primary storage element is completed. Since this data cannot be further shifted, the ACCEPT signal from the primary storage element of stage E is L
Set to OW. Upstream data can be shifted normally.

Here, as shown in cycle 5 of FIG.
Assume that devices connected downstream of the pipeline can accept pipeline data. This device puts the ACCEPT signal into the pipeline stage F during the φ1 phase of cycle 4
Send this event by setting to H.
Here, the primary storage element of stage F shifts data to the right, and the primary storage element of stage F can accept new data as well. Thus, since data D1 has been shifted during the φ1 phase of cycle 5, the primary storage element of stage F no longer contains the data that must be saved. Thus, during the φ1 phase of cycle 5, data D2 is shifted from the secondary storage element to the primary storage element in stage F. Stage F secondary storage elements can accept new data and signals by setting the ACCEPT signal HIGH in the stage E primary storage element. During one stage, i.e. during the transfer of data from its secondary to its primary storage element, both sets of storage elements contain the same data, but the data in the secondary storage element is stored in the primary storage element. Also retained, this data in the secondary storage element is overwritable without data loss. The same is true for data transfer from the primary storage element of one stage to the secondary storage element of the next stage.

Here, during the φ1 phase period of cycle 5, ACCE is applied to the primary storage element of stage F.
Assume that the PT signal goes LOW. This means that stage F cannot transfer data D2 from the pipeline. Therefore, the stage F performs an ACC from its secondary storage element to its temporary storage element to prevent overwriting of valid data D2.
Set the EPT signal to LOW. However, stage F
The data D2 stored in the secondary storage element cannot be overwritten without loss, and as a result, data D3 is stored in the secondary storage of stage F during the φ0 phase of cycle 6. Transferred within the element. Data D4 and D5 cannot be shifted downstream as normal. Once valid data D3 is stored in stage F together with data D2, as long as the ACCEPT signal to the primary storage element of stage F is LOW,
Any secondary storage element cannot accept new data, and the secondary storage element sends this by setting the ACCEPT signal to stage E LOW.

AC from downstream device to pipeline
If the CEPT signal changes from LOW to HIGH or vice versa, this change must not propagate further upstream in the pipeline than the immediately preceding storage element (either in the same stage or in the previous stage). Inside the pipeline stage). Furthermore, this change propagates upstream in the pipeline by one storage element block per clock phase.

As described in this example, FIGS.
The concept of "one stage" in the pipeline structure shown in FIGS. 6 and 7 is a perceptual problem. If the data is located between stages, it is transferred within the stage (from the secondary storage element to the primary storage element) (from the primary storage element of the upstream stage to the secondary storage element of the adjacent downstream stage). Thus, one stage can be considered to consist of a "primary" storage element followed by a "secondary storage element" instead of the case shown in FIGS. 4, 5, 6, and 7. Thus, the concept of "primary" and "secondary" storage elements is mostly a matter of labeling. In FIG. 4, FIG. 5, FIG. 6, FIG. 7, when data is transferred from one stage to the next stage or device, the primary storage element is the element from which the data is retrieved, and
Since the "secondary" storage element can be an "input" storage element for the same stage, the "primary" storage element can also be referred to as an "output" storage element.

As shown in FIGS. 1 and 3, when describing the above-described embodiment, only the data transfer under the control of the ACCEPT and VALID signals has been mentioned. In addition, each pipeline stage processes the data it has received arbitrarily before feeding between the internal storage elements of each pipeline stage or before feeding it to the next pipeline stage. It should be understood that is possible. Therefore, FIGS.
Referring once again to FIGS. 6 and 7, a pipeline stage includes input and output storage elements, and can be defined as part of a pipeline that optionally processes data stored in the storage elements.

Further, the "device" downstream from pipeline stage F need not be some other type of hardware structure, but rather may be another pipeline itself or a portion thereof. As described below, a pipeline stage requires multiple clock phases to finish processing that data, as well as when all of the downstream storage elements are filled with valid data. Even if that ACCEP
The T signal can be set LOW. This can occur as well if the pipeline stage produces valid data in one or both of its storage elements. In other words, it is not necessary for the stage to simply supply the ACCEPT signal based on whether the immediately downstream storage element contains valid data that cannot be supplied. Rather, the ACCEPT signal itself can be modified within the stage or by circuitry external to the stage to control the data path between adjacent storage elements. The VALID signal can be similarly processed in a similar manner.

Two-wire interface (VALID and A
One wire for each of the CCEPT signals)
The great advantage of is that it has the ability to control the pipeline without the control signals required to propagate the pipeline all the way back to its start stage. Referring again to cycle 3 of FIG. 1, for example, stage F "tells" stage E that it cannot accept the data, but stage E tells stage D, and stage D has stage C Tell As a practical matter, if there are more stages than valid data contained, this signal can propagate further down the pipeline. In the embodiment shown in FIGS. 4, 5, 6 and 7, cycle 3, the LOW ACCEPT signal does not propagate any further upstream of stage E but remains up to its primary storage element.

As described below, this embodiment can achieve this flexibility without any particular attachment to the silicon portion required to implement the design.
In general, each latch in the pipeline used for data storage requires only one extra transistor (highly efficient silicon fit). In addition, the ACCEP associated with the data latch in each half stage
Preferably, two extra latches and a small number of gates are added to process the T and VALID signals.

FIG. 8 shows a hardware structure for realizing the stages as shown in FIGS. 4, 5, 6, and 7.

By way of example only, 8-bit data is transferred in parallel through the pipeline (with or without further operation in optional combinational logic). Suppose
However, it should be understood that either 1-bit data or data of less than 8 bits can be used to implement the present invention. Furthermore, the two-wire interface according to the present embodiment is suitable for use with data buses of any width, and the width of the data bus may vary from stage to stage depending on the needs of a particular application. possible. An interface according to this embodiment can also be used to process analog signals.

As previously discussed, other conventional timing arrangements can be used, but the interface is preferably controlled by a two-phase non-overlapping clock. 8 to 16, these clock phase signals are referred to as PH0 and PH1. In FIG. 8, one line is shown for each clock phase signal.

The input data is a multi-bit data bus I
The data is input to the pipeline stage via N data, and then transferred to the next pipeline stage or the next receiving circuit via the output data bus OUT data. The input data is first loaded into the series of input latches (one for each input data signal), collectively referred to as LDIN and making up the above secondary storage element, in the manner described below.

In the example of this embodiment shown in the figure, the Q outputs of all latches follow their D inputs, ie, when the clock input is HIGH, ie, at the logic "1" level. Are loaded. In addition, the Q outputs retain their last values.
In other words, the Q outputs are "latched" at the falling edge of their corresponding clock signal.

Each latch may have one or two non-overlapping clock signals PH0 or PH1 (as shown in FIGS. 9 and 10) or one of these clock signals PH0 and PH1 for that clock. One and one logical signal logical AND combination. However, the present invention provides a latch that latches on the rising edge of the clock signal, or other known latch arrangements, as long as conventional methods are applied to ensure proper timing of the latch operation. Works equally well.

The output data from the input data latch LDIN is supplied via an optional and optional combinational logic circuit B1, which is provided for converting the output data from the input latch LDIN into intermediate data. This intermediate data may then be later loaded into an output data latch LDOUT, which consists of the primary storage element described above.

The output from the output data latch LDOUT can likewise be supplied via an optional and optional combinational logic circuit B2 before being supplied downstream as OUT data to the next device. The next device may be another pipeline stage or another device connected to the pipeline.

In the implementation of the present invention, each stage of the pipeline is likewise validated input latch LVIN,
Validation output latch LVOUT, receiving input latch L
AIN, and an acceptance output latch LAOUT. Each of these four latches is preferably a simple single stage latch. Latch U / IN, LVOUT,
The outputs from LAIN and LAOUT are Q
VIN, QVOUT, QAIN, and QAOUT. The output signal QVIN from the validation input latch is connected to the validation output latch LVOUT either directly as an input or through an intermediate logic device or circuit that changes the signal.

Similarly, the output validation signal QVOUT of a given stage can be connected to the input of the validation input latch QVIN of the next stage, either directly or through an intermediate device or logic circuit. . The device in this case may be a device that changes the validation signal. This output QVIN is likewise connected to a logic gate (described below), the output of which is connected to the input of the receiving input latch LAIN. Output QAOUT from receiving output latch LAOUT
Is connected to a similar logic gate (described below), optionally via another logic gate.

As shown in FIG. 8, the output validity check signal Q
VOUT is set to IN VALI by a subsequent stage.
OUT VAL that can be received as a D signal
Form an ID or simply indicate valid data to subsequent circuits connected to the pipeline. The next circuit or stage is ready to accept data by the signal OUTA.
Each stage is designated as CCEPT, and this signal
Preferably, it is connected as an input to the receiving output latch LAOUT via a logic circuit described below. Similarly, the output QAUT of the receiving output latch LAOUT is preferably connected to the receiving input latch L
Connected as input to AIN.

In implementing the present invention, the output signals QVIN, QVOUT from the validity checking latch LVIN are used to form the inputs to the receiving latches LAIU, LAQUT, respectively.
Each is combined with EPT1. In the embodiment shown in FIG. 8, these input signals are formed as logical NAND combinations of the respective validation signals QVIN, QVOUT as the logical inverse of the respective accepted output signals QAOUT , OUT ACCEPT. Conventional logic gates NAND1 and UAND2 perform the NAND operation, and inverters INV1 and INV2 form the logical inverse of the respective acceptance signals. As is well known in the digital design art, if any or all input signals of a NAND gate are in a logic "0" state,
The output from the NAND gate is a logical "1". Therefore, the output from the NAND gate will be a logical "0" only if all inputs of the NAND gate are in a logical "1" state.
It is. As is also well known in the art, the output of a digital inverter, eg, INV1, is a logic "1" when its input signal is "0" and the input signal is "1". ”Is“ 0 ”.

Therefore, when "NOT" indicates binary inversion, the input to NAND gate NAND1 is QVI
N and NOT ( QAOUT ). Using known techniques, the input to the receiving latch LAIN can be decomposed as follows.

NAND (QVIN, NOT (QAOUT)) = NOT (QVIN) OR QAQUT In other words, the signal QVIN is “0”, or
If the signal QAQUT is "1" or in both cases, the inverter INV1 and the NAND gate NAND
The combination of 1 is logic "1". Therefore, the gate N
AND1 and the inverter INV1 have one input coupled directly to the QAOUT output of the receiving latch LAOUT and another single input coupled to the inverse of the output signal QVIN of the validation input latch LVIN.
This can be realized by an R gate.

Similarly, as is well known in the digital design art, many latches suitable for use as a validation and acceptance latch have two outputs, Q, and NOT.
(Q), that is, Q, and its logical inverse. Therefore, if you choose this type of latch,
One input to the OP gate (and therefore) can be coupled directly to the NOT (Q) output of the validation latch LVIN. Gate NAND1 and inverter INV
1 can be realized using a known conventional technique. However, depending on the architecture of the latch used, a latch that does not invert the output is used, and the gate NAND1 and the inverter IN are used instead.
It may be more efficient to provide V1. Both of these can likewise be efficiently implemented in silicon devices. Thus, any known arrangement can be used to generate the Q signal and / or its inverse.

Both clock signals (PH at the output side)
0, and PH1 at the input side, and the outputs from the receiving latches on the same side are logic "1", then the data and validation latches LDIN, LDOUT, LVIN, and LVOUT connect their respective data inputs. To load. Thus, the clock signal (PH0 for the input latches LDIN and LVIN), and the output of each receiving latch (LAIN in this case) are used in a logical AND manner, and they are both logical "1" s.
Data is loaded only if

For example, in certain applications, such as a CMOS implementation of a latch, a logical AND operation that controls the loading of the latch (via CK, shown in the figure, or an activation "input") requires a respective activation input signal (via the activation input signal). For example, latch LVIN and PH for LDIN
0, and QAIN) to the gate to a MOS transistor connected in series to the input line of the latch. Therefore,
It is necessary to provide an actual logical AND gate,
This can cause timing problems due to propagation delays in high speed applications. Thus, the AND gate shown in the figure merely indicates the logic function to be implemented to generate the various latch activation signals.

Therefore, the data latch LDIN loads input data only when PH0 and QAIN are both "1". This data latch latches this data when either of these two signals goes to "0".

To clock the data and validation latches on the input (and output) side of the pipeline stage, one of the clock phase signals PH0 or PH1 is used.
While only one is used, the other clock phase signal is used directly to clock the receiving latch on the same side. In other words, the accept latch on either side of the pipeline stage (input or output)
Preferably, the "out of phase" is clocked using data and validation latches on the same side. For example, PH0 is used to generate a clock signal CK for the data latch LDIN and the validation latch LVIN, PH1 is used to clock the acceptance input latch.

As an example of the operation of a pipeline augmented by a two-wire validation and acceptance circuit, at the input to the circuit, either from the preceding pipeline stage or from the transmission device, the valid Assume no data is provided. In other words, since the system has been reset very recently, the validation input signal IN VALID to the stage shown in the figure is still "1".
Assume that it is not. Further, assume that several clock cycles have occurred since the system was last reset, and as a result, the circuit has reached steady state. Thus, during the next positive period of clock PH0, the validation input signal QVIN from validation latch LVIN is loaded as "0". Thus, during the next positive period of the clock signal PH1, the input to the receiving input latch LAIN (via gate NAND1, or other equivalent gate) is loaded as a "1". That is, because the data in the data input latch LDIN is not valid, the stage sends a signal that the stage is ready to accept input data (since the stage does not hold any data value storage).

Note that in this example, the signal IN ACCEPT is used to enable the data and validation latches LDIN and LVIN.
At this point, since the signal IN ACCEPT is "1", these latches effectively operate as conventional transparent latches, so that any data on the IN data bus will have a clock signal PHD of "1". , The data latch LDIN is simply loaded. Of course, as long as the output QAOUT from the receiving latch is "1", this invalid data is similarly loaded into the next data latch LDOUT of the next following pipeline stage.

Thus, during the next positive period of each clock signal, unless the data latch contains valid data, it will accept, or "load", any data provided. On the other hand, such invalid data is not loaded into any stage for which the accept signal from the corresponding accept latch is LOW (ie, “0”). In addition, the corresponding INVALID (or QVIN) to the validation latch
As long as the signal is low, the output signal from the validation latch (forming the validation input signal to the next validation latch) remains at "0".

If the input data to the data latch is valid, this is indicated by the validity check signal IN VALID rising to "1". The output of the corresponding validation latch then rises to "1" at the next rising edge of each clock phase signal. For example, at the next rising edge of clock phase signal PH0, if the corresponding IN VALID signal goes HIGH (ie, rises to “1”), latch LVIN validity input signal QVIN rises to “1”. I do.

Instead, the data input latch L
Assume that DIN contains valid data. When the data output latch LDOUT is ready to accept new data, its accept signal QAOUT
Is “1”. In this case, during the next positive cycle of clock signal PH1, data latch LDOUT and validation latch LVOUT are enabled, and data latch LDOUT loads the data located at its input. Since the clock signal is non-overlapping, the above operation occurs before the next rising edge of the other clock signal PH0. Thus, at the next rising edge of PH0, the leading data latch (LDIN) will not latch on new input data from the preceding stage until the data output latch LDOUT has safely latched the data transferred from latch LDIN. .

Therefore, since the operation is performed based on the alternating phase of the clock, the same sequence is continued by all adjacent pairs of data latches (intra-stage or between adjacent stages) that can receive data. Any data latch that is not ready to accept new data because it contains valid data that is not yet available will be low.
Has an output accept signal (the QA output from its accept latch LA) that is OW and its data latch LDI
N or LDOUT is not loaded. Thus, the acceptance signal (output from the acceptance latch) at a given stage, or one side (input or output) of a stage, is L
As long as it is OW, its corresponding data latch is not loaded.

FIG. 8 shows the reset function included in the preferred embodiment. In the example shown in FIG.
OTRESET0 is a validity check output latch LVOUT
(The inversion is conventionally indicated by a small circle). As is well known, this means that whenever the reset signal NOTRESET0 goes to "0", the validation latch LVOUT is forced to output "0". One advantage of resetting the latch when the reset signal goes low (goes to "0") is that resetting the latch by interrupting the transmission. In this case, whenever a valid transmission begins and the reset signal goes high, these latches are in an "empty" or reset state. Therefore, the reset signal NOTRESET0
Operates as a digital "on / off" switch. Therefore, this signal must be high to activate the pipeline.

Note that it is not necessary to reset all of the latches that hold valid data in the pipeline. As shown in FIG. 8, the validity check input latch LVIN is not directly reset by the reset signal NOTRESET0, but is reset indirectly.
Assume that reset signal NOTRESET0 drops to "0". Acceptance output latch LAOUT (Gate N
When the input to (via AND1) goes high, regardless of its previous state, the validation output signal QVOUT
Also falls to “0”. Similarly, the acceptance output signal QAOUT also rises to "1". Next, this QAOUT
The value “1” is regarded as “1” and the plausibility check input signal QVI
Regardless of the N state, it is forwarded to the accept input latch input LAIN. Next, the acceptance input signal QAIN becomes “1” at the next rising edge of the N clock signal PH1.
To rise. Assuming that the validity check signal IN VALID has been correctly reset to "0", if the validity check latch LVIN had been directly reset , when performed, at the next rising edge of the clock signal PH0, The output from the test latch LVIN becomes " 0 ".

As this example shows, resetting all validation latches requires only resetting the validation latch on only one side of each stage (including the last stage). is there. In fact, in many applications it is not necessary to reset all other validation latches. That is, the reset signal NOTRESET0 is set to the phase PH of both clocks.
If it can be guaranteed that it will be present for more than one complete cycle of 0, PH1, an "auto-reset" (backpropagation of the reset signal) will cause a validation latch in the preceding pipeline stage. Occurs for a period. As a practical matter, if the reset signal is held for at least the entire number of cycles of both phases of the clock as many as the number of pipeline stages present,
It is only necessary to directly reset the validation output latch in the last pipeline stage.

FIGS. 9 and 10 show the non-overlapping clock signal PH.
The two sides of the pipeline stage in the embodiment shown in FIG. 8 for the relationship between 0, PH1, the effect of the reset signal, the retention of the data, and the different orders of the validation and acceptance signals, and This shows the transfer of data during that time. In the examples shown in the timing diagrams of FIGS. 9 and 10, it is assumed that the outputs from the data latches LDIN, LDOUT are provided without further manipulation by the intervening logic blocks B1, B2. This is shown as an example and does not have a restrictive meaning. Every combinatorial logical structure is
It should be understood that it can be included between the data latches of successive pipeline stages or between the input and output of one single pipeline stage.
The values actually shown for the input data (for example,
HEX data words "aa", or "04") are likewise merely illustrative examples. As noted above, the width of the input data bus is arbitrary (and can be analog) as long as the data latch or other storage device can accommodate and latch or store the value of each bit or input word. Absent). Preferred Data Structure-"Tokens" In the sample application shown in FIG. 8, each stage is all Process input data. To provide greater flexibility, the present invention has a data structure in which "tokens" are used to distribute data and control information throughout the system. Each token consists of a series of binary bits divided into one or more token word blocks. Further, the bits correspond to one of the following three types: address bits (A), data bits (D), or extension bits (B). As an example only, without necessarily having a restrictive meaning,
Assume that it is transferred as a word over a 0-bit bus with a 1-bit extended bit line. An example of a four-word token is shown below in transmission order. Note that the extension bit E is used as an addition (preferably) to each data word. Furthermore, the length of the address field can be variable and is preferably transmitted immediately after the extension bits of the first word.

Therefore, the token is (2) in the present invention.
Hex) consists of one or more words of digital data.
Each of these words is preferably transferred in parallel and ordered. However, this transfer method is not always necessary, and serial data transfer using a known technique is also possible.
For example, in a moving image parsing system, control information is transmitted in parallel, and in this case, data is transmitted in series.

As shown by way of example, each token is:
Preferably, at the start, there is one address field (A-bit string) identifying the type of data contained in the token. In most applications, one single word, or part of a word, is sufficient to transfer the entire address field. However, even if the logic is included in the corresponding pipeline stage that can receive the entire address field and store some representation of the partial address field that is long enough to decode If so, the above conditions are not necessary for the present invention.

Note that no dedicated lines or registers are required to transmit the address field. Note that the address field is transmitted using data bits. As explained below,
If not intended to be activated by a particular address field, that is, if the stage can be supplied along with the token without delay, the pipeline stage will not be slowed down.

The remaining data in the token following the address field is not constrained by the use of the token.
These D data bits can have any value, and the meaning of these bits is not significant here. That is, the meaning of the data can change, for example, depending on where in the system the data was located at a particular point in time. The number of data bits D appended after the address field can be as long or as short as necessary, and the number of data words can vary significantly for different tokens. The address field and the extension bits are used to carry control signals to the pipeline stage. Since the number of words (string of D bits) in the data field is optional, the information carried in the data field can change accordingly. Accordingly, the following description is directed to the use of addresses and extension bits. In the present invention, a token is a particularly useful data structure when a number of blocks in a circuit are connected together in a relatively simple configuration. The simplest configuration is, for example, a pipeline of processing steps, one of which is shown in FIG. However, the use of tokens is not restricted only to use in a pipeline structure.

Assume again that each box represents a complete pipeline stage. In the pipeline of FIG. 1, data flows from left to right in the figure. The data enters the machine and feeds to processing stage A. This stage may or may not modify the data, and provides the data to stage B. If modified, it can be complicated, and in general,
The number of data items flowing into any stage is not the same as the number of flows. Stage B corrects the data again,
And supply it to stage C, etc. With this type of design, it is not possible for data to flow in the opposite direction. Thus, for example, stage C cannot supply data to stage A. This constraint is often perfectly acceptable.

On the other hand, it is highly desirable that stage A can transmit information to stage C even when these two blocks are not directly connected. The communication between the stages A and C is limited to the case of going to the stage B. One advantage of tokens is that they have the ability to accomplish this type of communication. Any processing stage that does not recognize the token simply supplies the unchanged block to the next block.

According to this example, one extension bit is transmitted with the address and data fields in each token, so that the processing stage does not need to decode the address at all, and the token ( (Which can be of any length).
According to this example, every token that contains an extension bit that is HIGH ("1") is followed by a subsequent word that is part of the same token. This subsequent word also has an extension bit, which indicates whether there are any more token words in the token. If the stage encounters a token word whose extension bit is LOW (one "0"), it knows that the token word is the last word of the token. Therefore, the next word is assumed to be the first word of the new token.

It should be noted that while a simple pipeline of processing stages is particularly useful, tokens can be applied to processing elements in more complex configurations. The following is an example of a more complex processing element.

In the present invention, it is not necessary to use the state of the extension bit to transmit the last word of a given token by providing the extension bit set to "0". One alternative to the preferred implementation plan is to move the extension bits to indicate the first word of the token instead of the last word of the token. This can be achieved by appropriate adaptation of the decoding hardware.

The advantage of using the extension bits of the present invention to transmit the last word instead of the first word of a token is that the block of circuitry in the circuit depends on whether the token has an extension bit. It is often useful to modify the mode of operation. An example of the above discussion is a token that activates a stage that processes video quantization values stored in a quantization table (typically a memory device). For example, a table containing 64 8-bit arbitrary binary integers.

To load a new quantization table into the quantizer stage of the pipeline, a "QUANT table" token is sent to the quantizer. In such a case,
For example, a token consists of 65 token words.
The first word contains the code "QUANT table", ie, creates a quantization table. This is followed by an integer of 64 words from the quantization table.

When coding moving picture data, it is sometimes necessary to transmit such a quantization table. To achieve this function, a QUANT table token without extended words can be sent to the quantizer stage.
When looking at this token and noticing that the extension bit of the first word is LOW, the quantizer stage reads the quantization table and QUANT containing 64 quantization table values.・ A table token can be created. Until the LOW extension bit corresponding to the value of the 64th quantization table indicates the new end of the token, the extension bit is HIGH, and the token is continued with the HIGH extension bit. , The extension bits of the first word (which was LOW) are changed. This proceeds in a general manner through the system and is encoded into a stream of bits.

Continuing the description with this example, the quantizer determines whether the first word of the QUANT table token has its extension bit set or not.
It is either possible to load the new quantization table into its own memory device or to read the table.

The choice of transmitting the first token word or the last token word in a token using the extension bits depends on the system in which the pipeline is used. Both alternatives are possible according to the invention.

Another alternative to the preferred extension bit scheme is to include a length count at the beginning of the token.
For example, if the token is very long, this type of device may be efficient. For example, assume that a typical token length for a given application is 1000 words. Using the proposed extension bits (with bits appended to each token word) as shown, the token requires 1000 additional bits to include all the extension bits. However, to encode the length of the token in binary form, only 10
A bit is needed.

Thus, although there are uses for long tokens, experience has shown that there are many uses for short tokens. Here, the preferred extension bit scheme is advantageous.
If the length of the token is only one word, only one bit is needed to transmit it.
However, the counting scheme requires the same 10 bits as in the above case.

The disadvantages of the length counting scheme are as follows. 1) Inefficient for short tokens. 2) Restriction on maximum length for tokens (if less than 1023 words, only 10 bits can be counted) 3)
The length of the token must be known before generating a count (possibly at the start of the token). 4) All circuit blocks handling tokens need to have hardware to count words. 5) If the count is corrupted (due to data transmission errors), it is not clear whether recovery is achievable.

The advantages of the extension bit scheme according to the invention are as follows. 1) The pipeline stage does not need to have a circuit block to decode all tokens, because unrecognized tokens can be correctly supplied by considering only the extension bits. 2) Encoding of extension bits is the same for all tokens. 3) There is no limit on token length. 4) This scheme is efficient for short tokens (in terms of overhead to represent token length). 5) Error recovery is achieved naturally. If the extension bit is corrupted, one random token is generated (for corrupted extension bits from "1" to "0") or the token is lost (corrosion extension bit is "0") To "1"). Furthermore,
The problem is localized only to the token concerned. After the token, the correct operation is automatically resumed.

Further, the length of the address field may be changed. This is highly advantageous because it allows the most common tokens to be squeezed into a very small number of words. This is of great importance in video data pipeline systems, as it ensures that all processing stages can operate continuously at full bandwidth.

According to the present invention, to enable a variable length address field, the addresses are chosen such that a short address followed by random data is never confused with a longer address. The preferred technique for encoding the address field (also serving as the "code" for activating the intended pipeline stage) is the well-known technique first disclosed by Huffman and commonly referred to as the "Huffman code". However, it should be understood that a person of ordinary skill in the art will find that other encoding schemes will be successful.

Although Huffman coding is well understood in the field of digital design, the following example is provided to provide a general background.

Huffman codes consist of words composed of a sequence of symbols (eg, in the context of a digital system such as the present invention, symbols are generally binary digits). The length of the codeword is variable , and a special property of the Huffman codeword is that the codeword is selected such that no longer codewords starting with the symbols forming the shorter codeword are possible. According to the present invention, the token address field is preferably (although not necessarily) selected using known Huffman coding techniques.

Furthermore, in the present invention, it is preferable that the address field starts at the most significant bit (MSB) of the first word token. (The manifestation on the MSB is optional, and the present invention can be modified to accommodate various manifestations on the MSB.) The address field continues through less significant neighboring bits. In a particular application, if a token address requires more than one token word, the address field, which is the least significant bit in any given word, will continue in the most significant bit of the next word. The minimum length of the address field is one bit.

To generate the token used in the present invention, any one of several known hardware structures can be used. One such structure is a microprogrammed state machine. However, known microprocessors or other devices can be used.

A major advantage of the token scheme according to the present invention is that it has the flexibility to accommodate unexpected needs. For example, when a new token is introduced, the introduction typically affects only a few pipeline stages. The most likely case is that only two stages or circuit blocks are affected. That is, one block generates tokens first, and the other block or stage is newly designed or modified to handle this new token. Note that the other pipeline stages do not require any modifications. On the contrary, these stages do not recognize this new token, and thus supply unmodified tokens, so that new tokens can be handled without modifying the design of these stages.

It is a distinct advantage of the present invention to have the ability to keep pre-designed existing devices substantially unaffected. To make some semiconductor chips in one chip set completely unaffected by improving in design some other semiconductor chips in said chip set Is possible. This is advantageous from both the customer and chip maker perspectives. Reuse the same design, even if the modification means that all chips are affected by the design change (conditions where the level of integration progresses gradually and the number of chips in the system decreases) This leaves a considerable advantage over what is achievable in terms of time to market.

In particular, note the conditions that occur when it becomes necessary to extend the token set to include a two word address. Even in this case, it is not yet necessary to modify the existing design. The token decoder in the pipeline stage attempts to decode the first word of such a token and concludes that the first word does not recognize the token. The token decoder then supplies the modified token by using the extension bits to correctly perform this operation. The token decoder "assumes" that the second word is part of the data field of the token that the token decoder does not recognize, so that the token decoder (even if the token contains address bits) Does not attempt to decode the second word of.

In many cases, a pipeline stage or connected circuit block modifies a token. This is generally however, not as a requirement, in the form of modifying the preparative chromatography click <br/> emissions data field. Further, it is common to change the number of data words in the token to be modified either by removing specific data words or adding new data words. In some cases, the token is completely removed from the token stream.

In most applications, the pipeline stage generally only decrypts a few tokens (activated by tokens). That is, the stage does not recognize other tokens and supplies the other tokens unchanged. Very often, only one token, i.e., the data token word over de itself is decoded.

In many applications, the operations of a particular stage depend on the results of its own past operations. Therefore, the "state" of the stage
Depends on the previous state. In other words, a stage relies on stored state information, which means that it must maintain some information about its own history in one or more previous clock cycles. This is another method to be described. The invention is well suited for use in pipelines that include this type of "state machine" stage, as well as in applications where the latches in the data path are simple pipeline latches.

A two-wire interface according to the present invention
Compatibility with this type of "state machine" circuit is a significant advantage of the invention. This is especially true if the data path is being controlled by a state machine. In this case, the two-wire interface technology described above can be used to ensure that the "current state" of the machine stays in line with the data being controlled in the pipeline.

FIG. 11 shows a simplified block diagram of one example of a circuit included in the pipeline stage for decoding the token address field. This figure shows a pipeline stage with the properties of a “state machine”.
Each word of the token contains one "extension bit", which is HIGH if there are more words in the token, or LOW if this is the last word of the token. If this is the last word of the token, the next valid data word is
It is the start of a new token, so its address must be decrypted. Thus, the decision as to whether to decode the token address in any given word depends on knowing the value of the previous extension bit.

For purposes of simplicity only, the two-wire interface (along with the acceptance and validation signals and latches) is not shown, and for all details dealing with resetting the circuit, It is omitted. As before, the 8-bit data word is:
It is assumed only by way of example, not by way of limitation.

This exemplary pipeline stage delays data bits and extension bits by one pipeline stage. In addition, this stage decrypts the data token. At the point when the first word of the data token is provided at the circuit output, the signal "Data A
DDR "is created and set HIGH.
The data bits are delayed by latches LDIN and LDOUT, each of which is in this example (8 inputs 8
This is repeated eight times for the eight data bits used for the output latch. Similarly, extension bits are delayed by extension bit latches LEIN and LEOUT.

In this example, the latch LEPREV is:
Provision is made for storing the most recent state of the extension bit. The value of the extension bit is loaded into LEIN, and
LEOUT is loaded on the next rising edge of non-overlapping clock phase signal PH1. Thus, the latch LEOUT contains the value of the current extension bit, but only during the second half of the non-overlapping two-phase clock. However, the latch LEPREV loads this extended bit value on the next rising edge of the clock signal PH0, the same signal that activates the extended bit input latch LEIN. Therefore, the output QEP of the latch LEPPEV
REV holds the value of the extension bit during the previous PH0 clock phase. The result of adding the non-inverted MD [2] of the latch LDIN to the 5 bits of the data word output from the inverted Q output is a series of logic gates NAND1, NAND2,
And the previous extension bit value QEPPEV in NOR1. These operations are well known in the digital design art. The name "NM
"D [m]" indicates a logical inversion of the bit m of the mid data word MD [7: 0]. Using known Boolean techniques, the previous extension bit is "0" (QPPEV =
"0"), this logical block (NOR1
Output signal SA is HIGH ("1").
It can be shown that It can be seen that the data word structure at the output of the non-inverting Q latch (original input word) LDIN is "000001xx". That is, the five high-order bits, MD [7] -M
The D [3] bits are all "0" and the bit M
D [2] is "1" and the bit at the zero-one position has any arbitrary value.

Thus, the four possible data words (there are four permutations of "xx") cause SA, and thus the output of address signal latch LADDR, whose input SA is connected to its input, to HIGH. In other words, this stage is performed if one of the four possible legal tokens is supplied and if the previous extension bit was zero, ie, if the previous data word was the last in the previous series of token words. The activation signal (data AD
DP “1”).

Therefore, the signal Q from the latch LEPREV is
If PREV is LOW, the value at the output of latch LDIN is the first word of the new token. Gates NAND1, NAND2 and NOR1 decode the data token (000001xx). However, the address decoding signal SA is delayed in the latch LADOP such that the signal data ADDR has the same timing as the output data OUT data and OUTEXTN.

Another simple example of a state-dependent pipeline stage according to the present invention is shown in FIG. This example uses the signal LA to indicate the value of the previous output extension bit OUTEXTN.
Generate STOUTEXTN. 2 to the current and last extension bit latches LEOUT and LEPPEV respectively
One of the two enable signals (at the CK input) indicates that the data is valid and that the Q outputs from the output validation and acceptance latches LVOUT and LAOUT are being accepted, respectively, HI
GH), derive from gate AND1 so that these latches load only the new values for these latches. In this way, these signals hold only valid extension bits, and non-true values associated with invalid data are not loaded into these signals. In the embodiment shown in FIG. 12, the two-wire valid / acceptable logic includes OR1 and OR2 gates supplied with downstream accept signals and input signals comprising the non-inverted outputs of validation latches LVIN and LVOUT, respectively. This illustrates one way that the gates NAND1 / 2 and INV1 / 2 in FIG. 8 can be replaced if the latch has an inverted output.

This is a very simple example of a "state-dependent" pipeline stage, ie one that relies on the state of only one single bit, but the data is actually transferred between the pipeline stages. Only if it is true that all latches holding state information are updated. In other words, only if the data are both valid and are being accepted by the next stage. Therefore, care must be taken to ensure that this type of latch is properly reset.

Generating and using tokens in accordance with the present invention provides a number of advantages over known encoding techniques for transferring data through a pipeline.

First, as described above, the length of the address field of the token can be variable (and, for example, Huffman coding) to provide an efficient representation of the general token. Is available).

Second, by performing consistent encoding on the length of the token, even if the token is not recognized by the token decoder circuit in a given pipeline stage, the end of the token (accordingly, , Allowing the start of the next token to be processed correctly (including simple non-operational transfers).

Third, the rules for handling unrecognized tokens (ie, providing tokens unchanged) and the hardware structure allow one stage and the nearest non-adjacent stage in the pipeline to a downstream stage. Enable communication with Furthermore, it increases the scalability and efficient adaptability of the pipeline, as it allows future changes to the token set without requiring extensive redesign of the existing pipeline stages. The tokens of the present invention are particularly useful when used with a two-wire interface, as described above and below.

The function of the exemplary pipeline stage shown in FIGS. 13 and 14 will now be described. When a stage is processing a scheduled token (called a data token in this example), the stage
All words other than the first word including the address field of the data token in this token are duplicated. On the other hand, if the stage is processing other tokens of any kind, it deletes all words. The overall effect is that only data tokens appear at the output, and each word in these tokens is repeated twice.

Many of the components of the system shown here can be the same as those shown in the much simpler structures shown in FIGS. 4, 5, 6 and 7.
This illustrates an important advantage. Modify it slightly or
Alternatively, the same two-wire interface can be used without any modification, so that even more complex pipeline stages have the same advantages in terms of flexibility and elasticity.

The data duplication stages shown in FIGS. 13 and 14 are but one example of the myriad different types of operations that the pipeline stage can perform in a given application. However, this "duplexing stage" may form a "bottleneck", and as a result, exhibit a tage such that the pipeline according to this embodiment is "packed together".

A "bottleneck" is one that takes a relatively long time to perform its operation, or
It can be any stage in the pipeline that produces more data than received. Furthermore, this example shows that the two-wire accept / enable interface according to this embodiment is very easily adaptable to different applications.

The duplication stages shown in FIG. 13 and FIG.
As shown in the example of FIG. 11, two latches L each latch the state of the extension bit at the input and output of the stage.
It has EIN and LEOUT. As shown in FIGS. 13 and 14, the input extension latch LEIN is
Clocked synchronously with DIN and validation signal IN VALID. For ease of reference, the various latches included in the duplexing stage form a pair with each unique output signal.

In the duplication stage, the data latch L
The output from DIN forms intermediate data called MID data. This intermediate data word is loaded into the data output latch LDOUT only if the intermediate accept signal (see "MID ACCEPT" in FIGS. 13 and 14) is set HIGH.

Acceptance latch LAI shown in FIGS. 13 and 14
The circuit sections under N, LAOUT are used to generate various internal control signals used to duplicate data,
This is a circuit added to the basic pipeline structure. These signals include a "data token" signal indicating that the circuit is processing a valid data token, and a NOT DUP used to control data duplication.
LICATE signal. If the circuit is processing a data token, the NOT DUPLICATE signal toggles between a HIGH state and a LOW state, thereby duplicating each word in the token once (and only once). . NOT DUPLICA if the circuit is processing a valid data token.
The TE signal is kept in the HIGH state. Therefore, this means that the token word being processed is not duplicated.

As shown in FIGS. 13 and 14, the upper 6 bits of the 8-bit intermediate data word and the output signal QI1 from the latch LI1 are supplied from the form input to the logic gate N.
Form the inputs to the group of OR1, NOR2, NAND18. The output signal from gate NAND18 is indicated as S1. Using well known Boolean algebra, the output signal QI
It can indicate that 1 is "1" and that signal S1 is "0" only when the MID data word has the following structure. "000001xx", that is, the upper 5 bits are all "0", the bit MID data [2] is "1", and the bit and the MID data [0] position in the MID data [1] are any arbitrary values. have. Therefore, the signal S1 has the structure in which the MID data signal is scheduled and the latch LI
Acts as a "token identification signal" which is low only if the output from 1 is "1". The nature of the latch LI1 and its output QI1 will be further described below.

Latch LO1 performs the function of latching the last value of the intermediate extension bit (denoted as "MID EXTN" and signal S4), and latches this value at the next rising edge of clock phase PH0.
Load to I1. The output of this latch is bit QI1 and is one of the inputs to the token decoding logic group that forms signal S1. As already explained,
Signal S1 simply falls to "0" when signal QI1 is "1" (and the MID data signal has the expected structure). Thus, the signal S1 simply drops to "0" at any time if the last extension bit was "0", indicating that the previous token has ended. Therefore, M
The ID data word is the first data word in the new token.

Latches LO2 and L12, together with NAND gates NAND20 and NAND22, form a storage device for the signal data token. Under normal conditions, signal QI1 at the input to NAND 20 and signal S1 at the input to NAND 22 are both logic "1". Again, Boolean techniques show that in this condition, these NAND gates operate in the same manner as the inverter. That is, signal Q12 from the output of latch LI2 is inverted in NAND 20, and then this signal is
2 to form a signal S2. In this case, since there are two logical inversions in this path, the signal S
2 has the same value as QI2.

[0237] The signal DATA Token at the output of latch LO2 is seen that forms the input to LI2. As a result, as long as QH1 and S1 both remain HIGH, the signal data token is:
The state (“0” or “1”) is maintained. Clock signals PH0 and PH1 are latched (L12,
And LO2) is also clocking. If one or both of signals QI1 and S1 are "0", the value of the data token can only be changed.

As described earlier, signal QI1 is "0" when the previous extension bit was "0".
Thus, whenever the NID data value is the first word of a token, the previous signal is "0" (and the address field for that token is included). Under this condition, the signal S1 is either “0” or “1”. As already mentioned earlier,
If the MID data word has a predetermined structure indicating a data token in this example, signal S1 is "0". If the MID data word has another structure (indicating that the token is another token that is not a data token), S1 is "1".

If QI1 is "0" and S1 is "1", this indicates that there is a token other than the data token. As is well known in the field of digital electronics, the output of NAND 20 is "1".
NAND gate NAND22 inverts this (as already described), and signal S2 is "0". As a result, this "0" value is loaded into latch LO2 at the start of the next PH1 clock phase, and the data token signal goes to "0", indicating that the circuit is not processing a data token.

If QI1 is "0" and S0 is "0", thereby indicating a data token (even though it is another input to NAND 22 from the output of NAND 20) The signal S2 is "1". As a result, this "1" value is loaded into latch LO2 at the start of the next PH1 clock phase, and the data token signal becomes "1", indicating that the circuit is processing the data token. .

The NOT DUPLICATE signal (output signal QO3) is loaded into latch L13 at the next rising edge of clock PH0. Latch LI
The output signal QI3 from 3 is combined with the output signal Q12 at gate NAND24 to form signal S3. As before, using Boolean algebra, it can be seen that signal S3 is "0" only if both signals QI2 and QI3 are at value "1". When the signal QI2 becomes “0”, that is, when the data token signal is “0”,
The signal 53 becomes "1". In other words, if there is no valid data token (QI2 = 0) or if the data word is not duplicated (QI3 = 0), signal S3 goes high.

Here, it is assumed that the data token signal remains HIGH for more than one clock signal. The NOT DUPLICATE signal (QO3) is "feedback" to latch LI3 and the gate N
The output signal QO3 is "0" because it is inverted by AND24 (its other input QI2 is held HIGH).
Toggles between and "1". However, if there is no valid data token, signal QI2 is "0", and signal S3 and output QO3 are forced high until the DATE token signal again becomes "1". The output QO3 (NOT DUPLICATE signal) is likewise fed back and a series of logic gates (together together) whose outputs are "1" only if both signals QA1 and QO3 are "1". Combined with the output QA1 from the receiving latch LAIN in NAND16 and INV16) forming an AND gate. As shown in FIGS. 13 and 14, an AND gate (a gate NAND1 followed by a gate INV16)
The output from 6) is likewise accepted.
To form This acceptance signal, as already mentioned,
Used in a two-wire interface structure.

The accept signal IN ACCEPT is used as an enable signal for the latches LDIN, LEIN, and LVIN. As a result, NOT DUPLI
If the CATE signal is low, the accept signal IN
ACCEPT is also low, and all three latches are disabled and hold the value stored on their outputs. NOT DUPLICATE signal is H
Until it becomes IGH, the stage does not accept new data. This is in addition to the above requirement to force the output from the receiving latch LAIN high.

As long as there is a valid data token (data token signal QO2 is "1"), signal QO3 is
Toggle between HIGH and LOW states. As a result, the input latch is activated and, at most, data is available over every other complete cycle of both clock phases PH0, PH1. "HIG
The additional condition that the next stage is ready to accept data, as indicated by the "H" OUT ACCEPT signal, must, of course, still be satisfied. Thus, over at least two full clock cycles, the output latch LDOUT places the same data word on the output bus OUT data. The OUT VALID signal is "1" only if a valid data token (QO2 HIGH) is present and the validation signal QVOUT is HIGH.

The signal QEIN, an extension bit corresponding to the MID data, is combined with the signal S3 in a series of logic gates (INV10 and NAND10) to form a signal S4. During the data token display period,
Each data word MID data has its output latch LD
Repeated by loading OUT twice. During these first periods, S4 is forced to "1" by the action of NAND10. The signal S4 indicates that the MID data is LDOUT to form OUT data [7: 0].
Is loaded into latch LEOUT to form OUTEXTN at the same time.

Thus, first, predetermined MID data is loaded into LEOUT, and the associated OUTEXT
N is forced high, but second, OUTEXTN
Is the same as the signal QEIN. Now consider the condition during the last word of one token for which QEIN is known to be low. During the first period, MID data is loaded into LDOUT and OID
UTEXTN is "1" and during the second period,
OUTEXTN is “0”, indicating the true end of the token.

The output signal QVIN from the validation latch LVIN is combined with the signal QI3 in a similar gate combination (INV12 and NAND12) to form the signal S5. Using well-known Boolean techniques, signal S5 will be HIGH when either validation signal QVIN is HIGH, or when signal QI3 is low (indicating that data is duplicated). It can be seen that it is. The MID data is loaded into LDOUT, and the intermediate extension bit (signal S4) is loaded into LEOUT while the signal S
5 is loaded into the validation output latch LVOUT.
Similarly, signal S5 is output validity check signal OUT VA
Combined with signal QO2 (data token signal) at logic gates NAND30 and INV30 to form the LID. As already mentioned earlier, OUT VALID is HIGH only if there is a valid token and the validation signal QVOUT is high.
It is.

In the present invention, the MID_ACCEPT signal is the signal S used as one of two enable signals for latches LO1, LO2, and LO3.
6 is combined with signal S5 in a series of logic gates (NAND 26 and INV 26) that perform a well-known AND function. MID ACCEPT signal is H
IGH and whether the validation signal QVIN is high or whether the token is duplicated (QI3
Is signal S6 in the case of a is) There Zureka "0" rises to "1". When the signal MID_ACCEPT is HIGH, whenever the valid input data is loaded at the input of the stage, the clock signal PH1 is high, or if the latched data is duplicated, the latch LO1- LO3 is enabled.

From the above discussion, it can be seen that the stages shown in FIGS. 13 and 14 receive and transfer data between stages under the control of validation and acceptance signals. The exception is that, as in the previous embodiment, the output signal from the receiving latch LAIN on the input side is combined with a toggling duplex signal, so that the data word is ready for a new word. It is output twice before.

For example, various logic gates such as the NAND 16 and the INV 16 can be replaced by an equivalent logic circuit (in this case, one single AND gate). Similarly, for example, when the outputs of the latches LEIN and LVIN are being inverted, the inverters INV10 and INV12 are not needed. Instead, the corresponding inputs to gates NAND10 and NAND12 can be directly coupled to the inverted outputs of these latches. As long as the appropriate logical operation is performed, the stages operate in the same way. Data words and extension bits are still duplicated.

Until the first data word of the token places a "1" in the third position of the word and a "0" in the five high order bits, the duplication function performed by the stage shown in the figure is stomach has been noted that not carried out.
(Of course, the other logic gates and the NOR1, NO
By selecting a connection other than the R2 and NND18 gates, the required pattern can be easily changed and set. 13) Further, as shown in FIGS. 13 and 14, unless the first data word has the structure of the description, OUT VA
The LID signal is forced low throughout the entire token. This has the effect of causing all but one token that causes the duplication process to be removed from the token stream. The reason is that the output terminals (OUT DATA , OUTEXTN, and OUT V)
This is because devices connected to the ALID do not recognize these tokens as valid data. As before, both validation latches L in that stage
VIN and LVOUT are one single conductor NOTR
ESETO and one single reset input R of the downstream latch LVOUT allow it to be reset using a backward propagating reset signal to force the upstream validation latch low in the next clock cycle. It is.

In the examples shown in FIGS. 13 and 14, the data contained in the data token is duplicated by the circuit ACCE.
Note that the PT and VALID signals are operable, so that more data serves only as an example of leaving the pipeline stage than reaching that input. Similarly, to merely illustrate how the circuit can operate the VALID signal to remove data from the stream,
In the examples shown in FIGS. 13 and 14, all non-data tokens are removed. However, in the most typical applications, the pipeline stage simply supplies without modification any tokens that the pipeline stage does not recognize. As a result, other stages further down the pipeline can act on said tokens as needed. FIG. 15 and FIG.
15 illustrates an example of a timing diagram for the data duplication circuit illustrated in FIGS. 13 and 14. This timing diagram shows the relationship between a two-phase clock signal, various internal and external control signals, and the manner in which data is clocked between the input and output of the stage and the data is duplicated. Reference is now made to FIG. 17 in more detail, which illustrates a reconfigurable process stage according to one aspect of the present invention.

The input latch receives an input via the first bus 31. A first output from input latch 34 is provided to token decode subsystem 33 via line 32. The second output from input latch 34 is provided as a first input via line 35 to processing unit 3.
6. A first output from token decode 33 is provided as a second input to processing unit 36 via line 37. Token decode 3
The second output from 3 is supplied via line 40 to an action identification unit 39. In addition, action identification unit 39 receives inputs from registers 43 and 44 via line 46. Registers 43 and 44 are
Maintain the state of the machine as a whole. This state is determined by the history of previously received tokens. The output from action identification unit 39 is provided via line 38 to processing unit 36 as a third input. An output from the processing unit 36 is supplied to an output latch 41. The output from the output latch 41 is supplied via a second bus 42.

Here, referring to FIG. 18, a start code detector (SCD) 51 receives an input through a two-wire interface 52. This input is either in the form of a data token or a data bit in the data stream. A first output from the start code detector 51 is provided via a line 53 to a first logical first in first out (FIFO) buffer 54. The output from the first FIFO 54 is
, Is logically supplied to the Huffman decoder 56 as a first input. The second output from the start code detector 51 is provided as a first input via line 57 as D
It is supplied to the RAM interface 58. Furthermore, D
RAM interface 58 is connected via line 60
Receives input from buffer manager 59. The signal is
It is transmitted and received by a DRAM interface 58 to an external DRAM (not shown) via line 61. A first output from DRAM interface 58 is provided as a first physical input to Huffman decoder 56 via line 62. Huffman decoder 56
The output from is routed via line 63 as input to the index up to data (ITOD) 64. Huffman decoder 56 and ITOD 64 operate together as one logical unit. The output from ITOD64 is
An arithmetic logic unit (ALU) 66 is provided via line 65. The first output from ALU 66 is line 70
Is supplied to a read-only memory (ROM) state machine 68 via the. The output from ROM state machine 68 is provided to Huffman decoder 56 via line 69 as a second physical input. Second from ALU66
Is supplied to a token format unit (TF) 71 via a line 70.

First output from TF 71 according to the present invention
Is supplied to a second FIFO 73 via a line 72. The output from the second FIFO 73 is provided as a first input via line 74 to an inverse modeler 75. A second output from T / F 71 is provided as a third input via line 76 to DRAM interface 58.
Supplied to A third output from DRAM interface 58 is provided as a second input to inverse modeler 75 via line 77. The output from the reverse modeler 75 is
It is provided as an input to inverse quantizer 79 via line 78. The output from inverse quantizer 79 is provided via line 80 as an inverse input to inverse zigzag 81 (IZZ). The output from IZZ 81 is provided via line 82 as an input to discrete inverse cosine transform 83 (IDCT). The output from IDCT 83 is line 84
Is supplied to the time decoder (FIG. 19).

Referring now to FIG. 19 in more detail, a temporal decoder according to the present invention is shown in this figure. Fork 91 receives as input an output from IDCT 83 (FIG. 18) via line 92. As a first output from fork 91, a control token, such as a motion vector or the like, is provided via line 93 to an address generator 94. Further, the data token is provided to an address generator 94 for counting purposes. This data is provided as a second output from fork 91 to FIFO 96 via line 95. Next, the output from FIFO 96 is provided as a first input to adder 98 via line 97. The output from address generator 94 is provided as a first input to DRAM interface 100 via line 99. Signals are sent and received by the DRAM interface 100 to an external DRAM (not shown) via line 91. The first output from the DRAM interface 100 is provided to the prediction filter 103 via line 102. The output from prediction filter 103 is provided as a second input to adder 98 via line 104. The first output from adder 98 is provided to output selector 106 via line 105. The second output from adder 98 is line 1
07, it is supplied to the DRAM interface 100 as a second input. DRAM interface 1
The second output from 00 is the second input as line 108
Is supplied to the output selector 104 via The output from the output selector 104 is supplied to the moving image formatting unit (FIG. 20) via a line 109.

Here, referring to FIG. 20, the fork 111 receives an input from the output selector 106 (FIG. 19) via the line 112. As a first output from fork 111, address generator 114 is supplied with a control token via line 113.
The output from the address generator 114 is as a first input
DRAM interface 116 via line 115
Supplied to The data from the fork 111 as the second output is provided via line 117 as the second input as D
It is supplied to the RAM interface 116. The signal is
DRAM interface 11 via line 118
6, the data is transmitted to and received from an external DRAM (not shown). The output from the DRAM interface 116 is sent via line 119 to the display pipe 120
Supplied to

It is clear from the above description that each line may have a plurality of lines as necessary.

Here, referring to FIG. 21, according to the MPEG standard, one picture 131 is encoded as one or a plurality of slices 132. Each slice 132 has a plurality of blocks 133 and is encoded column by column in each column from left to right. As shown, the span of each slice 132 is
3 may be exactly one row 132, B, C less than one row in block 133, or multiple rows C in block 133.

Referring to FIG. 22, JPEG and H.264 are used. In the H.261 standard, a common intermediate format (CIF) is used, and a picture 141 is encoded as six columns, each column including two groups of blocks (GOB) 142. The GOB 142 is constituted by an unlimited number of blocks 143 in either three rows or six rows. Each GOB 142 is zigzag encoded in the Z-shape direction indicated by arrow 144. As a result, GO
B142 is processed from left to right for each column in each column.

Referring now to FIG. 23, it can be seen that for both MPEG and CIF, the output of the encoder is in the form of a data stream 151. The decoder receives this data stream 151. Next, the decoder can reconstruct the image according to the format used to encode the image. In order for the decoder to be able to recognize the start and end points for each standard, the data stream 151 is divided into 33 blocks 152 in length.

The Venn diagram shown in FIG. 24 represents an area of values that can be selected from the table by the Huffman decoder 56 (FIG. 18) of the present invention. These values are based on the MPEG decoder and H.264. 2
This is a value that can be duplicated for a particular decoder and a particular H.61 decoder by one single table selection.
261 format is decoded.
Similarly, these values are duplicate values for the MPEG and JPEG decoders, indicating that one single table selection decodes both a particular MPEG and a particular JPEG format. Furthermore,
H. The 26l value and the JPEG value do not overlap, indicating that no single table selection exists to decode both formats by themselves.

Reference is now made to FIG. 25 in more detail, which shows an overview of variable length picture data based on the implementation of the present invention. First picture 1 to be processed
61 has a first picture start token 162, first picture information 163 of unlimited length, and a first picture end token 164. The second picture 165 to be processed includes a second picture start token 166, second picture information 16 of unlimited length.
7 and a second picture end token 168. Picture start tokens 162 and 166 are
The start of the pictures 161 and 165 for the processor is shown. Similarly, the picture end tokens 164 and 168 indicate the end of the pictures 161 and 165 to the processor. This allows the processor to:
The variable length picture images 163 and 167 can be processed.

In FIG. 26, split 171 receives an input via line 172. Split 171
Is provided to address generator 174 via line 173. The address generated by the address generator 174 is output on line 175 via the DRA
M interface 176. Signals are sent and received by a DRAM interface 176 via line 177 to and from an external DRAM (not shown). A first output from the DRAM interface 176 is provided via line 178 to the prediction filter 17.
9. The output from prediction filter 179 is provided as a first input to adder 181 via line 180. The second output from split 171 is provided via line 182 to a first-in first-out buffer (FIFO).
O) Supplied as input to 183. FIFO 183
Is provided as a second input to summer 181 via line 184. The output from the adder 181 is supplied to a write signal generator 186 via a line 185. A first output from write signal generator 186 is provided to DRAM interface 176 via line 187. A second output from the write signal generator 186 is provided via a line 188 to the read signal generator 1.
Supplied as a first input to 89. A second output from DRAM interface 176 is provided as a second input to read signal generator 189 via line 190. The signal from the read signal generator 189 is connected to the line 19
1 to video formatting (not shown in FIG. 26).

FIG. 27 shows the prediction filter process.
The forward prediction filter 201 has, as a first input,
The signal is supplied to an adder 203 via 202. The backward prediction filter 204 has as its second input line 2
The signal is supplied to the adder 203 through the line 05. Adder 20
The output from 3 is provided via line 206. As shown in FIG. 28, the slice 211 has one or a plurality of macroblocks 212. As a result, each macroblock 212 has four luminance luminance blocks 213,
And two chrominance blocks 214 and have information about the original 16 × 16 block of pixels. The size of each of the four luminance blocks 213 and two chrominance blocks 214 is 8 × 8 pixels. The four luminance blocks 213 are 1
Pixel Pixel has a pixel-by-pixel mapping of luminance (Y) information for the original 16x16 block of pixels. One chrominance block 214 contains an indication of the chrominance level of the blue signal (Cu / b), and another chrominance block 21 contains an indication of the chrominance level of the red signal (Cv / r). Each chrominance level is such that each 8 × 8 chrominance block 214 includes the chrominance level of its color signal for the entire original 16 × 16 block of pixels.
Subsampled.

Referring to FIG. 29, the structure and function of the start code detector should be clear. The value register 221 receives the image data via the line 222. The width of line 222 is 8 bits, allowing parallel transmission of 8 bits at a time. The output from value register 222 is output via line 223
The data is supplied to the decode register 224 in series. The first output from decode register 224 is provided to detector 225 via line 226. Line 226 is 24 bits wide, allowing for 24 bits of parallel transmission at a time. Detector 225 detects the presence or absence of an image corresponding to a start code independent of the 23 "zero" value standard followed by one "1" value. The 8-bit data value image follows the valid start code image. When the presence of the start code image is detected, the detector 225 transmits the start image to the value decoder 228 via the line 227.

The second output from decode register 224 is provided in series to value decode shift register 230 via line 229. The value decode shift register 230 can hold one data value image having a bit length of 15. Partial area 23
As indicated by 1, the 8-bit data value following the start code image is shifted to the right of the value decode shift register 230. As discussed below, this process eliminates duplication of start code images. A first output from the value decode shift register 230 is via line 232
The value is supplied to the value decoder 228. Line 232 is 15 bits wide, allowing for a parallel transmission of 15 bits at a time. The value decoder 228 decodes the value image using a first lookup table (not shown). Value decode shift register 23
The second output from 0 is provided via a line 235 to a value decoder 228 which provides a flag to the index / token converter 234. In addition, the value decoder 228 provides an index /
The information is supplied to the token converter 234. Information is
Either a data value image obtained from the first lookup table or a start code index image. The flag indicates the form to which the information is supplied. Line 236 is 15 bits wide,
Enables 15 bit parallel transmission at a time. In the present invention, 15 bits were selected as the width in this case, but it should be understood that bits of other lengths could be used. Index / token converter 234 is provided in Table 12-3 of the user's manual.
The information is converted into a token image using a second lookup table (not shown) similar to the lookup table obtained. Index / Tokens Converter 23
The token image generated by line 4 is line 23
7 is output. The width of the line 237 is 15 bits, and parallel transmission of 15 bits at a time is possible.

In FIG. 30, a data stream 241 consisting of individual bits 242 is input to a start code detector (not shown in FIG. 30). The first start code image 243 is detected by a start code detector. Next, the start code detector receives the first data value image 244. Prior to processing the first data value image 244, the start code detector detects that the second start code image 24 that overlaps the first data value image 244 in length 246.
5 could be detected. When this occurs, the start code detector does not process the first data value image 244, and instead receives and processes the second data value image 247.

Referring to FIG. 31, flag generator 251 includes:
Data is received via line 252 as a first input. Line 252 is 15 bits wide, 15 bits at a time.
Enables parallel transmission of bits. Similarly, flag generator 251 receives the flag as a second input via line 253 and receives an input valid image via a first two-wire interface 254. A first output from the flag generator 251 is provided via a line 255 to an input valid register (not shown). The second output from flag generator 521 is provided via line 256 to decode index 257. The decode index 257 produces the following four outputs.
That is, the picture start image is output via line 258, and the picture number image is output via line 259.
And the insert image is output on line 260
, And the replacement image is output via line 261. Data from the flag generator 251 is provided via line 262a. The header generator 263 uses a look-up table to generate a replacement image, which is provided via 262b. The extra word generator 264 outputs the MP to generate the insert image.
Using U, the insert image is provided via line 262c. Line 262a connects to output latch 265
To form the first input to the 262 line. Output latch 265 outputs data via line 266. Line 266 is 15 bits wide,
Enables 15 bit parallel transmission at a time.

An input valid register (not shown) provides the image as a first input to first OR gate 267 via line 268. The insert image is provided via line 269 as a second input to first OR gate 267. The output from the first OR gate 267 is provided via line 271 as a first input to a first AND gate 270. The logical negation of the remove image is provided via line 272 to the first AND gate 27
0 as the second input to line 273
, As a second input to the output latch 265. Output latch 265 provides an output valid image via a second two-wire interface 274. The output accept image is the second two-wire interface 2
Via 74, it is received by the output accept latch 275. The output from the output accept latch 275 is
An output accept register (not shown) is provided via line 276.

Output Accept Register (not shown)
Is connected via a line 278 to the second OR
The image is supplied to the gate 277. The logical negation of the output from the input valid register is provided via line 279 to the second
It is provided as a second input to OR gate 277. The removed image is provided via line 280 as a third input to a second OR gate 277. The output from the second OR gate 277 is sent to the second
Provided as a first input to ND gate 281. The logical negation of the insert image is via line 283:
It is provided as a second input to a second AND gate 281. The output from the second AND gate 281 is
4 to the input accept latch 285. The output from the input accept latch 285 is provided via a first two-wire interface 254. Table 600 Format Received Image Token 1 H. H.261 Sequence start Sequence start MPEG picture start Group start JPEG None Picture start Picture data 2H. 261 None Picture end MPEG None Padding JPEG None Flash stop after picture As shown in Table 600 showing the relationship between the presence and absence of a standard signal in a specific machine independent control token, image detection by the start code detector 51 Generates a series of machine independent control tokens. Each image listed in the "Received Images" column starts generating all machine independent control tokens listed in the group in the "Generated Token" column. As shown in the first row of Table 600, H.264. "Sequence start" during 261 processing period
Whenever an image is received or a "picture start" image is received during PEC processing, a full group of four control tokens is generated, each with its corresponding one or more data. Followed by value. Further, as shown in the second row of table 600, a second group of four control tokens is generated at the appropriate time regardless of the image received by start code detector 51. Table 601 Display Order I1 B2 B3 P4 B5 B6 P7 B8 B9 I10 Transmission Order I1 P4 B2 B3 P7 B5 B6 I10 B8 B9 One row of the table 601 showing the timing relationship between the transmitted picture and the displayed picture. Thus, picture frames are displayed in numerical order. However,
The frames are transmitted in a different order to reduce the number of frames that must be stored in memory. It is beneficial to start the analysis with intra-frames (I-frames). The I1 frames are transmitted in the order in which they are to be displayed. Next, the next predicted frame (P frame) P4 is transmitted. Next, any bidirectionally interpolated frames (B frames) to be displayed between the I1 and P4 frames are transmitted. These frames are represented by frames B2 and B3. This allows a transmitted B frame to refer to a previous frame (forward prediction) or a future frame (backward prediction).
After transmitting all B frames to be displayed between the I1 and P4 frames, the next P frame, P7, is transmitted. Next, all B frames corresponding to B5 and B6 to be displayed between the P4 and P7 frames are transmitted. Next, the next I frame 110 is transmitted. Finally, P7 and 1
All B frames corresponding to frames B8 and B9 to be displayed between 10 frames are transmitted. Transmitting frames in this order requires that only two frames be held in memory at any one time, and the transmission of the next P or I frame to display intermediate B frames. It does not require the decoder to wait.

Further information regarding the structure and operation of the present invention, as well as features, objects, and advantages, may be found at:
Persons of ordinary skill in the art should become readily apparent from the additional, detailed description of exemplary embodiments of the invention. The details are summarized in the following sections for clarity and convenience.

[0273] 1. 1. Multi-standard configuration JPEG still image of the decrypted 3. 3. Decompression of video RAM memory map 5. 5. Characteristics of bit stream 6. Reconfigurable processing stage 7. Multi-standard coding 8. Multi-standard processing circuit-second operation mode Start code detector 10. Token 11. DRAM interface 12. Prediction filter 13. Accessing register 14. Microprocessor interface (MPI) 15. MPI read timing 16. MPI write timing 17. Keyhole address location Picture end 19. Flushing operation 20. Flash function 21. Stop after picture 22. Multi-standard search mode 23. Reverse modeler 24. Inverse quantizer 25. Huffman decoder and parser
(Syntax analysis system) Various discrete cosine transformers 27. Buffer manager Multi-Standard Configuration As shown in the aforementioned US Pat. No. 5,212,742, various compression standards, ie, JPEG, MPEG,
And H. Since H.261 is well known, detailed specifications of these standards will not be repeated here.

As mentioned earlier, the present invention is capable of decompressing differently coded different picture data bit streams. Different coding standards deal with the data supplied to the output of the spatial decoder operating alone or to the serial output of the spatial decoder and the temporal decoder operating in combination (as will be explained in more detail subsequently). ) And reformulating this output for use with displays on computers or other display systems, including video display systems, requires a somewhat regulated form of output formatting. The manner in which this formatting is accomplished varies widely between coding standards and / or selected display types.

In the first embodiment according to the present invention,
As previously described with respect to FIGS. 17-19, a block of formatted data, ie, a first decoder (spatial decoder) or a first decoder (spatial decoder) and a second decoder (temporal decoder) ) And write the decrypted information to memory in raster order, and / or
Alternatively, an address generator is used for writing.
The video formatter described below provides a wide range of output signal combinations.

[0276] In the preferred multi-standard video decoder embodiment of the present invention, the spatial decoder and the temporal decoder comprise an MPEG coded signal and an H.264 video signal. 261 video encoding and decoding system. The DRAM interface of both of these devices uses a small picture format and can be configured to reduce the amount of DRAM needed when operating at low coded data rates. The reconfiguration of these DRAMs will be further described below in connection with the DRAM interface. Generally, one single 4 megabyte DRAM is required for each temporal and spatial decoder circuit.

The current spatial decoder performs all the required processing within one single picture. This reduces the redundancy within one picture.

The temporal decoder reduces the redundancy between the main picture related to the picture arriving before the main picture arrives and the picture arriving after the main picture arrives. . One aspect of the temporal decoder is to address the complex address functions required to read all these picture and related data using as few circuits as possible and with high speed and improved accuracy. The purpose is to provide a decoding network.

As previously described with respect to FIG. 18, the data consists of a start code detector preceding the Huffman decoder and parser, a FIFO, a second FIFO register, an inverse modeler, an inverse quantizer, an inverse zigzag and an inverse DCT.
Arriving through. The two FIFOs need not be located on the chip. In one embodiment, data does not flow through a FIFO located on the chip. The data is D
Supplied to RAM interface and FIFO
-IN storage register and FIFO- OUT register
In both cases, it is located off-chip. These registers, whose operation is completely independent of the standard, will be described in more detail subsequently.

The majority of the subsystems and stages shown in FIG. 18 are actually independent of the particular standard used, and
Includes a buffer manager 59 that generates addresses for the interface, an inverse modeler 75, an inverse zigzag 8l, and an inverse DCT 83. Standard independent units in the Huffman decoder and parser include ALU 66 and token formatting unit 71.

In FIG. 19, units independent of the standard include a DRAM interface 100 and a fork 9
1, a FIFO register 96, an adder 98, and an output selector 106 are included. The standard dependent unit is H.264. 26
Address generator 94, which differs between H.1 and MPEC; The prediction filter 103 can be reconfigured to conform to both H.261 and MPEG. JPEG data is
It flows through the whole machine, which is not changed at all.

FIG. 20 shows a high-level block diagram of the moving image formatting unit chip. Most parts of this chip are standard independent. The few items affected by the standard are H.264, which differs from MPEG or JPEG. In the case of H.261, data is written in the DRAM. In H.261, it is not necessary to code every single picture. There is some timing information that provides some information as to when the picture is intended to be displayed and is also referred to as a time reference that is also handled by the address generation type of the logic in the video formatting unit.

The remainder of the circuitry embodied in the video formatting section includes all of the color space conversion, all of the upsampling filters, and all of the gamma correction RAM, and is completely independent of the particular compression standard used. I have.

The start code detector of the present invention relies on a compression standard, in which the detector must recognize various different start code patterns in the bitstream for each of the standards. . For example, H. 261 has a 16-bit start code, MPEC has a 24-bit start code, and JPEG uses a marker code that is significantly different from other start codes. Once the start code detector recognizes these different start codes, its operation is essentially independent of the compression standard. For example, apart from circuitry that recognizes various different categories of markers, many of the operations are very similar between the three different compression standards.

The following unit is a state machine 518 (FIG. 1) located in the Huffman decoder and parser.
8). In this case, the actual circuit configuration is almost the same for each of the three compression standards. In fact, the only element affected by the standard in operation is the reset address of the machine. If the parser is simply reset, the parser will jump to a different address for each standard. In fact, there are four recognized standards. These standards are described in H.264. 261, JP
EG, MPEG, and one other standard, in the case of the last standard, the parser enters one code used for testing. The fact is that the circuit is the same in almost all aspects, only the microcode program for each standard is different. Therefore, one program is H.264. 261 and another different program is running,
There is no overlap between these programs. This is JP
The EG is also true, a third completely independent program.

The following unit is a Huffman decoder 56 which functions together with the data index unit 64. These two units work together to perform Huffman decoding. In this case, the algorithm used for Huffman decoding is the same regardless of the compression standard. The changes are which table is used and whether the data coming into the Huffman decoder is inverted. In addition, the Huffman decoder itself includes a state machine that understands some aspects of the coding standard. These different operations are selected in response to incoming instructions from the parser state machine. The parser state machine operates by a different program for each of the three compression standards,
And at different points in time to meet the operating standards,
Supply the correct instruction to the Huffman decoder.

[0287] The last unit on the chip that depends on the compression standard is the inverse quantizer 79, in which the mathematics performed by the inverse quantizer is different for each of the different standards. At this time, the coding standard token is decoded, and the inverse quantizer 79 stores under which standard it is operating. Next, any subsequent data tokens that occur after the event and may occur before other coding standards are handled in the manner indicated by the coding standard stored in the inverse quantizer. The tables referred to in the detailed description indicate different parameters in different standards and indicate which circuits correspond to these different parameters or mathematics.

H. 261 based on the address generation shown in FIG.
9 and not for each subsystem shown in FIG. 2 before or after the Huffman decoder shown in FIG.
The address generation method for generating an address for one FIFO does not change according to the coding standard. H. 261
In this case, the address generation occurring on the chip does not change. Essentially, the difference between these standards is M
The difference between PEG and JPEG, where the organization of macroblocks is arranged in linear rows that extend horizontally across the picture. As shown in FIG. 21, the first macroblock A
Covers one line. Macroblock B covers less than one row. Macroblock C covers multiple rows. M
In PEG, it is divided into slices and one slice may be one horizontal row A, one slice may be part of horizontal row B, or one slice If extending from one row to the next, C is also possible. Each of these slices is composed of a sequence of macroblocks.

H. In the case of H.261, the pictures are divided into groups of blocks (GOB), so the organization is somewhat different. A group of blocks corresponds to a macroblock with three columns in height and a width of 11 macroblocks. In the case of CIP pictures, there are 12 such block groups. However, it is not organized like one over the other. Rather, groups of six blocks in height are arranged in two groups before and after. That is, 6 GOBs and 2 GOBs are arranged vertically.

In all other standards, when addressing is performed, macroblocks are addressed sequentially, as already indicated. More specifically, the address proceeds along a row, and at the end of the row, the next row is started. H. In the case of H.261, the order of the blocks is the same as the order described within the group of blocks, but when moving to the next block group it is almost zigzag.

The present invention provides a circuit for handling the above effects. It addresses the generation of addresses in the spatial decoder and the video formatting section according to H.264. 261. This is accomplished whenever information is written to the DRAM. Since it is filled in with the knowledge about the above-mentioned address generation sequence, the location where it is physically located in the RAM is the same size of MPEG
Exactly the same as for pictures. Therefore, since the physical arrangement of the information in the memory is the same as that in the case of the MPEG sequence, all the address generation circuits for reading from the DRAM, for example, when forming predictions, use H.264. It is not necessary to understand that this is the case for the H.261 standard. Thus, in all cases, only data entry is affected.

In a temporal decoder, the circuit appears to be something different from what is actually occurring. 2
Abstraction is performed on 61. That is, each group of blocks is conceptually expanded so that instead of a rectangle being an 11 × 3 macroblock, the macroblock is
It is extended to a block group having a height of one macroblock and a length of 33 blocks (FIG. 23). In this way, exactly the same counting technique used in the temporal decoder to count through a group of blocks is used for MPFG.

H. of the block 261 group and MPEG
The circuit is designed so that there is a match between the slices. H. After the start code detector. When 261 data is processed, each block group is preceded by a slice start code. The next block group is preceded by the next slice start code. If counting is done in the temporal decoder to count through this structure, it looks as if it is a group of one macroblock in height and 33 macroblocks in length. Similarly, the circuit counts every 10 intervals, which is sufficient. When the eleventh macroblock or the twenty-second macroblock is counted, some counters are reset. This is accomplished by a simple circuit with another counter that counts up each macroblock and, when it reaches 11, resets to zero. The microcode interrogates it and performs its actions. All circuits in the temporal decoder of the present invention are essentially independent of the compression standard with respect to the physical arrangement of macroblocks.

There are a number of different tables for multi-standard adaptability, and the circuit selects the appropriate table to apply the appropriate standard at the appropriate time. Each standard has multiple tables, and the circuit selects from the set of tables at any given time. Within any one standard, the circuit selects one table at a time and another at another time. Within different standards, the circuit selects a different set of tables. As pointed out earlier in the discussion of FIG. 24, there is some intersection between these tables. For example, one of the tables used for MPEG is used for JPEG as well. These tables are not completely separate sets. FIG. 26
One set, an MPEG set, and a JPEG set are shown. H.
Note that there is a very large overlap between the H.261 set and the MPEG set. The tables used by these standards are quite common. There is a slight overlap between MPEG and JPEG; Since there is no overlap between H.261 and JPEG, these standards have a completely different set of tables.

As noted above, most system units are independent of the compression standard. If a unit is standard independent, this type of unit:
There is no need to remember which coding standard is being processed. All standard-dependent units remember the compression standard as the coding standard token flows through these units. First
The information encoded / decoded in the encoding standard is distributed throughout the machine, and if the machine is changing standards, the machine before being microprocessor-controlled is generally H.264. 261 compression standard. MPU in this kind of previous machine
Generates signals at a number of different locations in the machine where the compression standard is changing. The MPU makes changes at different times and flushes throughout the pipeline.

According to the present invention, the first in the pipeline
This change in the compression standard can be easily handled by causing a change in the coding standard token in a start code detector arranged as a unit of the compression code. The token indicates that a coding standard is being launched, and the control information is:
The machine flows downstream, and configures all other registers at the appropriate time. The MPU does not need to program each register.

The prediction token tells how to use the bits in the bitstream to form a prediction. Depending on which compression standard is in operation, the circuit converts information found in that standard from a bitstream to a prediction mode token. This processing is performed by a Huffman decoder and a parser state machine. In this case, it is easy to manipulate bits based on specific conditions.
The start code detector generates this prediction mode token. Next, the token goes down the machine,
It flows to the circuit of the time decoder, which is the device responsible for forming the prediction. Since the bits in one standard do not change in three different standards, the circuitry of the spatial decoder interprets the token without knowing which standard the standard operates in. The spatial decoder does only what was said in response to the token. Owning these tokens and using them properly simplifies the design of other units in the machine. The program can be somewhat complicated, but the advantage is that hardwire logic, which is difficult to design for multiple standards, can be used in this case.

[0298] 2. JPEG Still Image Decoding As noted earlier, the present invention relates to signal decompression, and more particularly, to decompression of coded video signals independent of the compression standard used.

One embodiment of the present invention relates to a method for processing a first encoded signal (MPE) in a pipeline processing system.
G or H. 261 encoded video signal) and a first encoded signal (JPEG encoded video signal) in combination with a second decoder circuit (temporal decoder) for decoding.
Is to provide a first decoder circuit (spatial decoder) for decoding. No temporal decoder is required for JPEG code decoding.

In this regard, the present invention facilitates the decompression of multiple signals encoded in different ways by using one single pipeline decoder and decompression system. The codec decoding and decompression pipeline processor is a special configuration that allows the handling of multi-standard coded video signals using technology that is unique and fully compatible with single pipeline decoders and processing systems. It is organized in. The spatial decoder is combined with the temporal decoder, and the video formatter is used to drive the video display.

Another aspect of the present invention is to use a combination of a spatial decoder and a moving image formatting unit for use with still images only. A spatial decoder independent of the compression standard performs all data processing within the boundaries of one single picture. This type of decoder
The spatial expansion of the internal picture data that passes through the pipeline and is allocated in a standard independent address generation circuit for handling the storage and retrieval of information to and from the associated constant speed call storage, memory deal with. Still image data is decoded at the output of the spatial decoder, and this output is used as an input to a multi-standard configurable video formatting unit that provides output to a display terminal. In a first sequence of similar images,
Until the image reaches the output of the spatial decoder, each decompressed image at the output of the spatial decoder is the same bit length. The second sequence of images can be of a completely different image size, and thus can have a different length when compared to the first length. Again, until such a picture reaches the output of the spatial decoder, all such second sequences of similar pictures have the same bit length.

Another aspect of the present invention is a method for selecting and organizing an incoming standard-dependent bitstream to operate as a standard-independent, reconfigurable pipeline processor, and arranged in an ordered arrangement. Internally organized into a series of control and data tokens combined with multiple possible processing stages.

Regarding JPEG decoding, DRA outside the chip
One single spatial decoder without M can rapidly decode the baseline JPEG image. The spatial decoder supports all the functions of the baseline JPEG coding standard. However, the image size that can be decoded may be limited by the size of the installed output buffer. The spatial decoder circuit includes a constant speed call storage circuit having a machine dependent, standard independent address generation circuit for handling the storage of information in memory.

As already pointed out, a temporal decoder is not required to decode a JPEG-encoded video. Therefore, the signal carried by the data token is
If a temporal decoder is configured for JPEG operation, it is fed directly through the temporal decoder without further processing.

Another embodiment of the present invention relates to a Huffman decoder /
Providing a pair of memory circuits, such as buffer memory circuits, for example, in a spatial decoder, to operate in conjunction with a video demultiplexer circuit (HD & VDM). , The first buffer storage device is HD & V
Placed before the DM, and the second buffer is
It is located after HD & VDA. KD & VDM
Decodes a bit stream consisting of binary ones and zeros. These numbers are located in the standard encoded bit stream, and the bit stream is
Convert to numbers used downstream. An advantage of a two-buffer system is that it can be used to implement a multiple decompression system. For these two buffers,
This will be described in detail below in combination with the validated embodiment of the Huffman decoder.

A further aspect of the present multi-standard decompression circuit is that it is combined with a start code detector circuit located upstream of a first forward buffer that operates in combination with a Huffman decoder. One advantage of this combination is that it increases the flexibility that must be added to the bitstream when dealing with the input bitstream, especially padding. Placing these verified components, start code detector, memory buffer, and Huffman decoder enhances the handling of specific sequences in the input bitstream.
Further, the off-chip DRAM is used to decode a JPEG encoded moving image in real time.
The size and speed of the buffers used with DRAM
Depends on the video encoded data rate.

The coding standard identifies all information of the standard-dependent type required to be stored in the DRAM associated with the spatial decoder using circuits independent of the standard.

[0308] 3. Moving Picture Decompression In the present invention, when a moving picture is being decompressed through a decoding process, a temporal decoder is further required. The temporal decoder combines the data decoded in the spatial decoder with an already decoded image intended to be displayed after the picture image currently being decoded. The temporal decoder receives information for identifying the temporally replaced information in the image encoded data stream. The temporal decoder addresses the temporally and spatially arranged information, retrieves the information, is currently being decoded and completes, and transmits it to the video formatter to drive the display screen The information is combined in such a way as to decode the information arranged in one image using an image that ends the resulting image suitable for.
Alternatively, the resulting image can be stored for later use for temporal decoding of subsequent images.

In general, a temporal decoder performs inter-picture processing either early and / or late on the picture currently being decoded. The temporal decoder reintroduces uncoded information into the coded representation of the image. The reason is that the information is redundant and is already available at the decoder. More specifically, any given image can include similar information, both temporally surrounding the information both before and after. This similarity can be further increased if motion compensation is applied. Temporal decoders and decompression circuits also reduce redundancy between related pictures.

[0310] In another aspect of the invention, a temporal decoder is used to handle standard-dependent output information from a spatial decoder. This standard-dependent information for one single image is such that the decompressed output information processed by the spatial decoder is a spatially decoded image information temporally arranged with respect to the temporal position of the first image. In order to combine one image of the spatially decoded information packet of the other D.I.D. by another constant speed paging storage device having yet another machine dependent and standard independent address generation circuit.
In such a way as to be stored in a RAM register, DR
It is distributed among several areas of the AM.

In a multiplex standard circuit capable of decoding an MPEG-encoded signal, a larger logical D
The RAM buffer may be required to support a larger image format compatible with MPEG.

Image information is moving through a serial pipeline in an 8 pixel × 8 pixel block. In one form of the invention, the address decoding circuit handles (stores and retrieves) these pixel blocks along block boundaries. In addition, the address decoding circuit handles the storage and retrieval of 8.times.8 pixel blocks across boundaries. This versatility will be described more fully below.

Similarly, the second temporal decoder may directly supply the output of the first decoder circuit (spatial decoder) to the moving picture formatting unit in order to handle the signal without delay in signal processing.

Further, the temporal decoder reorders the blocks of image data for delays caused by the display circuit. As will be explained later, the address decoding circuit makes this reordering possible.

As already mentioned, one important feature of the temporal decoder is that it sums image information that arrives earlier or later than the current image from the image selection.

In describing a picture in this context, a picture means any of the following contents.

[0317] 1. 5 is an encoded data representation of a picture.

[0318] 2. The result, that is, the final decoded picture resulting from adding the process steps performed by the decoder.

[0319] 3. This is a decoded picture already read from the DRAM.

[0320] 4. It is the result of spatial decoding. That is, the data range between the picture start token and the next picture end token.

After the picture data information has been processed by the temporal decoder, the information is displayed in a picture storage location or written back. This information is then retained as a further reference used in processing another different encoded data picture. For rearrangement of MPEG encoded pictures for visual display, the required scrambled pictures are:
Includes the abilities achieved by changing the reordering function of the temporal decoder.

[0332] 4. RAM Memory Map The spatial decoder, the temporal decoder, and the video formatting unit all use an external DRAM. Preferably, the same DRAM is used for all three devices. Even if all three devices use DRAM and all three devices use a DRAM interface with an address generator,
What each implements in a DRAM is not the same. That is, each chip, for example, a spatial decoder and a temporal decoder, have different DRAM interfaces and address generation circuits even when using the same physical external DRAM.

In short, the spatial decoder is a common DRAM
Implements two FIFOs within. Referring to FIG. 18 again, one FIFO 54 has a Huffman decoder 5
6 and before the parser, and the other is after the Huffman decoder and parser. FIFO
Is implemented in a relatively straightforward manner. A special part of the DRAM is that for each FIFO there is a FIFO in it.
Is deducted as physical memory for implementing

Spatial decoder DRAM interface 5
The address generator associated with 8 uses two pointers to keep track of the FIFO address. 1
One pointer points to the first word stored in the FIFO, and the other pointer points to the last word stored in the FIFO. Therefore, a read / write operation to a predetermined word is enabled. If the end of the physical memory is reached during the course of a read or write operation, the address generator "wraps around" to the start of the physical memory.

In short, no matter what coding standard (MPEG or H.261) is specified, the temporal decoder according to the present invention must be able to store two complete pictures or frames. For the sake of simplicity, D is to store two frames in it.
The physical memory of the RAM shall be divided into two halves, each half dedicated (with appropriate pointers) to a particular one of the two pictures.

MPEG uses three different types of pictures: intra (I), prediction (P), and bidirectional interpolation (B). As already mentioned, a B picture is based on prediction from two pictures. One picture comes from the future, and the other comes from the past. I-pictures do not require further decoding by the temporal decoder, but must be stored in one of the two picture buffers for later use in decoding P and B pictures. Must. Decoding a P picture requires forming a prediction from already decoded P or I pictures. The decoded P picture is used for decoding P and B pictures.
Stored in one picture. B pictures can require prediction from both picture buffers. However, the B picture is stored in the external DRAM.

When I and P pictures are decoded,
Note that it is not output from the temporal decoder. Instead, the I and P pictures are stored in one of the picture buffers.
And the next I or P picture is read only if it arrives for decoding. In other words, as described further below in this section on flushing, the temporal decoder relies on the next P or I picture to flush the previous picture from the two picture buffers. In short, the spatial decoder can provide a false I or P at the end of a video sequence to flush a P or I picture. Consequently, when the next video sequence starts, this fake picture is flashed. Upon decoding a B picture, a load of peak memory bandwidth occurs. The worst case is when all predictions are made with half-pixel accuracy and a B-frame is formed from this type of prediction supplied from both picture buffers.

As previously described, the temporal decoder is:
It can be configured to provide reordering of MPEG pictures. This picture re-ordering allows the P and I to stay until the decoding of the next P or I picture in the data stream by the temporal decoder starts.
The output of the picture is delayed.

When a P or I picture is reordered, a particular token is temporarily stored on the chip as the picture is placed in the picture buffer. When the picture is read for display, these stored tokens are retrieved. At the output of the temporal decoder, the data token of the newly decoded P or I picture is exchanged for an older P or I picture.

On the other hand, H. H.261 produces predictions only from the pictures just decoded. As each picture is decoded, it is filled into one of the two picture buffers and is available for the next picture decoding. The only DRAM memory operation required is 8x
Writing eight blocks and forming predictions with motion vectors with integer precision.

In short, the moving image formatting section
Store three frames or pictures. 3 to accommodate functions such as repeating or skipping pictures
One picture needs to be stored.

[0332] 5. With particular reference to the spatial decoder according to the invention,
It is useful to review the bitstream characteristics of the encoded data stream. The reason is that these properties must be handled by the spatial and temporal decoder circuits. For example, under one or more compression standards, the compression ratio of the standard is achieved by changing the number of bits used to encode multiple pictures of a picture. The number of bits can vary over a wide range. In particular, this means that the length of the bitstream used to encode the reference picture of one picture can be identified as one unit length, while the other pictures have the length of multiple units. However, the third picture may be a part of the unit.

The current standards (MPEG1.2, JPEG,
H. 261) does not define how to end the picture image, and it is implied that when the next picture starts, the current picture ends. In addition, the standards (particularly H.261) allow imperfect pictures to be generated by the encoder.

In accordance with the present invention, there is provided a method for indicating the end of a picture by using one picture end of the token. Still encoded data away from the Start code detector started by the picture-start token and is terminated by picture-end token consists picture varying in length considerably. There may be other information transmitted here (between the first and second pictures), but it is known that the first picture has ended.

The data stream at the output of the spatial decoder has the same length (number of bits) for a given sequence and still consists of picture start and picture end pictures. The length of time between picture start and picture end can vary.

The video formatting unit receives these pictures which are non-uniform in time and displays them on the screen at a fixed picture rate determined by the type of display being driven. Different display rates are used worldwide, such as the PAL-NTSC television standard. This, in a unique way, is achieved by selectively dropping or repeating the pin <br/> puncturing. Normal "frame rate converters", e.g., 2-3 pulldown, operate with a fixed input picture rate, but the video formatting unit can handle variable input picture rates.

[0337] 6. Reconfigurable Processing Stage Referring again to FIG. 17, a reconfigurable processing stage (RPS) includes a two-wire interface 33 and a token decode circuit 32 used to receive incoming tokens from an input latch 34. Having. The output of the token decode circuit 33 is a two-wire interface 36
And, it is supplied to the processing circuit 35 via the action identification circuit 39. The processing circuit 35 is suitable for data processing under the control of the action identification circuit. After the processing is completed, the processing circuit 36 connects the completed signal to the output of the two-wire interface bus 40 via the output latch 41.

The action identification decode circuit 39 is supplied from the token decode circuit 33 via the two-wire interface bus 40 and / or is supplied from the memory circuits 43 and 44 via the two-wire interface bus 46, respectively. Has input. The token from the token decode circuit 33 is supplied to the action identification circuit 39 and the processing circuit 36 at the same time. The action identification function as well as the RPS will be described in more detail in the next part of the specification using tables and figures.

The functional block diagram in FIG. 17 shows stages that are not circuits independent of the standards described in FIGS. 18, 19, and 20. The data flow is passed to the processing stage 35 via the token decoder 32.
Through the output latch 41 to the two-wire interface circuit 42. If the control token is recognized by the RPS, it is decoded in the token decode circuit 33, and an appropriate action is performed. If it is not recognized, 2
The signal is supplied to the line interface circuit 42 without change. The present invention functions as a pipeline processor with a two-wire interface circuit for controlling the movement of control tokens through the pipeline. This feature of the present invention has been disclosed in further detail in previously filed European Patent Application No. 923036038.8.

In the present invention, the token decode circuit 3
3 is used to identify whether the token currently arriving via the two-wire interface 42 is a data token or a control token. If it is recognized that the token is being examined by the token decoder circuit 33, it is output to the action identification circuit 39 by an appropriate index or flag signal indicating the action to be performed. At the same time, the token decode circuit 33 supplies an appropriate flag or index signal to the processing circuit, and warns the processing circuit of the presence of the token being handled by the action identification circuit 39. Control tokens can be processed in a similar manner.

The various types of tokens that can be used in the present invention are described in further detail below. For this part of the specification it is sufficient to note that the address carried by the control token is decoded in the decoder 33 and is used to access the registers contained in the action identification circuit 39. . If the token being examined is a recognized control token, action identification circuit 39 uses its reconfigured state circuit to distribute control signals throughout the state machine. As already mentioned, this activates the state machine of the action identification decoder, which reconfigures itself. For example, the decoder may change the coding standard. In this way, the action identification circuit 39 decodes a required action for handling a specific standard being supplied via the state machine shown in FIG.

Similarly, processing circuit 36, controlled by action identification circuit 39, is ready to process the information contained in the data field of the data token when appropriate to cause this event. In many cases, the control token arrives first, reconfigures the action identification circuit 39, and then immediately follows the data token processed by the processing circuit 36. The control token exits the output latch circuit 41 via the output two-wire interface 42 which immediately precedes the processed data token in the processing unit 36.

In the present invention, the action identification circuit 39
Is a state machine that holds a history state. Registers 43 and 44 hold the information decoded from token decoder 33 and stored in these registers. This type of register can be either on-chip or off-chip as required. These state registers contain the action information that is currently being identified in the action identification circuit 39 connected to the action identification. This action information is stored from the previously decrypted token and can influence the selected action. Connection 40 connects linearly from token decode 33 to action identification block 39. this is,
It is intended to indicate that the action can also be affected by the token currently being processed by the token decode circuit 33.

[0344] The token decryption and data processing according to the present invention will be described. The data processing is performed by the action identification circuit 39.
It is performed as constituted by. Actions are affected by a number of conditions and by information obtained entirely from already decrypted tokens, or more particularly, from registers already decrypted tokens in registers 43 and 44. Information, the current token being processed, and the state and history information that the action identification unit 39 has acquired on its own. This indicates the distinction between control tokens and data tokens.

In every RPS, some tokens are seen by the RPS unit as control tokens. In this case, these tokens should affect the operation of the RPS at some later point. Another set of tokens is seen by RPS as data tokens. Such data tokens include information processed by the RPS in a manner as determined by the particular circuit design, already decoded tokens, and the state of the action identification unit 39.

A particular RPS identifies a particular set of tokens for a particular RPS control and another set of tokens as data, which is a view of that particular RPS. Another PPS may have another different view for the same token. On the one hand, some tokens can be viewed as data tokens by one RPS unit, and on the other hand, determined by another RPS unit to be actually control tokens. For example, the quantization table information is data at least as far as the Huffman decoder and the state machine are concerned. The reason is that the information arrives at its input as coded data, which is formatted into a series of 8-bit words,
Then, it is formed into a token called a quantization table token (QUANT table) that moves downstream in the processing pipeline. As far as the machine is concerned, all the information would have been data, and that information was handling data, converting one type of data to another, which was clearly Is a processing function performed by the relevant part. However,
When the information reaches the inverse quantizer, the inverse quantizer stores the information in the token, which is a plurality of registers. In fact, since there are 64 8-bit numbers and there are many registers, there will generally be many registers .
May be. This information is considered as control information, and thus affects the processing performed on the next data token, as the information affects the number by which each data word is multiplied. In some instances, one stage considers the token to be data and another stage considers the token to be control.

The token data according to the present invention is almost always considered to be data passing through a machine. One important aspect is that generally each stage of the circuit with a token decoder is looking for a particular set of tokens, and tokens that the stage does not recognize will pass through the stages unchanged, and Moving down the pipeline. As a result, there is the advantage that downstream stages that follow the current stage see these tokens and can respond to these tokens. This is an important feature. That is, communication between blocks is possible by using the token mechanism for non-adjacent blocks.

Another important feature of the present invention is that each stage of the circuit has the processing power to the extent that it can perform the operations required for each standard, and must be performed at any given time. The ability to perform control as a token on operations that must be performed. To provide this capability, there is one processing element that differs between the different stages. In the parser state machine ROM, there are three completely different, separate programs. Each program corresponds to each standard handled. Which program is executed depends on the coding standard token.
In other words, each of these three programs has the ability to handle both decoding and coding standard tokens within it. If each of these programs understands which coding standard is to be interpreted next, they will literally jump to the start address for that program in the microcode ROM. This is how the stage handles multiple standards.

Two things are affected by different standards
You. First, the length of the start marker code is detected.
Bitstream to reconfigure the shift register for
Which pattern of bits in the system
Is recognized as a marker code. No.
2. What does the start or marker code mean?
One piece of information that indicates the location is in the microcodeYou
You. Bit encoding differs between the three standards.
I want to be remembered. Therefore, the microcode
In tables specific to Pressa standards,
What is standing, that is, the token
See Ip. In most cases, each of the various standards
It provides a specific code generated by the standard,
Tokens are generally independent of the standard.

[0350] The inverse quantizer 79 has a number physical capacity.
The quantizer performs multiplication and addition, and has the ability to implement all three compression standards configured by parameters. For example, a flag bit in the ROM in the controller tells the inverse quantizer whether to add a constant K. Another flag tells the dequantizer whether to add another constant. Inverse quantizer token stores coding standard token when, in registers supplied by the quantizer. If the data token subsequently passes, the inverse quantizer stores what the standard is and searches for the parameters that need to be supplied to the processing element for proper operation. For example, the inverse quantizer may set K to 0 for a particular compression standard, or
Alternatively, it is searched whether it is set to 1, and the result is supplied to the processing circuit. In a similar sense, the Huffman decoder 56 has a number of tables therein, some for JPEG and some for H.264. H.261, some of which are for MPEG. In fact, the majority of these tables serve one or more of these compression standards. Which table is used depends on the syntax of the standard. The Huffman decoder works by receiving a state machine or furnace command telling which table to use. Thus, the Huffman decoder does not itself have one state directly input to, stored in, and asserting what encoding is being performed. Rather, it is a combination of a parser state machine and a Huffman decoder that together contain the information in them.

With respect to the spatial decoder of the present invention, the address generation is modified and similar to the case shown in FIG. 17, where a lot of information is decoded from tokens, for example coding standards. Similarly, coding standards and additional information are recorded in registers, and affect the progression of the address generator state machine if the information passes through macroblocks in the system and counts one by one. . The last stage is two modes H. H.261, or MPEG, and is an easily identified prediction filter 407-9 (FIG. 26).

[0352] 7. Multi-standard encoding More particularly, a control token according to the invention has a plurality of words in the token. In this case, one bit, known as an extension bit, is set, specifying the use of an additional word in the token to carry additional information. Certain of these additional control bits include an index indicating information used to create a set of standard independent index signals in a corresponding state machine. The remainder of the token is used to indicate and identify internal processing control functions that are standard for all data streams passing through the pipeline processor.

In one form of the invention, token extension is used to hold the current encoding standard that is decoded by relative token decoding circuits distributed throughout the machine. And, and whenever it is appropriate to operate under the new coding standard, it is used to reconfigure the action identification circuit 39 of the machine-wide stage. In addition, the token encoding circuit can indicate whether the control token is relevant to one of the selected standards designed to handle the circuit.

More specifically, an MPEG start code,
And the JPEG marker are followed by an 8-bit value. H. The 261 start code is followed by a 4-bit value. In this context, the start code detector 5
A 1 indicates that the next 8 bits contain a value associated with the start code by detecting either the MPEG start code or the JPEG marker. Next, the detector is independently either an MPEG start code or a JPEG marker;
A signal indicating that the signal is not a H.261 start code can be generated. In this first case, the 8-bit value is input to a decoding circuit, and a portion of the decoding circuit creates signals indicating the indexes and flags used in the current circuit to handle tokens passing through the circuit. . This is also used to insert the portion of the control token that is subsequently referenced to determine which standard is being addressed. In this sense, the control token includes a part indicating that it is related to the MPEG standard, as well as a part indicating the type of operation that operates on the accompanying data. As already discussed,
This information is used in the system to reconfigure the processing stages used to perform the functions required by the various standards created for that purpose.

For example, H. Regarding the H.261 start code, this code immediately follows the start code.
Related to bit value. Start code detector
This value is provided to the token generator state machine. This value is supplied to an 8-bit decoder that creates a 3-bit start number. The start number is used to identify the picture start of the number of pictures as indicated by the value. In addition, the system is compatible with 2
Includes multiple parallel processing pipelines operating under the principle of a line interface. Each stage is generally shown in FIG.
Including machines in the form shown in The token decode stage 33 is used to derive a token that is causing the action identification circuit 39 or the processing unit 36 to appropriately enter a state machine. The processing unit has been reconfigured by the next previous control token to the form needed to handle the current coding standard, which is currently being entered into the processing stage and carried by the next data token. It is. Furthermore, in accordance with this aspect of the invention, a continuous state machine in the processing pipeline is a single encoding standard, namely
H. H.261, while the previous stage can operate under a proprietary standard, such as MPEG. The same two-wire interface is used to carry both control and data tokens.

In addition, the system of the present invention uses control tokens that are required to decode multiple coding standards with a fixed number of reconfigurable processing stages. More specifically, since it is important to indicate when a picture actually ends, a picture end control token is used. Therefore, when designing a multi-standard machine, it is necessary to create additional control tokens in the multi-standard pipeline that indicate which standard decoding technique to use. This type of control token is a picture end token. This picture end token is used to indicate that the current picture has ended, forcing the buffer to flush and pushing the current picture to the display through the decoder.

[0357] 8. Multi-standard processing circuit-second mode of operation The compression standard-dependent circuits in the form of the start code detectors already mentioned are suitably interconnected via appropriate buses to circuits independent of the compression standard. Standard dependent circuits are connected to dependent independent combinational circuits via the same bus and additional buses. Standard-independent circuits provide additional inputs to standard-dependent independent circuits, while standard-dependent independent circuits provide information back to standard-independent circuits. Information from the standard independent circuit is provided to the output via another suitable bus. Table 600 shows that the multiplex standard applied to the input to the standard dependent start code detector 51 includes a specific bit stream having a standard dependent meaning in each encoded bit stream.

[0358] 9. Start Code Detector As already mentioned, the start code detector according to the present invention comprises MPEG, JPEG and H.264. A series of ownership tokens that handle 261 bit streams and are significant to the rest of the decoder can be generated from the stream. As an example in which multi-standard decoding is achieved, MPEG (1, and 2) picture start codes, 261 picture start code and J
The PEG start of scan (SOS) marker is treated as equivalent by the start code detector, and
All of these generate an internal picture start token. In a similar manner, the MPEG sequence start code and the JPSG 501 (start of image) marker both generate a machine sequence start token. However, H. The H.261 standard does not have an equivalent start code. Therefore, the start code detector performs the first H.264. A sequence start token is generated in response to the H.261 picture start code.

[0359] None of the above-mentioned images are used directly except for the SCD. Rather, for example, a machine picture start token is considered to be equivalent to a picture start image included in the bitstream. In addition, we want to keep the following in mind: the machine picture start itself is
It is not a direct image of the start. Rather, it is a control token used in combination with other control tokens to provide a standard independent decoding function that emulates the operation of the image in each compression coding standard. The combination of the control token combined with the reconfiguration of the circuit based on the information carried by the control token, and furthermore, the combination with the index and / or flag generated by the token decoding circuit portion of each state machine is unique. is there. A typical reconfigurable state machine is described subsequently.

Referring again to Table 600, the left column shows the name of the standard image group.
In the right column, do not exist in the standard image,
Alternatively, a machine dependent control token used for emulation of an unused standard encoded signal is indicated.

In Table 600, as described above, when decoding any one of the standard signals described in Table 600, it can be seen that the machine sequence start signal is generated by a start code detector. The start code detector produces a sequence start, group start, sequence end, slice start, user data, extra data, and picture start token to feed a two-wire interface used throughout the system. . Each of these stages operating with these control tokens is constituted by the contents of the token or by an index created by the contents of the token, and
The picture data token is ready to handle data expected to be received when it arrives at the station.

As described above, for example, H.264. One compression standard, such as H.261, has no sequence image start in its data stream and no picture end image in its data stream. The start code detector detects a picture code in the incoming bit stream.
Indicates the endpoint and PICTUtZEEN
Make a D token. In this regard, the system of the present invention is intended to carry a data word that is fully packed to contain one bit of information at each register location selected for use in the implementation of the present invention. For this purpose, 15 bits were chosen as the number of bits supplied between the two start codes. Of course, those of ordinary skill in the art will appreciate that any selection of more or less than 15 bits can be made. In other words, it is required for proper operation that all data words supplied from the start code detector to the DRAM interface be 15 bits. Thus, the start code detector creates an extra bit called padding that is inserted into the last word of the data token. For illustrative purposes, 15 data bits were selected.

To perform a padding operation according to the present invention, a number of binary ones followed by two
The base 0 is automatically inserted to complete the 15-bit data word. This data is then provided through a coded data buffer and to a Huffman decoder that removes padding. Therefore,
Any number of bits can provide a fixed size and width buffer.

[0364] In one embodiment, a slice start control token is used to identify a slice of a picture. The slice start control token is used to divide a picture into smaller areas. The size of this region is selected by the encoder, and the start code detector may provide a slice start to the machine dependent state stage located downstream from the start code detector to divide the received picture into smaller regions. Identify this unique pattern of code. The size of the region is identified by the start code detector and selected by the encoder used by the recombining circuit and control token to decompress the encoded picture. The slice start code is mainly used for error recovery.

[0365] The start code provides the only way to start the decoder, and this will be described in more detail subsequently. If the start code detector is placed before the coded data buffer, after the coded data buffer, and the Huffman decoder and the video
Numerous advantages are obtained over placing the start code detector before the multiplexor. If a start code detector is placed before the first buffer, 1) the token can be assembled, 2) the standard control signal such as a start code can be decoded, and 3) the data can be decoded. Is possible to pad the bit stream before entering the buffer, and 4) create an appropriate sequence of control tokens to empty the buffer and put available data from the buffer into the Huffman decoder. It is possible.

Most of the control tokens output by the start code detector directly reflect the syntax elements of various pictures and video coding standards. The start code detector converts syntax elements into control tokens. In addition to these natural tokens, some unique,
And / or a machine dependent token is generated. Unique tokens are specifically designed for use by the system of the present invention, are unique internally and externally,
Also included are tokens used to assist with the multi-standardity of the present invention. Examples of such unique tokens include picture end and coding standards.

In addition, tokens are introduced to remove some of the syntactic differences between coding standards and to cooperate with error conditions. Automatic token generation occurs after sequential analysis of the standard dependent data. Thus, the spatial decoder responds equally to tokens supplied directly to the input of the spatial decoder, ie, the SCD, as well as tokens generated following detection of a start code in the encoded data. A series of extra tokens are inserted into the two-wire interface to control the multi-standardity of the present invention.

MPEG and H.264. The H.261 encoded video stream includes a standard dependent non-data identifiable bit pattern, one of which will be referred to hereinafter as a start image and / or a standard dependent code. J
In PEG, a similar function is provided by a marker code. These start / marker codes identify important parts of the syntax of the encoded data stream. The analysis of the start / marker code performed by the start code detector is the first stage of the coded data analysis.

The start / marker code pattern is designed so that the pattern can be identified without decoding the entire bitstream. Therefore, those patterns can be used in accordance with the present invention to assist in error recovery and decoder start. The start code detector provides functions to detect errors in the coded data structure and assist in starting the decoder. The error detection capability of the start code detector will be described later in detail as the decoder starts.

The above description was mainly concerned with the characteristics of the machine-dependent bit stream and the relationship with the addressing characteristics of the present invention. The following is a description of the characteristics of the bitstream of the standard-dependent coded data for the start code detector.

Each standard compression encoding system uses a unique start code configuration, or image, selected to identify a particular compression specification. Each start code has a start code value. The start code value is used to identify the type of operation associated with the start code in the language of the standard. In the multi-standard decoder of the present invention, as described above, the compatibility is as follows.
Based on control token and data token configuration. The index signal including the flag signal is generated as a circuit in each state machine, and will be appropriately described below.

The start and / or marker codes included in the standard and other standard words as opposed to data words are used to control,
And / or with respect to the content of the data token,
And / or are often identified as images to avoid confusion with the use of machine dependent code. Similarly, the term start code refers to JPEG marker codes, MPEG and H.264. 261 is often used as a generic term. Marker code and start serve the same purpose. Furthermore, "flash"
The term ( flash ) means both a flush token and, as a verb, for example, flushing a start code detector shift register (including a "flushed" signal). Used. Flash tokens are always capitalized to avoid confusion. All other uses of the term (verb or noun) are in lower case.

A standard-dependent coded input picture input stream contains data of varying length and a start image. The start image carries along with it a value telling which operation should be performed on the immediately following data according to the standard. However, in the multi-standard pipeline processing system of the present invention that requires compatibility with multiple standards, the system is optimized to handle all functions in all standards. Thus, in many conditions, a unique start control token is not only compatible with the values contained in the encoded signal standard image values, but also for each standard as is well known in the art. The various stages must be controllable in order to emulate the operation of the standard according to the indication by the specified parameters. Standards of this kind are all included in the room rate set to herein as reference material Murrell.

It is important to understand the relationship between tokens that emulate non-data information contained in a standard bitstream, either alone or in combination with other control tokens. A separate set of index signals, including flag signals, is generated by each state machine to handle some processing within the state machine. The values carried by the standard can be used to access the machine's dependent control signals to emulate the handling of standard data and non-data signals. For example, the slice start token is a two-word token, and thus is input to the two-wire interface as described above.

The data input to the system of the present invention may be any suitable data, such as a disk, tape, etc., that provides 8 bits of data to the first functional stage within start code detector 51 (FIG. 18). It can be a data source from the source. The start code detector has three shift registers, ie, the first
Are 8 bits wide, and the next is 24 bits.
Bit width, and then 15 bit width. Each register is part of a two-wire interface. Data from the data source is loaded into the first register as one single 8-bit byte during one timing cycle. Thereafter, the contents of the first shift register are decoded one bit at a time (second).
The data is shifted to the shift register. After 24 cycles, 2
The 4-bit register becomes full. Every eight cycles, an 8-bit byte is loaded into the first shift register. Each byte is loaded into the value shift register 221 (FIG. 29), and an additional 8 cycles empty the value shift register and shift register 23
Used to load 1. Shift register 23
Eight cycles are used to empty 1 and therefore
After these three operations, or 24 cycles, there are still three bytes in the 24-bit register. The value decode shift register 230 is still empty.

Assuming now that there is one picture start word in the 24-bit shift register, the detection cycle recognizes the picture start code pattern and provides a start signal as its output.
Once the detector detects a start, the subsequent byte is the value associated with the start code, and this is currently sitting in the value register 221.

Since the content of the detection shift register has been identified as a start code, these three bytes are used to remove this content from the 2-wire interface to ensure that no further processing occurs. Must. The decode register is emptied and the value decode shift register 230 waits for the value to be shifted to this type of register.

At this stage, the contents of the low order bit position of the value decode shift register include the value associated with the picture start. The spatial decoder equivalent to the standard picture start signal is called the SD picture start signal. Here, the SD picture start signal itself is about to be included in the token header,
This value is about to be included in the extension word for the token header.

[0379] 10. Token In the implementation of the present invention, a token is a universal adaptation unit in the form of an interactive interface messenger package for control and / or data functions, and for performing various operations in response to one recognized token. The reconfigurable processing stage (RP) is one stage that reconfigures itself to
Adapted for use with S). Tokens can be either position dependent or position independent to achieve various functions, depending on the processing stage. Further, the token is changed by the processing stage,
Subsequently, the pipeline may be fed downstream to achieve yet another function, which may be alterable. Token interacts with all or any smaller portion than the stage, and, from this point of view, adjacent, and / or, be considered to interact with non-adjacent stages no problem. Tokens are position-dependent for some functions and may be position-independent for other functions, and certain interactions with a stage may take place before that stage. Can be adjusted by the processing history in.

[0380] The picture end token is a method of transmitting the picture end in the multi-standard decoder.

A multi-standard token is an MPS using a mixture of standards-dependent and standards-independent hardware and control tokens.
EG, JPEG, and H.E. 261 data stream to 1
This is a method of mapping to one single decoder.

The search mode token is an MPEG that enables random access and enhanced error recovery.
JPEG, and H.A. 261 is a technique for searching for a data stream.

[0383] The stop after picture token is
A way to achieve the clear end of decoding, sending the end of the picture, and clearing the decoder pipeline, ie, channel changes.

Furthermore, padding a token is a method of supplying an arbitrary number of bits through a buffer having a fixed size and a fixed width.

The present invention is directed to a pipeline processing system having a variable configuration using a token and a two-wire system. The use of control and data tokens in combination with a two-wire system facilitates the achievement of a multi-standard system that allows for having extended operating capabilities compared to systems that do not use control tokens.

Control tokens are generated by circuitry in the decoder processor and emulate the operation of a number of different types of standards-dependent signals that feed into the serial pipeline processor for handling.
A technique for examining all parameters of a multiplex standard selected to perform processing by a serial processor and to consider the following items is used. 1) their similarities, 2) their differences, 3) their needs and requirements, and 4) the correct token function to effectively process all standard signals sent to the serial processor. Selection. The function of the token is to emulate the standard. The control token function is used in part as an emulation / translation between standard-dependent signals and as an element for communicating control information via a pipeline processor.

In prior art systems, dedicated machines are designed according to well-known techniques to identify standards and to create dedicated circuits by using a microprocessor interface. Signals from the microprocessor are used to control the flow of data through dedicated downstream components. The selection, timing, and organization of this decompression function is under the control of fixed logic circuits assisted by signals coming from the microprocessor.

In contrast, the system of the present invention
The downstream function stage is configured under the control of the control token. Options are provided to obtain necessary and / or alternative controls from the MPU.

Tokens provide and create an excellent format for communicating information through the decompression circuit pipeline processor. In the design chosen and used in the preferred embodiment shown below, the width of each word of the token is at least 8 bits,
And a single token can extend beyond one or more words. The width of the token is variable, and the number of bits can be arbitrarily selected. Extension bit indicates whether a token is extended beyond the current word, i.e., indicating whether bits definitive to all the word tokens except the last word of the token is set to binary 1. If the first word of the token has an extension bit of zero, this indicates that the length of the token is only one word.

Each token is identified by an address field starting at bit 7 of the first word of the token. The address field is variable in length and is potentially possible to extend beyond multiple words. In the preferred embodiment, the length of the address is no more than 8 bits. However, this is not a limitation in the present invention, but rather the size of the process chosen to be achieved by the use of these tokens. If the extension bits in words 1 and 2 are one 1
Note that signifying the succession of the additional word is indicated by the extended bit identification label. The extension bit in word 3 is zero, thus indicating the end of the token.

Further, the token has a variable bit length.
For example, a total of 10 bits are used by adding an extension bit to a 9-bit token word. In the design of the present invention, the width of the output bus is variable. Width of the output from the spatial decoder is 10 bits in the case of either a 9-bit, or include extension bit. In a preferred embodiment,
The only token that utilizes these extra bits is the data token, and all other tokens ignore this extra bit. It should be understood that this is not a limiting condition, but merely an example.

By using the data token and control token configurations, it is possible to change the length of the data represented by the number of bits in one word being carried by these data tokens. For example, the data bits in a word of the data token may be combined with the data bits in other words of the same data token for use in accessing the constant access memory used throughout the serial decompression processor. Or 10
It has been considered that the address of the bit can be formed. This facilitates wide versatility and adds variability.

As described above, the data token is 1
Carry data from one processing stage to the next. Thus, the characteristics of this token change as it passes through the decoder. For example, at the input to the spatial decoder, the data token carries bit-serial encoded video data packed into 8-bit words. Here, there is no limit on the length of each token. However, to illustrate the versatility of this aspect of the invention (at the output of the spatial decoder circuit), assume that each data token has exactly 64 words and that each word is 9 bits wide. More specifically, the standard coded signal allows different strengths and details of the image to be coded for messages of different lengths. The first image of the group usually has the longest number of data bits, since it is necessary to provide the most processing unit information. As a result, the first image can start decompressing as much information as possible. Subsequent words generally have a shorter length as they contain a different signal when compared to the first word with respect to the second position in the scanning information field.
The words are interspersed such that a variable amount of data is provided at the input of the spatial decoder, as required by the standard coding system. However, after the spatial decoder has functioned, the information is provided at its output at a picture format rate suitable for the on-screen display. For example, the output rate over time of the spatial decoder can be varied to interface worldwide with various display systems such as NTSC, PAL, and SECAM. The moving picture formatting unit converts the variable picture rate into a constant picture rate suitable for a display. However, the picture data is still carried by a data token consisting of 64 words.

[0397] 11. DRAM Interface A single high performance configurable DRAM interface is used for each of the three decoder chips. Generally, the DRAM interface on each chip is substantially the same. However, interfaces are different from each other in the method of handling channel priority. This interface is
It is designed to directly drive an external DRAM used by a spatial decoder, a temporal decoder, and a video formatter. Generally, no external logic, buffers, or components are required to connect the DRAM interface to the DRAM in these systems.

According to the present invention, the interface can be configured by the following two methods. 1. Detailed timing interfaces can be configured to accommodate different DRAM types.

[0396] 2. The width of the data interface to the DRAM can be configured to provide a cost / performance trade-off for different applications.

In general, the DRAM interface is a standard independent block implemented on each of the three chips in the system. Again, these chips are the spatial decoder, the temporal decoder, and the video formatting unit. 18, 19, and 20, which are block diagrams showing the relationship between the DRAM interface and the remaining blocks of the spatial decoder, the temporal decoder, and the video formatting unit, respectively. is there. In each chip, the DRAM interface connects the chip to an external DRAM. Currently, external DRAMs are used because it is not practical to make the required relatively large amount of DRAM on a chip. (Note: Each chip has its own external DRAM and its own DRAM interface.)
When the M interface is independent of the compression standard, the multiplex standard H.M. The interface must be configured to implement each of H.261, JPEG, and MPEG. How to reconfigure the DRAM interface for multi-standard operation will be described in more detail later.

To understand the operation of the DRAM interface, it is necessary to understand the relationship between the DRAM interface and the address generator, and how to communicate between them using a two-wire interface. is necessary.

Generally, as the name implies, an address generator is used to address a DRAM (eg, D
When reading / writing to a specific address in RAM)
Generate the addresses required by the DRAM interface. When using 2-wire interface, DRAM
Reading and writing occur only if the interface has both data (from the previous stage in the pipeline) and a valid address (from the address generator). The use of a separate address generator simplifies the configuration of both the address generator and the DRAM interface, as discussed further below.

In the present invention, the DRAM interface is operable from a clock that is synchronous with both the address generator and the clock of the stage through which data is supplied. Special techniques are needed to handle the asynchronous nature of operations.

Data is generally transferred between the DRAM interface and the rest of the chip in 64-byte blocks (the only exception being the prediction data in the temporal decoder). The transfer is performed by a device known as a "swing buffer."
The swing buffer essentially fills or empties one RAM , while at the same time other components of the chip empty or fill the other RAM.
A pair of RAMs operated in a double-buffered configuration using an AM interface
It is. A separate bus carrying addresses from the address generator is associated with each swing buffer.

In the present invention, each chip has four swing buffers, and the functions of these swing buffers are different in each case. In the spatial decoder,
One swing buffer stores coded data in D
One swing buffer is used to read coded data from the DRAM, and a third swing buffer is used to transfer the tokenized data to the DRAM. And
The fourth swing buffer stores the tokenized data in D
Used to read from RAM. However, in the time decoder, one swing buffer is used to write intra or predicted picture data to the DRAM, the second swing buffer is used to read an in-preparative La or predicted data from the DRAM, and,
The other two are used to read forward and backward prediction data. In the video formatting part, one swing buffer is used to transfer data to DRAM, and the other three are used to read data from DRAM, luminance (Y), and red and blue. 1 for color difference data (Cr and Cb, respectively)
Used one by one. One write swing buffer,
And the operation of one virtual DRAM interface with one read swing buffer will be described in the next section. Essentially, this is the same as the operation of the DRAM interface of the spatial decoder. The operation is shown in FIG.

FIG. 32 shows an address generator 301, DRA
The control interface between the M interface 302 and the remaining stages of the chip that supply data indicate that they are all two-wire interfaces. The address generator 301 may generate an address as a result of receiving the control token, or may simply generate a fixed sequence of addresses (eg, for a FIFO buffer of a spatial decoder). The DRAM interface handles the 2-wire interface associated with the address generator 301 in a special way. Instead of holding accept high when the accept line is ready to receive an address, the address line waits for a valid address supply by the address generator, processes the address, and waits for one clock period. To set the accept line high. In this way, a request / acknowledgment (PEQ / ACK) protocol is implemented.

A unique feature of the DRAM interface 302 is the ability to communicate independently of the address generator 301 and the stages that supply or accept data. For example, the address generator may generate an address associated with the data in the write swing buffer (FIG. 33), but the write swing buffer may be used to write a block of data ready for writing to an external DRAM. No action is taken until it sends a message that it exists. Similarly, the write swing buffer may contain blocks of data that are ready to be written to the external DRAM, but the address is
No action is taken until it is supplied from the address generator 301 to the bus. In addition, once one of the RAMs in the write swing buffer is full of data, the other RA may be activated before the data input is stalled (the 2-wire interface accept signal is set LOW ).
M can be completely filled and then "swinged" to the DRAM interface side.

In understanding the operation of the DRAM interface 302 according to the present invention, in a properly configured system, a DRAM interface may be provided between the swing buffer and the external DRAM 303.
It is important to note that data transfer is possible with a data rate at least equal to the sum of all average data rates between the swing buffer and the rest of the chip.

Each DRAM interface 302 determines which swing buffer will service next. Generally, this is a "round robin"
n) (that is, the next serviced swing buffer is
Either the next available swing buffer in the least recent order) or a priority encoder (ie, where some swing buffers have higher priority than others) is there. In both cases,
Additional requests with higher priority than all other requests come from the refresh request generator. The refresh request is generated from a refresh counter that is programmable via a microprocessor interface.

Here, reference is made to FIG. 33, which shows a configuration diagram of the write swing buffer.
The write swing buffer interface has the first R
Two blocks, an AM 311 and a second RAM 312, are included. As will now be discussed further, the data is under the control of the write address 303, and a control unit 314, is entered from the previous stage in RAM 3 1 1 and RAM 312. Data is written from the RAM 311 and the RAM 312 to the DRAM 315. While writing data to the DRAM, as described further herein, the DRAM
The row address is provided by an address generator, and the column address is provided by a write address and control. In operation, valid data is provided at input 316 (data in). In general,
Data is received from a previous stage. As each data is accepted by the DRAM interface, the RAM 311 is written, and the write address control increments the RAM 311;
The next one data can be written in the RAM 311. The entry of data into the RAM 311 is continued until there is no more data or the RAM 311 is full. If the RAM 311 is full, the input side gives up control and sends a signal to the reader to indicate that the RAM 311 is ready to be read. Thus, this signal is provided between the two asynchronous clock regimes and is provided via three synchronization flip-flops. Assuming that the RAM 312 is empty, the next item of data arriving at the input is the RAM 312
Is filled in. Otherwise, this occurs when RAM 312 is empty. If the round robin or priority encoder indicates a swing buffer in the order in which it is read (depending on which is used by a particular chip), the DRAM interface will
Read the contents of AM311 and export them to external DRA
Fill in M. Next, a signal is sent back through the asynchronous interface, indicating that RAM 311 is ready to be refilled.

The DRAM interface is the RAM 311
Is empty, and if the input side "swings" before filling the RAM 312, continuous acceptance of the data by the swing buffer is possible. Otherwise, if RAM2 is full, the swing buffer will set its accept signal low until RAM 311 is "swing" backwards for use by the input side.

The operation of the read swing buffer according to the present invention is the same, except that the input and output data are inverted.

The DRAM interface of the present invention is designed to maximize the available memory bandwidth. Each 8x8 block of data is the same DRAM
Stored on the page. In this way, the DRAM high-speed page access mode can be used completely. In this case, 1
One row address is provided, followed by a number of column addresses. In particular, the row address is provided by an address generator, while the column address is
Provided by the AM interface. In addition, a function is provided that allows the width of the data bus to the external DRAM to be 8, 16, or 32 bits. Thus, DRAM usage can be tailored to the size and bandwidth requirements of a particular application.

In this example (exactly how the DRAM interface on the spatial decoder works), the address generator supplies the DRAM interface with block addresses for each of the read and write swing buffers. . This address is used as a row address for the DRAM. The 6-bit column address is provided by the DRAM interface itself, and these bits are used as well as the address for the swing buffer RAM . The width of the data bus to the swing buffer is 32 bits. Thus, if the bus width to the external DRAM is less than 32 bits, then 2 or 4 external DRAM accesses will be performed before the next word is read from the write swing buffer or the next word will be stored in the read swing buffer. Before being filled, it must be done (read and write mean the direction of transfer to the external DRAM).

In the case of the temporal decoder and the moving picture formatting unit, the conditions are more complicated. The addressing of the temporal decoder is more complicated due to its predictive aspects as discussed further in this section. As discussed further in this section with respect to the video formatting section, video formatting addressing is more complicated because of the multiple video output standard aspects.

As described above, the temporal decoder has four swing buffers. Two of them are used to perform reading and writing of decoded point and predicted (I call P) picture data. They are,
Works as described above. The other two are used to receive prediction data. These buffers are even more interesting.

In general, the prediction data is offset from the position of the processed block, as specified in the motion motion vector as x and y. Thus, the data block to be searched is coded (and written to DRAM) and generally does not coincide with the block boundaries of the data. In FIG. 34, as shown in FIG. 34, a shaded portion represents a block being formed, and an outline shown by a dotted line represents a block which is being predicted based on the block. The address generator converts the addresses specified by the motion vectors into offset blocks (total number of blocks), as indicated by the large arrows, and into pixels offset by the small arrows.

At the address generator, a frame pointer, a base block address, and a vector offset are added to form the address of the block to be retrieved from the DRAM. If the pixel offset is zero, only one request is generated.
If there is an offset in either the x or y dimension,
Two requests are generated: the original block address and the block address immediately below. If there are offsets in x and y, four requests are generated. For each block to be searched, the address generator calculates start and stop addresses, as best shown in the example of the figure.

The pixel offset (1, 1) corresponding to the shaded portion in FIG. 35 will be considered. The address generator makes four requests, labeled A through D in the figure. The problem to be solved is how to quickly supply the required sequence of row addresses. The solution is to use a "start / stop" technique as shown below.

The block A in FIG. 35 will be considered. The reading must start at position (7,7) and end at position (1,1).
At this stage, assume that one byte is being read at a time (ie, an 8-bit DRAM interface). The x value in the coordinate pair is the three LS of the address
Form B and the y values form three MSBs. x and y
The start value is 1 for both, providing 9 for the address. Data is read from this address, and, x value is incremented main cement. The process is repeated until the x value reaches its stop value, at which point the y value is incremented by one, and the x start value is reloaded,
One address 17 is provided. As each byte of data is read, the x value is incremented again until it reaches the stop value. The process is repeated until both x and y values have reached their stop values. In this way, 9, 1
0, 11, 12, 13, 14, 15, 17. . . 23,
25,..., 31, 33,..., 57,.

In a similar manner, the start and stop coordinates for block B are (1, 0) and (7, 0)
And (0, 1) and (0,
7) and (0,0) for block D
And (0,0).

The next question is where to put this data. Obviously, observing block A, the data read from address 9 must be written at address 0 of the swing buffer and the data from address 10 must be written at address 1 of the swing buffer. . And so on. Similarly, the data read from address 8 in block B must be written to address 15 in the swing buffer, and the data from address 16 must be written to address 15 in the swing buffer. This feature is very easy to implement, as outlined below.

Let us consider block A.
At the start of reading, the swing buffer address register is loaded with the inverse of the stop value. The inverse stop value of y forms three MSBs and x
Form three LSBs. In this case, the DRAM interface is reading address 9 in the external DRAM, but the swing buffer address is zero. As shown in Table 500, "Predicted Addressing", as the external DRAM address register is incremented, the swing buffer address register is also incremented.

The description so far has concentrated on the 8-bit DRAM interface. In the case of a 16 or 32 bit interface, a few minor modifications have to be made. First, the pixel offset vector must be "clipped" so that it points to a 16 or 32 bit boundary. In the example used here, for block A, the first read
DRAM points to address 0, and data from addresses 0 to 3 is read. Second, unnecessary data must be discarded. This is accomplished by writing all of the data to the swing buffer (in this case, the swing buffer must be physically larger than needed for the 8-bit case) and reading along with the offset. When performing MPEG half-pixel interpolation, 9 bytes in x and / or y must be read from the DRAM interface. In this case, the address generator provides the appropriate start and stop addresses. Some additional logic is used in the DRAM interface, but there is no fundamental change in the way the DRAM interface operates. The last thing to note about the temporal decoder DRAM interface of the present invention is that additional information must be provided to the prediction filter to indicate what processing needs to be performed on the data. is there. The contents of the necessary processing are shown below.

Transfer (64, 72 or 81 bytes)
"Last byte signal" indicating the last byte of

H. 261 flag.

A bidirectional prediction flag.

Two bits indicating the dimension of the block (8 or 9 bytes in x and y).

One 2-bit number indicating the order of the block.

As data is read from the swing buffer, a last byte flag can be generated. Other signals are obtained from the address generator and are piped through the DRAM interface so that the signals are combined with the correct blocks of data as the data is read from the swing buffer by the predictive filter block.

In the moving picture formatting unit, data is written in the external DRAM in the block.
However, they are read in raster order. Writing is exactly the same as described above for the spatial decoder,
However, reading is slightly more complicated.

The data in the moving picture format section and the external DRAM is organized so that at least eight blocks of data fit into one single page. These eight blocks are eight consecutive horizontal blocks. During rasterization, eight bytes need to be read from each of eight consecutive blocks and written to the swing buffer (ie, the same column in each of the eight blocks).

Consider the top column (and assuming a 1 byte wide interface), and as with the y address (3MSBS), the x address (3L
SBS) is set to zero. Next, the x address is incremented as the first eight bytes are each read. At this point, the top part of the upper part of the address (bit 6 and above—LSB = bit 0) is incremented and the x address (3LSBS)
Is reset to zero. This process is repeated until 64 bytes have been read. If the width of the interface to the external DRAM is 16 or 32 bits, instead of incrementing the x address by 1, the x address is simply incremented by 2 or 4, respectively.

In the present invention, although a multiple of 8 bytes is always read, the address generator can send to the DRAM interface that less than 64 bytes must be read (this is the start of a raster line). Or may be required upon termination). This is achieved by using start and stop values. The start value is used for the top part of the address (bits 6 and above) and the stop value is compared to the start value to generate a signal indicating when the read must be stopped.

In order to place the edge of the DRAM signal at an accuracy of one-fourth of the clock period of the system, the DRAM interface timing block in the present invention uses a timing chain. Two quadrature clocks from the phase clocked loop are used. These clocks are combined to form a conceptual 2x clock. Thus, every single chain is made up of two shift registers with the opposite phase to the 2x clock connected in parallel.

First, there is one chain for the page start cycle, and another chain is for the read / write / refresh cycle. The length of each cycle is programmable via the microprocessor interface, after which the page start chain has a fixed length, and during the page start, the length of the cycle chain changes accordingly .

When reset, the chain is cleared,
Then, a pulse is created. The pulses travel along the chain and are directed by status information from the DRAM interface. The pulse generates a DRAM interface clock. Each DRAM interface clock cycle corresponds to one cycle of the DRAM. Therefore, if the length of the DRAM cycle is different, the DRAM interface clock is not constant speed.

Further, an additional timing chain combines the pulses from the above chain with information from the DRAM interface, for example, notcas, notr
Generate output strobes and enables such as as, notwe, notbe. 12. Prediction Filter Referring again to FIGS. 19, 20, and more particularly to FIG. 40, a block diagram of the temporal decoder is shown. This includes a prediction filter. FIG. 2 shows the relationship between the prediction filter and the remaining elements of the temporal decoder.
6 shows the details. The essence of the structure of the prediction filter is shown in FIGS. A detailed description of the operation of the prediction filter is provided in the "More Detailed Description of the Invention" section of this section.

In general, the prediction filter according to the present invention
MPEG and H.264. Used in 26l mode,
Not used in JPEG mode. Recall the case in JPEG mode. That is, the time decoder
It merely feeds the data through the video format without any substantial decoding beyond the range achievable by the spatial decoder. Referring again to FIG. 27, in MPEG mode, the forward and backward prediction filters are the same, and filter the respective MPEG forward and backward prediction blocks. However, H. H.261 does not use backward prediction. In the H.261 mode, only the forward prediction filter is used.

Each of the two prediction filters of the present invention is substantially the same. Reference is again made to FIGS. 17 and 505, and more particularly to FIG. The figure shows a block diagram of the structure of the prediction filter. Each prediction filter has four stages arranged in series. The data is input to the format stage 505-7 and is formatted for easy filtering. In the next stage 505-2, the ID prediction is
Performed on the X coordinate. After the required transport has been performed by the dimension buffer stage 505-3, the ID prediction is performed on the Y coordinate in stage 505-4. We will describe in more detail how the stage performs the filtering action. The conditions required for the filtration action are defined by compression standards. H. 26
In case 1, the actual filtering effect is similar to that of a low-pass filter.

Referring again to FIG. 26, the multi-standard operation is either MPEG or H.264. The prediction filter needs to be reconfigurable to perform any of the H.261 filtering, or to perform no filtering at all in the JPEG mode. As with many other reconfigurable aspects of a three-chip system, the prediction filter
Reconstructed by token. The token is also used to inform the address generator about a particular mode of operation. In this case, the address generator is M
The address of the required data, which varies significantly between PEG and JPEG, can be provided to the prediction filter.

13. Accessing Registers Most registers in a microprocessor interface (MPI) are modifiable only if the stage to which the interface relates is stopped. Accordingly, groups of registers are generally associated with access registers. If the value in an access register is zero, the group of registers associated with that particular access register must not be modified. Writing a 1 to the access register requests that the stage be stopped. However, the stage cannot be stopped immediately, so the stage access register holds the value zero until stopped.

Any user software associated with the MPI and used to perform functions via the MPI must wait until a 1 is read from the access register "after writing a 1 to the request access register." No. If the user writes a value to the configuration register, the result is unknown until the access register is set to zero at the same time.

14. Microprocessor Interface A microprocessor interface (MPI) having a standard byte width is used in all circuits in the spatial decoder and the temporal decoder. MPI operates asynchronously with various spatial and temporal decoder clocks. Referring to Table 37, this table shows various MPI signals used in this interface.
The character of the signal is shown in the input / output column, the name of the signal is shown in the signal name column, and a description of the signal function is shown in the description column. The MPI electrical specifications are set forth with respect to Table 38. All specifications are categorized by type, and the symbol box shows three types. What these symbols represent is shown in the parameter column. The actual specifications are shown in the respective columns in minimum, maximum and units.

The DC operating conditions are shown with respect to Table 39. The column headings are the same as in Table 38. DC electrical properties are shown with respect to Table 40 and the same headings as in Tables 38 and 39 are used.

[0443] 15. MPI Read Timing The AC characteristics of the MPI read timing diagram are shown with respect to FIG. Each line in the figure is labeled by the corresponding signal name, and the timing is shown in nanoseconds. The read timing characteristics of the complete microprocessor interface are shown with respect to Table 41. The column number indicates a signal corresponding to the signal name described in the characteristic column. The columns identified by MIN and MAX provide the minimum length of time that indicates the maximum amount of time that the signal is available. The unit column indicates a unit of measurement used to describe the signal.

[0444] 16. MPI Write Timing A general description of the MPI write timing diagram is shown with respect to FIG. This figure shows the names of individual signals related to the MPI write timing. Names, signal characteristics, and various other physical characteristics are set forth with respect to Table 42.

[0445] 17. Keyhole Address Location In the present invention, the memory map with low access frequency is located behind the keyhole register. The keyhole register has two registers associated with it. The first register is a keyhole address register, and the second register is a keyhole data register. The keyhole address specifies a location in the extended address space. A read or write operation to the keyhole data register accesses the location specified by the keyhole address register. After accessing the keyhole data register, the associated keyhole address register is incremented. Random access within the extended address space is only possible by writing a new value to the keyhole address register for each access.
Circuits within the scope of the present invention may have more than one keyhole map. Nevertheless, there is no interaction between the different keyholes.

[0446] 18. Picture End Referring again to FIG. 18, which shows a general block diagram of the spatial decoder used in the present invention. The description of the picture end function applies throughout this block diagram. The picture end function is described in H.264. 261
It has the advantage of multiple standards that it can handle coded picture information, MPEG and JPEG signals.

As already mentioned, the overall block diagram of FIG. 18 is interconnected by the two-wire interface already described. Each functional block is arranged to operate based on the state machine configuration shown with respect to FIG.

Generally, a picture end according to the present invention starts at a start code detector that generates a picture end control token. The picture end control token is supplied unchanged to the DRAM interface via the start-up control circuit. In this case, the token is used to flush the write swing buffer in the DRAM interface. Recall that the contents of the swing buffer are written to RAM only when the buffer is full. However, the processing is terminated even at a point where the buffer is not full, and the picture data may be stuck. The picture end token forces data out of the swing buffer.

Since the invention is a multi-standard machine, it operates differently for each compression standard. More specifically, the case of operating according to a machine dependent action cycle will be fully described. For each compression standard, the total number of available action cycles can be selected by a combination of control tokens and / or output signals from the MPU, or
The total number of all available action cycles can also be selected by the design of the control token itself. In this regard, the present invention is organized to delay information from entering the next block until all information has been collected in the upstream block. The system waits until it is ready to supply data to the next stage. In this way, the picture end signal is provided to the coded data buffer, and the control portion of the picture end signal causes reading of the contents of the data buffer and to the Huffman decoder and video demultiplexer circuit. Supplied.

Another advantage of the picture end control token is that, for use by the Huffman decoder demultiplexer, the generally expected full range of signals supplied to the Huffman decoder and video demultiplexer circuit, and / or
Alternatively, even when the control token has no number, the control token identifies the end of the picture. Under this condition, the information held in the coded data buffer is supplied to the Huffman decoder and the moving image demultiplexer as a complete picture. In this way, the Huffman decoder and the video demultiplexer state machine can still handle data depending on the system design.

Another advantage of the picture end control token is its ability to completely empty the coded data buffer so that stray information does not inadvertently remain in the off-chip DRAM or swing buffer.

A further advantage of the picture end function is that
Its use in error recovery. For example, assuming that the amount of data held in the coded data buffer is less than the amount commonly used to indicate spatial information for one single image, the last image will have a full swing buffer. , But by definition, the buffer never fills. At some point, the machine determines that an error condition is removed by withdrawal. Thus, the picture end token is decoded, and to the extent that the data in the coded data buffer is forced to be provided to the Huffman decoder and the video demultiplexer, the last image is decodable, and , The information is emptied from the buffer. As a result, the machine does not enter error recovery mode and successfully processes the encoded data and continues.

[0453] Yet another advantage of the use of picture end tokens is that the serial pipeline processor continues to process interruptless data. By using the picture end token, the serial pipeline processor is configured to handle less than the expected amount of data and, as a result, continues processing. Generally, prior art machines stop due to an error condition. As already mentioned, the coded data buffer counts macroblocks as they arrive in its storage area. In addition, the Huffman decoder and video demultiplexer generally know the amount of information expected when decoding each image, i.e., the state machine portion of the Huffman decode and video demultiplexer during each image recovery cycle. Know the number of blocks to process. If the correct number of blocks do not arrive from the coded data buffer, an error recovery routine generally results. However, by using the picture end control token to reconstruct the Huffman decoder and the video demultiplexer, the control token is handling a practically appropriate amount of information for the man decoder and the video demultiplexer by reconstruction. So you can keep working.

Referring again to FIG. 17, the token decoder part of the buffer manager detects the picture end control token generated by the start code detector. In the normal operating state, as already mentioned, for normal operation of the swing buffer, the buffer register is filled and emptied. Again, a swing buffer that is partially full of data, until the swing buffer is completely filled,
And / or does not empty until it knows when to empty. The picture end control token is decoded in the token decoder portion of the buffer manager, and flushes the contents of the partially full swing buffer to the coded data buffer . This is, ultimately, direct,
Alternatively, it is supplied to a Huffman decoder and a moving image demultiplexer via a DRAM interface.

[0455] 19. Flushing operation Another advantage of the picture end control token is its function associated with the flash token. The flash token is not associated with either the reconfiguration control of the state machine or the data path to the system. Rather, this token, in order to handle by machine dependent of the state machine, to the front of the partial signal to complete. Each state machine recognizes the flash control token as information that must not be processed. Thus, the flash token is used to fill all of the remaining empty parts of the coded data buffer, and is used to allow a sufficient set of information to be sent to the Huffman decoder and video demultiplexer. Is done. Thus, the flush token acts like padding on the buffer.

[0456] The token decoder in the Huffman circuit recognizes the flash token and ignores the bogus data that the flash token pushed into it.
Next, the Huffman decoder operates only on the data content of the last picture buffer, if present before the arrival of the picture end token and the flash token. A further advantage of the use of picture end tokens alone or in combination with flash tokens is the reconfiguration and / or reorganization of the Huffman decoder circuit. Upon the arrival of the picture end token, the Huffman decoder circuit knows that it has less information than normally expected to decode the last image. The Huffman decoding circuit finishes processing the information contained in the last image,
And this information is passed through the DRAM interface
Output to the reverse modeler . Upon discrimination of the last two images, the Huffman decoder goes into a cleanup mode and re-adjusts for the arrival of the next image information.

20. Flush function The flush token is supplied according to the present invention throughout the pipeline processor, and that the buffer is empty and that other circuits are reconfigured to wait for new data to arrive. Used to guarantee. More specifically, the present invention has a combination of picture end tokens, padding words, and flash tokens that indicate to the serial pipeline processor that image processing for the form of the current picture is complete. After that, the various state machines
It needs to be reconfigured to wait for new data to arrive for new handling. Further, note that the flush token acts as a special reset for the system. The flash token resets each stage upon passing. However, the processing of the next stage can be continued. This prevents data loss. In other words, a flash token is a variable reset as opposed to an absolute reset.

[0458] 21. Stop After Picture The stop after picture function is used to close the decompression circuit of the serial pipeline at a logical point in its operation. At this point,
A picture end token is generated, indicating that data has completed incoming from the data input line and that the padding operation has been completed. The padding function
Partially fill an empty data token. Next, a flush token is generated and fed through the serial pipeline system, and pushes all information out of the registers, forcing the registers to return to their neutral standby state. Next, a stop-after-picture event is generated, and no input is accepted until either the user or the system clears this condition. In other words, the picture end token sends the end of the picture, while the stop after picture operation sends the end of all current processing.

[0459] 22. Multi-Standard Search Mode Another feature of the present invention is the use of a SEARCHNODE control token used to reconfigure the input to the serial pipeline processor to examine the incoming bit stream. When the search mode is set, the start code detector detects a specific start code,
Alternatively, only the marker used for any one of the compression standards is searched. However, it should be understood that other images from other data bitstreams can be used for this purpose. Thus, these images are modified throughout the present invention into a combination of control tokens and other embodiments capable of using data tokens with reconfiguration circuitry to provide similar processing. Can be used for

The use of the search mode in the present invention is convenient in a number of conditions, including the following: 1) When a break in the data bit stream occurs,
2) When the user intentionally changes the channel to cut the data bit stream, for example, the arrival of data by cable-carried compressed digital video or
3) By fast forward or reverse user activation from a controllable data source such as, for example, an optical disc, or a video disc. In general, the search mode is useful when the user interrupts the normal processing of the serial pipeline in that the machine does not anticipate an interrupt.

If any of the search modes are set, the start code detector looks for an incoming start image suitable for making a machine independent token. All data coming into the start code detector prior to the identification of the standard-dependent start image is meaningless, and if the machine is waiting for this information, the machine is abandoned as idle.

The start code detector can assume any one of the Numeric 0 configuration configurations. For example, one of these configurations allows a search for a group of pictures or higher start codes. With this pattern, the start code detector discards all its inputs and looks for a group start standard image. If such an image is identified, the start code detector generates a group start token and the search mode is automatically reset.

It is important to note that one single circuit, Huffman decoder, and video demultiplexing circuit work with a combination of input signals, including standard independent setup signals, as well as coding standard signals. . The coding standard signal is transmitting information directly from the incoming bit stream, as required by Huffman decoders and video demultiplexing circuits. However, on the other hand, the Huffman decoder and the video demultiplexing circuit function under the operation of the standard independent sequence signal.

Since this mode of operation is most effective and can be designed such that a special control token is used instead of carrying the actual signal itself when carrying the standard dependent input to the Huffman decoder and video demultiplexer, This operation mode was selected.

[0465] 23. Inverse Modeler Inverse modeling is a feature of all three standards,
And the same is true for all three standards. In general,
The data token in the token buffer contains information about the value of the quantized coefficient, and information about the number of zeros between the displayed coefficients (run-length encoding 1).
Shape). The inverse modeler of the present invention is adapted for use with tokens, and simply expands the information on the execution of zero so that each data token contains 64 values as a prerequisite. After that,
The value in the data token is a quantized coefficient that can be used by the inverse quantizer.

[0466] 24. Inverse Quantizer The inverse quantizer of the present invention, which is an element required in the decoding sequence, has been implemented in such a way that the entire IC set can handle multi-standard data. Further, the inverse quantizer has been adapted for use with tokens. The inverse quantizer consists of an inverse modeler and an inverse D
CT (IDCT). For example, in the present invention, the adder in the inverse quantizer uses data having ID
Prior to moving to the C T, it is used to add a constant to the number of pixels decoded.

[0467] ID C T, use the number of pixels decoded that varies depending on the standard used to encode the information.
To correctly decode the information, the value 1024 is added to the number of decodes by the inverse quantizer before the data continues to enter the IDCT.

Circuits or software to handle data compressed according to various standards by using adders already in the inverse quantizer to normalize the data before it reaches the IDCT Eliminates the need to add. Other operations ready for multi-standard operation are performed during the post-quantization function and will be discussed later.

The various standardization routines that require the control token associated with the data to be decoded and performed by the inverse quantizer are identified in detail below. All of these "post-quantization" functions are implemented to avoid circuit duplication and allow the IC to handle multi-standard decoded data.

25. Huffman Decoder and Parser (Syntax Parser) Referring again to FIGS. 18 and 36, the spatial decoder includes a Huffman decoder for decoding Huffman-coded data according to various compression standards.
Standards JPBG, MPEG, and H.264. Each of the H.261 requires specific data to be Huffman coded, while the differences in Huffman decoding methods required by each standard have significant implications. In the spatial decoder of the present invention, without designing and creating a total of three individual Huffman decoders, one for each standard, the present invention identifies the common aspects of each Huffman decoder, and Creating a feature only once saves valuable die space. In addition, a sensible multi-part algorithm is used, that is, an algorithm that further strengthens the commonality of the aspects of each Huffman decoder that is common to other standards. In summary, the Huffman decoder 32
1 works with the other units shown in FIG. These other units are the parser state machine 322,
In shifter 323, data index unit 32
4, an ALU 325, and a token formatting unit 326. As already mentioned, the connections between these blocks are managed by a two-wire interface. How these units work will be described in more detail subsequently, with a focus on particular aspects supporting the multi-standard operation of the Huffman decoder according to the invention. .

The parser state machine of the present invention is a programmable state machine that acts to integrate the operations of other blocks in the video parser. The parser state machine controls other blocks on which the control word operates by generating control words in response to the data that are placed in parallel with the data and supplied to other blocks. Since the blocks are connected via a two-wire interface, it is not only useful but essential that the control word be provided side by side with the relevant data. Thus, data and control arrive at the same time. The passage of the control word passes below the data lines connecting the blocks, as shown in FIG. 36 by control lines. In particular, this codeword identifies the particular standard that is being decoded.

[0472] The Huffman decoder also performs certain control functions. In particular, the Huffman decoder 321 includes a state machine that can control specific functions of the data index unit 324 and the ALU 325. Control of these units by the Huffman decoder is necessary to correctly decode the block level information. Having the parser state machine 322 make these decisions would be too time consuming.

An important aspect of the Huffman decoder of the present invention is the ability to invert coded data bits when reading the data bits into the Huffman decoder. This ability is described in Required to decode H.261 Huffman style codes. The reason is H. The particular type of Huffman code used by H.261 (essentially MPEG) is due to having the opposite polarity to the code used by JPEG. Thus, by using an inverter, the same table used by the Huffman decoder is made substantially usable for all three standards.
Other aspects of how the Huffman decoder implements all three standards are described in more detail in the "More Detailed Description of the Invention" section.

Data index unit 324 performs the second part of the multi-part algorithm. This unit contains a look-up table that provides the actual Huffman decoded data. Entries in this table are organized based on the number of indexes generated by the Huffman decoder.

The ALU 325 implements the rest of the multi-part algorithm. In particular, the ALU handles sign extension. In addition, the ALU includes a register file that holds vector and DC predictions. The use of this file describes in related to prediction filter section. In addition, the ALU includes a counter that counts through the structure of the picture being decoded by the spatial decoder. In particular, the dimensions of the picture are programmed into registers associated with the counter to facilitate detection of "picture start" and macro-block code start.

According to the present invention, the token-matching unit 326 (TF) assembles the decoded data into a data token. These tokens are then provided to the remaining stages or blocks in the space-time decoder.

In the present invention, the inshifter receives data from a FIFO buffering the data that supplies the start code detector. There are generally two types of data received by the inshifter: a data token and a start code that is exchanged for each token by a start code detector, as discussed further in the "Tokens" section. . Note that most of the data is data tokens that need to be decrypted.

The inshifter supplies data serially to the Huffman decoder, while supplying control tokens in parallel. In the Huffman decoder, the Huffman encoded data is decoded according to a first part of a multi-part algorithm. In particular, a particular Huffman code is identified and then exchanged for an index number.

Further, the Huffman decoder identifies specific data that needs special handling by other blocks shown in FIG. This data includes block ends and escapes. In the present invention, time is saved by detecting them at the Huffman decoder, rather than at the data index unit. Next, this index number is supplied to the data index unit 324. The data index unit is
It is essentially a look-up table. The look-click over up table based on the one embodiment of the algorithm, J
There is not much difference from the Huffman code table specified by PEG. In general, it generally means that JPEG is an alternative JP
The format specified to transfer the EG table is a compressed data format.

The decoded index number, or other data, is provided from data index unit 324, along with the associated control word, to ALU 504-5, which performs the operations described above.

The data and control words are supplied from the ALU 325 to the token format section 326 (TF). In the token format section, data is combined with control words as needed to form tokens. Next, the token is carried to the next stage of the spatial decoder. Note that at this point, there are as many tokens as used by the system.

26. Discrete inverse cosine transform The discrete inverse cosine transform (IDCT) according to the present invention expands data related to the frequency of the DC component of the picture. If a particular picture is being compressed, the light frequency in the picture is quantized, reducing the overall amount of information that needs to be stored. IDCT is
Using the quantized data, it is expanded and returned to frequency information.

The IDCT operates on parts of the picture that are 8 × 8 pixels in size. The mathematics applied to this data is governed primarily by the particular standard used to encode the data. However, as the important applications of the present invention, in order to avoid unnecessary duplication of circuitry is this <br/> and constructed from a common Mathematical functions between standards. By using a particular scaling order, the symmetry between the upper and lower parts of the algorithm is increased, so that common mathematical functions can be reused and the circuit
The additional need for is eliminated.

The IDCT responds to a number of multi-standard tokens. The first part of the IDCT checks the incoming data to ensure that the size of the data token is correct for processing. In fact, if the error is not very large, the token stream is conditionally correctable.

[0485] 27. Buffer Manager The buffer manager of the present invention receives incoming video information, and provides data arrival timing, display,
And information about the frame rate to an address generator. Multiplexing buffers are used to allow for both display and display rates to be changed. Display and display rates generally vary according to the coded data and the monitor on which the information is being displayed. Data arrival rates generally vary depending on the errors contained in the raw materials used to encode, decode, or create the data. When the information arrives at the buffer manager, it is decompressed. However, the data is arranged in an order that is useful for the decompression circuit but not for the particular display unit in use. When a block of data is input to the buffer manager, the buffer manager provides information to the address generator so that the blocks of data can be arranged in an order that can be used by the display device. This allows the buffer manager to use the necessary frame rate conversion to adjust the incoming data blocks so that the data blocks can be displayed on the particular display device in use.

In the present invention, the buffer manager supplies information mainly to the address generator. However, it is also necessary to interface other elements of the system. For example, there is an interface with an input FIFO that transfers the tokens to a buffer manager that supplies these tokens to a write address generator.

Further, the buffer manager also interfaces with the display address generator to receive information regarding whether the display device is ready to display new data. Similarly, the buffer manager verifies that the display address generator has cleared information for display from the buffer.

The buffer manager of the present invention stores whether a particular buffer is empty, full, ready for use, or busy, and
The display number associated with the specific data in each buffer is stored. In this way, the buffer manager determines the state of the buffers, in part, by having only one buffer at a time ready for display. Once the buffer is displayed, the buffer is in an "empty" state. When the buffer manager receives a picture start, a flush, a valid token, or an access token, the buffer manager
And prepare to accept new data. For example, the picture start token causes the buffer manager to cycle through each buffer to find a buffer that can accept new data.

In addition, the buffer manager can be configured to handle the multi-standard requirements dictated by the token it receives. For example, H. In the 26l standard, during display, data can be skipped. When such a token arrives at the buffer manager, the data to be skipped is flushed from the buffer where it is stored.

By managing the buffer in this manner, the data can be effectively stored according to the compression standard used to encode the data, the rate at which the data is decoded, and the particular type of display device in use. Can be displayed.

The foregoing description has been generalized, with enough detail to enable a person of ordinary skill in the art to implement the invention with all the attendant features, objects, and advantages. It is believed that the concepts, system implementations, and operations of various aspects of the present invention have been adequately described. However, in order to facilitate a more thorough understanding of the present invention and additional details associated with more specific and commercial implementations of various embodiments of the present invention, further description and It is preferable to continue the description below.

The following is a more detailed description of the chipset of a multi-standard video decoder. The description is divided into three parts, A, B and C.

For purposes of organization, clarity, and convenience of the description, additional disclosure will be re-presented in the following sections.

Description of features common to chips in a chip set.

• Token • 2-wire interface • DRAM interface • Microprocessor interface • Clock • Spatial decoder chip description • Time decoder chip description Section A. 1 "How to Use This Description" The first description section covers most of the electrical design issues associated with the use of chip sets.

A. 1.1 "Printing conventions" Some printing conventions are used to emphasize certain classes of information. An example is shown below.

Token Name Wire Name Active High Signal Wire Name Active Low Signal Register Name Section A. 2 "Video decoder family" * 30MHz operation * Decode MPEG, JPEG & H.264 261 * Encoded data rate for 25 Mb / s * Video data rate for 21 MB / s * MPEG resolution 704 x 480, 30 Hz, 4:
Up to 2: 0 * Chroma sampling format with flexibility * Whole JPEG baseline decoding * Glueless page mode DRAMA interface * Pin PQFP package of 208 * Independent coded data and decoder clock * Reorder MPEG picture sequence Video decoder family Provides a low chip count solution to realize a high resolution digital video decoder. Currently, chip sets are available in three different video and picture coding systems: JPEG, MPE
G and H .; 261 can be configured.

All JPEG baseline picture decoding is supported. 720 × 480, 30 Hz, 4: 2: 2 J
PEG encoded video can be decoded in real time.

CIF (Common Interchange Format) and Q
CIF H. 261 moving pictures can be decoded. 740x
All special function MPEG moving pictures having formats up to 480, 30 Hz and 4: 2: 0 can be decoded.

Note: The foregoing values are given by way of illustration only and are not necessarily indicative of the limiting conditions of one embodiment of the present invention. Thus, it should be understood that other values and / or ranges may be used.

A. 2.1 "System Configuration" 2.1.1 "Output Formatting" In each of the examples shown below, the form of the output formatting unit may be to use the data supplied to the output of the spatial or temporal decoder, and The system needs to be reformatted. The details of this formatting depend on the application. If BRIEF As an example, using the data output which is Bed locked formatted by the decoder chip and only requires an address generator for writing the data output in raster order.

The image formatting unit is a single-chip VLSI device that provides a wide range of output formatting functions.

A. 2.1.2 "JPEG Still Image Decoding" One single spatial decoder with non-off-chip DRAM can decode baseline JPEG images at high speed. The spatial decoder supports all features of baseline JPEG. However, the image size that can be decoded may be limited by the size of the output buffer supplied by the user. The characteristics of the output formatting unit can limit the chroma sampling format and the color space that can be supported.

A. 2.1.3 "JPEG video decoding" By adding an off-chip DRAM to the spatial decoder, it is possible to decode a JPEG encoded video in real time. The required size and speed of the buffer depends on the rate of the video and coded data. The temporal decoder does not need to decode the JPEG encoded video. However, if the temporal decoder is on a multi-standard decoder chip set and the system is configured for JPEG operation, it will simply supply data via the temporal decoder without change or modification. Absent.

A. 2.1.4 “H.261 decoding” The spatial and temporal decoders are based on H.261 decoding. Both are required to implement a H.261 video decoder. The DRAM interface on both devices requires the D D required for proper operation when operating at low coded data rates in small picture formats.
It can be configured so that the amount of RAM can be reduced. In general, each spatial and temporal decoder is
Requires one single 4Mb (eg, 512k × 8) DRAM.

A. 2.1.5 “MPEG Decoding” The configuration required for MPEG operation is described in H.264. 261. However, as will be appreciated by those of ordinary skill in the art, larger DRAM buffers may be required to support the larger picture formats available in MPEG.

Section A. 3 "Tokens" A. 3.1 "Token Format" In accordance with the present invention, tokens provide an extensible format for communicating information via a decoder chip set. In the present invention, the minimum width of each word of the token is 8 bits, but those of ordinary skill in the art will appreciate that the width of the token can be arbitrary. Further, a token is extendable over one or more words, which is achieved using an extension bit in each word.

The extension bit indicates whether the token continues into another word. All but the last word of the token are set to one. If the first word of a token has an extension bit of 0, this indicates that the token is only one word long.

Each token is identified by an address field where it starts at bit 7 of the first word of the token. The length of the address field is variable and is potentially scalable over multiple words (although none of the current chips address more than 8 bits in length; Will understand that, again, the length of the address can be arbitrary).

[0510] Depending on the interface, data 8
Transfer more bits than For example, the output width of the spatial decoder is 9 bits (10 bits including the extension bits). The only token that utilizes these additional bits is the data token. A data token may have as many bits as necessary to perform processing at a particular location in the system. All other tokens ignore the extra bits.

A. 3.2 "Data Token" A data token carries data from one processing stage to the next. Thus, the characteristics of this token change as it passes through the decoder. Furthermore, the meaning of the data carried by the data token changes depending on where in the system the data token is, ie the data is location dependent. In this regard,
The data may be either frequency domain data or pixel domain data depending on where in the spatial decoder the data token is located. For example, at the input of the spatial decoder, the data token has bit-serial coded video data packed into 8-bit words. In this regard, there is no limit on the length of each token. However, in contrast, at the output of the spatial decoder, each data token has exactly 64 words, each word being 9 bits wide.

A. 3.3 Use of Token Formatted Data Some applications require that the circuit be connected directly to the input or output of a decoder or chipset. In most cases, it is sufficient to collect data tokens and detect a few tokens that provide synchronization information (eg, like PICTURE START). In this regard, see Section A. below. 16 "Connection to the output of the spatial decoder"; See Section 19, "Connecting to the Output of the Temporal Decoder".

As already mentioned, it is sufficient to observe the activity on the extension bits to identify when each new token starts.
Again, the extension bit sends the last word of the current token. Further, the address field can be tested to identify the token. Unnecessary or unrecognized tokens can be consumed (and discarded) without knowing their contents. However, the recognized token causes an appropriate action to be taken.

Further, the data input to the spatial decoder can be provided as bytes of coded data or in data tokens (section A.10.
See "Coded data entry"). Providing the token via an encoded data port or microprocessor interface allows many features of the decoder chip set to be composed of the data stream. This provides an alternative to performing configuration via a microprocessor interface.

[0515]

[Table 1]

[0516]

[Table 2] A. 3.4 Token Description This section details the tokens implemented in the spatial and temporal decoder chips according to the present invention. Note: "r" means bit currently reserved,
And the value is 0. Unless otherwise specified, all integers are unsigned.

[0517]

[Table 3]

[0518]

[Table 4]

[0519]

[Table 5]

[0520]

[Table 6]

[0521]

[Table 7]

[0522]

[Table 8]

[0523]

[Table 9]

[0524]

[Table 10]

[0525]

[Table 11] A. 3.5 "Number sent in token" 3.5.1 “Component ID Number” A component ID number according to the present invention is a 2-bit integer that specifies a color component. This 2-bit field is generally
It is placed as part of the header in the data token. MPEG, and H.264. In the case of H.261, the correlation is very simple.

[0526]

[Table 12] The color components that can be used in JPBG are not limited.
In the case of PEG, the conditions are more complicated. The decoder chip allows up to four different color components in each scan. As color component specifications arrive at the decoder, IDs are assigned sequentially.

A. 3.5.2 "Number of horizontal and vertical samplings" For each of the four types of colors, there is a specification regarding the number of blocks arranged horizontally and vertically in a macroblock. This specification includes two-bit integers that are one less than the number of blocks containing a two-bit integer. For example, 4: 2: 0 in MPEG (or H.261)
Table 1 shows the array of component IDs for chroma sampling (FIG. 45).
3 is shown.

[0528]

[Table 13] For JPEG and 4: 2: 2 chroma sampling,
The component assignment to the component ID differs depending on the application. Section A. See 3.5.1.

Note: When processing 4: 2: 2 data, JPEG applies 2:
Requires a 1: 1 structure.

[0530]

[Table 14] A. 3.6 "Special Token Format" According to the present invention, for example, data token and QUAN
T-table tokens are used for their "extended form" within the decoder chip set. In the extended form, the token contains some data.
In the case of a data token, such a token may include coded data or pixel data. Q
For UANT table tokens, these tokens include quantizer table information.

[0531] Furthermore, the "non-extended form" of these tokens
Is defined as "empty" in the present invention.
This token format provides a place in the token stream that is subsequently filled by an extended version of the same token. This format is mainly applicable to encoders, and therefore will not be described in further detail.

[0532]

[Table 15]

[0533]

[Table 16] A. 3.7 Use of Tokens for Different Standards Each standard uses a different subset of tokens defined according to the invention.

Section A. 4 "2-wire interface" A. 4.1 "Two-Wire Interface and Token Port" In the chip set, a simple two-wire enable / accept protocol is used to control the flow of information.
Data is simply transferred between blocks when it is observed that the transmitter and the receiver are ready for clock generation.

1) Data transfer 2) The receiving side is not ready 3) The transmitting side is not ready If the transmitting side is not ready (3) the transmitting side is ready If not, the receiver must wait for input. If the receiver is not ready (above 2) the receiver is not ready), the sender continues to supply the same data to its output until it is accepted by the receiver.

When token information is transferred between blocks, the two-wire interface between blocks is called a token port.

A. 4.2 "Location of use" The decoder chip set according to the invention uses a two-wire interface to connect three chips. Further, the encoded data input to the spatial decoder is also a two-wire interface.

A. 4.3 "Bus Signals" The width of the data words transferred by the 2-wire interface varies depending on the needs of the interface concerned (see Figure 44 "Tokens on interfaces wider than 8 bits"). For example, a 12-bit coefficient is only 9
By simply outputting bits, a discrete inverse cosine converter (ID
CT).

[0539]

[Table 17] In addition to the data signals, there are three other signals sent over the two-wire interface.

* Valid signal (valid) * Accept signal (accept) * Extension signal (extension) 4.3.1 “Extension signal” The extension signal corresponds to the token extension bit described above.

A. 4.4 Design Considerations The 2-wire interface is for short-range, inter-chip serial communication.

The decoder chips must be placed close to each other to minimize the length of the PCB track between the chips. Wherever possible, the length of the truck must be kept below 25 mm. PCB track capacitance must be kept to a minimum.

The clock distribution must be designed to minimize clock through between chips. If there is any clock through, the "receiving chip" must be arranged so that the clock is seen before the "transmitting chip".

All chips communicating over the two-wire interface must operate from the same digital power supply.

A. 4.5 “Interface timing”

[0546]

[Table 18] Note: FIG. 47 shows a two-wire interface between the system demux chip and the coded data port of the spatial decoder operating from the main decoder clock. This is optional because the two-wire interface can operate from a coded data clock that can be asynchronous to the decoder clock. Section A. See 10.5, "Coded Data Clock". Similarly, the display interface of the image formatting unit can operate from a clock that is asynchronous to the main decoder clock.

A. 4.6 "Signal Level" The 2-wire interface uses COMS inputs and outputs. VIHmin is about 70% of VDD, and VILmax is VIL
About 30% of DD. The values shown in Table 19 are the values of VIH and VIL when VDD is the worst. VDD = 5.0
± 0.25V.

[0548]

[Table 19] A. 4.7 "Control Clock" Generally, the clock that controls the transfer via the two-wire interface is the decoder clock of the chip. The coded data port input to the spatial decoder is an exception. This is controlled by the encoding clock. The clock signal will be further described here.

Section A. 5 "DRAM interface" 5.1 "DRAM Interface" One single high performance, configurable DRAM interface is used in each video decoder chip. Generally, the DRAM interface on each chip is substantially the same. However, the interfaces differ from each other in the way they handle channel priority. The interface is the DRA used by each decoder chip
It is designed to drive M directly. In general,
External logic, buffers, or components are DR
DR interface on most systems with AM interface
Not required to connect to M.

A. 5.2 "Interface signal"

[0551]

[Table 20] According to the invention, the interface can be configured in two ways:

* For the detailed timing of the interface,
It can be configured to accommodate a variety of different types of DRAM.

* The "width" of the DRAM interface is
Configurable to provide cost / performance tradeoffs in different applications.

A. 5.3 "DRAM Interface Configuration" Generally, there are three groups of registers associated with the DRAM interface: the interface timing configuration register, the bus configuration register, and the refresh configuration register. . The registers shown in the refresh configuration register table 23 must be configured last.

A. 5.3.1 "Conditions after reset" After reset, the DRAM interface according to the invention starts operation with a set of default timing parameters (corresponding to the slowest mode of operation). Initially, the DRAM interface continuously performs refresh cycles (except for all other transfers). This continues until the value is entered in the refresh interval. The DRAM interface can then perform other types of transfers between refresh cycles.

A. 5.3.2 “Bus Configuration” Registers in bus configuration 22 should be made only if no data transfer by the interface has been attempted. The interface is
Immediately after reset and before the value is entered in the refresh interval, this condition is placed. The interface can later be reconfigured, if necessary, only if no transfer has been attempted. The temporal decoder chip access register (A.18.3.1) and the spatial decoder buffer manager access register (A.13.1.
See 1).

A. 5.3.3 Interface Timing Configuration According to the present invention, the modification of the interface timing configuration information is controlled by an interface timing access register. When 1 is written in this register, it is shown in the interface timing register 21)
Can be modified. While interface timing access = 1, the DRAM interface continues to operate with its previous configuration. 1
The user must wait until a 1 can be read back from the interface timing access before writing any interface timing registers after writing.

When the configuration is complete, the interface timing access must be filled with zeros. Next, the new configuration is transferred to the DRAM interface.

A. 5.3.4 "Refresh Configuration" The refresh interval of the DRAM interface according to the present invention can be configured only once after reset. Until the refresh interval is configured
The interface performs the refresh cycle continuously. This prevents any other data transfer. After the refresh interval has been filled, the data transfer can start.

As is well known in the art, DRAMs generally have a 1
It requires a "pause" between 00 and 500 microseconds, and is followed by a number of refresh cycles before normal operation is possible. Therefore, before filling in the refresh interval,
These DRAM start requirements must be met.

A. 5.3.5 "Read access to configuration registers" All DRAM interface registers of the present invention are readable.

A. 5.4 "Interface Timing (Tick)" DRAM interface timing is derived from a clock running at four times the input clock rate of the device (decoder clock). This clock is generated by an on-chip PLL.

For the sake of simplicity, the period of this high-speed clock is called a tick.

A. 5.5 “Interface register”

[0565]

[Table 21]

[0566]

[Table 22] A. 5.6 “Interface Operation” The DRAM interface uses the high-speed page mode. Three different types of access are supported.

* Read (read) * Write (write) * Refresh Each read or write access transfers one burst of 1 to 64 bytes to one single DRAM page address. Read and write transfers are not mixed within one single access, and each successive access is treated as a random access to a new DRAM page.

[0568]

[Table 23] A. 5.7 "Structure of Access" Each access has two parts.

* Access Start * Data Transfer In the present invention, each access begins with an access start and is followed by one or more data transfer cycles. In addition, there are read, write, and refresh variants (variants) for both access start and data transfer cycles.

Upon completion of the last data transfer for a particular access, the interface enters its default state (see A.5.7.3) and remains in this state until it is ready to start a new access. When the last access is completed and the new access is ready to start, the new access starts immediately.

A. 5.7.1 "Access Start" An access start provides a page address for a read or write transfer, and establishes some initial signal conditions. According to the invention, there are three different access starts.

* Start of reading * Start of writing * Start of refresh

[0573]

[Table 24] a; this value must be less than RAS falling to guarantee CAS before RAS refresh occurs. Table A. 5.5 DRAM Interface Timing Parameters In each case, the timing of the RAS and row address is
It is controlled by the register RAS falling and the page start length. The state of OE and DRAM data [31: 0] is RA
It is held until S drops. The three different types of access start differ only in the way they drive OE and DRAM data [31: 0] when RAS drops. Reference FIG.

A. 5.7.2 Data Transfer In the present invention, there are different types of data transfer cycles.

* Fast page read cycle * Fast page delayed write cycle (Fast page)
e refresh write cycle) * Refresh cycle The start of a refresh can only be followed by one single refresh cycle. The start of the read (or write) can be followed by one or more fast page read (or write) cycles. At the start of the read cycle, C
AS is driven high and the new column address is driven.

In addition, an early write cycle is used.
WE is driven low at the start of the first write transfer and stays low until the end of the last write transfer. The output data is driven by the address.

[0577] CAS before RAS refresh cycle
Is started by the start of the refresh cycle, so that the interface signals are inactive during the refresh cycle. The purpose of the refresh cycle is to meet the minimum RAS row period required by the DRAM.

A. 5.7.3 Interface Default State The interface signal in the present invention enters the default state at the end of the access.

[0579] RAS, C AS, and WE are high.

* Data and OE remain in their previous state.

* Addr maintains a stable state.

A. 5.8 “Data bus width” 2-bit register, DRAM data width is DR
Allows the width of the data path of the AM interface to be configured. This allows DRAM costs to be minimized when used in small picture formats.

[0583]

[Table 25] A. 5.9 "Row Address Width" The number of bits taken from the middle section of the 24-bit internal address to provide the row address is configured by the row address bit register.

[0584]

[Table 26] A. 5.10 "Address bits" An on-chip 24-bit address is generated. How this address is used to form the column and row addresses depends on the width of the data bus and the number of bits selected for the row address. Because some configurations do not allow all internal address bits to be used, "hidden bits" are created.

Similarly, the row address is extracted from the center part of the address. This therefore, the rate at which the DRAM is naturally riff Re' shoe is maximized.

[0586]

[Table 27] A. 5.10.1 "Low Order Row Address Bits" The least significant 4 to 6 bits of the row (column) address are used to provide up to 64 bytes of high-speed page mode transfer addresses. The number of address bits required to control these transfers depends on the width of the data bus (see A.5.8).

A. 5.10.2 “More DRAM
Row Address Decoding to Access Banks "If only one single bank of DRAM is used, the width of the row address used will be
Depends on the type of In general, for applications requiring more memory than can be provided by one single DRAM bank, it is possible to configure a wider row address, thus making one single DRAM bank Several row address bits can be decoded to select.

Note: The row address is extracted from the center of the internal address. To select a DRAM bank,
If some bits of the row address are decoded,
All the values that these "bank select bits" can take must select one bank of the DRAM. Otherwise, a hole is left in the address space.

A. 5.11 Enabling the DRAM Interface In the present invention, there are two ways to make all output signals on the DRAM interface high impedance. That is, a method of setting a DRAM enable register and a method of using a DRAM enable signal. In order for the driver on the DRAM interface to work, both these registers and signals must be logic ones. If either is low, the interface is high impedance.

Note: On-chip data processing is not terminated if the DRAM interface is high impedance. Thus, if the chip attempts to access the DRAM, an error will occur and at the same time the interface will be high impedance.

In accordance with the present invention, the ability to make the DRAM interface high impedance can be used to test other devices or, if the spatial decoder (or time decoder) is not in use, the spatial decoder (or time decoder). Is provided for using the DRAM controlled by. It is not intended that memory sharing by other devices be possible during normal operation.

A. 5.12 "Refresh" Unless disabled by writing to the no-refresh register, the DRAM interface will operate at the previous / RAS / refresh cycle at the interval determined by the register refresh interval.
Use CAS / to automatically refresh the DRAM. Here, / signal name / indicates an inverted signal of the signal.

The value in the refresh interval specifies the interval between refresh cycles within a period of 16 decoder clock cycles. The values in the range 1.255 are configurable. The value 0 is automatically loaded after reset, and
The DRAM interface forces continuous execution of the refresh cycle until a valid refresh interval is configured (once enabled). It is recommended that the refresh interval be configured only once after each reset.

When / reset / is asserted, D
The RAM interface makes it impossible to refresh the DRAM. However, the reset time required by the decoder chip is short enough,
Reset these decoder chips, and then
It would be possible to reconfigure the DRAM interface before the contents of the DRAM collapse .

A. 5.13 “Strength” The drive strength of the output of the DRAM interface is 3
It can be configured by the user using a bit register CAS strength, RAS strength, addr strength, DRAM data strength, and OEWE strength. The MSB of the 3-bit value selects either the high-speed or low-speed edge rate. The two less significant bits make up the output for different load capacitances.

[0596] The default strength after reset is 6,
And this means that when loaded with 24 pF, GND
And an output that requires about 10 ns to drive the signal between V DD and V DD.

[0597]

[Table 28] When the output is properly configured for the load it is driving, the output conforms to the AC electrical characteristics specified in Tables 32 through 35. If properly configured, each output will roughly match its load, and thus will experience minimal overshoot after signal transients.

A. 5.14 “Electrical Specifications” All information presented in this section is merely exemplary of the invention and is provided by way of example and not necessarily by way of limitation.

[0599]

[Table 29] Table 29 only shows the maximum ratings for the example.
Particularly for this embodiment only, stresses below the values shown in this table must be used to ensure operational reliability.

[0600]

[Table 30]

[0601]

[Table 31] A. 5.14.1 "AC characteristics"

[0602]

[Table 32]

[0603]

[Table 33]

[0604]

[Table 34]

[0605]

[Table 35] When reading from DRAM, the DRAM interface samples DRAM data [31: 0] as the / CAS / signal rises.

[0606]

[Table 36] Section A. 6 "Microprocessor interface (MPI)" Standard byte-width microprocessor interface (M
PI) is used for all chips in the video decoder chip set. However, one of ordinary skill in the art will appreciate that microprocessor interfaces of other widths can be used as well. MPI operates synchronously with various decoder chip clocks.

A. 6.1 “MPI signal”

[0608]

[Table 37] A. 6.2 "MPI electrical specifications"

[0609]

[Table 38]

[0610]

[Table 39]

[0611]

[Table 40] A. 6.2.1 "AC characteristics"

[0612]

[Table 41]

[0613]

[Table 42] A. 6.3 “Interrupt” In the present invention, “event” is a term used to indicate an on-chip condition that a user may want to observe. The event may indicate an error or may be beneficial to the user's software.

There are two single bit registers associated with each interrupt, or "event". These are a condition event register and a condition mask register.

A. 6.3.1 "Condition Event Register" The condition event register is a 1-bit read / write register, the value of which is set to 1 by a condition occurring in the circuit. The register is set to 1 even if the condition is only temporary and has now passed. Thus, the register is guaranteed to remain set to 1 (or the entire chip is reset) until reset by user software.

* The register is set to zero by writing a value of one.

* By writing zero in the register,
Leave registers unchanged.

* The register must be set to zero by the user software before this condition occurs once more.

* Registers will be reset to zero on reset.

A. 6.3.2 Condition mask register The condition mask register is a 1-bit read / write register that enables the generation of an interrupt request when the corresponding condition event register is set. If a condition event has already been set, an interrupt request is issued immediately when 1 is written in the condition mask.

* Value 1 enables interrupts.

* Registers are cleared to zero on reset.

[0624] Unless otherwise stated, blocks are:
Stop operation after generating the interrupt request, and resume operation after either the condition event or the condition mask register is cleared.

A. 6.3.3 Event and Mask Bits Event bits and mask bits are always arranged in groups at corresponding bit positions in consecutive bytes in the memory map (see Table 61, Table 141). this is,
To identify which event generated the interrupt,
Enables interrupt service software to use the value read from the mask register as a mask as a mask for the value in the event register.

A. 6.3.4 Chip event and mask Each chip has one single global event bit that summarizes the event activity on the chip. The chip event register provides an OR of all on-chip events with 1 in their mask bits.

A 1 in the chip mask bit allows the chip to generate an interrupt. A 0 in the chip mask bit prevents any on-chip event from generating an interrupt request.

[0627] Writing 1 to 0 in the chip event has no effect. The chip is only cleared if all events (activated by writing either 1 to one of the mask bits) are cleared.

A. 6.3.5 "irq signal" The / irq / signal is asserted when both the chip event bit and the chip event mask are set.

The / irq / signal is an active-low open-collector output that requires an off-chip pull-up resistor. If active, / irq / output is 1
Pulled down by an impedance of 00 ohms or less.

It should be appreciated that for most applications, a pull-up resistor of about 4 kOhm is suitable.

A. 6.4 "Access to Registers" 6.4.1 "Stopping Circuit Enabling Access" Most registers in the present invention can be modified only when the block to which the register relates is stopped. Accordingly, groups of registers are generally associated with access registers.

A value of 0 in an access register indicates that the group of registers associated with the access register must not be modified. Writing a 1 to the access register requests that the block be stopped. However, the block does not have to stop immediately, and the access register of the block holds the value 0 until the block stops.

[0633] Thus, the user software should wait (after writing a 1 to request access) until a 1 is read from the access register. When the access register is set to 0 and the user writes a value in the configuration register,
The results are undefined.

A. 6.4.2 "Register holding integer" The least significant bit of any byte in the memory map is the bit associated with signal data [0].

A register holding an integer value greater than 8 bits is divided over any two or four consecutive byte positions in the memory map. The byte order is "big endian" as shown in FIG. However, no assumptions are made regarding the order in which bytes not made for an order are written to the multi-byte register.

[0636] Unused bits in the memory map excluding unused bits in the register holding the signed integer return 0 upon reading. In this case, the most significant bit in the register is sign-extended. For example, a signed 12-bit register is sign-extended to fill a 16-bit memory map location (2 bytes). A 16-bit memory map location holding an unsigned 12-bit integer returns 0 from its most significant bit.

A. 6.4.3 "Keyhole Address Location" In the present invention, the memory map location with a low access frequency is located behind the "keyhole". A "keyhole" has two registers associated with it: a keyhole address register and a keyhole data register.

The keyhole address specifies a position in the expanded address space. A read or write operation to the keyhole data register accesses the location specified by the keyhole address register.

The associated keyhole address register increments after accessing the keyhole data register. Random access within the expanded address space is only possible by writing a new value to the keyhole address register for each access.

A chip according to the present invention may have more than one "keyhole" memory map. There is no interaction between the different keyholes.

A. 6.5 "Special registers" 6.5.1 “Unused registers” Registers or bits marked “not used” are locations in the memory map that were not used to implement the device. In general, the value 0 can be read from these positions. Writing 0 in these positions has no effect.

As will be appreciated by one of ordinary skill in the art, in order to maintain compatibility with future variants of this type of product, the user's software must read from an unused location. It is recommended that you do not rely on the values given. Similarly, when configuring the device, this type of location should be avoided or
Should be set to the value 0.

A. 6.5.2 Reserved Registers Similarly, registers or bits described as "reserved" in the present invention have no documented effect on the operation of the device.

A. 6.5.3 “Test Registers” Further, registers or bits described as “test registers” control various aspects of the testability of the device. Therefore, these registers are not used for standard use of the device and need not be accessed by standard device configuration and control software.

Section A. 7 "Clocks" In accordance with the present invention, many different clocks are identifiable in video decoder systems. An example of a clock
As shown in FIG.

Data is resynchronized (on-chip) with each new clock as it feeds between different clock regimes in the video decoder chip set.
In the present invention, the maximum frequency of any input clock is 30 MHz. However, those of ordinary skill in the art should understand that other frequencies, including frequencies greater than 30 MHz, can be used as well. In each chip, the microprocessor interface (MPI) operates asynchronously with respect to the chip clock. Further, the image formatting unit can generate a low-frequency audio clock synchronized with the picture rate of the decoded moving image. Thus, this clock can be used to provide audio / video synchronization.

A. 7.1 "Spatial decoder clock signal" The spatial decoder has two different (and possibly asynchronous) clock inputs.

[0648]

[Table 43] A. 7.2 "Time decoder clock signal" The time decoder has only one clock input.

[0649]

[Table 44] A. 7.3 “Electrical Specifications”

[0650]

[Table 45]

[0651]

[Table 46] Table A. 7.4 Clock input condition 7.3.1 "CMOS level" The clock input signal is a CMOS input. VIHmin
Is about 70% of VDD and VILmax is V
It is about 30% of DD. The values shown in Table 46 are
These are the values of VIH and VIL under the worst condition of DD.
VDD = 5.0 ± 0.25V A. 7.3.2 "Clock Stability" In the present invention, the clock used to drive the DRAM interface and the chip-to-chip interface is derived from the input clock signal. Timing specifications for these interfaces assume that the input clock timing is stable in the following range of ± 100 ps.

Section A. 8 "JTAG" As the density of circuit board installation increases, it is not possible to inspect the connections between components by conventional methods, such as in-circuit testing using "bed-of-nails" techniques. It becomes increasingly difficult. In an attempt to solve the access problem and standardize the methodology, the Joint Test Action Group (JTAG) was formed. The culmination of this group's work is the "Standard Test Access Port and Boundary Scan Architecture" now adopted by the IEEE as Standard 1149.1. Spatial and temporal decoders conform to this standard.

The standard utilizes a boundary scan chain that connects each digital signal pin on the device in series. The test circuit is responsive (transparent) under normal operating conditions, but in the test mode the boundary scan chain allows the test pattern to be shifted in and
Enable to supply to device pins. The resulting signal appearing on the circuit board at the input to the JTAG device can be scanned and checked by relatively simple test equipment. With this method, the connection between components as well as the logic area on the circuit board can be tested.

All JTAG operations are performed through a test access port (TAP) having five pins. The trst (test reset) pin resets the JTAG circuit to ensure that the device does not power up in test mode. tck
The (test clock) pin clocks the clock serial test pattern to the tdi (test data input) pin,
It is used to clock from the tdo (test data output) pin. Finally, the mode of operation of the JTAG circuit is set by clocking the appropriate bit sequence to the tms (test mode select) pin.

The JTAG standard is extensible to provide additional features at the discretion of the chip manufacturer. The spatial and temporal decoders have nine user instructions, including three JTAG mandatory instructions. Additional instructions (extra line instructions)
It allows for performing a certain degree of internal device testing and provides additional external testing flexibility. For example, all device outputs can be created to float with a simple JTAG sequence.

For details on the available functions and how to use the JTAG port, refer to the individual JTAG application notes.

A. 8.1 "JTAG pin connection in non-JTAG systems"

[0658]

[Table 47] A. 8.2 "Conformance level to IEEE 1149.1" 8.2.1 Rules The following clauses are noted, but all rules apply.

[0659]

[Table 48]

[0660]

[Table 49] A. 8.2.2 "Recommended conditions"

[0661]

[Table 50]

[0662]

[Table 51] A. 8.2.3 "Permission conditions"

[0663]

[Table 52] Section A. 9 "Spatial decoder" * 30 MHz, operation * Decoders MPEG, JPEG, and H.264 26l * Coded data rate up to 25Mb / s * Video data rate up to 21MB / s * Flexible chroma sampling format * All JPEG baseline decoding * Glueless DRAM interface * Single + 5V power supply * 208 pin PQFP package * Maximum consumption 2.5 W power * Independent coded data and decoder clock * Uses standard page mode DRAM Spatial decoders are available in a variety of JPEG, MPEG, and H.264.
Configurable VLSI decoder chip for use in H.261 picture and video decoding applications.

In a minimal configuration without off-chip DRAM, the spatial decoder is one single-chip, high-speed JPEG decoder. DRAM
To allow the spatial decoder to decode the JPEG encoded video. 720 × 480, 3
0 Hz, 4: 2: 2 “JPEG moving image” can be decoded in real time.

By using a temporal decoder, the spatial decoder can 26l, and MPEG (also JPE
G) can be used to decode 704x480,
30 Hz, 4: 2: 0 MPEG moving pictures can be decoded.

The foregoing values are merely examples and are provided by way of example, not necessarily with any limiting intent, and are again typical of one embodiment of the present invention. Please note. Thus, one of ordinary skill in the art will appreciate that other values and / or can be used.

A. 9.1 "Spatial decoder signal"

[0668]

[Table 53]

[0669]

[Table 54]

[0670]

[Table 55]

[0671]

[Table 56]

[0672]

[Table 57] A. 9.1.1 ““ nc ”Non-Connected Pins” In Table 57, the pins labeled nc represent pins that are not currently used. These pins must be left unconnected.

A. 9.1.2 "VDD, and GND pins" As will be appreciated by ordinary skill in the art, all of V _DD and GND pins are equipped, have to be connected to the respective corresponding power supply Must. As long as all V _DD and GND pins are not used correctly, the correct operation of the device is not possible guarantee.

A. 9.1.3 Connection of test pins for normal operation The nine pins of the spatial decoder are reserved for internal testing.

[0675]

[Table 58] A. 9.1.4 JTAG pins for normal operation Section A. See 8.1.

A. 9.2 “Spatial decoder memory map”

[0677]

[Table 59]

[0678]

[Table 60]

[0679]

[Table 61]

[0680]

[Table 62]

[0681]

[Table 63]

[0682]

[Table 64]

[0683]

[Table 65]

[0684]

[Table 66]

[0685]

[Table 67]

[0686]

[Table 68]

[0687]

[Table 69]

[0688]

[Table 70]

[0689]

[Table 71]

[0690]

[Table 72]

[0691]

[Table 73]

[0692]

[Table 74]

[0693]

[Table 75]

[0694]

[Table 76]

[0696]

[Table 77]

[0696]

[Table 78]

[0697]

[Table 79]

[0698]

[Table 80]

[0699]

[Table 81] Section A. 10 "Coded Data Input" The system according to the present invention must know which moving picture standard is being input for processing. From now on, the system can accept either pre-existing tokens or raw byte data. This raw byte data can then be placed in the token by a start code detector.

Therefore, the coded data and the configuration token can be supplied to the spatial decoder through the following two routes.

* Coded Data Input Port * Microprocessor Interface (MPI) The choice of the route to use depends on the application and system environment. For example, if the data rate is low, both for controlling the decoder chip set and for multiplexing the system bitstream,
It is possible to use one single microprocessor. In this case, it is possible to input the coded data via the MPI. Alternatively, if the coded data rate is high, the coded data must be provided via a coded data port.

For some applications, it may be appropriate to use a mixture of MPI and coded data port inputs.

A. 10.1 "Coded data port"

[0704]

[Table 82] The coded data port according to the present invention can be used in two modes: token mode and byte mode.

A. 10.1.1 "Token Mode" In the present invention, when the byte mode is low,
The coded data port operates as a token port in the normal manner, and accepts tokens under control of coded enable and coded accept. See Section A. for details on the electrical operation of this interface. See No. 4.

[0706] In the signal byte mode, data [7: 0],
At the same time as the encoding extn and the encoding validity,
Sampled on the rising edge of the coded clock.

A. 10.1.2 "Byte mode" where byte mode is high, however, one byte of data is the data [7:
0]. In this case, the encoded extn
Is ignored. Subsequently, the bytes are assembled on-chip into data tokens until the time the input mode is changed.

1) First word (head) of token supplied in token mode 2) Last word of supplied token (coded ex
tn goes low) 3) First byte of data provided in byte mode. New data tokens are created automatically on-chip.

A. 10.2 Supply of Data via MPI The token can be supplied to the spatial decoder via MPI by accessing the coded data input register.

A. 10.2.1 Entry of Token via MPI The coded data registers of the present invention are grouped into two bytes in the memory map to allow efficient data transfer. The 8 data bits, coded data [7: 0] are located in one place, and the control register, coded visual, enable mpi input, and coded extn are located in another place. Table 62,
See Table 63).

If configured for token entry via MPI, each time a value is entered into coded data [7: 0], the current token is extended with the current value of coded extn. . It is the software's responsibility to set the coded extn to 0 before the last word of every token is written into the coded data [7: 0].

For example, the data token is encoded ex
1 for tn and 0x04 for coded data [7: 0]
Start by filling in The start of this new data token then feeds the spatial decoder for processing.

Each time a new 8-bit value is entered into coded data [7: 0], the current token is extended. Only when ending the current token, for example to introduce another token, the coded extn needs to be accessed again. The last word of the current token is encoded ext followed by the entry of the last word of the current token into the coded data [7: 0].
Indicated by a zero entry into n.

[0714]

[Table 83] Prior to coded data [7: 0], each time the coded busy must be examined to determine if the interface is ready to accept more data.

A. 10.3 Switching between input modes It is possible to change the data input mode dynamically, provided that appropriate precautions are taken. Generally, the transfer of a token via any one route must be completed before switching mode.

[0716]

[Table 84] With the first byte provided in byte mode, a data token header can be generated on-chip. All bytes transferred further in byte mode will be appended to this data token until the input mode changes. Recall that a data token can include as many bits as needed.

The MPI register bit, coded Biz,
And the signal, coded accept, indicate at which interface the spatial decoder is trying to accept data. Observing these signals correctly ensures that no data is lost.

A. 10.4 "Acceptance Rate of Coded Data" In the present invention, the input circuit supplies a token to the start code detector (see Section A.11). The start code detector analyzes the data serially as data token bits. The normal processing rate of the detector is
One bit per clock cycle (of the coded clock). Therefore, the decoder uses the coded clock
1 byte of the coded data is decoded every eight cycles. However, additional processing cycles may be required, such as when a non-data token is supplied or when a start code appears in the coded data. If such event occurs, the start code detector, over a short period of time, that Do impossible to accept any more information.

After the start code detector, the data is provided to a first logic coded data buffer. If this buffer becomes full, the start code detector will not be able to accept any more information.

[0720] Thus, more coded data (or other tokens) may be accepted at the coded data port or via the MPI. in this case,
The start code detector remains unable to accept any more information. This is indicated by the state of signal coded accept and register coded busy.

The use of coded accept and / or coded busy ensures that no coded information is lost for the user. However,
A person of ordinary skill in the art, if the spatial decoder cannot accept the data, the system may buffer the newly arriving coded data, or (or
Stop the arrival of new data).

A. 10.5 "Coded Data Clock" In accordance with the present invention, the coded data port, input circuits, and other functions in the spatial decoder
controlled by k. Further, this clock may be asynchronous with respect to the main decoder clock. Data transfer is synchronized with the on-chip decoder clock.

Section A. 11 "Start code detector" 11.1 "Start Code" As is well known in the art, MPEG and H.264. The H.261 coded video stream includes an identifiable bit pattern called a start code. JPEG
, A similar function is provided by a marker code. The start / marker code identifies a significant part of the syntax of the coded data stream. The analysis of the start / marker code performed by the start code detector is the first step in parsing the coded data. The start code detector is the first block in the spatial decoder following the input circuit.

The start / marker code pattern is designed to be identifiable without decoding the entire bitstream. Thus, the start / marker code pattern can be used to aid error recovery and decoder start according to the present invention. The start code detector detects an error in the coded data structure,
Then, a function for assisting the start of the decoder is provided.

A. 11.2 Start Code Detector Registers As discussed above, a number of start code detector registers are always used by the start code detector. Therefore, accessing these registers is less reliable when the start code detector that processes the data is processing the data. It is the user's responsibility to ensure that the start code detector stops prior to accessing the register.

Register start codeDetector access
Stops the start code detector and, consequently,
Used to allow access to registers.
Start code detector stops after generating interrupt
I do.

With respect to when the start code search and all data mode discards can be initiated,
There are further constraints. For these constraints,
A. 11.8, and A.I. It has been described in 11.5.1.

[0728]

[Table 85]

[0729]

[Table 86]

[0730]

[Table 87]

[0731]

[Table 88]

[0732]

[Table 89]

[0733]

[Table 90] A. 11.3 "Start Code to Token Conversion" The function of the start code detector in normal operation is to identify the start codes in the data stream and then convert these codes to the corresponding start code token. It is to be. In the simplest case, the data is provided to the start code detector as one long single data token. The output of the start code detector is a number of shorter data tokens with the start code token interrupted.

Alternatively, according to the present invention, the input data to the start code detector can be divided into a number of shorter data tokens. Regarding how to divide the coded data into data tokens, where n is an integer,
There is no restriction other than that each data token must include 8xn bits.

Other tokens can be supplied directly to the input of the start code detector. In this case, the token is provided without processing to the other stages of the spatial decoder via the start code detector. These tokens can be inserted only immediately before the start code position in the coded data.

A. 11.3.1 Start Code Format According to the start code detector of the present invention, three different start code formats are recognized. This is configured via a register start code detector coding standard.

[0737]

[Table 91] A. 11.3.2 Start Code Token Equivalent Upon detecting a start code, the start code detector considers the value associated with the start code and generates an appropriate token. Generally, the token is
Named after related MPEG syntax. However, one of ordinary skill in the art will understand that tokens follow an additional naming format. The currently selected coding standard constitutes the relationship between the start code value and the generated token. This relationship is shown in Table 92.

[0738]

[Table 92] A. 11.3.3 Enhancements to the coding standard The coding standard provides a number of mechanisms that allow the embedding of data into data streams whose use has not been determined by the coding standard. This can be viewed as a specific "user data" application that provides additional ease of use to a particular manufacturer, and can instead be viewed as "extended data".
The coding standard authority has reserved the right to use extended data to add functionality to the coding standard in the future.

[0739] Two obvious mechanisms are used. J
In PEG, a marker code precedes a user and a block of extended data. However, H. At 261, “additional information” indicated by additional information bits in the coded data is inserted. In MPEG, both of these technologies can be used.

According to the present invention, MPEG / user / extension data preceded by a start / marker code
JPEG blocks can be detected by a start code detector. H. 261 / MPEG “Additional Information”
Is detected by the Huffman decoder of the present invention.
A. See 14.7 “Receiving additional information”.

The register, discard extension data, and discard user data can configure the start code detector to discard user data and extension data. If this data is not discarded by the start code detector, it can be accessed when it reaches the video demux. A. l4.6, "Reception of user and extension data"
Please refer to.

The spatial decoder of the present invention supports the JPEG baseline function. The JPEG non-baseline function is considered as extended data by the spatial decoder. Therefore, for a non-baseline JPEG, all JPEs that precede the data
The G marker code is treated as extension data.

A. 11.3.4 JPEG Table Definition JPEG supports downloaded Huffman and Quantizer tables. In JPEG data, these table definitions are preceded by marker codes DNL and DQT. The start code detector generates tokens DHTMMARKER and DQTMMARKER when these marker codes are detected. These tokens indicate to the video demux that the subsequent data token contains coded data describing a Huffman or quantizer table (using the format described in JPEG).

A. 11.4 "Error Detection" The start code detector is capable of detecting certain errors in the coded data and provides some functionality that allows recovery by the decoder after errors are detected. (See A.11.8, “Searching for a Start Code”).

A. 11.4.1 “Illegal JPEG Length Counting” Most JPEG marker codes have 16 associated with them.
Has a bit length count field. This field indicates how much data is associated with this marker code. Length counts of 0 and 1 are invalid. Illegal lengths only occur when following a data error. In the present invention, if the illegal length count mask is set to one, the occurrence of an incorrect length generates an interrupt.

It is presumed that recovery from an error in JPEG data requires additional application specific data because it is difficult to search for a start code in JPEG. Paragraph A. 11.8.1
reference).

A. 11.4.2 "Start / Marker Code Duplication" In the present invention, start code duplication occurs only when a data error follows. FIG. 73 shows the MPEG sequence byte duplication start code. In this case, the start code detector first looks at a pattern that looks like a picture start code. Next, the start code detector sees that this picture start code overlaps with the group start. Accordingly, the start code detector generates a duplicate start event. Furthermore,
If the overlapping start mask is set to 1, the start code detector will generate an interrupt and stop.

It is not possible to determine which of the two start codes is correct and which cause the data error was. However, the start code detector according to the present invention discards the first start code,
Then, after the duplicate start code event has been serviced, the second "as the second start code is correct"
Continue decoding the start code of. If there is a sequence of duplicate start codes, the start code detector discards all these codes except the last code (generates an event for each duplicate start code).

A similar error is possible in non-aligned byte systems (H.261, or perhaps MP
EG). In this case, the state of the Ignore / Non-alignment must be considered as well. FIG. 74 shows that the first start code found is an array byte, but
An example in which a non-sequence start code overlaps is shown. Ignore
If the non-alignment is set to 1, the second duplicate start code is treated as data by the start code detector. Therefore, no duplicate start code event occurs. This hides any data communication errors that may have occurred. If Ignore / Non-align is set to 0, the start code detector looks at the second non-aligned start code. And see that it overlaps with the first start code.

A. 11.4.3 "Unrecognized start code" The start code detector can generate an interrupt if an unrecognized start code is detected (if unrecognized start mask = 1). The start code value that caused this interrupt can be read from the register start value.

The start code value 0xB4 (sequence error) is used in the MPEG decoder system to indicate a channel error or a media error.
For example, when an uncorrectable error is detected, the start code may be inserted into data by the ECC circuit.

A. [0753] 11.4.4 Event Generation Order In the present invention, certain coded data patterns (often indicative of error conditions) cause one or more of the aforementioned error conditions to occur in a short period of time. Therefore, the following describes the order in which the start code detector checks the coded data for error conditions.

1) Non-Sequence Start Code 2) Duplicate Start Code 3) Unrecognized Start Code Therefore, if a non-sequence start code overlaps with the other later start code, the first event generated is , Associated with a non-sequenced start code. After this event has been serviced, the operation of the start code detector continues, and after a short period of time a duplicate start code is detected.

After all non-sequenced and duplicate start code tests have been completed, the start code detector simply attempts to recognize the start code.

A. 11.5 "Starting and Stopping the Decoder" The start code detector allows the current decoding task to be completed completely and provides the ability to start a new task.

There are limitations to using these techniques with JPEG coded video since data segments can contain values that emulate marker codes (see A.11.8.1).

A. 11.5.1 Clear Termination of Decoding Once the data for the current picture is complete, the start code detector can be configured to generate an interrupt and stop. This is done by setting stop after picture = 1 and stop after picture mask = 1.

Once the end of the picture has provided the start code detector, a flash token is generated (A.E.
11.7.2), an interrupt is generated and the start code detector stops. Note that the just completed picture is decoded in the usual way. In some applications, it may be appropriate to detect the flash arriving at the output of the decoder chip set. The arrival of this output indicates the end of the current video sequence. For example, the display could stick to the last picture output.

When the start code detector stops, there may also be data from an "old" video sequence that is "trapped" in a buffer implemented by the user between the media and the decode chip. Register discar
Setting the dall data causes the spatial decoder to consume this data and discard it. This continues until the flash token reaches the start code detector or until the discardall data is reset via the microprocessor interface.

If any data from the "old" sequence is discarded, at this stage the decoder is ready to begin operation according to the new sequence.

A. 11.5.2 "Discard All Modes (dis
card) start timing "Immediately after 1 is written in the discard data register, discarding of all modes starts. If this is done when the start code detector is actively processing data, the results are unpredictable.

After any of the start code detector events (such as a non-aligned start event) have generated an interrupt, all mode discards can be safely initiated.

A. 11.5.3 Start of New Sequence If it is not known where in a coded data a new coded video sequence starts, a start code search mechanism can be used. This mechanism discards any unnecessary data preceding the start of the sequence. A. See 11.8.

A. [0764] 11.5.4 "Jump between sequences" This section shows applications of some of the techniques described above. The purpose is to "jump" from one part of one coded video sequence to another. In this example, the filing system only allows access to "blocks" of data.
This block structure can also be derived from the sector size of the disk or block error correction system. Therefore, the positions of the entrance and the exit in the coded moving image data may not be related to the filing system block structure.

[0765] Stop after picture and disca
The rdall data mechanism allows for discarding unnecessary data from old video sequences. After the end of the last filing system data block, the discardall data mode is reset by inserting a flash token. Next, the start code search mode is used to discard any data in the next data block preceding the appropriate entry.

A. 11.6 Alignment of Bytes As is well known in the art, different coding schemes have quite different views on byte alignment of start / marker codes in a data stream. For example,
H. H.261 sees the communication as a serial bit. Therefore, there is no concept regarding the byte alignment of the start code. By setting Ignore / Non-align = 0, the start code detector can detect a start code having an arbitrary bit alignment. By setting the non-aligned start mask = 0, a start code non-arrangement interrupt is suppressed.

However, in contrast, JPEG is
Designed for computer environments where byte alignment is guaranteed. Therefore, the marker code should only be detected if the bytes are aligned. Coding standard is JP
When configured as an EG, the Ignore Non-Align Register is ignored, and a non-aligned start event is never generated. However, to ensure compatibility with future products, it is recommended to set Ignore / Non-align = 1 and Non-align start mask = 0.

[0768] MPEG, on the other hand, was designed to meet the needs of both communications (serial bit) and computer (byte-oriented) systems. Start codes in MPEG data must usually be aligned bytes. However, the standard is designed to allow a serial bit search for the start code (the MPEG bit pattern does not look like a start code for any bit alignment unless it is a start code) ). Thus, MPEG decoders can be designed to tolerate loss of byte alignment in serial data communications.

If a non-aligned start code is found, it usually indicates that a communication error has already occurred.
If the error is a "bit-slip" in a serial bit communication system, the data containing the error has already been provided to the decoder. It is speculated that this error may cause other errors in the decoder. However, new data arriving at the start code detector can subsequently be decoded after this alignment has been lost.

By setting Ignore / Non-align = 0 and Non-align start mask = 1, an interrupt can be generated when a non-aligned start code is detected. Responsibilities depend on the application. All subsequent start codes are unaligned (until byte alignment is restored). Thus, it may be appropriate to set non-aligned start mask = 0 after byte alignment is lost.

[0771]

[Table 93] A. 11.7 Automatic Generation of Tokens In the present invention, most of the tokens output by the start code detector directly reflect the syntax elements of various picture and video coding standards. In addition to these "natural" tokens, some useful "invented" tokens are generated. Examples of these proprietary tokens are picture end, and coding standards. In addition, tokens are introduced to remove some syntactic differences between coding standards and to order under error conditions.

This automatic token generation is performed after the serial analysis of the coded data (see FIG. 70, "Start Code Detector"). Thus, the system responds equally to tokens supplied directly to the input of the spatial decoder via the start code detector and tokens generated by the start code detector following detection of the start code in the coded data.

A. 11.7.1 "End of Picture Indication" In general, coding standards do not explicitly transmit the end of a picture. However, when the start code detector of the present invention detects information indicating that the current picture is completed,
Generate a picture end token. The token that causes the picture end to be generated is shown below. Sequence start, group start, picture start, sequence end, and flash.

A. 11.7.2 "Stop after picture end option" If the register stop after picture is set, the start code detector stops after supplying the picture end token. However, the flash token is inserted after the picture end to "push" the end of the coded data through the decoder and reset the system. A. 11.
See 5.1.

A. 11.7.3 “Introduction of sequence start for H.261” 261 has no syntax element equivalent to a sequence start (see Table 92). If the insert sequence start register is set, the start code detector ensures that there is one sequence start token before the next picture start, i.e. the start code detector is If it does not see a sequence start, one token is introduced. If one already exists, no sequence start is introduced.

This function must not be used with MPEG or JPEG.

A. 11.7.4 "Setting the coding standard for each sequence" All sequence start tokens leaving the start code detector are always preceded by a coding standard token. This token is loaded with the current encoding standard for the start code detector. this is,
Set the encoding standard for the entire decoder chip set for each new video sequence.

A. 11.8 Search for Start Code A start code detector according to the present invention can be used to search for a specific type of start code in a coded data stream. This allows the decoder to restart decoding from the specified level in some coded data syntax (after discarding any preceding data). The application for this is shown below.

* Start of the decoder after jumping to the coded data file at an unknown location (for example, for random access).

Search for known points in the data to aid recovery after a data error.

For example, Table 94 shows that M searched for a start code search of different configurations.
Indicates a PEG start code. Equivalent H. 26l and JP
The EG start / marker code can be found in Table 92.

[0782]

[Table 94] If a non-zero value is entered in the start code search, the start code detector will begin discarding all incoming data until the specified start code is detected. Next, the start code search register is reset to 0, and normal operation continues.

[0783] start code search, after the non-zero value has been entered in the start code search register, to start immediately. If this is done while the start code detector is actively processing data, the results are unpredictable. Therefore, before starting the start code search, the start code detector must be stopped so that no data has been processed. If any start code detector event (such as a non-aligned start event) has just completed generating an interrupt, the start code detector will always be at this condition.

A. 11.8.1 “Restrictions When Using Start Code Search with JPEG” Most JPEG marker codes have 16 associated with them.
Has a bit length count field. This field indicates the length of the data segment associated with the marker code. This segment may include a value that emulates a marker code. In normal operation, the start code detector does not look for a start code in these segments of data.

If random access to certain JPEG coded data "lands" on such a segment, the start code search mechanism cannot be used with high reliability. In general, JPEG coded video requires additional external information to identify the entrance for random access.

Section A. 12 "Decoder start control" 12.1 Overview of Decoder Start At the decoder, the moving picture display is usually displayed a short delay after the coded data is first available. During this delay, the coded data accumulates in a buffer in the decoder. By pre-filling the buffer in this way, it is ensured that the buffer is never empty during the decoding period, and thus that the decoder can decode new pictures at regular intervals. .

In general, two functions are required to start the decoder correctly. First, there must be a mechanism to measure how much data has been provided to the decoder. Second, there must be a mechanism to prevent the display of new video streams. The spatial decoder of the present invention includes a bit counter near its input to determine how much data has arrived, and to prevent a new video stream being output from starting. And an output gate near its output.

[0788] The complexity of controlling these functions is 3
There are two levels.

* Output gate is always open * Basic control * Advanced control By keeping the output gate always open, the picture output is output as soon as possible after the coded data starts to arrive at the decoder. Starts. this is,
Suitable when decoding still images or when the display is being delayed by some other mechanism.

The difference between the basic control and the advanced control is how many short video streams can be accommodated in the decoder buffer at any one time. Basic controls are sufficient for most applications. However, the advanced controls allow the user software to assist the decoder in managing the start of several very short video streams.

A. 12.2 “MPEG Moving Image Buffer Verifier” MPEG describes “moving image buffer verifier (VBV)” for a constant data rate system. VBV
Using the information allows the decoder to prefill its buffer before starting to display the picture. Again, this prefilling ensures that the decoder's buffer will never be empty during the decoding period.

In summary, each MPEG picture is a vbv
It has a delay parameter. This parameter is the first
Defines the time required for the coded data buffer of the "ideal decoder" to be filled with coded data before the next picture is decoded. Note the start delay for the first picture and automatically adapt to the requirements of all subsequent pictures.

[0793] MPEG therefore defines the requirement for a start as a delay. However, in a constant bit rate system, this delay can be easily converted to a bit count. This is the basis of the start control operation of the spatial decoder of the present invention.

A. 12.3 “Definition of Stream” In this application, the term stream is used to avoid confusion with the term sequence in MPEG. Thus, a stream refers to the amount of video data that is of interest to the application. Thus, one stream may be a number of MPEG sequences or one picture.

[0795] The decoder start function described in this chapter performs the VBV operation on the first picture in one stream.
Related to meeting requirements. The requirements of subsequent pictures in the stream are automatically adapted.

A. 12.4 “Start Control Register”

[0797]

[Table 95]

[0798]

[Table 96] A. 12.5 Normally Open Output Gate The output gate can be configured to remain open. This configuration is appropriate if the still image is being decoded, or if some other mechanism is available to manage the start of the video decoder.

The configuration required after reset is as follows (writing 1 to Startup Access gives access to the Start Control Logic):

* Set off-chip queue = 1 * Set enable stream = 1 * Ensure that all decoder start event mask registers are set to 0, disabling interrupts in those registers (this Is the default state after reset). (See A.12.7.1 for an explanation of why this holds the output gate open).

A. 12.6 "Basic Operation" In the present invention, basic control of the start logic is sufficient for most MPEG video applications. In this mode, the bit counter communicates directly with the output gate. When the end of the video stream provides an output gate, as indicated by the flash token, the output gate automatically closes. The gate remains closed until one enable is provided by the bit counter circuit when the stream has reached its start bit count.

The configuration required after reset is as follows (writing 1 to Startup Access gives access to Start Control Logic):

* Set bit count prescale for nearly the predicted range of coded data.

* To enable this error condition to be detected, a counter flushed too early mask = 1
Is set.

The following two interrupt service routines are required.

* Moving picture demultiplex service to obtain vbv delay value for first picture in each new stream.

* Counter fl for responding to this condition
used too early service.

When decoding the new video stream's vbv delay (ie, when the first picture arrives at the video demultiplexer after flashing), the video demultiplexer (aka video parser) can generate an interrupt. . The interrupt service routine must calculate the appropriate value for the bit count target and fill it in. When the bit counter reaches this goal, it inserts one enable into the short queue between the bit counter and the output gate. When the output gate opens, it removes one enable from this queue.

A. 12.6.1 “Start of new stream immediately after the end of another stream” As an example, an MPEG stream that is about to end
, And the MPEG stream to be started is called B. A flash token must be inserted after the end of A. This token pushes the last of the coded data through the decode, alerting the user that different sections of the decoder are expected to have new streams.

Normally, the bit counter has been reset to zero, and A is already in a state conforming to its start condition. After the flush, the bit counter starts counting bits in stream B. When the video demux has finished decoding the vbv delay from the first picture in stream B, an interrupt is generated, making the bit counter configurable.

As the flash marking the end of stream A passes through the output gate, the gate closes. The gate holds until B meets its starting conditions.
Keep closed. Depending on a number of factors, such as, for example, the start delay for stream B and the depth of the buffer, it is possible that B has already met its start condition when the output gate is closed. In this case, one enable is waiting in the queue, and the output gate opens immediately. Otherwise, stream B must wait until it meets its start requirements.

[0812] A. 12.6.2 "Consecutive Short Streams" The capacity of the queue, located between the bit counter and the output gate, allows the three individual video streams to meet their start conditions and to terminate decoding Is enough to allow you to wait for the previous stream. In the present invention, this condition only occurs if a very short stream is being decoded, or if the off-chip buffer is very large compared to the picture format being decoded.

In FIG. 78, stream A is being decoded, and the output gate is open. Streams B and C meet their start conditions and are completely contained in a buffer managed by the spatial decoder. Stream D is still arriving at the input of the spatial decoder.

[0839] The enables for streams B and C are in the queue. Thus, when stream A is completed, B can start immediately. Similarly, C can immediately follow B.

If D still meets the output gate while D meets its start goal, 1
One enable is added to the queue to fill the queue.
If no enable has been removed from the queue by the time the end of D passes the bit counter (ie, A is passing through the output gate), the new stream passes through the bit counter. I can't start. Since the output gate is open so that B can supply the output gate, the coded data is held up at the input until A is complete and one enable is removed from the queue.

A. [0816] 12.7 Advanced Operation In accordance with the present invention, advanced control of the start logic is based on A.I.
Enables user software to extend the length of the enablement queue without limitation as described in 12.6 “Basic Operation”. If the video decoder is A.
This level of control is only needed if a series of short video streams longer than described in 12.6.2 "Short Stream Continuation" must be accommodated.

[0827] In addition to the configuration required for basic operation of the system, after reset, the following configuration is required (by writing a 1 to the start up access, the Access).

* Off-chip queue = 1 is set.

* If one enable is removed from the queue, set Accept Enable Mask = 1 to enable interrupts.

If the bit count target of the stream has been reached, set the target met mask = 1 to enable interrupts.

The following two additional interrupt service routines are required.

* Enablement Interrupt * Target Achievement Interrupt When a target achievement interrupt target occurs, the service routine must add one enable to its off-chip enablement queue.

A. 12.7.1 Operation of the Output Gate Logic Writing 1 to the enable stream register loads one enable into the short queue.

[0824] Flag (to mark end of stream)
The gate closes as the cash passes through the output gate. If one available enable is at the end of the queue, the gate opens and generates an accept enable event. Accept enable mask is 1
If set, an interrupt can be generated and one enable removed from the end of the queue (the register enable stream is reset).

[0825] However, if the accept enable mask is set to zero, no interrupt is generated following the accept enable event, and the enable is not removed from the end of the queue. This mechanism is described in It can be used to keep the output gate open, as described in 12.5.

A. [0827] 12.8 "Bit Count" The bit counter starts counting after the flash token passes through this counter. This flash token indicates the end of the current video stream. In this regard, the bit counter has a bit count tar
Counting continues until the bit count target set in the get register is met. Next, a target match event is generated, and the bit counter resets to zero and waits for the next flush token.

Further, when the bit counter reaches the maximum count (255), the bit counter stops incrementing.

A. 12.9 “Bit Count Prescale” In the present invention, incrementing the bit counter once requires 2 (bit count prescale + 1) × 512 bits. Furthermore, the bit count prescale is
This is a 3-bit register that can hold a value between 0 and 7.

[0829]

[Table 97] Since some elements of the video stream have already been tokenized (eg, a start code), the bit counts are approximate and thus include non-data tokens.

A. 12.10 "Counter Flush Too Early" If the flash token arrives at the bit counter before the bit count goal has been reached, an event is generated that can cause an interrupt (counter flush
d too early mask = 1). If an interrupt is generated, the bit counter circuit stops, preventing further data input. It is the responsibility of the user software to determine when to open the output gate after this event has occurred. An output gate can be created to open by writing 0 as the bit count target. These situations should only occur when trying to decode a video stream that lasts only a few pictures.

Section A. 13 "Buffer Management" The spatial decoder consists of two logical data buffers:
Manages coded data buffer (CDB) and token buffer (TB).

[0832] The CDB buffers the coded data between the start code detector and the input of the Huffman decoder.
This provides a buffering effect on the low data rate coded video data. TB is the output of the Huffman decoder and the spatial video decoding circuit (inverse modeler, quantizer, DC
Buffer data between input of T). This second logical buffer allows the processing time to include extensions to accommodate processing of pictures with varying amounts of data.

[0832] Both buffers are physically held in one single off-chip DRAM array. These buffer addresses are generated by the buffer manager.

A. 13.1 "Buffer Manager Register" The spatial decoder buffer manager is intended to be configured only once, immediately after the device has been reset. During normal operation, there are no requirements for buffer manager reconfiguration.

After the reset is removed from the spatial decoder, the buffer manager is stopped (sets the buffer manager access register to 1) and waits for configuration. After the registers are configured, the buffer manager access can be set to 0 and decoding can begin.

During operation of the buffer manager, most of the registers used in the buffer manager cannot be accessed reliably. Before attempting to access any of the buffer manager registers, a buffer manager access of 1
Must be set to This makes it mandatory to follow the waiting protocol until the value 1 is read from the buffer manager access. To monitor buffer conditions, for example, cdbfull and cdbempty
When polling such a register, it is necessary to consider the time required to secure and abandon access.

[0837]

[Table 98] A. 13.1.1 “Buffer Manager Pointer Value” Generally, data is stored in a spatial decoder and an off-chip DRAM.
(A high-speed page mode of the DRAM is used). All buffer pointers and length registers represent these blocks of 64 bytes (512 bits) of data. Therefore, the buffer manager's 18-bit register contains 25
6k block linear address space (ie, 128M
Describe b).

The 64 byte transfer is independent of the width of the DRAM interface (8, 16, or 32 bits).

A. 13.2 Use of Buffer Manager Registers The spatial decoder buffer manager has two sets of registers that define two similar buffers. The buffer limit register defines the physical upper limit of the memory space. All addresses are calculated modulo this number.

Within the limits of the available memory, the range of each buffer is two registers: a buffer base (cdbbase and tbbase), and a buffer length (cdblength and tbleng).
h). All the registers described so far must be configured before the buffer can be used.

[0841] The current state of each buffer is visible in four registers. The buffer read registers (cdread and tread) indicate the offset from the buffer base from which the next data is read. Buffer number register (cdnumb
er and tbnumber) indicate the amount of data currently held by the buffer. Status bits cdb
full, tbfull, cdempty, and tb
empty indicates whether the buffer is full or empty.

A. As described in 13.1.1, the unit for all the above registers is a 512-bit data block. Therefore, to determine the number of bits in the coded data buffer, cdbnumber
The value read from r must multiplied by 512.

A. 13.3 "Zero Buffer" Still image applications where the "real time" requirement does not apply (eg using JPEG) do not require a large off-chip buffer supported by the buffer manager. In this case, the DRAM interface can be configured to ignore the buffer manager (by writing a 1 to the register zero buffer) to provide a 128 bit stream on-chip FIFO to the coded data buffer and token buffer.

[0844] In addition, the zero buffer option may be suitable for applications that operate with small picture formats at low data rates.

Note: The register zero buffer is a DRAM
Since it is part of the interface, it must be set only during the post-reset configuration of the DRAM interface.

A. 13.4 “Buffer Operation” Data transfer through the buffer is controlled by the handshake protocol. Therefore, if the buffer is full or empty, it is guaranteed that no data error will occur. If the buffer is full, circuits attempting to send data to the buffer are halted until space is available in the buffer. If the buffer continues to be full, further processing stages located upstream of the buffer will stop until the spatial decoder can no longer accept data at its input port. Similarly, if the buffer is empty, circuits attempting to remove data from the buffer will stop until data becomes available.

A. As shown in 13.2, the location and size of the coded data and token buffers are specified by the buffer base and length registers. It is the responsibility of the user to configure these registers and to ensure that the memory usage between the two buffers is consistent.

Section A. 14. Video Demultiplexer A video demultiplexer, also called a video parser, completes the task of converting coded data into tokens started by a start code detector. The video demultiplexer has four main processing blocks,
That is, a parser state machine, a Huffman decoder (IT
OD), macroblock counter, and ALU.

The parser or state machine follows the syntax of the coded video data and points to other units. The Huffman decoder converts variable length coded (VL0) data into integers. The macroblock counter keeps track of the picture section that is currently being decoded. The ALU performs the necessary arithmetic calculations.

A. 14.1 "Movie demultiplexer register"

[0851]

[Table 99]

[0852]

[Table 100]

[0853]

[Table 101]

[0854]

[Table 102]

[0855]

[Table 103] A. 14.1.1 Loading Registers and Generating Tokens A number of registers in the video demultiplexer hold values that are directly related to the parameters normally transmitted in coded picture / video data. For example, the horizontal pixel register corresponds to MPEG sequence header information, horizontal size, and JPEG frame header parameters, X. These registers are loaded by the video demultiplexer when the coded data is decoded. Similarly, these registers are also associated with tokens.

For example, it relates to a horizontal pixel register, a token, and a horizontal size. The token is generated by the video demultiplexer when (or shortly after) the encoded data is decoded. Similarly, the token can be provided directly to the input of the spatial decoder. In this case, the value of the token constitutes a moving image demultiplexer associated with the token.

[0857]

[Table 104]

[0858]

[Table 105]

[0859]

[Table 106]

[0860]

[Table 107]

[0861]

[Table 108]

[0862]

[Table 109]

[0863]

[Table 110]

[0864]

[Table 111]

[0865]

[Table 112] A. 14.2 "Picture Structure" The dimensions of a picture in the present invention are described to the spatial decoder as two different units: pixels and macroblocks. JPEG and MPEG are both
Transmit picture dimensions as pixels. By transmitting the dimensions as pixels, the area of the buffer containing valid data is determined. In this case, the area may be smaller than the entire buffer size. By transmitting the dimensions as macroblocks, the size of the buffer needed by the decoder is determined. The macroblock dimensions must be determined by the user from the pixel dimensions. The spatial decoder registers associated with this information are as follows: horizontal pixel, vertical pixel, horizontal macroblock, and vertical macroblock.

[0866] Spatial decoder register, number of blocks h
n, vn, maxh, maxv, and maxc
component id is a combination of macroblocks (J
PEG minimum coding unit). Each is a two-bit register that can hold a value in the range from 0 to 3. max compo
All registers except the tent id specify a block count from 1 to 4. For example, register ma
If xh holds 1, the width of the macroblock is 2 blocks. Similarly, max component
id specifies the number of different color components involved.

[0867]

[Table 113] Table A. 14.6 Configurations for Various Macroblock Formats 14.3 "Huffman Table" In 14.3.1 "JPEG style Huffman table description" The present invention, Huffman table descriptions, in order to transmit the table description between the encoder and decoder are provided in the Spatial Decoder via the format used by the JPE G You. Each table description has two elements: BITS
And HUFFVAL. Users are guided to the JPEG specification for a complete description of how tables are encoded.

A. 14.1.1.1 "BITS" BITS is a table showing values that describe how many different symbols are encoded using each length of the VLC.
Each entry is one 8-bit value. JPEG is V
The maximum length of the LC is 16 bits. Thus, each table has 16 entries.

[0869] BITS [0] describes how many different 1-bit VLCs are present, while BITS [1]
Describes how many different 2-bit VLCs exist, and so on.

A. 14.3.1.2 "HUFFFVA
L "HUFFFVAL is a table of 8-bit data values arranged in increasing VLC length order. The size of this table is VL
It depends on the number of different symbols that can be coded by C.

The JPEG specification describes in more detail how the Huffman coding table is coded or decoded for this format.

A. 14.3.1.3 “Configuration with Token” The description of the Huffman table used to encode AC and DC coefficients in the JPEG bit stream is D
The HT marker precedes. Start code detector is DHT
When recognizing a marker, the detector generates a DHT marker token and places the Huffman table description in the next following data token (see A.11.3.4).

The construction of the AC and DC coefficient Huffman tables in the spatial decoder can be achieved by providing data and DHT marker tokens at the input of the spatial decoder, while the spatial decoder is configured for JPEG operations. . This mechanism can be used to construct the DC coefficient Huffman table needed for MPEG operation, provided that the table is downloaded and the encoding standard of the spatial decoder is JP
Must be set to EG.

[0874]

[Table 114] A. 14.1.4 "Configuration with MPI" The AC and DC coefficient Huffman tables can likewise be entered directly into registers via MPI. Table 104
Please refer to.

* Register dc bits 0 [15: 0]
And dc bits1 [15: 0] hold BITS values for tables 0x00 and 0x01.

* Register ac bits0 [15: 0]
And ac bits1 [15: 0] hold the BITS values for Tables 0x10 and 0x11.

* Register dc huffval0 [1
1: 0] and dc huffval1 [11: 0]
Holds HUFFVAL values for tables 0x00 and 0x01.

* Register ac huffval0 [16
1: 0] and ac huffval1 [161: 0].
Holds the HUFFVAL values for tables 0x10 and 0x11.

A. 14.4 “Configurations for Different Standards” Video demultiplexers are MPEG, JPEG, and H.264. 261 requirements. The coding standard is
CODINC generated by start code detector
It is automatically configured by the STANDARD token.

A. 14.4.1 “H.261 Huffman Table” All Huffman tables needed to decode H.261 are kept in ROM in the spatial decoder and more specifically in the parser state machine of the video demultiplexer, requiring user intervention. And not.

A. [0881] 14.4.2 “Structure of H.261 picture” H.261 is defined as supporting only two picture formats: CIF and QCIF. The picture format in use is transmitted in the PTYPE section of the bitstream. This data, when decoded by the spatial decoder, is H
261 picture type register and picture type token. Further, all picture and macroblock configuration registers are automatically configured.

The information in the various registers is placed in their associated tokens, see Tables 109-112), and this ensures that other decoder chips (eg, temporal decoders) are correctly configured. Guarantee.

A. 14.4.3 “MPEG Huffman Table” Most of the Huffman coding table necessary for decoding MPEG is held in the ROM in the spatial decoder (repeated that it is in the parser state machine). And no user intervention is required. The tables required to decode the DC coefficients of an intra macroblock are an exception. Two tables are needed, one for chroma and one for luma. These tables must be constructed by the user software before decoding begins.

[0884]

[Table 115] Table 117 shows the sequence of tokens needed to construct the DC coefficient Huffman table in the spatial decoder. Alternatively, writing this information to the register via the MPI achieves the same result.

The register dc huffn controls which DC coefficient Huffman table to use with each color component.
Table 116 shows how it must be configured for MPEG operation. This is MPI
, Or directly by using an MPEG DCH table token.

[0886]

[Table 116]

[0887]

[Table 117]

[0888]

[Table 118]

[0889]

[Table 119]

[0890]

[Table 120] A. 14.4.4 “Structure of MPEG Picture” The configuration of a macroblock defined for MPEG is described in H.264.
261 is the same as the structure used. The dimensions of the picture are coded into coded data.

For Standard 4: 2: 0 operation, the properties of the macroblock must be configured as indicated in Table 115. This can be done by filling in registers as indicated, or by supplying an equivalent token to the input of the spatial decoder (see Tables 109-112).

[0981] The method used to construct the picture dimension depends on the application. If the picture format is known before decoding starts, Table 115
Can be initialized with appropriate values. Alternatively, the picture dimension can be decoded from the coded data, and
It can be used to configure a spatial decoder. In this case, the user must support parser error MPEG sequences. A. 14.8
See "Changes in MPEG Sequence Layer".

A. [0993] 14.4.5 "JPEG" Within the baseline JPEG, there are a number of encoder options that significantly change the complexity of the control software required to operate the decoder. In general, a spatial decoder is
It is designed to require minimal support if the following conditions are met: * The number of color components per frame is less than 5 (Nf ≦ 4).

[0894] A. 14.4.6 JPEG Huffman Table In addition, JPEG allows Huffman coded tables to be downloaded. These tables are used when decoding VLC describing coefficients. Two tables are allowed per scan to decode the DC coefficients, and two tables are also allowed for the AC coefficients.

There are three different types of JPEG files: interchange format, compact format for compressed image data, and compact format for table data. The interchange format file contains both the compressed image data and the definitions of all the tables (Huffman, quantization, etc.) needed to decode the image data. The table definition is omitted from the shortened image data format file. The shortened table format file contains only table definitions.

[0896] The spatial decoder accepts all three formats. However, if all the required tables have been defined, only the shortened image data file can be decoded. The other two types of JPEG
This definition can be implemented via either of the files, or alternatively, the table can be set up by user software.

If each scan uses a different set of Huffman tables, the definition of the table is placed in the coded data (by the encoder) before each scan. These definitions are automatically loaded by the spatial decoder for use during the scan and subsequent scans.

To improve the performance of Huffman decoding, certain commonly used symbols are specially partitioned . These symbols are a zero magnitude DC coefficient, the end of a block AC coefficient, and a run of 16 zero AC coefficients. The values for these special cases must be entered in the appropriate registers.

A. 14.4.6.1 “Table Selection” Registers dc huff n and ac huff n
Controls which AC and DC coefficient Huffman tables to use with which color components. During JPEG operation, these relationships are defined in the scan header syntax TDj.
And Taj fields.

A. 14.4.7 JPEG Picture Structure There are two distinct levels of baseline JPEG decoding supported by the spatial decoder: levels up to 4 components per frame (Nf ≦ 4) and per frame. The level is larger than four components (Nf> 4). Nf
If> 4 is used, the required control software is more complex.

A. 14.4.7.1 “Nf ≦ 4” The frame component specification parameters included in the JPEG frame header are configured in a macroblock configuration register when decoding them (see Table 115). No user intervention is required, since all the specifications required to decode the four different color components are defined.

For details on the options provided by JPEG, consult the JPEG specification. Similarly, for the JPEG picture format, see Section A.3. This is briefly described in 16.1.

A. 14.4.7.2 “JPEG with more than 4 components” The spatial decoder supports up to 256 different color components (JPEG
JPEG file including the maximum number allowed by the JPEG file) can be decoded. However, if more than four color components are to be decoded, additional user intervention is required. In JPEG, only a maximum of four components are allowed in any scan.

A. 14.4.8 “Nonstandard Variants” As already mentioned, the spatial decoder uses JPEG and MP.
Supports more picture formats than the format defined by the EG.

JPEG limits the minimum coding unit so that the coding unit does not include more than 10 blocks per scan. The spatial decoder calculates the number of blocks hn, the number of blocks v n, max h, and max
This limit does not apply to spatial decoders, since any minimum coding unit that can be described by v can be processed.

In MPEG, see Table 115, which is defined only for 4: 2: 0 macroblocks. However, the spatial decoder can process three other component macroblock structures (eg, 4: 2: 2).

A. 14.5 "Video Events and Errors" The video demultiplexer can generate two types of events: parser events and Huffman events. For a description of how to handle events and interrupts, see A.A. See 6.3 “Interrupts”.

A. 14.5.1 "Huffman Event" Huffman events are generated by a Huffman decoder. The Huffman event and the events indicated in the Huffman mask determine whether an interrupt is generated. If the Huffman mask is set to 1,
An interrupt is generated and the Huffman decoder stops. The register Huffman error code [2: 0] holds a value indicating the cause of the event.

If a Huffman event is filled with 1 after servicing an interrupt, the Huffman decoder
Attempt to recover from the error. Similarly, if the Huffman mask is set to 0 (mask the interrupt and do not stop the Huffman decoder), the Huffman decoder will automatically attempt to recover from the error.

A. 14.5.2 Parser Events Parser events are generated by the parser. This event is indicated in the parser event. Thereafter, whether an interrupt is generated is determined by the parser mask. If the parser mask is set to 1, an interrupt is generated, and
The parser stops. The register parser error code [7: 0] holds a value indicating the cause of the event.

[0911] After servicing the interrupt, if the Huffman event is filled with a 1, then the Huffman decoder will:
Attempt to recover from the error. Similarly, if the Huffman mask is set to 0 (mask the interrupt and do not stop the Huffman decoder), the Huffman decoder will automatically attempt to recover from the error.

[0991] After servicing the interrupt, if the parser event is to be filled with 1, the parser will resume operation. If the event indicates a bitstream error, the video demultiplexer attempts to recover from the error.

If the parser mask is set to 0, the parser sets the event bit, but does not generate an interrupt or stop. The parser continues the operation and attempts automatic recovery from the error.

[0914]

[Table 121]

[0915]

[Table 122]

[0916]

[Table 123]

[0917]

[Table 124]

[0918]

[Table 125]

[0919]

[Table 126] Each standard uses a different subset of the defined parser error codes.

[0920]

[Table 127]

[0921]

[Table 128] A. 14.6 “Receiving User Data and Extension Data” MPEG and JPEG use a similar mechanism for embedding user data and extension data. Data is preceded by a start / marker code. If the application is not interested in the data,
A start code detector can be configured to delete this data (see A.11.3.3).

A. 14.6.1 “Data Source Identification” Parser Events, EREXTENSION Tokens,
And the ERR user token indicate the arrival of the extension data or the user data token in the video demultiplexer. If these tokens are generated by the start code detector (A.11.
3.3)), these tokens have the value of the start / marker code that caused the start code detector to generate the token (see Table 92). This value can be read by reading the rom revision register while supporting parser interrupts. The moving image demultiplexer remains stopped until 1 is written in the parser event (see A.6.3, “Interrupt”).

A. 14.6.2 "Reading Data" EXTENSION data and user data tokens are expected to be immediately followed by data tokens with extension data or user data. The video demultiplexer indicates that the arrival of this data token
Generate either RREXTENSION data or ERR user data parser events. The first byte of the data token contains r while servicing the interrupt.
It can be read by reading the om revision register.

[0924] The continuation state of the moving image demultiplexer register determines the behavior after the event is cleared. If this register holds the value 0, any remaining data in the data token is consumed by the video demultiplexer and no event is generated. If continuation is set to 1, an event is generated as each byte or user data of the extension arrives at the video demultiplexer. This continues until the data token is exhausted or the continuation is set to zero.

Notes: 1) The first byte of extension / user data is always presented via the romrevision register, regardless of the state of the continuation.

2) There is no event indicating that the last byte of extension / user data has been read.

A. 14.7 “Reception of Additional Information” H.261 and MPEG allow information that extends the coding standard to be embedded in blocks (H.261) or slice (MPEG) pictures and groups. This mechanism is different from the mechanism for extended data and user data (described in Section A.14.6). Since the start code does not precede the data, it can be deleted by the start code detector.

[0928] H. During the H.261 operation, the parser events ERR PSPARE and ERR GSPA
The RE instructs detection of this information. The corresponding event during the MPEG operation is ERR EXTRA
A picture and an ERR EXTRA slice.

When a parser event is generated, the first byte of additional information is presented via the register romrevision.

[0930] The continuation state of the video demultiplexer register determines the manner of action after the event has been cleared.
In retaining this register value 0, any remaining additional information is consumed by the video demultiplexer and no events are generated. If continuation is set to 1, an event is generated as each byte of additional information arrives at the video demultiplexer. This continuation continues until the additional information is exhausted or the continuation is set to zero.

Notes: 1) The first byte of extension / user data is always presented via the romrevision register, regardless of the state of the continuation. 2) There is no event indicating that the last byte of the extension / user data has been read.

A. [0932] 14.7.1 "FIELD INF
Generation of O Token "During MPEG operation, register field i
If nfo is set to 1, then any ex
The first byte of the tra information picture is placed in the FIELD INFO token.
This behavior is not covered by MPEG standardization activities. Tables 4 to 11 show the definition of the FIELD INFO token.

If the field info is set to 1, no parser event is generated for the first byte of the extra information picture. However, extra informati
An event is generated for every subsequent byte of the on picture. If there is only one single byte of the extra information picture, no parser event will occur.

A. 14.8 “Changes in MPEG Sequence Layer” The MPEG sequence header describes the following properties of the moving picture to be decoded.

* Horizontal and vertical size * Pixel aspect ratio * Picture rate * Coded data rate * Video buffer verifier buffer size When these parameters change when the spatial decoder decodes the sequence header, Generates a parser event ERR MPEG sequence.

A. 14.8.1 "Picture Size Change" When the picture size changes, the user's software reads the values in horizpels and vertpels , and then registers horizmacr
obblocks and vertmablocks
Calculate the new value to load into.

Section A. 15 "Spatial decoding" According to the present invention, spatial decoding occurs between the output of the token buffer and the output of the spatial decoder.

[0938] There are three main units responsible for spatial decoding: the inverse modeler, the inverse quantizer, and the inverse discrete cosine transformer. At the input of this section (from the token buffer), the data token contains a run and level representation of the quantized coefficients. Output (Reverse D
In CT), the data token is the pixel information 8
× 8 blocks are included.

A. 15.1 "Inverse Modeler" The data token in the token buffer contains information about the value of the quantized coefficients and the number of zeros between the displayed coefficients. The inverse modeler expands on information about runs of zero so that each data token contains 64 values. At this stage, the value in the data token is a quantized coefficient.

The inverse modeling process is the same regardless of the coding standard currently in use. No configuration is required.

To better understand all the requirements for modeling and de-modeling functions, the reader can explore any picture coding standard.

[0942] A. 15.2 Inverse Quantizer In an encoder, a quantizer divides the DCT output to reduce the resolution of DCT coefficients. The function of the inverse quantizer in the decoder is to multiply these quantized DCT coefficients in order to restore them to approximate the original values.

A. 15.2.1 Overview of the Standard Quantization Plan There are important differences in the quantization plans used by each of the different coding standards. To gain a detailed understanding of the quantization scheme used by each standard, the reader should study the relevant coding standard documents.

The register iq coding standard configures the operation of the inverse quantizer to meet the requirements of different standards. In normal operation, this coded register is automatically loaded by the coding standard token. For more information on the configuration of coding standards, see Section A.1. See 21.1.

The main difference between the quantization schemes is the source of the numbers by which the quantized coefficients are multiplied. These are outlined below. Further, although not described herein, there are specific differences in the required arithmetic operations (rounding, etc.).

A. 15.2.1.1.1 “H.261 I
Overview of Q ”H. At 261, one single "scale factor" is used to adjust the coefficients. The encoder is
This scale factor can be changed periodically to adjust the data rate created. Slightly different rules apply to “DC” coefficients in intra-coded blocks.

A. 15.1.2.1.2 “JPEG IQ
Overview Baseline JPEG allows pictures containing up to four different color components in each scan. For these four color components, a 64-entry quantization table can be specified. Each entry in these tables can be used as a "scale" factor for one of the 64 quantized coefficients.

[0948] The value for the JPEG quantization table is the coded JP
Included in the EG data and automatically loaded into the quantization table.

A. 15.2.1.3 "MPEG IQ
Overview of MPEG. H.261 and JPEG quantization technology. As with JPEG, four quantization tables with 64 entries each are available. However, the use of tables is completely different.

[0950] The two "types" of data are intra and non-intra. A different table is used for each data type. The two "default" tables are MPEG
Defined by One is for intra data,
The other is for non-intra data, see Table 130 and Table 131). These default tables must be entered in the spatial decoder's quantization table memory before MPEG decoding is enabled.

Similarly, MPEG allows two “download” quantization tables. One is for use with intra data, and the other is for use with non-intra data. The values for these tables are
Included in the MPEG data stream and automatically loaded into the quantization table memory.

[0932] The values output from the table are modified by the scale factor.

A. [0953] 15.2.2 "Inverse Quantizer Register"

[0954]

[Table 129] In the present invention, before the quantization table memory can be accessed, the iq access register must be set. If a read is attempted on the table while iq access is set to 0, the quantization table memory returns the value zero.

A. 15.2.3 "Dequantizer Configuration" In normal operation, there is no need to configure the inverse quantizer coding standard, as it is automatically configured by the coding standard token.

H. [0956] For the H.261 operation, no quantizer table is used. No special configuration is required. For JPEG operation, the tables required by the inverse quantizer must be automatically loaded with information extracted from the coded data. MPEG operations require that a default quantization table be loaded. This loading must take place while iq access is set to one. The values in Table 130 are from locations 0x00 to 0x3F of the extended address space of the inverse quantizer.
(Accessible via keyhole register iq keyhole address and iq keyhole data). Similarly, the values in Table 131 are from locations 0x40 to 0x in the extended address space of the inverse quantizer.
Must be completed by 7F.

[0957]

[Table 130]

[0958]

[Table 131] A. 15.2.4 “Table Construction from Tokens” Instead of constructing the inverse quantizer tables via MPI, it is possible to initialize these inverse quantizer tables with tokens. These tokens can be supplied by either an encoded data port or MPI.

[0959] For the QUANT table token,
These are described in Tables 3 to 11. The token is shown in Table 4
It has one 2-bit field tt that specifies which of the (0-3) locations is defined by the token. For MPEG operations, the default definitions in Tables 0 and 1 need to be loaded.

A. [0960] 15.2.5 Quantization Table Values For both JPEG and MPEG, the quantization table entry is an 8-bit number. Values between 255 and 1 are valid. The value 0 is invalid.

A. [0961] 15.2.6 "Numerical Order of Quantization Tables" The values of the quantization tables are used in a "zigzag" scanning order (see coding standards). The table must be considered as a one-dimensional array with 64 values (not an 8x8 array). The table entry at the lower address corresponds to the lower frequency DCT coefficient.

[0961] If the quantization table value is carried by the QUANT table token, the first value after the token header is the table entry for the "DC" coefficient.

A. [0963] 15.2.7 “Inverse Quantizer Test Register”

[0964]

[Table 132] Table A. 15.4 Inverse Quantizer Test Register 15.3. "Discrete Inverse Cosine Transform" The inverse discrete transform processor of the present invention is based on the CCITT recommendation H.264.
261, conforms to the requirements specified in IEEE specification P1180, and conforms to the requirements described in the current revision of MPEG.

[0965] The discrete inverse cosine transform process is the same regardless of which coding standard is used.
No user configuration is required.

[0966] There are two events associated with the inverse discrete transform processor.

[0967]

[Table 133] To better understand the DCT and inverse DCT functions, the reader can explore any picture coding standard.

Section A. 16 "Connection to Spatial Decoder Output" The output of the spatial decoder is a standard token port for a 9-bit wide data word. See Section A. for more information on the electrical behavior of the interface. 4
Please refer to.

[0969] The token at the output depends on the encoding standard being employed. As an example, this section of the disclosure considers the output of a spatial decoder when configuring for JPEG operation. Since the temporal decoder does not modify the resulting token sequence of JPEG, this section describes the token sequences that are observed at the output of the temporal decoder during JPEG operation.

[0970] However, MPEG and H.264 are used. H.261 both require the use of a temporal decoder. MPEG and H.264.
For information on connecting to the temporal decoder output when configured for H.261 operation, see Section A.261. See FIG. Further, this section identifies which tokens are available at the output of the spatial decoder and which tokens are most useful in designing a circuit to display the output. Other tokens exist, but their output is not required for display and will not be discussed here. The following are the items that we will focus on in this section.

* Method of identifying start and end of sequence.

* Method of identifying start and end of picture.

* A method of identifying when to display a picture.

* Method of Identifying Picture Data Placement Location in Display A. 16.1 JPEG Picture Structure This section gives an overview of the features of the JPEG syntax. See the coding standard for details.

[0976] JPEG provides various mechanisms for encoding individual pictures. JPEG does not attempt to describe a method of coding a collection of pictures together to provide a mechanism for coding moving pictures.

[0976] The spatial decoder according to the present invention uses JPEG.
Supports sequential operating mode as a baseline.
This syntax has three main levels: image, frame, and scan. One sequential image contains only one single frame. One frame is
Between 1 and 256 different image (color) components can be included. These image components can be collected in a scan in various ways. Each scan is 1
(See FIG. 90 "Overview of Sequential Structure as JPEG Baseline"). If the scan contains one single image component, it is a non-interleaved scan; if it contains multiple image components, it is an interleaved scan. One frame may include a mixture of interleaved and non-interleaved scans. The number of scans that a frame can contain is determined by the 256 limit on the number of image components that a frame can contain. Within one interleaved scan, data is stored in MPEG and H.264. H.261, the smallest coding unit (M
CU). These MOUs are arranged in raster order in the picture. The MCU in a non-interleaved scan is one single 8x8 block. Also in this case, the MCU is raster-organized.

[0977] The spatial decoder can easily decode JPEG data containing 1 to 4 different color components. A file describing a large number of components can be similarly decoded. However, some reconstruction may be required between scans to accommodate the next set of components to be decoded.

A. [0978] 16.2 "Token Sequence" JPEG marker codes are converted by the start code detector into similar MPEG designated as tokens, see Table 92 and FIG. 91 "Tokenized JPEG Pictures".

Section A. 17 "Time decoder" * 30, MH7 operation.

* MPEG and H.264 261 video decoding provides temporal decoding.

* H. 261 CIF and QCIF formats.

* MPEG video resolution up to 704 × 48
0, 30 Hz, 4: 2: 0.

* Flexible chroma sampling format.

* MPEG picture sequence reordering is possible.

* Glueless DRAM interface
(Glue-less DRAM interface
e) .

* Single + 5V power supply.

[0987] * 208-pin PQFP package.

* Maximum power consumption 2.5W.

* Uses standard page mode DRAM.

The temporal decoder is a companion chip to the spatial decoder, and 261 and M
Provides the temporal decoding required by PEG.

[0991] The temporal decoder uses MPEG and H.264. 26
1 performs all the prediction forming functions required. One single 4Mb DRAM (eg, 512k ×
8), the time decoder uses CIF and QCIF
H. 261 video can be decrypted. 8Mb D
Using RAM (for example, two 256k × 16)
704 × 480, 30 Hz, 4: 2: 0 MPEG moving pictures can be decoded.

[0992] Intra coding scheme (eg JPEG)
Does not require a time decoder . If the temporal decoder is included in the multi-standard decoder, the temporal decoder:
It supplies the decoded JPEG picture up to its output. Note: The foregoing values are merely exemplary of one embodiment of the present invention, and are not necessarily intended to be limiting. It should be understood that other values and ranges can be used without departing from the scope of the invention.

A. [0993] 17.1 "Time decoder signal"

[0994]

[Table 134]

[0995]

[Table 135]

[0996]

[Table 136]

[0997]

[Table 137]

[0998]

[Table 138] A. 17.1.1 “Unconnected Pin“ nc ”” The pins labeled “nc” in Table 138 are pins that are not currently used in the present invention and are reserved for future products. . These pins must be left unconnected. These pins are connected to VDD, GND,
Do not connect with each other or any other signals.

A. 17.1.2 "VDD and GND Pins" As should be appreciated, all VDD and GND pins must be connected to the appropriate power supply, and if all VDD and GND pins are not used properly, Device does not work properly.

[1000] A. 17.1.3 Connection of Test Pins for Normal Operation Nine pins of the time decoder are reserved for internal testing.

[1001]

[Table 139] A. 17.1.4 [JTAG Pins for Normal Operation] Section A. See 8.1.

[1002]

[Table 140]

[1003]

[Table 141]

[1004]

[Table 142]

[1005]

[Table 143]

[1006]

[Table 144]

[1007]

[Table 145]

[1008]

[Table 146]

[1009]

[Table 147]

[1010]

[Table 148] Section A. 18 "Time decoder operation" 18.1 "Data Input" The input data port of the time decoder is a standard token port with 9-bit wide data words. In most applications, this will be connected directly to the output token port of the spatial decoder. For more information on the electrical activity of this interface, see Section A. 4
See

A. 18.2 "Auto-Forming" Parameters relating to the encoded video picture format are automatically loaded into registers in the temporal decoder by tokens generated by the spatial decoder.

[1012]

[Table 149] A. 18.3 "Manual Configuration" The user must configure the application dependent elements (via the microprocessor interface).

[1013] A. 18.3.1 When to Form A temporal decoder should only be formed when no data processing is taking place. This is the default state after reset is released. By writing 1 to the chip access register, the time decoder can be stopped and re-formed. After the formation is completed, 0 must be written to the chip access.

For details on when to form the DRAM interface, see Section A. See 5.3.

[1015] A. 18.3.2 DRAM Interface The timing of the DRAM interface must be formed before predictive encoded video (eg, H.261 or MPEG) can be decoded.
Section A. See 5 “DRAM Interface”.

[1016]

[Table 150]

[1017]

[Table 151] A. 18.3.3 “Picture Buffer Register Number” The picture buffer pointer (18 bits) and component offset (17 bits) registers specify the block (8 × 8 byte) address, not the byte address.

[1018] A. 18.3.4 “Picture buffer storage allocation” Predictively encoded video (H.261 or MP
To decode EG), the temporal decoder must process two picture buffers. See Section A.3 for details on how these buffers are used. 18.4 and A.I. See 18.4.4.

[1019] The user may use the picture buffer pointer (pic) to store a single picture of the required video format (without overlapping with other picture buffers).
cure buffer 0 and picture bu
It must be ensured that there is sufficient memory on each of fffer 1). Typically, one of the picture buffer pointers is set to 0 (ie, the bottom of storage) and the other is set to point to the middle of storage space.

[1020] A. 18.3.4.1 "General formation for MPEG or H.261" Both H.261 and MPEG use a ratio of 4: 1: 1 between different color components (i.e., there are four times as bright pixels as pixels in either chrominance component).

A. As documented in 3.5.1, "Component Specific Number", component 0 is the luminance component and components 1 and 2 are the chrominance.

An example of forming a component offset register is as follows: component 0 starts at the picture buffer pointer.
Set component offset 0 to 0. Similarly, component offset 1 is set to 4/6 of the picture buffer size, and compo
Nent offset 2 could be set to 5/6 of the picture buffer size.

A. 18.3.5 "Picture sequence re-ordering" MPEG uses three different picture types: intra (I), expected (P), and bidirectionally interpolated (B). . B-pictures are based on predictions from two pictures: those from the future and those from the past. The order of the pictures is such that the B picture is
The encoder modifies the I and P pictures so that they are decoded from the encoded data.

The picture sequence must be modified before these pictures can be displayed. The temporal decoder can provide this picture reordering (by setting the register MPEG reordering = 1). Alternatively, the user may wish to perform picture reordering as part of his display interface function. Forming a temporal decoder to provide picture reordering may reduce the video resolution that can be decoded. A. See 18.5.

[1025] A. 18.4 “Predictive Formation” The prediction formation requirements of H.261 decoding and MPEG decoding are quite different. Coding standard tokens are automatically formed so that the temporal decoder accommodates different standards of prediction requirements.

[1026] A. 18.4.1 “JPEG Operation” When configured for JPEG operation, no prediction is made since JPEG does not require temporal decoding.

A. [1027] 18.4.2 “H.261 Operation” In H.261, the prediction is made only from the decoded picture. A motion vector is only specified as a condition of the accuracy of an integer pixel. The encoder can specify that a low pass filter be applied to the prediction result.

[1028] As each picture is decoded, it is written to a picture buffer in the off-chip DRAM for use in decoding the next picture. The decoded picture appears at the output of the temporal decoder as it is written to the off-chip DRAM.

For details on the predictions and the related arithmetic operations, the readout device is based on H.264. 261 Standard. The temporal decoder of the present invention is based on H.264. 261
Fully complies with the requirements of

[1030] A. 18.4.3 MPEG operation (without rearrangement) The operation of the temporal decoder is three different MPEG
It changes for each of the picture types (I, P, B). I-pictures do not require further decoding by a temporal decoder, but must be stored in a picture buffer (frame store) for later use in decoding P and B pictures.

[1030] Decoding a P picture requires forming predictions from previously decoded P or I pictures. The decoded P picture is stored in a picture buffer for use in decoding P and B pictures. MPEG allows motion vectors to be specified with half-pixel accuracy. On-chip filters provide interpolation to support this half-pixel accuracy.

[1032] B pictures can request prediction from both picture buffers. As with P-pictures, half-pixel motion vector resolution accuracy requires on-chip interpolation of picture information. B pictures are not stored in off-chip buffers. They are only temporary.

All pictures appear at the output port of the temporal decoder as their codes are decoded. Therefore, the picture sequence is the same as in the encoded MPEG data (see the upper part of FIG. 94).

For details on predictions and related arithmetic operations, refer to the draft of the proposed MPEG standard. These requirements are met by the temporal decoder of the present invention.

A. [1035] 18.4.4 “MPEG operation (with reordering)” MPEG operation with picture reordering (MPE
When formed for G reordering = 1), the predictive formation operation is performed as described in Section A.1 above. 1
Same as in 8.4.3. However, additional data transmission is performed to rearrange the picture sequence.

[1036] B picture decoding is performed in section A. As described in 18.4.3. However, I and P pictures are not output when decoded. Instead, they are written to the off-chip buffer (as described above) and read only when the next I or P picture arrives for decoding. A. 18.4.4.1 Decoder Startup Characteristics Output of the first I picture is delayed until decoding of the next P (or I) picture is started. This must be taken into account when estimating the start-up characteristics of the video decoder.

[1037] A. 18.4.4.2 Decoder Stop Characteristics The temporal decoder relies on the next P or I picture to flush the previous picture from its off-chip buffer (frame store). This has consequences at the end of the video sequence and when starting a new video sequence. The spatial decoder provides the facility to create a "false" I / P picture at the end of the video sequence to flush the last P (or I) picture. However, this "false" picture is flushed when the next video sequence begins.

[1038] The spatial decoder provides an option to suppress this "false" picture. This is useful if the new video sequence is known to be provided to the decoder immediately after the completion of the old sequence. The first picture in this new sequence will flush the last picture of the previous sequence.

A. [1039] 18.5 "Video Resolution" When decoding MPEG, the video resolution that a temporal decoder can support is limited by the memory bandwidth of its DRAM interface. MP
For the EG, two cases need to be considered: MP
There are cases where EG picture rearrangement is involved and cases where it is not accompanied.

[1040] Section A. 18.5.2 and A.I. 1
8.5.3 discusses the worst-case requirements required by the current draft of the MPEG standard. A subset of MPEG with lower memory bandwidth requirements is contemplated. For example, using only integer resolution motion vectors,
Alternatively, it significantly reduces memory bandwidth requirements without using B-pictures. The analysis for such a subset is not performed here.

A. [1041] 18.5.1 [DRAM Interface Characteristics] The number of cycles taken to transfer data across the DRAM interface depends on a number of factors: • Timing configuration of the DRAM interface to match the DRAM used • Data Bus width (8, 16 or 32 bits) Data transmission type: 8x8 block read or write For prediction for half pixel precision For prediction for integer pixel precision For information on the detailed configuration of the DRAM interface Section A. See 5, DRAM Interface.

[1042] Table 152 shows how many DRAM interface "cycles" are required for each type of data transfer.

[1043]

[Table 152] Table 154 takes the numbers in Table 152 and evaluates them for a "typical" DRAM. In this example, 27MH
Assume z clocks. It should be recognized that 27 MHz is used here, but is not so limited. 11 ticks (102
ns), and 6 ticks (56) for data transmission.
ns) is required.

A. 18.5.2 "M without rearrangement
The loading of the "PEG resolution" peak memory bandwidth occurs when decoding B pictures. In a "worst case" scenario, B-frames are formed from predictions from both picture buffers, and all predictions are for half-pixel accuracy.

[1045]

[Table 153] Using the numerical example from Table 153, it can be seen that a DRAM interface 3815ns is required to read the data required for two accurate half-pixel precision predictions (via a 32-bit wide interface). The resolution that the temporal decoder can support is determined by the number of these predictions that can be performed in one picture time. In this example, the temporal decoder can process 8737 8 × 8 blocks in one 33 ms picture period (eg, for 30 Hz video).

[1046] Required video format is 704 × 48
If 0, each picture contains 7920 8 × 8 blocks (assuming 4: 2: 0 chroma sampling). This video format is available (before taking into account other factors such as DRAM refresh)
Consumes about 91% of M interface bandwidth. Therefore, the temporal decoder can support this video format.

A. [1047] 18.5.3 "MPE with Reorganization
G Resolution With MPEG picture reordering, worst case scenarios are encountered while P pictures are being decoded. During this time, three loads are made on the DRAM interface: morphological prediction write back the result read previous P or I picture.

Using the numerical examples from Table 152, one can find the required number of times for each of these tasks, if a 32-bit wide interface is available.
Predictive formation requires 1907 ns / n, while read and write each require 991 ns, for a total of 3889 ns. This is because the time decoder is 33
8485 8 × 8 blocks can be processed during the ms period.

Thus, processing 704 × 480 video would use almost 93% of the available memory bandwidth (ignoring refresh).

[1050] A. 18.5.4 “H.261” 261 is a CIF (35) with a picture rate up to 30 Hz.
It only supports two picture formats, 2 × 288) and QCIF (172 × 144). A CIF picture contains 2376 8 × 8 blocks. The only memory operations required are 8x8 blocks of wiring,
This is prediction formation using an integer precision motion vector.

Using the numerical example from Table 153 for an 8-bit wide memory interface, 3657 ns is required to write to each block, while 3963 ns / n is required for predictive formation of one block, It turns out that 7620 ns is required for each block as a whole.
The processing time for one CIF picture is about 18 ms, the 33 m needed to support 30 Hz video
significantly less than s.

A. [1052] 18.5.5 “JPEG” The resolution of JPEG video that can be supported is determined by the capabilities of the spatial decoder or display interface of the invention. The temporal decoder does not affect the JPEG resolution.

A. [1053] 18.6 “Events and Errors” 18.6.1 "Chip Stop" The present invention requires that writing a 1 to a chip access causes the temporal decoder to halt operation and allow re-formation. Once accepted, the normal time decoder will continue operation until it reaches the end of the current video sequence. Thereafter, the time decoder is stopped.

When the chip stops, a chip stop event occurs. chip stopped mask = 1
If so, an interrupt occurs.

A. 18.6.2 "Count Error" The temporal decoder of the present invention comprises an adder that adds a prediction to the error data. If there is a difference between the number of error data bytes and the number of predicted data bytes, a count error event occurs.

[1056] If count error mask = 1, an interrupt is generated and prediction formation stops.

[1057] 1 in count error event
Is written, the event is cleared and the time decoder advances. This is followed by the DATA token that caused the error. However, the DA that caused the error
The TA token will not be of the correct length (46 bytes). This will easily create additional problems. Thus, a counting error should only occur if a serious hardware error has occurred.

Section A. 19 "Connection to the Output of the Time Decoder" The output of the time decoder is a standard token port with an 8-bit wide data word. See Section A. for more information on interface electrical activities. See No. 4.

The token present at the output of the temporal decoder depends on the coding standard used,
In the case of G, it will depend on whether the pictures are rearranged or not. This section identifies which tokens are available at the output of the temporal decoder and which are most useful in designing circuits to display that output. Other tokens will be present, but they need not be displayed, so they are not discussed here.

[1060] This section focuses on and discusses the following points: how to identify the start and end of a sequence, how to identify the start and end of a picture, and when to display a picture And how to specify where to place the picture data on the display.

A. 19.1 "JPEG output" When decoding JPEG data, the token sequence output by the temporal decoder is the same as that seen at the output of the spatial decoder. Remember that JPEG does not require processing by a temporal decoder. However, the temporal decoder looks at the intra data token for negative values (arising from the limited arithmetic precision of the IDCT in the spatial decoder),
Replace them with 0.

A detailed discussion of the output sequences observed during JPEG operation is provided in Section A.1. 1
See No. 6.

A. 19.2 “H.261 output” 19.2.1 “Start and End of Session” H.261 does not signal the start and end of the video stream in the video data. Nevertheless, this is implied by the application. For example, the sequence starts when telecommunications is connected and ends when the line is interrupted. Thus, the highest layer in the video syntax is the “picture layer”.

[1064] The start code detector of the spatial decoder according to the present invention allows a sequence start and a coding standard token to be automatically inserted before the first picture start. Section A. 11.7.
3 and A. See 11.7.4.

[1065] H. At the end of the 261 session (eg, when the line is interrupted), the user must insert a flash token after the end of the encoded data. This has many effects (see A.31.1): It guarantees that the picture end is signaled to signal the end of the last picture.

It ensures that the end of the encoded data is pushed through the decoder. A. 19.2.2 "Picture acquisition" Each picture consists of a hierarchy of elements called a syntax layer. H. When decoding H.261,
The sequence of tokens at the output of the temporal decoder reflects this structure.

A. 19.2.1 "Picture Layer" Each picture is preceded by a picture start token,
A picture end token immediately follows the picture.
H. 261 does not naturally include the picture end. This token is automatically inserted by the start code detector of the spatial decoder. The picture start token will be followed by the time standard token and the picture type token. The time standard token supports a 10-bit number that indicates when the picture is to be displayed (of which 5LS
Only B is H. 261). H. 261
This should be studied by the display system since the encoder can omit pictures from the sequence (to achieve low data rates). Omission of pictures may be detected by a time reference that increases by one or more minutes between consecutive pictures.

Next, the picture type token has information about the picture format. The display system can examine this information and detect whether the CIF or QCIF picture has been decoded.
However, by examining the registers in the Huffman decoder, information about the picture format is also available. <Xref: Huffman decoder section> 19.2.2.2 "Block layer group" A 261 picture is composed of a number of “block groups”. Each is preceded by a slice start token (derived from the H.261 group number and group start code). This token has an 8-bit value that indicates where in the display the group of blocks should be placed. This provides an opportunity for the decoder to re-synchronize after a data error. In addition, it provides a mechanism for the encoder to skip blocks if there are picture areas that do not require additional information to render the picture. The spatial and temporal decoders each picture contains the correct number of blocks,
By the time the slice start reaches the output of the temporal decoder, that information is effectively redundant since we have already used this information to ensure that the blocks are in the correct location. Thus, by counting the number of blocks output since the start of the picture, it is possible to calculate where to place the data blocks output by the temporal decoder.

The number supported by the slice start is
H. This is one less than the group of the number of blocks of H.261 (refer to the H.261 standard for detailed information). FIG. 103 shows H.264 in CIF and QCIF pictures.
26 shows the positioning of a 261 block group.

Note: In the present invention, the block numbering shown is the same as that supported by the slice start. This is the H.264 for numbering these groups. 261 rules.

(Indicates the start of each block group)
There may be other tokens between the slice start and the first macroblock. Since they do not need to display picture data, they can be ignored.

A. 19.2.2.3 “Macroblock Layer” The sequence of macroblocks in each group of blocks is H.264. 261. There is no special token information describing the position of each macroblock. The user must count through the macroblock sequence to determine where to display each piece of information.

FIG. 105 shows a sequence in which macroblocks are arranged in each group of blocks.

Each macroblock contains six data tokens. The sequence of data tokens included in each of the six groups is described in H.264. 261 is limited by the macroblock structure. Each data token is 8x of one color component
It should contain exactly 64 data bytes for an 8 pixel area. The color components are included in the 2-bit number in the data token (see Section A.3.5.1).
However, H. et al. The sequence of the color components in H.261 is limited.

[1078] Each group of data tokens is preceded by a number of tokens that convey information about motion vectors, quantizer scale factors, and the like. These tokens do not need to have the picture displayed and can be ignored.

Each data token contains 64 data bytes for one 8.times.8 color component. These are in a raster state.

A. 19.3 MPEG Output MPEG includes many layers in its syntax. These embody concepts such as video sequences and picture groups.

A. [1078] 19.3.1 "MPEG Sequence Layer" A sequence can have multiple entry points (sequence start), but should have only one exit point (sequence end). When the MPEG sequence header code is decoded, the spatial decoder generates a coding standard token followed by a sequence start token.

After the sequence start, there will be many tokens of sequence header information describing the video format etc. See the draft MPEG standard for information signaled in the sequence header, and see Tables 3 through 11 for information on how this data is converted to tokens. This information describing the video format is also available in registers in the Huffman decoder.

This sequence header information may occur several times in an MPEG sequence if the sequence has several entry points.

A. [1081] 19.3.2 "Picture Layer Group" The MPEG group of pictures provides different types of "entry" points to those provided at the start of the sequence. The sequence header provides information about the picture / video format. Therefore, if the decoder has no knowledge of the video format used in the sequence, it must start at the sequence start. However, once the video format is configured in the decoder, it should be possible to start decoding at any group of picture locations.

[1082] MPEG does not limit the number of pictures in a group. However, in many applications, one group of random access reasonable grain
When providing a child , this corresponds to approximately 0.5 seconds.

The start of a picture group is indicated by a group start token. The header information provided after the group start has two useful tokens: T
Includes IME CODE and BROKEN CLOSED.

The TIME CODE owns a subset of the SMPTE time code information. This may be useful in synchronizing the video decoder to other signals. BROKEN CLOSED is MPEG clos
possesses ed gap and brokenlink bits. For the implications of random access and decoding of edited video sequences, see Section A.1. 1
See 9.3.8. A. 19.3.3 Picture layer The start of a new picture is indicated by a picture start token. This token is followed by a time standard token and a picture type token. If the temporal decoder is not configured to provide picture reordering, temporary reference information may be useful. The picture type information is displayed when the display system is particularly open GO.
It may be useful if you want to process B pictures at the start of P (see section A.19.3.8).

Each picture is composed of many slices.

A. 19.3.4 Slice layer Section A. 19.2.2.2 is H.264. 261 discusses the block groups used. MP
Slices in the EG perform a similar function. However, the slice structure is not fixed by reference. The 8-bit value owned by the slice start token is the MPE
This value is one less than the “slice vertical position” transmitted by G. See the MPEG Standard Draft for a description of the slice layer.

Since the spatial and temporal decoders have already used this information to ensure that each picture contains the correct number of blocks in the correct position,
By the time the slice start reaches the output of the time decoder, the information is effectively redundant. Thus,
By counting the number of blocks that have been output since the start of the picture, it is possible to calculate where to place the data blocks output by the temporal decoder.

For a discussion of the effects of using MPEG picture reordering, see Section A.1. See 19.3.7.

A. [1089] 19.3.5 "Macroblock Layer" Each macroblock contains 6 blocks. These are (MP
Appears at the output of the temporal decoder in raster state (as specified by the draft EG convention).

[1090] A. 19.3.6 "Block layer" Each macroblock contains six data tokens.
The sequence of data tokens contained in each of the six groups is defined by the MPEG draft standard, which is the same as the H.261 macroblock structure. Each data token should contain exactly 64 data bytes for an 8x8 pixel area of one color component. The color components are included in the 2-bit number in the data token (A.
See 3.5.1.). However, the sequence of color components in MPEG is limited.

[1091] Each group of data tokens is preceded by a number of tokens that convey information about motion vectors, quantizer scale factors, and the like. These tokens do not need to have the picture displayed and can be ignored.

A. [1092] 19.3.7 “Effect of MPEG Picture Rearrangement” As described in 18.3.5, the temporal decoder provides MPEG picture reordering (MPEG r
eordering = 1). The output of P and I pictures is delayed until the decoding of the next P / I picture in the data stream is started by the temporal decoder. At the output of the temporal decoder, the data token of the newly decoded P / I picture is replaced by the data token from the old P / I picture.

When rearranging P / I pictures, the picture start, time standard, and picture type tokens for the picture are temporarily stored on-chip as the picture is written to the off-chip picture buffer. When the picture is read for display, these stored tokens are retrieved. Thus, the reordered P / I pictures have the correct values for picture start, temporal standard, and picture type.

[1094] All other tokens below the picture layer are not reordered. As the reordered P / I picture is read out for display, it picks up the lower level non-data tokens of the picture just decoded. Thus, these sub-picture layer tokens should be ignored.

[1095] A. 19.3.8 “Random Access and Edited Sequences” The spatial decoder uses edited MPEG video data and M
Provide facilities to help correct video decoding after random access to PEG video data. A. 19.3.8.1 "Open GOP" A picture group (GOP) can start with a B picture predicted from a P picture in the previous GOP. This is called an “open GOP”. FIG. 116 illustrates this. Pictures 17 and 18 are the second GO
This is a B picture at the start of P. When the GOP is "opened", the encoder can encode these two pictures using predictions from P-picture 16 and I-picture 19. Alternatively, the encoder could be restricted to using predictions only from I-pictures 19. In this case, the second GOP is called a "closed GOP."

[1096] When the decoder starts video decoding in the first GOP, the GOP has already decoded the P picture 16,
Will not cause any problems if a second GOP is encountered, even if is open. However, if the decoder performs random access and starts decoding in the second GOP, it cannot decode B17 and B18 if they depend on P16 (ie, if the GOP is open). .

When the spatial decoder of the present invention encounters an open GOP as the first GOP following a reset or receives a flush token, it is assumed that a random access to the open GOP has occurred. In this case, the Huffman decoder would consume data for B pictures in the usual way. However, it is I
It will output a B picture predicted with a (0,0) motion vector away from the picture. As a result, pictures B17 and B18 (in the example above) will be identical to I19.

This action ensures the correct maintenance of the MPEG VBV rules. In addition, it ensures that B pictures are present in the output at locations in the output stream expected by other data channels. For example,
The MPEG system layer provides display time information about the audio data to the video data. The video display time stamp indicates the first display picture in the GOP, i.e., the picture with time reference 0. In the above example, after random access to the second GOP, the first picture displayed is B17.

[1099] Broken closed token is MPE
Owns the G closed gop bit. Therefore,
At the output of the temporal decoder, it is possible to determine whether the output of the B picture is genuine, or whether a "substitute" has been introduced by the spatial decoder. Some applications may wish to take special action when these "substitute" pictures are present.

[1100] A. 19.3.8.2 Edited Video If an application edits an MPEG video sequence, it may break the relationship between the two GOPs. If the edited GOP is an open GOP, it will no longer be able to decode B pictures correctly at the beginning of the GOP. MPEG
The application that edits the data is the GOP after editing
Can set a broken link bit to indicate to the decoder that these B pictures cannot be decoded.

[1101] G with link broken for spatial decoder
If an OP is encountered, the Huffman decoder will decode the data for the B picture in the usual way. However, it has moved away from the I picture (0,
0) Will output the B picture predicted by the motion vector. As a result, picture B1 (in the above example)
7 and B18 will be identical to I19.

[1102] Broken closed token is MPE
Owns G's broken link bit. Therefore, it is possible to determine whether the output of the B-picture is genuine or the "substitute" introduced by the spatial decoder in the output of the temporal decoder. Some applications may wish to take special action when these "substitute" pictures are present. Section A. 20 "post write DRAM Interface" interface can be configured in two ways: detailed timing of the interface is a variety of different D
It can be configured to accommodate a RAM type.

The "width" of the DRAM interface can be configured to provide a cost / performance trade-off.

[1104]

[Table 154]

[1105]

[Table 155]

[1106]

[Table 156]

[1107]

[Table 157]

[1108]

[Table 158]

[1109]

[Table 159] A. 20.1 "Interface Timing (tick)" In the present invention, the DRAM interface timing is a clock (decode) operating at four times the input clock rate of the device.
er clock). This clock is generated by the on-chip PLL.

[1110] For simplicity, the period of this high-speed clock is called a tick.

A. 20.2 "Interface Operation" The interface uses the fast page mode of the DRAM. Three different types of accesses are supported: • Read • Write • Refresh Each read or write access is one DRAM
A burst of 1 to 64 bytes is transmitted at the page address. Read and write transmissions are not mixed in one access. Each successive access is a new DRAM
Treated as random access to the page.

A. [1112] 20.3 "Access Structure" Each access consists of two parts: Access start Data transmission Each access is started by an access start, followed by one or more data transmission cycles. There are read, write and refresh variants for both access start and data transfer cycles.

At the end of the last data transmission in one access, the interface defaults,
It remains in this state until a new access is ready to start. When the last access is completed and the new access is ready to start, the new access starts immediately.

[1114] A. 20.3.1 "Access Start" The access start provides a page address for a read or write transmission and sets some initial signal states.
There are three different access starts: read start write start refresh start In each case, the timing of / RAS / and the row address are in the registers RAS falling and page.
It is controlled by the start length. / O
The state of E / and DRAM data [31: 0] is maintained from the end of the previous data transmission until it becomes / RAS /. The three different types of access start are /
When RAS / becomes / OE / and DRAM data
The only difference is the method of driving [31: 0]. See FIG.

[1115]

[Table 160] Table A. 20.3 Access Start Parameter Note a: This value is RAS fall to ensure that CAS is before a RAS refresh occurs.
ing must be smaller. A. 20.3.2 Data Transmission There are three different types of data transmission cycles: Fast page read cycle Fast page delayed write cycle Refresh cycle A refresh start is followed by only one refresh cycle. A read (or write) start is followed by one or more fast page read (or write) cycles.

At the start of the read cycle, the CAS
Is driven high, and a new column address is driven.

[1117] A delayed write cycle is used. / WE /
Is low by one tick after / CAS /. The output data is driven one tick after the address.

[1118] As / CAS / before / RAS /, the refresh cycle is initiated by a refresh cycle start, and there is no interface signal activity during the refresh cycle. The purpose of the refresh cycle is to meet the minimum / RAS / low period required by the DRAM.

[1119] A. 20.3.3 "Interface Default State" Interface signals enter a default state at the end of access: / RAS /, / CAS /, and / WE / are high. Data and / OE / remain at their previous state. Addr remains stable A. 20.4 “Data Bus Width” The 2-bit register DRAM data width configures the width of the data path of the DRAM interface. This minimizes DRAM costs when working with small picture formats.

[1120]

[Table 161] A. 20.5 “Address Bits” An on-chip 24-bit address is created. If this address is used and how to form the row and column addresses are different by the number of bits selected for the data bus width and the row address. Some configurations do not allow the use of all of the internal address bits (thus creating "hidden bits").

[1121] The row address is derived from the middle part of the address. This maximizes the rate at which the DRAM is naturally refreshed.

[1122] A. 20.5.1 "Low Order Column Address Bits" The least significant 4-6 bit column addresses are used to provide addresses for fast page mode transmission up to 64 bytes. The number of address bits required to control these transmissions depends on the width of the data bus. (See A.20.4) 20.5.2 “Row Address Bits” The number of bits taken from the middle section of the 24-bit internal address to provide a row address is stored in register r
ow address bits.

[1123]

[Table 162] The width of the row address used depends on the type of DRAM used and whether the MSB of the row address is a decoded off-chip for accessing multiple banks of DRAM.

Note: The row address is derived from the middle of the internal address. Bit with row address is DRAM
When decoding to select a bank, all possible values of these "bank select bits" must select a DRAM bank. Otherwise, holes will be left in the address space.

[1125]

[Table 163] A. 20.6 "DRAM interface enabled (ena
ble) "There are two ways to make all output signals on the DRAM interface high impedance. DRAM
An enable register and a DRAM enable signal. Both registers and signals must be logic 1 for the DRAM interface to operate. If either is low, the interface is made high impedance and data transmission over the interface is stopped.

[1126] The ability to bring the DRAM interface to high impedance is due to the fact that other devices are controlled by the spatial decoder (or time decoder) when the spatial decoder (or time decoder) is not in use.
Provided to allow RAM to be tested or used, but not to allow other devices to share memory during normal operation.

[1127] A. 20.7 "Refresh" Unless disabled by writing to the register no refresh, the DRAM interface will operate at / CA prior to the / RAS / refresh cycle at intervals determined by the register refresh interval.
Use S / to automatically refresh the DRAM.

[1128] The value of the refresh interval specifies the interval between refresh cycles in the period of 16 decoder clock cycles. 1
A value in the range of ~ 255 can be selected. Value 0 is automatically loaded after reset, forcing the DRAM interface to perform successive refresh cycles until a valid refresh interval is formed (once enabled). refres
It is recommended that hinterval be formed only once after each reset.

[1129] A. 20.8 "Signal Strength" The driving force of the output of the DRAM interface is a 3-bit register / CAS / strain, / RAS / s
It is formed by the user using the strength and the addr strength. The MSB of the 3-bit value selects either a high-speed or low-speed edge rate. Two less significant bits form the output for different load capacitances.

[1129] The default strength after reset is 6, and when loaded at 12 pF, forms an output that takes approximately 10 ns for the drive signal between GND and VDD.

[1131]

[Table 164] When the output is formed, approximately for the driving load, it will meet the AC electrical characteristics specified in Tables 168-169. When properly formed, each output will approximately match its load, and thus minimal overshoot will occur after a signal transition.

[1132] A. 20.9 "After Reset" After reset, all DRAM interface configuration registers are reset to their default values.
The most important of these default configurations are described below:-The DRAM interface is disabled,
You are allowed to go to high impedance.

The refresh interval is formed with a special value 0, which means that a continuous refresh cycle is performed after the interface has been re-enabled.

The DRAM interface is set to its lowest speed configuration.

[1135] Most DRAMs are initially applied with power and then after a number of refresh cycles before normal operation is possible, after 100 μs to 500 μs.
Request a “pause” for μs.

[1136] Immediately after the reset, the DRAM interface outputs the DRAM enable signal and the DRAM enable signal.
The inactive register is inactivated until both are set. When these are set, the DRAM interface will be activated (almost every 400 ns, depending on the clock frequency used) until the DRAM interface is formed.
A refresh cycle will be performed.

[1136] The user should be able to ensure that there is enough time after enabling the DRAM interface to ensure that the required number of refresh cycles after power up and before the attempted data transfer has occurred.
There is a responsibility to ensure the "pause" of the AM.

While declaring reset, the DRAM interface cannot refresh the DRAM. However, the reset times required by the decoder chips are short enough that they can be reset and then re-enable the DRAM interface before the contents of the DRAM collapse. This may be needed during debugging.

[1139]

[Table 165]

[1140]

[Table 166]

[1141]

[Table 167] A. 20.10.1 "AC characteristics"

[1142]

[Table 168]

[1143]

[Table 169] Section B. 1 "Start code detector" 1.1 “Outlook” As described above in FIG. 18, the start code detector (SCD) is the first block on the spatial decoder.
Its basic purpose is to use MPE in the input data stream.
G, JPEG and H.P. 261 start codes and replace them with the relevant tokens. It further allows user access to the input data stream via a microprocessor interface, and performs pre-formatting and "cleaning" of the token data stream. Recall that the SCD can receive either raw byte data or data already assembled in token format.

[1144] Typically, the start code is MPEG,
H. 24, 16 and 8 bits for H.261 and JPEG, respectively. The start code detector receives input data in bytes from either the microprocessor interface (upi) or the token / byte port and moves it through three shift registers. The first register is an 8-bit parallel serial out,
The second register is a programmable length (16 or 24 bits) where the start code is detected, and the third register is 15 bits wide and is used to reformat the data into 15 bit tokens. used. In addition, there are two "tag" shift registers (SRs) running in parallel with the second and third SRs. These include tags to indicate whether the associated bit in the data SR is good or bad. SCD not part of data token
Allows input bytes that are not recognized by to bypass the shift register and is output when all three shift registers have been flushed (empty) and the content has been output successfully. The recognized non-data token is S
Used to form CDs, spring traps, set flags. Furthermore, they bypass the shift register and are output unchanged.

[1145] B.I. 1.2 "Main Block" The hardware for the start code detector consists of 10 state machines.

[1146] B. 1.2.1 “Input circuit (scdip
c. sch. iplm. M) "The input circuit has three modes of operation: token, byte and microprocessor interface.
These modes assume that the data is a raw byte stream (but using a two-wire interface)
It can be input as a token stream or by the user via upi. In all cases,
The input circuit always outputs the correct data token by generating a data token header when appropriate. The transition to / from the upi mode is synchronized to the system clock and the upi is waited to a safe point in the data stream before gaining access. The byte mode pin determines whether the input circuit is in token mode or byte mode. Further, an initial notification to the system as to which criteria are being decrypted (and thus a coding standard token is issued) can be made in any of the three modes. B. 1.2.2 "Token decoder (scdipne
w. sch, scdipnem. M) "This block decodes incoming tokens and issues commands to other blocks.

[1147]

[Table 170] Note: Changes in coding standards are sent to all blocks via the two-wire interface after the SR has been flushed. This ensures that changes from one data stream to another occur at the correct point throughout the SCD. This principle applies throughout the display so that changes in coding standards can flow through all chips before a new stream.

[1148] B.I. 1.2.3 “JPEG (scdjp
eg. sch, scdjpegm. M) "The start codes (markers) in JPEG are sufficiently different, and every JPEG has its own state machine. In the present invention, this block is J
It handles all PEG marker detection, length counting / checking, and data removal. The detected JPEG marker is flagged as a start code (having v nott, see text below), and scdipne
Commands from w are overridden and forced to bypass. Operations are best described in code. switch (state) ｛case (LOOKING): if (input = 0xff) ｓｔ state = GETVALUE; / * Found a marker * / removed; / * Marker gets removed * / ＩＮK; (Input = 0xff) ｓｔ state = GETVALUE; / * Overlapping markers * / remove;｝ else if (input = 0x0-0) ｛state = LOOKING; / * the 0 × ff back / {else} command = BYPASS; / override command / if (lc) / Doset he marker have a length count / state = GETLC0; else state = LOOKING; break; case (GETLC0): loadlc0; / load the top length; LC; Break; case (DECLC): lcnt = lcnt-2 state = CHECKCK; break; case (CHECKCKLC): if (lcnt = 0) state = LOOKING; / No more to do / first 0 = LOOKING; / generate Illegal Le gth Error / else state = COUNT; break; case (COUNT): decrement length count until1 if (lc <= 1) state = LOOKING;} B. 1.2.4 “Input shifter (scinshft.
sch, scinshm. M) "The basic operation of this block is quite simple.
This block takes a data byte from the input circuit and
Load the shift register and shift it. However, it also follows the command from the input decoder,
Process transition to / from bypass mode (other SR
When a BYPASS command is received, the associated byte is not loaded into the shift register. Instead, use "rubbish" (tag =
1) is forced to output the data held in the other shift registers. The block then waits for a "flushed" signal indicating that this "rabish" has appeared on the token generator. The input byte is then sent directly to the token generator.

[1149] B.I. 1.2.5 Start Code Detector (scdetect.sch, scdetm.M) This block contains 16 or 24-bit start code detection logic and two shift registers that can be programmed into the "valid content" detection logic. . The MPEG start code requires a full 24 bits, but 2
61 requires only 16 bits.

In the present invention, the first SR is for data, the SR has no gap or stall (in the sense of a two-wire interface), but the second SR is whether or not a bit in the data SR is valid. , But the bits they contain may be flushed while being invalid (Ravish). When a start code is detected, a bit of the tag shift register is set to invalidate the contents of the detector SR.

The start code cannot be detected unless the contents of the SR are all valid. A non-byte aligned start code may be detected and flagged. Further, when a start code is detected, the non-aligned start code cannot be clearly flagged until the overlapping start code is looked up. To perform this function, the "value" of the detected start code (followed by a byte) is shifted right and scifshift through scinshift and scdetect. If scoshift is reached without detecting another start code,
Removed is the overlapping start code, which is flagged as a valid start code.

B. [1152] 1.2.6 "Output shifter (sco
shift. sch, scochm. M)] The basic operation of the output shifter is scdetect
To extract serial data (and a tag) from the data, pack it into a 15-bit word, and output it. Other functions are as follows: 1.2.6.1 "Data Padding" The output consists of 15-bit words, but the input can consist of any number of bits. Therefore, to flush, additional bits need to be added to make the last word up to 15 bits. These additional bits are called padding and must be recognized and removed by the Huffman block. Padding is defined as:
After the last data bit, a "zero" is inserted, followed by enough "things" to make up a 15-bit word.

A data word containing padding is output with low extension bits to indicate the end of a data token.

[1154] B.I. 1.2.6.2 Flush Occurrence According to the present invention, the occurrence of a "flush" operation involves detecting when all SRs are flushed and signaling it to the input shifter. When the "Ravish" inserted by the input shifter reaches the end of the output shifter and the output shifter has completed its padding,
A "flashed" signal is emitted. This "flushed" signal must pass through the token generator before it is safe for the input shifter to enter bypass mode.

[1155] B. 1.2.6.3 “Display of Valid Start Code Flag” When scdetect indicates that a start code has been found, padding is performed and the current data is output. The start code value (next byte) is shifted through the detector to remove overlapping start codes. If "value" reaches the output shifter without another start code being detected, it is not superimposed and the value is a flag vnott (ValueNotTok) indicating that it is a start code value.
en). However, while another start code is detected (by scdetect),
If the output shifter is waiting for its value, an overlapping error will be issued. In this case, the first value is discarded and the system waits for the second value. This value can also be repeated, so that the same procedure is repeated until a non-overlapping start code is found.

[1156] B. 1.2.6.4 "tyding up" after the start code has been detected and output, a new data header is created when data (not rabbis) starts to arrive.

B. [1157] 1.2.7 “Data stream generators (stokrec.sch, scokrem.
M) "The data stream generator is one from scinshift for bypassed tokens and the other is scoshi for packed data and start codes.
It has a two wire interface input from ft. Switching between the two sources is only allowed after the current token (from either source) has completed (the low extension bit that has arrived).

[1158] B. 1.2.8 “Start value for starting number conversion (scdromhw.sch,
schrom. M) "The process of converting start values into tokens is performed in two stages. This block deals primarily with coding standard dependent issues that reduce 520 odd position codes to 16 coding standard independent indexes. As mentioned earlier, the start value (including the JPEG value) is identified by a flag (value not token) from all other data. If v not t is high, this block will convert the 4- or 8-bit value to a standard-independent 4-bit s, depending on the coding standard.
Convert to start number and flag the unrecognized start code. The starting numbers are as follows:

[1159]

[Table 171]

[1160]

[Table 172]

[1161]

[Table 173] B. 1.2.9 "Start Number for Token Conversion (convert.sch, convert.
M) "In the second stage of conversion, the start number (or index) is converted into a token. This block also handles the extension and search modes, which properly discard the extension and user data.

The search mode is a means for entering a data stream at random points. The search mode can be set to one of eight values: 0: normal operation-find the next start code.

11/2: The system level search is not performed for the spatial decoder.

[1164] 3: Search for more than sequence 4: Search for more than group 5: Search for more than picture 6: Search for more than slice 7: Search for next start code Non-zero search mode is desired Data is discarded until a start code (or higher in syntax) is detected.

[1165] This block further includes PICTURE and S
Add a token extension to the LICE start token.

[1166] Picture start is PICTURE N
UMBER is extended by a 4-bit count of a picture.

The slice start is extended by svp (slice vertical position). This is the start code minus 1 (MPEG, H.261) and minus OXDO
(JPEG) “value”.

B. [1168] 1.2.10 “Data stream formatting (scinsert.sch, sci
nserx. M) "In the present invention, data stream formatting relates to the conditional insertion of picture end, flash, coding standard, sequence start tokens, and the occurrence of a STOP AFTER PICTURE event. Its function is best simplified and described in software: switch (input data) case (FLUSH) 1. if (in picture) output = PICTURE END output = FLUSH if (in picture & stop after
3. er picture) sap error = HIGH in picture = FALSE; in picture = FALSE; break case (SEQUENCE START) 1. if (in picture) output = PICTURE END if (in picture & stop after
er picture) 2a. output = FLUSH 2b. 2. saperror = HIGH in picture = FALSE output = CODING STANDARD 4. output = standard5. 5. output = SEQUENCE START in-picture = FALSE; break case (SEQUENCE END) case (GROUP START): 1. if (in picture) output = PICTURE END if (in picture & stop after
er picture) 2a. output = FLUSH 2b. 2. saperror = HIGH in picture = FALSE 3. output = SEQUENCE END or GROUP START in-picture = FALSE; break case (PICTURE END) 1. output = PICTURE END if (stop after picture) 2a. output = FLUSH 2b. saperror = HIGH 3. in-picture = FALSE break case (PICTURE START) 1. if (in picture) output = PICTURE END if (in picture & stop after
er picture) 2a. output = FLUSH 2b. saperror = HIGH 3. if (insert sequence star
t) 3a. output = CODING START 3b. output = standard 3c. output = SEQUENCE START insert sequence start = FAL
SE 4. output = PICTURE START in picture = TRUE break default: Just pass it through
Ugh section B. 2 "Huffman Decoder and Parser (p
arser) "B. 2.1 Overview This section describes the Huffman decoder and parser circuit according to the present invention.

FIG. 127 shows a high level block diagram of the Huffman decoder and parser. For clarity, the main diagram omits many signals and buses, and in particular there are some places where data is sent backwards (within the large loop shown).

In essence, the Huffman decoder and parser of the present invention consist of a number of dedicated processing blocks (shown along the bottom of the diagram) controlled by a programmable state machine.

The data is received from the encoded data buffer by "in shift" blocks. At this point, there are essentially two types of information that will be encountered: the encoded data owned by the data token, and the star code that has already been replaced by each token by the start code detector. All tokens (other than data tokens) are handled in the same way, although other tokens may be encountered. The token (start code) is treated as a special case (in H.261, JPEG or MPEG) as more data is to be encoded.

In the present invention, all data possessed by the data token is transmitted to the Huffman decoder in serial form (bit by bit). Of course, this data includes many fields that are not Huffman encoded, but are encoded with a fixed length. Nevertheless, this data is sent serially to the Huffman decoder. In the case of Huffman coded data, the Huffman decoder performs only the first stage of decoding where the actual Huffman code is replaced by the number of indices. If the special code table to be decoded includes N District Huffman codes, the range of this "Huffman index" is 0-N-1.
In addition, the Huffman decoder has a "no op" or "no operation" mode, which allows it to be sent to the next stage along with the data or token information without processing by the Huffman decoder.

The data unit index is a relatively simple circuit block that performs a table lookup operation. It retrieves its name from the second stage of the Huffman decoding process, where the index numbers obtained at the Huffman decoder are converted into actual decrypted data by a simple table lookup. The data unit index acts as one logical unit in cooperation with the Huffman decoder.

The ALU is the next block and is provided to add other transformations to the decrypted data. The data unit index portion is suitable for relatively arbitrary mapping, and the ALU can be used where arithmetic is more appropriate. The ALU has a register file that can be manipulated to implement various parts of the decoding algorithm. In particular, registers holding vector prediction and DC prediction are included in this block. ALU is based around a simple adder with operand selection logic. In addition, it includes dedicated circuitry for operation of the sign extension type. Although shift operations are likely to be performed, this will be performed in a serial fashion and there will be no barrel shifter.

The token formatting unit according to the present invention is the last block in the video parser and is responsible for finally incorporating the decrypted data into a token that can be sent to the rest of the decoder. At this point, there are many tokens that will be used by the decoder for this particular picture.

The parser state machine, which is 8 bits wide and is used with a two-wire interface,
Do the job of coordinating the operation of the other blocks.
In essence, it is a very simple state machine, creating a very wide range of "macrocode" control words that are sent to other blocks. FIG. 127 shows that the command word passes on the data side from block to block. It is important to understand that this is the case and that transmission between different blocks is controlled by a two-wire interface.

In the present invention, there is a two-wire interface between each block in the video parser. Further, the Huffman decoder operates with serial, data, and control tokens, and the inshifter inputs data one bit at a time. Thus, there are two modes of operation. When data is input to the Huffman decoder via a data token, the data passes through the shifter one bit at a time. In addition, there is a two-wire interface between the inshifter and the Huffman decoder. However,
Other tokens are not shifted one bit at a time (serial), but rather in the header of the token. When the data token is input, the header including the address information is deleted, and the data next to the address is shifted one bit at a time. If it is not a data token, all tokens, headers and everything are displayed all at once at the Huffman decoder.

It is important to understand that in the present invention, a two-wire interface for a video parser is unusual in having two valid lines. One line is valid serially and the other line valid for token. Furthermore, both line tokens may not be able to assert at the same time. If one line is asserted or there is no valid data, there may be two valid lines and neither can be asserted, and there is only one accept wire in the other direction. You should be aware. However, this is not a problem. The Huffman decoder can know whether it wants serial data or token information as needed based on the current syntax, as needed. Accordingly, a valid accept signal is set accordingly and Accept is sent from the Huffman decoder to the inshifter. If the appropriate data or token is present, the inshifter sends a valid signal. For example,
A typical command decodes the Huffman code, translates it in the data unit index, and places the result in A
It can be modified in the LU and the result is formed in the token word. One microcode command word is created that contains all the information to accomplish this. Commands are sent directly to the Huffman decoder, which “inshifts” until it has decoded the complete symbol.
Request data bits one by one from the block. Control tokens are input in parallel. Once this occurs, the decrypted index value is sent to the data unit index along with the original microcodeword.
The Huffman decoder requires several cycles to perform this operation, and in fact the number of cycles is determined by the data to be decoded. The data unit index then maps this value using the table specified in the microcode command word.
This value is sent again to the next block, ALU, along with the original microcodeword. When the ALU has completed the appropriate operation (the number of cycles may also be data dependent), the ALU sends the appropriate data to the token formatting block, along with the microcode words that control how the token words are formed.

The ALU has a "condition code" that is sent back to a number of status wires or parser state machines. This allows the state machine to execute conditional jump commands. In fact, all commands are conditional jump commands: one of the selectable conditions is wired to the value "False". By selecting this condition, a "no jump" command can be configured.

According to the present invention, the token formatting unit has two inputs: a data field from the ALU and / or a constant field coming from the parser state machine. In addition, there is a command telling the token formatting unit how many bits to take from one source and to fill with the remaining bits from the other source for a total of 8 bits. For example, HORI
ZONTAL SIZE is HORIZONTAL SI
It has an 8-bit field that is an unchanging address that identifies it as a ZE token. In this case, 8 bits are obtained from certain fields and no data is obtained from the ALU. However, if it were a data token, six bits from a given field would be readily available, with the lower two bits indicating the color component from the ALU. Therefore, the token formatting unit obtains this information and places it in the token for use in the rest of the system. It should be noted that in the above example, the number of bits from each source is for illustrative purposes only and those skilled in the art will recognize that the number of bits from any source can be varied. .

The ALU contains a counter bank used to count through the structure of the picture. The dimensions of the picture are programmed into registers associated with counters that appear in the "microprogrammer" as part of the register bank. Some condition codes are output from this counterbank, which allows conditional jumps based on "picture start", "macroblock start", etc.

It should be noted that the parser state machine is also called "demultiplex state machine". Both terms are used in this document.

In the present invention, the input shifter is composed of two pipeline stage data paths “hfidp” and control Zcells “hfp”.
This is a very simple circuit composed of i ″.

In the first pipeline stage, token decoding occurs. At this stage, only the data token is recognized. The data contained in the data token is shifted one bit at a time to the Huffman decoder. The second pipeline stage is a shift register. In the last word of the data token,
Special coding occurs so that any number of bits can be transmitted through the encoded data buffer. All possible patterns in the last data word are described below.

[1185]

[Table 174] As the data bits are shifted left one by one in the shift register, the bit pattern "all numbers following 0" is sought (padding). This indicates that the remaining bits in the shift register are not valid and are discarded. Note that this operation occurs only in the last word of the data token.

As mentioned above, all other tokens are sent to the Huffman decoder in parallel. They are also loaded into the second pipeline stage, but no shift occurs. Note that the data header is discarded and not sent to Huffman at all. Two "live" wires (out
valid and serial valid) are provided. Only one is asserted at a given time, which indicates what type of data is displayed at that moment.

[1187] B. 2.2 “Huffman Decoder” The Huffman decoder has a number of operation modes. The most notable is that it deciphers the Huffman code,
The idea is to convert them to Huffman index numbers.
In addition, the Huffman decoder is capable of decoding (in bits) a fixed length code of a length determined by the command word. The Huffman decoder can also receive tokens from the inshift block.

The Huffman decoder is a very small state machine. This is used when decoding block level information. This is because the parser state machine takes too long to make a decision (because it has to make decisions about the data and wait for the data to flow through the data unit index and the ALU before issuing a new command). Because it must be). When this state machine is used, the Huffman decoder itself includes the data unit index portion and the AL unit.
Issue a command to U. Since the Huffman Decoder State Machine cannot control all of the microcode command bits, it cannot issue a full range of commands to other blocks.

[1189] B. 2.2.1 "Theory of Operation" When decoding a Huffman code, the Huffman decoder of the present invention uses an arithmetic procedure to decode an input code into a Huffman index number. This number is between 0 and N-1 (for a code table with N entries). Bits are received one by one from the input shifter.

A number of tables are required to control the operation of the machine. These are the codes (1
For each possible number of bits (.about.16 bits), specify how many codes are of that length. As expected, this information is typically not enough to specify a common Huffman code. However, MPE
G, H. In H.261 and JPEG, the Huffman code is selected such that this information alone can specify the Huffman code table. Unfortunately, there is one exception: H.264, which is also used in MPEG. 261
9 is a Tcoefficient table from. This requires additional tables described elsewhere (exceptions were intentionally introduced in H.261 to avoid start code emulation).

It is important to recognize that the tables used by this Huffman decoder are exactly the same as those transmitted to JPEG. This allows these tables to be used directly, while other designs of the Huffman decoder may have required the creation of internal tables from those transmitted. This would have required additional storage and additional processing for the conversion.
MPEG and H.264. The table at H.261 can be described similarly (with the exceptions mentioned above), making a multi-standard decoder practical.

The following "C" fragment describes the decoding process: int total = 0; int s = 0; int bit = 0; unsigned long code = 0; int index = 0; while (index> = total) Ｉ if (bit> = max bits) fall (“huff decode: ran off end of huff table＼n”); code = (code << 1) Index bit0; index = code-s + total; S = (s + codes per bit [bit]) <<1; bit ++;｝ Generally, there is an advantage in the fact that certain intermediate values can be calculated in the clock phase before they are needed. The process is directly mapped into the silicon implementation.

From the code fragment: EQ1. total_{n + 1}= Total_n+ Cpb
_n  EQ2. ’S_{n + 1}= 2 ('S_n+ Cpb_n) EQ3. code_{n + 1}= 2 code_n+ Bit_n  EQ4. index_{n + 1}= 2 code_n+ Bit
_n+ Total_n-'S_n However, In hardware, the "shifted" variable
Is a series of modified expressions where is used in place of the variable "S"
Turned out to be easier to use. This place
If: EQ5. shifted_{n + 1}= 2shifted
_n+ Cpb_n  We see the following: EQ6. i_n= 2 Shifted_n  Therefore, replacing this with Equation 4 again gives the following equation:
Yes: EQ7. index_{n + 1}= 2 (code_n-Sh
ifted_n) + Total_n+ Bit_n  In addition to calculating successive values of the "index",
Need to know when the calculation is complete. "
From the C "code fragment: EQ8.index_{n + 1}<Total_{n + 1}  It turns out that it is completed at the time.

[1194] By replacing Equations 7 and 1, EQ9. 2 (code _n −shifted _n ) + bit
It can be seen that the process is completed when _n− cpb _n <0.

In the hardware implementation of the present invention,
Q. 7 and EQ. 9, a common term (code _n
−shifted _n ) is calculated one phase before the rest of these expressions are evaluated to give the final result and information that the calculation is “completed”.

[1196] One warning word. Various "C" codes,
Especially behavior edited code Huffman decoder, and sm4
In the code project, the "C" fragment is used almost directly, but the variable "S" is effectively called "shifted". Thus, there are two different variables called "shifted". One of the "C" codes and the other one in the hardware implementation. These two variables depend on two factors.

[1197] B. 2.2.1.1 Data Bit Inversion There is another piece of information needed to correctly decode the Huffman code. This is the polarity of the encoded data. H. 2
It can be seen that 61 and JPEG use the opposite convention. This is H. The start code of 261 is zero bits, whereas the JPEG marker byte is one bit.

In order to process both rules, the encoded data is H.264. To decode a Huffman code in the H.261 style, it is necessary to invert the encoded data bits as they are read into the Huffman decoder. This is waste
It performed in the obvious way of using the other OR gate. Note that when decoding a fixed length code, the inversion is performed only for the Huffman code, since the data is not inverted.

MPEG uses a defined mixture of the two. H. In the phase inherited from H.261, 261
Provisions are used. In aspects inherited from JPEG (DC intra coefficient decoding), JPEG rules are used.

B. 1200. 2.2.1.2 "Conversion coefficient table" There are some anomalies when using the transform coefficient tables in H.261 and MPEG. First, the MPEG table is H.264. This is a super set of 261 tables. In the hardware implementation of the present invention, there is no distinction drawn between the two standards, which is an H.264 code that includes code from an extension of the table (ie, the MPEG code). Means that the H.261 stream will be decrypted in a "correct" manner. Of course, other aspects of the compression standard are similarly deciphered . For example, these extension codes are
261 will cause a start code emulation.

[1201] Second, the conversion coefficient table is code per
It has an anomaly meaning that it cannot be explained by a normal method using a bit table. This anomaly occurs with a 6-bit code. These codewords are systematically replaced by replacement codewords. In the encoder,
The correct result is obtained in the usual way by the first encoding. Then, for all codes 6 bits or more in length, a simple table lookup operation replaces the first 6 bits with another 6 bits. In the decoder according to the invention, the decoding process is interrupted just before the sixth bit is decoded, the codeword is replaced using a table lookup and decoding continues.

In this case, there are only 10 possible 6-bit codes, so the lookup table required is very small. In addition, the operations are the top two
Helped by the fact that the bits are not changed by the operation. As a result, there is no need to use a true lookup table. Instead, a small group of gates is routed and the appropriate conversion is performed. The module that does this is called "hftcfrng".
This type of code replacement is referred to in the text as a "ring" because each code from the possible code set is replaced by another code from that set (no new code is introduced or old code is omitted). Stipulated.

Further, a unique implementation is made for the first coefficient in the block. In this case, it is not possible for a block end code to occur, so that the most commonly occurring symbols can use codes that would otherwise be interpreted as block ends. Is corrected. This saves one bit. A configuration for decoding according to the invention, which is easily accommodated. Briefly, if the "index" is value zero, then for the first bit of the first coefficient,
Decoding is considered finished. Furthermore, after decrypting only one bit, there are only two possible values for the "index", zero and one, and only one bit needs to be tested.

B.1204. 2.2.1.3 "Register and Adder Size" The Huffman decoder of the present invention can process Huffman codes up to 16 bits. However, decoding machines are 8 bits wide. This is possible because we know that the Huffman index value to be decoded is at most 255. In fact, this is an extended JP
It can only occur in the EG, and in current applications the limit is somewhat lower (but greater than 128 so 7 bits is not enough).

[1205] For all legal Huffman codes,
It can be seen that not only the final value of the “index” but also all the intermediate values are in the range of 0 to 255. However, for attempts to decode illegal codes, i.e. codes that are not in the current code table (possibly due to data errors), the index value can exceed 255.
Since we are using an 8-bit machine, at the decoding end, the final value of the "index" is 255
Not exceed. The more important bits that tell us that an error has occurred have been discarded. Thus, whenever the index value during decoding exceeds 255 (ie, a carry from the adder forming the index), an error occurs and decoding is abandoned.

[1206] The 12 bits of the "code" are protected. 3
This is not necessary for decoding Huffman codes where a bit register is sufficient. These upper bits are needed for a fixed length code that can read up to 12 bits.

[1207] B. 2.2.1.4 "Operation for Fixed Length Codes" For fixed length codes, the "code per bit" value is forced to be zero. This means that "overall" and "shifted" remain zero throughout the operation, so the "index" is the same as the code.
In fact, Adders et al. Ensure that only 8-bit values are created for the "index". Thus, when decoding a fixed length code, the upper bits of the output word are taken directly from the "code" register. When decoding the Huffman code, these upper bits are forced to be zero.

The fact that enough bits have been read from the input is calculated in an obvious way. The comparator compares the desired number of bits to a "bit" counter.

[1209] B.I. 2.2.2 "Decoding coefficient data" The parser state machine according to the invention is generally only used for fairly high levels of decoding. 8
Very low level decoding in bit-by-bit data blocks is not directly handled by this state machine. The parser state machine issues commands to the Huffman decoder in a "decrypt block" form. The Huffman decoder, data unit index, and ALU work together under the control of a dedicated state machine (essentially in the Huffman decoder).
This arrangement allows for high performance decoding of entropy coded coefficient data. There are also other feedback paths operated in this operation mode. For example, in JPEG decoding where the VLC is decoded to provide SIZE and RUN information, the SIZE information is sent back to the Huffman decoder directly from the output of the data unit index to determine how many FLC bits to read. Instruct the decoder. In addition, several accelerators are implemented. For example, using the same example and considering the Huffman index value before the data index stage, all VLC values that result in a zero size are explicitly captured. This means that for non-zero SIZE values, the Huffman decoder can proceed to read one FLC bit before the actual SIZE value is known. This means that no clock cycle is wasted since the reading of the first FLC bit overlaps with one clock cycle required to perform a table lookup in the data unit index.

[1210] B. 2.2.2.1 "MPEG and H.264"
FIG. 133 shows that AC coefficients are MPEG and H.264. 261 shows the decryption method. A flowchart detailing the operation of the Huffman decoder is shown in FIG.

[1211] The process starts by reading the VLC code. In a normal event, the Huffman index is directly mapped to a 6-bit RUN and a value representing the absolute value of the coefficient. Thereafter, the FLC1 bit is read, giving the sign of the coefficient. The ALU assembles the absolute value of the coefficient with this sign bit and provides the final value of the coefficient.

At this point, since the data format is of the sign magnitude, there is almost no difficulty in this operation. The RUN value is sent to a 6-bit auxiliary bus, while the coefficient value (level) is sent to a normal data bus.

There are two special cases, which are captured by considering the decrypted index value before the data index operation. These are block end (EOB) and escape coded data. In the case of an EOB, the fact that this has occurred is passed through the data unit index section and the ALU block so that the token formatting section can properly close the opened data token.

The escape coded data is more complicated. The first 6 bits of the RUN are read and these are sent directly through the data unit index and
U. Thereafter, the FLC1 bit is read. This is the case for MPEG and H.264. 261 is the most significant bit of the eight bits of the escape described in
Give a level sign. The signature is read explicitly in this implementation, because different commands need to be sent to the ALU for negative versus positive value. This allows the ALU to convert the two's complement value in the bitstream to sine magnitude. In either case, the remaining 7 FLC bits are subsequently read. If this is value zero, an additional 8 bits must be read.

In the present invention, the internal state machine of the Huffman decoder is responsible for generating commands for its own control and also for controlling the data unit index, ALU, and token formatting. As shown in FIG. 133, the commands for the Huffman decoder come from one of three sources; the parser state machine, the Huffman state machine, or one of the commands stored in a register previously received from the parser state machine. In essence, primitive commands from the parser state machine (which let the Huffman state machine take over control and read the coefficients) are kept in registers, that is, used each time a new VLC is needed. All other commands for decoding are supplied by the Huffman State Machine.

[1216] B. 2.2.2.2 "MPEG DC coefficient data" This is processed in the same way as JPEG DC coefficient data.
It is the responsibility of the controlling microprocessor to ensure that the same (loadable) table is used and that its contents are correct. The only real difference from the MPEG standard is that the predictor is set to zero (as in the case of JPEG) and the correction is made in the inverse quantizer.

[1217] B. 2.2.2.3 "JPEG Coefficient Data" FIG. 129 is a block diagram showing hardware for decoding JPEG AC coefficients according to the present invention. DC
The diagram works for both AC and DC coefficients, since the process for coefficients is essentially a simplification of the JPEG process. The only thing that really adds to the previous diagram for MPEG AC coefficients is that the "SSSS" field is sent back and can be used as part of a Huffman decoder command to specify the number of FLC bits to be read. The remaining commands are provided by the Huffman State Machine.

FIG. 130 depicts a flowchart for Huffman decoding of AC and DC coefficients.

The process for AC coefficients is first addressed, but the process starts by reading the VLC using the appropriate table (there are two AC tables). The Huffman index is then converted to a RUN and SIZE value in the data unit index. Two values are captured at the Huffman index stage, but for EOB and ZRL. These are the only two values that do not read any FLC bits. If the decode index is not for these two values, the Huffman decoder immediately returns FLC1
While reading the bits, wait for the data unit index to complete the lookup operation and determine how many bits are actually needed. EO
In case B, no further processing is required by the Huffman state machine in the Huffman decoder, and another command is read from the parser state machine. For ZRL, no FLC bits are needed, but the block is not completed. In this case, the Huffman decoder uses (using the same table as before) a further VLC
Start decrypting immediately.

There are special problems in detecting index values associated with ZRL and EOB. This is because the Huffman table is downloadable (unlike H.261 and MPEG). Two JPEG A
Two registers are provided for each of the C tables (one for ZRL and one for EOB). These are loaded when the table is downloaded. They hold index values associated with the appropriate symbol.

The ALU must convert the SIZE bit FLC code to the appropriate sign magnitude value. These are loaded when the table is downloaded. They hold index values associated with the appropriate symbol. The ALU must convert the SIZE bit FLC code to the appropriate sign magnitude value. This is done by first sign-extending the value with the wrong sign.
When the sign bit is newly set, the remaining bits are then inverted (one's complement).

In the case of DC coefficients, there is no equivalent in the ZRL field, so decision making in the Huffman decoding stage is somewhat easier. The only symbol that causes a zero FLC bit to be read is an indication of a zero DC difference. This is again captured in the Huffman index stage, to hold this index for each (downloadable) JPEG DC table,
A register is provided.

The ALU of the present invention (known as prediction)
It does the job of forming the final decoded DC coefficient by keeping a copy of the last DC coefficient value. 4
Four predictors are required, one for each of the active color components. When the DC difference is decoded, ALU
Adds the appropriate predictor to form the decoded value. This is also stored as a predictor for the next DC difference for that color component. Since the DC coefficients are signed (due to the DC offset), a conversion from 2's complement to sine magnitude is required. Thereafter, the value is output with a RUN of zero. In fact, the command to perform part of this last stage is not provided by the Huffman state machine. They are simply performed by the parser state machine.

In a similar way for the AC coefficients, A
The LU must first generate a DC difference from the SIZE bits of the FLC. However, this requires that the two complement values be added to the predictor. This is formed by first sign-expanding with the wrong sign, as described above. If the result is negative, one must be added to form the correct value. Of course, this can be added simultaneously with the predictor by stuffing the carry into the adder.

[1225] B. 2.2.3 “Error processing” Error processing is worth explaining. There are actually four sources of error to be detected: Off the table end.

When a token is expected, it is serial.

The token is when the serial is expected.

There are too many coefficients in the block.

The first of these occurs in two situations. When the bit counter reaches 16 (legal value is 0 to 15), an error occurs because the longest legal Huffman code is 16 bits. If the intermediate value of the “index” exceeds 255, the section B. As described in 2.2.1.3, an error occurs.

The second occurs when serial data is encountered when a token is expected. The third occurs when the opposite situation occurs.

The last type of error occurs when a block has too many coefficients. This is actually detected in the data unit index part.

When any of these conditions occur, the error is noted in the Huffman error register and the parser state machine is interrupted. It is the responsibility of the parser state machine to handle errors and issue the necessary commands for recovery.

Huffman cooperates with the parser state machine upon interruption to ensure correct operation. When the Huffman decoder interrupts the parser state machine, it can wait for a new command to be accepted at the output of the parser state machine. The Huffman Decoder will not accept this command for two full cycles after interrupting the parser state machine. This allows the parser state machine to remove the command there (which should not be executed now) and replace it with the appropriate one. After these two cycles, the Huffman decoder restarts normal operation and accepts a valid command, if any. Otherwise, it will do nothing until the parser state machine shows a valid command.

[1234] If any of these errors occur,
If the "Huffman Error" event bit is set and the mask bit is set, the block will stop and the control microprocessor will be interrupted in the usual way.

In some situations, what looks like an error may not actually be an error. The most important situation where this occurs is when reading a macroblock address. MPEG, H .; 261 and JPEG
In the syntax of, it is legal for a token to occur instead of the expected macroblock address. If this happens in a legal way, the Huffman error register is loaded with zero (meaning no error), but the parser state machine is still interrupted. The parser state machine code is aware of this no error situation and responds accordingly. In this case, the "Huffman Error" event bit will not be set and the block will not stop processing.

[1236] Various situations must be dealt with.
First, the token occurs immediately and the serial bit does not advance. In this case, a "token error when serial is expected" would have occurred, but instead, no
Error errors occur in the manner described above.

Second, there are a few serial bits before the token. In this case, a decision is made. If all bits before the token had the value 1,
(Recall that in H.261 and MPEG, the coded data is inverted, so remember that the coded data file has zero bits.) No error occurs. However, if any of them are zero, they are not valid stuffing bits and thus an error will occur and a "token if serial is expected" error.

Third, there are many bits before the token. In this case, the same decision is made. If all 16 bits are 1, they are treated as padding bits and a no error error occurs. If any of them is zero, an error "off the Huffman table" occurs.

Another place where tokens occur unexpectedly is in JPEG. When processing either the Huffman table or the quantizer table, any number of tables can occur in the same marker segment. The Huffman decoder cannot tell how many tables there are. Thus, after each table is completed, the Huffman decoder reads another 4 bits of FLC and assumes that it is the new table number.
However, when a new marker segment starts, a token will be encountered instead of a 4-bit FLC. This requirement is not anticipated, and therefore Ignore
An Errors command bit has been added.

1240. 2.2.4 Huffman Commands Here are the bits used by the parser state machine to control the Huffman decoder blocks and their definitions. The data unit index part command bit is also included in this table. From a microprogrammer's point of view, the Huffman decoder and the data unit index act as one compact logic block.

[1241]

[Table 175] B. 2.2.4.1 “FLC Read” In this mode, Ignore Errors, Dow
nload, Alutab, Token, First
Coeff, Special and VLC are all zero. Bypass is set so that data index conversion does not occur.

The binary numbers in table [3: 0] indicate how many bits to read. Numbers 0-12 are legal. Value zero actually reads the zero bit (as would be expected), so this command is a Huffman decoder NOP command. Value 13, 14,
15 is inactive and value 15 is used when the Huffman state machine is under control and indicates the use of "SSSS" as the number of FLC bits to be read.

B.1124 2.2.4.2 "VLC Read" In this mode, Ignore Errors, Dow
nload, Alutab, Token, First
Coeff, and Special are zero, and V
LC is 1. Normally, Bypass is set so that data index conversion occurs.

In this mode, Token, First
Coefficient and Special are all zero and VLC is one.

The binary numbers in table [3: 0] indicate the table to be used as shown below.

[1246]

[Table 176] In the case of a table held in RAM (that is, a JPEG table), bit 1 is not used and the
Note that it occurs several times. When a non-baseline JPEG decoder is created, there are four DC tables and four AC tables, and table [1] is required.

If table [3] is zero, the table is H.264. To be read correctly as a 261 style table, the input data is inverted when used. If Table [3: 0] = 0, the appropriate Ring modification is also applied.

[1248] B. 2.2.4.3 “NOP Command” As described above, the operation of reading the zero-bit FLC is used as the No Operation command. No data (either token or serial) is read from the input port and the Huffman decoder outputs a data value of zero with the command word.

[1249] B. 2.2.4.4 “TCoeffic
ient first coefficient " The H.261 and MPEG TCoefficient tables have a special non-Huffman code used for the first coefficient of the block. To decode the TCoefficient at block start,
The First Coefficient bit may be set to table zero with the VLC command. First
One of the many effects of the Coefficient bit is to allow this code to be decoded.

In normal operation, TCoeff
Note that issuing a "simple" command to read the client VLC is unusual. This is usually S
This is because by setting the special bit, control is passed to the Huffman decoder.

B. [1251] 2.2.4.5 "Read Token Word" To read a token word, the Token bit should be set to one. Special and First C
The effective bit should be zero.
If the table [0] bit works correctly, VLC
Bits should also be set.

In this mode, bit table [1] and table [2] are used to modify the read token action as follows:

[1253]

[Table 177] If Table [0] and Table [1] are zero, the presence of serial data before the token is considered an error and such a signal is issued.

If table [1] is set, all serial data is discarded until a token word is encountered. No error will occur due to the presence of this serial data.

If table [0] is set, the padding bits will be discarded. Of course, it is necessary to know the polarity of the padding bit. This is VLC
It is determined by table [3] in exactly the same way as for data reading. If table [3] is zero, the input data is first inverted and then any "1" bits are discarded. If table [3] is set to 1, the input data is not inverted and the "1" bit is discarded. Since the operation of inverting data according to the table [3] bit is conditional on the VLC bit, this bit must be set to one. A bit that is not a padding bit is encountered (ie, H.2
61 and "1" bit in MPEG)
Errors are reported.

Note that in these commands only one token word is read. The state of the extension bit is ignored and it is the responsibility of the demultiplexer to test this bit and act accordingly. Directives to read multiple words are also provided-see section on special directives.

B. [1257] 2.2.4.6 "ALU Registers Specify Tables" If the Alutab bit is set, the registers in the ALU register file can be used to determine the actual table number used. The table number supplied in the command along with the VLC bit indicates which ALU
Determine if registers are used:

[1258]

[Table 178] For a fixed length code, the correct number of bits are read to decode the vector. If rsize is zero, a NOP command occurs.

In the case of the Huffman code, the generated table number is table [3] set to 1, and the resulting number refers to one of the JPEG tables. B. 2.2.4.7 Special Commands All commands (or operation modes) described so far are considered "simple" commands. For each command received, an appropriate amount of input data (whether serial data or token data) is read and the resulting data is output.
If no errors were detected, exactly one output would occur for each command.

[1260] The invention is characterized in that the special command is such that one or more output words can be generated for one command. To perform this function, the internal state machine of the Huffman Decoder will take control and issue itself as needed until the parser determines that the requested command has been completed.

For all special commands, the first actual command in the sequence to be executed is issued with the Special bit set to one. This means that every sequence must have a unique first order. The advantage of this scheme is that the first actual command in the sequence is available without the lookup operation required based on the command received from the parser.

There are four recognized special directives: TCoefficient JPEG DC JPEG AC Token The first is until the block end symbol is read.
H. 261 and MPEG conversion coefficients are read. If the block is a non-intra block, this command will read the entire block. In this case, First Coef
The fientent bit should be set so that the first coefficient trick is applied. If the block is an intra block, the DC terms should have been read and the First Coefficient bit should be zero.

[1263] H. 261 intra blocks,
The C term is read using a "simple" command to read the FLC 8-bit value. In MPEG, special instructions of JPEG DC described below are used. J
The PEG DC command is (FLC indicated by VLC
Used to read JPEG-style DC terms. First Coeffi
The client bit must be set in the data unit index to reset the counter (counting the number of coefficients). JPEG AC
The command is used to read the rest of the block after the DC term until an EOB is encountered or the 64th coefficient is read.

[1264] The Token command is used to read all tokens. The token word is read until the extension bit is clear. It is a convenient way to handle unrecognized tokens.

1265. 2.2.4.8 “Download Table” In the present invention, the Huffman decoder table is a Downlo
It can be downloaded using the ad bit. The first step is to name the tables to download. This is the Download bit set and F
This is done by issuing a command to read the FLC with the first Coeff bit set. This is NO
Treated as P, so no bits are actually read, but the table number is stored in a register,
Used to identify which tables will be loaded in the next download.

[1266]

[Table 179] As the table above shows, either an AC or a DC table can be loaded, and table [3] can be loaded into the code-pe (in the Huffman decoder itself).
Determine whether it is an r-bit table or a data index table to be loaded.

[1267] Once the table is nominated, the Downl
The required number of FLCs (always 8 bits) with the oad bit set (and First Coeff bit zero)
By issuing a command to read the data, the data is downloaded into that table. This causes the encoded data to be written into the named table. The address counter is maintained, the data is written to the current address, and then the address counter is incremented. The address counter is reset to zero whenever the table is dispatched.

When downloading the data index table, data and addresses are monitored. Note that the address is the Huffman index number, while the data loaded at that address is the symbol that is ultimately decoded. This information is used to automatically load the register holding the Huffman index number for the symbol concerned. Therefore, JPEG
When data having a value corresponding to ZRL is recognized in the AC table, the current address is stored in the register CED as indicated by the table number.
H KEY ZRL INDEX0 or CED H
Written to KEY ZRL INDEX1.

The decoded data is written to the codes-per-bit table one phase after it is decoded, so that data cannot be read from the table during this phase. Thus, a command to read the VLC issued immediately after a table download command will fail. In an actual application (ie, when performing JPEG), there is no reason for such a sequence to occur. However, it is possible to build a simulation test that does this.

[1270] B. 2.2.5 "Huffman State Machine" The Huffman State Machine according to the present invention operates to provide Huffman decoder commands that are created internally in some cases. All commands that can be made by the internal state machine can be provided to the Huffman decoder by the demultiplexer.

The basic structure of the state machine is as follows. When a command is issued to a Huffman decoder, it is stored in a series of auxiliary latches and can be reused later. The commands are further executed by a Huffman decoder and analyzed by a Huffman state machine.
The Huffman Decoder State Machine takes over control of the Huffman Decoder from the Parser State Machine when the command is recognized as being the first in a known command sequence and the SPECIAL bit is set. At this point, there are three sources of commands for the Huffman decoder: 1) Parser state machine: this choice is made at the completion of the special command (eg, when the EOB is decoded) and the next demultiplexer command Is accepted.

[1272] 2) Huffman state machine. The Huffman state machine can have any command.

[1273] 3) By the parser state machine,
Primitive command issued to start the command.

In case (2), the table number can be provided by feedback from the data unit index, which will replace a field in the Huffman state machine ROM.

In case (1), in some cases, the table number is provided by the value obtained from the ALU register file (eg, for AC and DC table numbers and F-numbers). These values are stored in the auxiliary command storage device, and when the command is later reused, the table number is the one stored. Since the counter is normally moving to quote the next block, it will not be recovered from the ALU again.

The decision needs to be made late in the cycle, because the choice of the next command to use depends on the data being decoded. Thus, the general structure is such that all possible commands are prepared in parallel, and multiplexing in the second half of the cycle determines the actual command.

In each case, in addition to determining the command that the Huffman decoder will use during the next cycle, the state machine ROM also passes the current data to the data unit index and then to the ALU. Attention has sometimes been given to determining the directives that will be attached to the current data. In exactly the same way, all three commands are prepared in parallel and a choice is made later in the cycle.

Again, there are three choices for this part of the command, corresponding to the three choices for the next Huffman decoder command as described above.

1) Certain commands appropriate for block end.

2) Huffman State Machine. The Huffman state machine can provide any command for the data unit index.

[1281] 3) A primitive command issued by the parser to start the command.

B. [1282] 2.2.5.1 EOB Comparator The output of the EOB comparator essentially forces a selection of constant commands to be displayed in the data unit index, and the next Huffman command is the next command from the parser. Will let you. The exact function of the comparator is controlled by bits in the Huffman state machine ROM.

[1279] Behind the EOB comparator, AC and D
There are four registers in the C JPEG table that hold the EOB symbol index. In the case of a DC table, there is of course no block end symbol, but there is a zero size symbol, which is created by the DC zero difference. This causes the zero bits of the FLC to be read exactly as in the case of the EOB symbols, so that they are treated exactly the same.

A constant value 1 can be used in addition to the three index values held in the register. This is H.
261 and the index number of the EOB symbol in MPEG.

B.1285. 2.2.5.2 "ZRL comparator" In the present invention, this is a general purpose comparator. It allows you to select either the Huffman State Machine command or the original command to be used by I to D.

There are four values behind the ZRL comparator. Two are in registers and hold the ZRL code index in the AC table. The other two
One value is a constant, one is value zero, and the other is 12 (the index of ESCAPE in MPEG and H.261). Constant zero is FL
Used for C. The constant 12 is used whenever the table number is less than 8 (and VLC).
One of the two registers is determined by the low order bits of the table number and is used when the table number is greater than 7 (and VLC).

A bit in the state machine ROM is provided to enable the comparator, and another bit is provided to invert its operation. T in the command
If the OKEN bit is set, the comparator output is ignored and replaced by the extension bit. This continues until the end of the token.

[1288] B. 2.2.5.3 "Huffman State Machine ROM" The command fields in the Huffman State Machine are as follows: nxtstate [4: 0] The address to use in the next cycle. This address can be modified. state1 Enables modification of the next state address. If zero, the state machine address is not modified; otherwise, the LSB of the address is replaced with the value of one of the following two comparators:

[1289]

[Table 180] Note: In each case, if the next Huffman command is selected as the "Rerun Primitive Command", the state machine will determine that location 0,
Will jump to 1, 2 or 3. eobct [1: 0] This controls the selection of the next Huffman command based on the EOB comparator and the extn bits as follows:

[1290]

[Table 181] zrlct [1: 0] This controls the selection of the next Huffman command based on the ZRL comparator. If the conditions are met, take the state machine command, otherwise rerun the primitive command. In either case, if the eobctl + condition takes a demultiplexer command, this (eobctl +) has priority as follows:

[1291]

[Table 182] smtab [3: 0] In the present invention, if the selected command is a state machine command, this is the table number used by the Huffman decoder. However, lever to fit ZRL comparator, zrltab [3: 0] field is used in preference.

If another table number does not need to be used depending on whether a ZRL match occurs, sm
tab [3: 0] and zrltab [3: 0] will have the same value. However, this is Lsim
Note that may lead to strange simulation problems in. In the case of MPEG, there is no apparent need to load a register indicating the Huffman index number for ZRL (JPEG only configuration). However, they are still selected, and in all cases where the ZRL comparator may be "unknown" (and thus not critical whichever is selected), smtab [3:
0] and zrltab [3: 0] have the same value, the ZRL comparator will be "unknown" and the next state will also be "unknown". zrltab [3: 0] This is the table number that would be used by the Huffman decoder if the selected command was a state machine command. However, if the ZRL comparator matches, the zrltab [3: 0] field will be used in preference.

This is the VLC bit used by the Huffman decoder if the selected command is a state machine command. aluzrl [1: 0] This field controls the selection of commands sent to the ALU. It may be a command from the parser state machine (stored at the start of the command sequence) or a command from the state machine:

[1294]

[Table 183] aleob This wire controls the modification of commands sent to the ALU based on the EOB comparator. This simply forces the ALU output mode to zinput. This is an optional choice; any output mode remote from none is acceptable. This sends the block end command word to the token formatting section, where it controls the proper formatting of the data token:

[1295]

[Table 184] The remaining fields are ALU command fields. These are properly documented in the ALU description.

[1296] B. 2.2.5.4 "Modification of Huffman State Machine" In one aspect of the state machine, the data unit index portion is an escape coded Tcoef
It is necessary to "know" when the RUN part of the client is sent to the data unit index part. While this can be achieved using the appropriate bits in the control ROM,
To avoid ROM changes, another approach has been used. In this regard, the address entering the ROM is monitored and an address value 5 is detected. This is RUN
It is the proper place to be named in the ROM that processes the field. Of course, it would be obvious if one wanted to program the ROM to use another selected address value. In addition, the above approach using the bits of the control ROM could have been utilized.

[1297] B. 2.2.6 "Schematic Guided Tour" In the present invention, the Huffman decoder is called hd, and hd actually contains the data unit index portion (this is required due to the limitations of edited code generation). Thus, hd contains the following main blocks:

[1298]

[Table 185] The following description of the Huffman module is provided by a general description of the various subsystem areas shown in the detailed parts of the drawings, which will be readily apparent to those skilled in the art.

[1299] B. 2.2.6.1 "Description of" hd "" The logic for controlling the two-wire interface includes three ports: data input, data output, and command, which are typically controlled by a two-wire interface. In addition to it,
There are two "valid" lines from the input shifter: a token valid indicating that the token is displayed in data [7: 0] and a serial valid indicating that the data is displayed serially. is there.

The most important signal generated is the enable going to the latch. Most important is e1, which is an enable for the ph1 latch. Many of the ph0 latches are not enabled, but two enables are provided for them, e0 associated with serial data and e0t associated with token data.

In the present invention, the done signal (done, n)
otdone and don of their ph0 variants
e0 and notdone0) indicate when the primitive Huffman command is completed. If a Huffman state machine command is executed, the done will be recognized upon completion of each primitive command, including all state machine commands. The signal notnew prevents acceptance of new commands from the parser state machine until all Huffman state machine commands have been completed.

With respect to controlling the information received from the data unit index, control logic for the size field is sent back to the Huffman decoder during JPEG coefficient decoding. This actually happens in two ways. If the size is exactly 1, this is the dedicated signal not
Returned to fbone0. Otherwise, it is returned from the output of the data unit index. (O
out data [3: 0] and signal fbvalid1 indicate that this occurs. A signal muxsize is generated to control the multiplexing of the feedback data into the command register (sheet 10). In addition, there is feedback with exactly 64 coefficients decoded. Since EOB is not coded in this case in JPEG, a signal forceob is created. By analogy, as mentioned above, with the signal for the feedback size, there are actually two ways this can be implemented. Normal feedback is provided (jpe
geob), as data is fed back, only latch i-971 is loaded and not cleared until a new parser state machine command is accepted. The signal forceob is not actually produced until the Huffman code is decoded. in this way,
Fixed length codes (ie, size bits) are not affected, but the next Huffman coded information is replaced by the forced block end. Size is 1 and j
If pegob0 is used, i-1255 and i-1256 delay the signal until the correct time because only one bit is read. It should be noted that since the only symbols with zero size are EOB and ZRL, it is not possible for zero size to occur in this situation.

[1303] The decoding is tcoeff tab0
(Huffman decoding using the Tcoeff table), mba tab0 (Huffman decoding using the MBA table), and fairly random decoding of commands to make nop (no operation). There are several reasons for generating a nop. Zero-length fixed length code is one of them,
The forceeob signal is one of them (because no data should be read from the input shifter even if the output is made to signal an EOB), and finally a table download nomination is the third reason.

Notfrczero (created by zero size FLC, NOP) ensures that when the NOP command is used, the result is zero. Furthermore,
Invert indicates when the serial bits should be inverted before Huffman decoding (see section B.2.2.1.1). ring indicates when the transform coefficient ring is to be applied (see section B.2.2.1.2).

[1305] Decoding is further performed by codes-per
Achieved with respect to the address of the bit ROM. These are built from a small data path ROM. The signal is duplicated (eg, csha and csla). The address may be a bit counter (bit [3: 0]) or a microprocessor interface address (key addr) according to the UPI access to the selected block.
[3: 0]).

[1306] The additional decoding relates to UPI reading of registers such as those holding Huffman index values for JPEG tables (EOB, ZRL, etc.). Also included are these registers and co
This is a tri-state driver control for reading UPI of des-per-bit RAM.

[1307] Arithmetic data path decoding is also provided for certain significant bit numbers. first bit
Is used in conjunction with Tcoeff's first coefficient trick, and bit five relates to applying the ring into the Tcoeff table. Note the use of forceob to simulate the behavior of the EOB comparator to match the decoded index value.

With respect to the extn bits, if a token is read from the input shifter, the associated extn bits are read with it. Otherwise, the last value of extn is saved. This allows the microcode program to test the extn bits any time after the token has been read.

When zerodat is asserted, the upper four bits of the Huffman output data are forced to be zero. Since they only have valid values when decoding fixed length codes, they are zeroed when decoding VLC, tokens, or when the NOP command is implemented for any reason.

[1310] In addition, the circuit detects when each command is completed and issues a done signal. Essentially, there are two groups of reasons for being done: normal and exceptional. These are each processed by one of the two three-way multiplexers.

[1311] The lower multiplexer (i-1275) handles the usual reasons. In the case of FLC, the signal ndnflc
Is used. This is the output of the comparator that compares the bit counter with the table number. For VLC, the signal ndnvlc is used. This is the output from the arithmetic data path and directly reflects Equation 9. NO
In the case of a P command or token, only one cycle is needed, so the system is unconditionally done.

In the present invention, the upper multiplexer (i-1)
274) handles exceptional cases. In JPEG decoding, when the decoder expects size feedback (fexpctd0), the decoder is done because only one bit is needed. If the decoder is processing the first bit of the first coefficient using the Tcoeff table, it is done if bit zero of the current index is zero (see section B.2.2.1.2). . If neither of these conditions is met, there is no exceptional reason for being a done.

The NOR gate (i-1293) finally changes the done state. The condition caused by i-570 (i.e., the data is not valid) forces done. This may seem a bit strange. It basically prepares for the first command (done resets all counters, registers, etc.)
Used after reset to bring the machine to the done state.

The signal notdonex is necessary for detecting an error. If an error is detected, the done is forced anyway, so that a normal done signal cannot be used.
The use of done would provide a combined feedback loop.

The error detection and processing is performed by a circuit that detects all possible error conditions. These are i-
In 1190, both are 0Red. In this case, i-
1193, i-585 and i-584 form a 3-bit Huffman error register. Note i-1253 and i-1254 which disable the error when there is no "real" error (see section B.2.2.3).

[1313] In addition, i-580 and i-579
Provides, with associated circuitry, a simple state machine that controls the acceptance of the first command after error detection.

As described above, the control signal is delayed in the data unit index portion and the ALU to match the pipeline delay.

[1313] Itdbypass is the actual bypass signal sent to the data unit index.
It is modified whenever the Huffman state machine is controlled to have to bypass whenever the fixed length code is decoded.

[1319] Aluinstr [32] is a bit that causes the ALU to feed back (condition code) to the parser state machine. Further, when the Huffman state machine is being controlled, it is important that the signal be acknowledged only once (rather than each time one of the primitive commands is completed).

[1320] Aluinstr [36] is (other ALU
A bit that causes the ALU to step through the block counter (if the command bit specifies an increment). This also has to be certified only once.

In addition, these bits must be recognized only for ALU commands that output data for token conversion. Otherwise, the counter is incremented before the first output to token conversion, which may result in an incorrect value of cc in the data token.

In the illustrated embodiment of the present invention, if the ALU is output to the token formatting unit,
Either mode [1] or alunode [0] will be low.

FIG. 127 shows a Huffman state machine data path called hdstdp. There is also a UPI decode for reading the output of the Huffman state machine ROM.

[1324] Multiplexing is provided for processing in case of location (Section B2.2.4.
6).

[1325] The modification of aluinstr [3: 2] is AL
Processing to force the Uoutsrc command field to non-none (Section B.2.2.5.3, al
ueob).

With respect to the command register for the Huffman decoder block (x), each bit of the command has an associated multiplexer that selects between the possible sources of the command. Four control signals control this selection: Selhold causes registers to hold the current state.

[1327] Selnew causes a new command to be loaded from the parser state machine. This also allows for loading of registers holding the original parser state machine commands for later use.

The [1328] Selold causes the command to be loaded from the register holding the command of the original parser state machine.

[1327] / selsm causes the loading of commands from the Huffman state machine ROM.

In the case of the table number, the situation is a little more complicated because the table number is also loaded from the output data of the data unit index part (s
elholdt and muxsize).

[1331] Latch is Huffman state machine ROM
Holds the current address in Logic is possible 4
Detect which command is being executed. These signals are combined to form the lower two bits of the start address in the case of a new command.

The logic also detects when the output of the state machine ROM is meaningless (usually because the command is a "simple" command). Signal notignor
Erom effectively disables operation of the state machine, and in particular, disables modification of commands sent to the ALU.

The circuit that generates fixstate0 controls the limited jumping capability of this state machine.

[1334] Decoding is also provided to drive the signal to the Huffman state machine ROM. This is a data path style combined ROM.

The occurrence of escape run is described in section B 2.2.5.4.

In addition, decoding prepares a register holding a Huffman index number for symbols such as ZRL and EOB. These registers can be loaded from the UPI or datapath. cent
Decoding in er (es [4: 0] and zs [3: 0] generates a select signal for a multiplexer that selects which register or constant value to compare with the decode Huffman index.

Relating to the control logic for the Huffman state machine. Here, Huffman State Machine RO
The "command" bit from M tells what to do next,
Various conditions are combined to determine how to modify the command word for the LU.

In the present invention, the signals notnew and nott are used.
old is used on sheet 10 to control the operation of the Huffman Decoder command register. They are referred to here as Huffman index comparators (n
state machine ROM (section B.2.2.5.) along with eobmatch and nzrlmatch).
3 (described in 3).

Further, selection of a source for a command sent to the ALU is performed. The actual multiplexing is performed in the Huffman state machine data path hfstdp. Four control signals are generated.

[1340] If no block end is encountered,
Either one of aluseldmx (select parser state machine command) or aluselmsm (select Huffman state machine command) will be created. In addition, the outsrc field of the ALU command is modified to push it to zinput.

[1341] The register holds the table number designated during table download. Decoding is provided for code-per-bit RAM. Additional decoding recognizes when symbols such as EOM and ZRL are downloaded so that the Huffman index number register is automatically loaded.

With regard to the bit counter, when reading the FLC, the comparator detects when the correct number of bits are being read. B. 2.2.6.2 "Description of" hddp "" The comparator detects a special value of the Huffman index. The register holds the value for the downloadable table. Multiplexer (meob
[7: 0] and mzr [7: 0]) select the value to be used, and the exclusive-or gate and gating constitute the comparator.

The adders and registers are described in section
Evaluate directly the equation described in 2.2.1. No further explanation is deemed necessary here. Exclusive OR is described in Section B.3. Used to invert the data (i-807) described in 2.2.1.1.

The code register is 12 bits wide.
The multiplexing arrangement is described in section B.
Implement the ring permutation described in 2.2.1.2.

For pipeline lag for data and multiplexing between decoded serial data (index [7: 0]) and token data (ntoken0 [7: 0]), the Huffman index value is ZR
Determined within the L and EOB symbols.

The Codes-per-bit ROMs and their multiplexing are used to determine which table to use. This arrangement is used because the table select information arrives late. Thereafter, all tables are accessed and the correct table is selected.

For Codes-per-bit RAM, final multiplexing of codees-per-bit ROM and code-per-bit RAM
Occurs inside the block hdcpbram.

[1348] 2.2.6.3 "" hdstdp "
Description In the present invention, Hdstdp is composed of two modules. hdstdel is concerned with delaying the parser state machine control bits until the appropriate pipeline stage, for example, when they are provided for ALU and token conversion. It processes only about half of the command words sent to the ALU, and the rest
Processed by dstmod.

Hdstmod includes a Huffman state machine ROM. Several bits of this command are used by the Huffman state machine control logic. The remaining bits are used to replace unprocessed parts in hdstdel of the ALU command word (from the parser state machine).

The Hdstmod is self-explanatory and requires no explanation. There is only a pipeline delay register.

[1351] Hdstdel is also very simple,
Processed by a multiplexer that modifies the M and ALU commands. The rest of the circuit is a Huffman state machine ROM
Relates to UPI read access to half of the output. Buffers are also used for control signals.

[1352] B. 2.3 "Token Formatting" Huffman decoder token formatting according to the present invention is at the end of the Huffman block. Its function is
As the name implies, formatting the data from the Huffman decoder into an appropriate token structure. The input data is multiplexed with the data in the microinstruction word under the control of the microinstruction word command field. Block has two modes of operation; data word and data token. 2.3.1 "Micro instruction word"

[1353]

[Table 186] B. 2.3.2 “Operation mode”

[1354]

[Table 187] B. 2.3.2.1 Data Word In this mode, the eight most significant bits of the input are sent to the output. The bottom 8 bits are either the bottom 8 bits of the input, the token field of the microinstruction word, or a mixture of both, depending on the mask field. The mask is: out data [16: 8] = in data [1
6: 8] out data @ 7: 0] = (Token [7: 0]
& (Ff << mask) in data [7: 0] represents the number of input bits in the mix.

When the mask is set to 0x8 or more, the output data is equal to the input data. This mode is used for output words in non-data tokens. If the mask is set to 0, out data [7: 0] will be the microinstruction word token field. This mode is used to output a token header that does not contain any data. If the token header contains data, the number of data bits is given by the mask field.

When external Extn (Ee) is set, o
out extn = in extn, otherwise out extn = De. Bt and Eb is do
n't care. B. 2.3.2.2 "Data Token" This mode is used for formatting with data tokens, signals, first coefficie.
There are two functions depending on nt. On reset, f
The first coefficient is set. When the first data coefficient arrives with the microinstruction word with cmd set to 1, out data
[16: 2] is set to 0x1, and out data
[1: 0] is Bt of the microinstruction word
Take the value of the field. This is the header of the data token. When this word is accepted, the coefficient with the command is loaded into register RL and first c
"officient" takes the value of Eb. When the next coefficient arrives, out data [16: 0] takes the previous coefficient stored in RL. This means that when the end of the block is encountered, Eb is set and the first
event is set, and the next data token, that is, If (first coefficient) ｅｎｔ out data [16: 2] = 0x1 out data [1: 0] = Bt [1: 0] RL [16: 0] = in data [ 16: 0]｝ else ｛out data [16: 0] = RL [16: 0] RL [16: 0] = in data [16: 0]｝ out extn = -Eb to ensure that it is ready .

[1357] B. 2.3.3 Notes According to the invention, most of the command bits are supplied by the parser state machine in the usual way. However, in practice the two fields are provided by other circuits. The Bt field described above is connected directly to the output of the ALU block. These two bit fields are c
Gives the current value of c or color component. Thus, when the data token header is constructed, the two lowest order bits take the color component directly from the ALU counter. Second, whenever the block end symbol id is decoded (or in the case of JPEG, where 1 is assumed since the last coefficient in the block is coded), the Eb bit is identified in the Huffman decoder. .

[1358] In the Huffman decoder, in extn
A signal is derived. It only makes sense for tokens when the extension bits are supplied with the token word in the usual way.

[1359] B. 2.4 "Parser State Machine" The parser state machine of the present invention is actually a very simple piece of circuitry. Complicated is the programming of microcode ROM, which is described in Section B.1. Discussed in 2.5.

The machine consists essentially of a register that holds the current address. This address is looked up in a microcode ROM to create a microcode word. Further, the address is incremented in a simple incrementer, this incremented address being one of two possible addresses used for the next state. The other address is microcode ROM
A field within itself. Thus, each command is a potential jump command and can jump to a location specified in the program. If no jump is made, control proceeds to the next location in the ROM.

A series of 16 condition code bits are provided. One of these conditions may be selected (by a field in the microcode ROM) and additionally inverted (also by a bit in the microcode ROM). The resulting signal selects either the incremented address or the jump address in the microcode ROM. One of the conditions is wired to evaluate as False. When this condition is selected, no jump occurs. Alternatively, this condition is selected and inverted so that a jump, an unconditional jump, always occurs.

[1362]

[Table 188] B. 2.4.1 Two-Wire Interface Control Two-wire interface control according to the present invention is somewhat unusual in this block. There is a two-wire interface between the parser state machine and the Huffman decoder. This is used to control the progress of the command. The parser state machine will wait until a given command is accepted before proceeding to read the next command from ROM. In addition, the condition code is sent back over the wire from the ALU.

Each command has a bit in the microcode ROM, which allows to specify that feedback should be waited for. If this occurs, no new commands will be displayed after the command has been accepted by the Huffman decoder until the feedback wire from the ALU is certified. This wire, fb_valid, indicates that the condition codes currently supplied by the ALU are valid in the sense that they reflect the data associated with the command asking it to wait for feedback.

According to the present invention, its features are utilized in constructing a conditional jump command that determines the next state to jump to a special piece of data as a result of decoding (or processing). . In two-wire control, it is uncertain when a command will reach a given processing block (ie, in this case, the ALU), so without this convenience testing conditions that depend on data in the pipeline would be necessary. Would not be able to.

[1365] Not all commands are sent to the Huffman decoder. Certain directives can be executed without the need for a data pipeline. These tend to be jump commands. A bit in the microcode ROM selects whether the command is displayed at the Huffman decoder. Otherwise, the Huffman Decoder does not need to accept the command, and thus can continue execution in these situations even if the pipeline is stalled.

[1366] B.I. 2.4.2 Event Processing Two event bits are placed in the parser state machine. One is called a Huffman event and the other one is
One is called a parser event.

The parser event is the simplest. The "condition" monitored by this event is only a bit in the microcode ROM. Thus, a command can cause a parser event by setting this bit. Typically, a command to do this writes an appropriate constant to the rom control register so that the interrupt service routine can determine the cause of the interrupt.

After servicing the parser event (or immediately if the event is masked out), control recovers at the point where it stopped. If the command that caused the event has a jump command (evaluates the state to be real), the jump is performed in the usual manner. Therefore, by coding the jump
Ri, after the service, it is possible to jump to the error handler.

[1369] The Huffman event is different. The condition monitored is the OR of the three Huffman error bits.
In reality, this state is handled for parser events in a very simple way. However, an additional wire from the Huffman decoder, huffintrpt, is qualified whenever an error occurs. This causes control to jump to the error handler in the microcode program.

Therefore, when a Huffman error occurs, the sequence includes interrupt generation and block stop. After servicing, control is transferred to the error handler. ca
There is no 11 mechanism and, unlike a normal interrupt, it is not possible to return to a point in the microcode before an error that occurs following error handling.

[1371] Huf error does not occur and hufman
fintrpt can be certified. This is described in section B. As discussed in 2.2.3, no-e
Occurs in special cases of error. In this case, no interrupt is generated (at the microprocessor interface) and control is passed to the error handler in microcode (the Huffman error register is now apparent, so the microcode error handler can Oh to determine that, to respond in accordance with the Re this
Can be.

[1372] B. 2.4.3 Special locations The microcode ROM has several special locations. The first four locations in ROM are the entry points to the main program. Control proceeds to one of these four locations on reset. The location to jump to is the ALU register, codings
td. Is determined by the coding standard selected in Control proceeds to location zero because this location is itself reset to zero by a true reset. However, CED H TRAC
The UPI register bit CED H TRACE in E
Only the parser state machine can be reset using RST. In this case, coding std
The registers are not reset and control proceeds to the appropriate one of the first four locations.

[1373] The second four locations (0x004 to
0x007) is used when a Huffman interrupt occurs. Typically, an actual error handler is located at each of these locations. Again, the choice of location is made as a result of coding standards.

[1374] B. 2.4.4 "Tracing" As a diagnostic aid, a tracing mechanism is implemented. This causes the microcode to be single-stepped. Bits in register CED H TRACE CED H TRACE EVENT and CED H
TRACE MASK controls this. As the name implies, they operate on normal event bits in a very similar way. However, due to some differences (especially the absence of UPI interrupts), they are not grouped with other event bits.

The tracing mechanism is turned on when CED H TRACE MASK is set to 1. A trace event occurs after each microcode command is read from ROM, but before it is displayed at the Huffman decoder. In this case, CED H TRA
CE EVENT becomes 1. Since no interrupt occurs, it must be registered. All microcode words are in registers CED H KEY DMX
WORD 0-CED H KEY DMXWORD
Available at 9. The directive can be modified at this point if necessary. CED H TRACE EVE
When 1 is written to NT, the command is executed and CED
Clear H TRACE EVENT. Shortly thereafter, the next microcode word to be implemented is read from the ROM and a new trace event occurs.

1376. 2.5 "Microcode" Microcode is programmed using the assembler hpp, which is a very simple tool and most of the sampling is done using a macro preprocessor. A standard C preprocessor cpp is used for this purpose.

[1377] The code is indicated as follows.

[1378] Ucode. u is the main file. First, this is tokens. h. Next, regfile. h is the ALU register map
Is defined. fields. u defines the various fields in the microcodeword and provides a list of symbols defined for each possible bit pattern in the field. Next, the labels used in the code are defined. After this step, inst to define a number of cpmpros that clarify the basic directives,
r. u. Next, errors. h defines the number that defines the parser event. Next, unw
ord. u defines the order in which fields are placed to build a microcodeword.

[1379] The remaining ucode. u is the microcode program itself.

1380. 2.5.1 "Directive" In this section, ucode. The various commands defined in u are described. In many cases, there are few variations on one theme (especially ALU directives), so not all directives will be described here.

[1381] B. 2.5.1.1 "Huffman and Data Index Command" In the present invention, the Huffman decoder uses the H NOP command. It is a no-operation command. Huffman does nothing in the sense that no data is decoded. The data produced by this command is always zero. Therefore, the related command is sent to the ALU.

[1382] The next command is a token group; H TOK
SRCH, H TOKSKIP PAD, H TOKS
KIP JPAD, H TOKPASS and H TOK
READ. They all read tokens from the input shifter and send them to the rest of the machine. H T
OKREAD reads one token word. H TO
KPASS can be used to read all tokens up to zero extn bits. The associated command is repeated for each word of the token. H TOKSRCH discards all serial data before the token and reads one token word. H TOKSKIP PAD skips padding bits (H.261 and MPEG) and reads one token word. H TOKSKIP JPAD
Does the same for JPEG padding.

[1383] The H FLC (NB) reads a fixed length code of NB bits.

[1384] H VLC (TBL) is (Mnemoni
c, read vic using indicated table (e.g., sent as HVLC (tcoeff)).

The H FLC IE (NB) is the same as the H FLC, but with the errorerrors bit set.

[1386] H TEST VLC (TBL) is HF
Similar to LC, but with the bypass bit set so that the Huffman index is sent through the unmodified data unit index.

[1387] H FWD R and H BWD R are AL
U registers r fwd r size and r bwd r
Read the FLC of the size indicated by each size.

HDDCJ reads the JPEG style DC coefficient and the table number from the ALU.

[1389] H TC / OE / FF and H DCTC /
The OE / FF reads the transform coefficients. HDCTC / OE / FF
, The first coeff bit is set and non
H T while for the intra block
C / OE / FF is intra after DC term is read
For the block.

HNOMINATE (TBL) names a table for the next download.

[1390] H DNL (NB) reads the NB bit,
Download them to the named table.

1392. 2.5.1.2 "ALU directives" In practice, there are too many ALU directives to elaborate. The basic method by which Mnemonics is constructed should be discussed so that the instructions can be read. Furthermore, they must be easily understood by one of ordinary skill in the art.

Many ALU commands involve moving data from place to place, so a general "load" command is used. In Mnemonic, A
LDxy knows that the contents of y are loaded into x, that is, the destination is recorded first and the source comes next.

[1394]

[Table 189] Table B. 2.10 As an example of characters to indicate possible sources and destinations of data, LDAI loads the A register with data from the data input port of the ALU. If the ALU register file is specified, Mnemonic will send the LDAF (R
A) will take the address to load A with the contents of location RA in the register file.

The ALU has the ability to modify data as it is moved from source to destination.
In this case, the arithmetic is indicated as part of the source data. Therefore, Mnemonic LDA AADDF
(RA) loads A with the current contents of the A register plus the contents of the indicated location in the register file. Another example is LDA ISGXR, which takes input data, the sign extends from the bit indicated in the RUN register, and stores the result in the A register.

[1396] In many cases, one or more destinations are specified for the same result. Again, by way of example, LDF LDA ASUBC (RA) loads the result of A minus a constant into both the A register and the register file.

[1310] Other Mnemonics exist for special operations. For example, CLRA is used to clear the A register and RMBC is used to reset the macroblock counter. These are fairly self-explanatory, instr. This is explained in the comments in u.

One exception is the use of the suffix O to indicate that the result of the operation is output to token formatting in addition to normal operation. Thus, the LDFIO (RA) stores the input data and sends it to token formatting.
Alternatively, if desired, this can be an LDF
It could be LDO I (RA). B. 2.5.1.3 "Token Formatting Command" This is a T NOP "No Operation" command.
This is a misnomer because it is not possible to construct a no-operation command in practice. However, this is used when the command is not important because the ALU is not output on token formatting.

[1398] T TOK outputs a token word.

[1400] T DAT outputs a data token word (used only with Huffman state machine commands).

T GENT8 generates a token word based on the 8 bits of a constant field.

[1402] T GENT8E is the same as T GENT8, but the extension bit is one. T OPD (NB) is the NB of the data from the bottom NB bits of the output, with the rest of the bits coming from the constant field.
bit.

[1400] TOPDE (NB) is the same as TOPD, but the extension bit is high.

[1404] T OPD8 is a short hand for T OPD (8).

[1404] T OPD8E is a short hand for TOPDE (8).

[1406] B. 2.5.1.4 “Parser State Machine Command” This command, D NOP, is a no operation,
Addresses increase normally, and the parser state machine does nothing special. The remainder of the command is sent to the data pipeline. No waiting occurs.

D WAIT is similar to D NOP, but waits for feedback to occur.

[1408] Simple jump group. D JMP (A
Mnem like DDR) and DJNX (ADDR)
onics jumps if the condition is met. The command is not output to the Huffman decoder.

[1409] External jump group. D XJMP (A
Mne like DDR) and D XJNX (ADDR)
monics . These are similar to the simple counterparts described above, but their commands are output to a Huffman decoder.

[1410] Jump and Wait Groups. D WJNZ
Mnemonics such as (ADDR). These commands are output to the Huffman decoder, and the parser waits for feedback from the ALU before evaluating the state.

The following Mnemonics are used for the state itself.

[1412]

[Table 190] EVENT causes an event to occur.

[1413] D DELETE is for construction of a default command. This triggers the event and the label df
Jump to location with lt. This command is R
It is used to fill the OM and must not be performed because unused locations are trapped.

[1414] D ERROR causes an event,
Label src assumed to attempt recovery from error
Jump to h dispatch. Section B.
3 "Huffman Decoder ALU" 3.1 Introduction According to the present invention, the Huffman Decoder ALU sub-block provides general arithmetic and logical functionality for the Huffman Decoder block. It includes addition and subtraction operations, various types of sine expansion operations, and run-
It has the ability to format into sign-level triples. In addition, it has a flexible structure whose exact operation and configuration is specified by microinstruction words arriving at the ALU synchronously with the input data, ie under the control of a two-wire interface.

In addition to the 36-bit command and 12-bit data input ports, the ALU has a 6-bit run port and an 8-bit constant port (actually on the token bus). All of these, except the microinstruction word, drive buses of each width through the ALU data path. Represents the extension bit, 17 bit run
Output with sign level (out data)
There is one bit in the microinstruction word. At each end of the ALU data path is a two-wire interface and a series of condition codes that are output with their own valid signal, cc valid. ALU
There is a register file accessible to other Huffman decoder sub-blocks and the microprocessor interface via.

B. [1416] 3.2.2 “Basic Structure” The basic structure of the Huffman ALU is as shown in FIG. It includes the following components: Input block Output block Condition code block A register with source multiplexing Run register with source multiplexing (6
Bit) adder / subtractor with source multiplexing sign extension logic register file with source multiplexing (except for output blocks) each of these blocks pushes its output onto a bus running through the data path, These buses are then used as inputs to multiplexing for block sources. For example, an adder is one of the possible inputs to the A register, its own data
Having a pass bus . Similarly, the A register has its own bus which forms one of the possible inputs to the adder. In this regard, there is only a subset of all possibilities, as specified in section 7 on microinstruction words.

In a single cycle, it is possible to execute either an add-based command or a sign extension-based command. Further, both of them may be performed in a single cycle only if their operations are exactly parallel. In other words, a sequence of addition and sign extension or sign extension and addition is not allowed. The register file is read or written in a single cycle, but not both.

The output data has three fields:-run-6 bits-sign (sign) -1 bit-level-10 bits-if data is sent straight through the ALU, the least significant of the input data registers 11 bits are signed
Field and level fields are latched.

[1400] Limited ALU multi-cycle operation can be programmed. At this point, the number of cycles required is determined by the contents of the register file location, the address of which is specified in the microinstruction, and the same operation is performed repeatedly while the iteration counter decreases to one.
This facility is typically used to perform a left shift, adding an A-register to itself using an adder and storing the result back in the A-register.

B. [1420] 3.3 “Adder / Subtractor Subblock” This is a 12-bit wide adder, and its input2
, And an arbitrary setting of carry-in bit. The output is a 12-bit sum, car
ry-out is not used. There are seven modes of operation: ADD: add the carry of the set to zero: input1 + input2 ADC: add the carry of the set to 1: input1 + input2 + 1 SBC: invert the input2 and carry the set To zero: input1-input2-1-SUB: Invert input2 and set carry to 1: input1-input2-TCI: If input2 <0, use SUB; otherwise use ADD . This is used with input1 set to zero to get the magnitude value from the two's complement value.

DCD (DC difference): If input2 <0, perform ADC; otherwise, perform ADD.

VRA (vector residual add): input
If t1 <0, perform ADC; otherwise, perform SB.
Perform C.

[1423] 3.4 "Signature Extension Subblock" This is a 12-bit unit where the sign extends the input data from the size input in various modes. Size is 0
4-bit values from 0 to 11 (0 for least significant bit, 11 for most significant bit). The output is the 12-bit modified data value,
The "sign" bit.

In SGXMODE = NORMAL, si
All bits greater than or equal to size-th bits are size-t
Take the value of h bits. All of the following remain unchanged. The sign takes a value of size-th bits.
For example: data = 1010 1010 1010 size = 2 output = 0000 0000 0010, sign = 0 In SGXMOD = INVERSE, all bits greater than or equal to size-th bits take the reciprocal of size-th bits, while all of the following It remains unchanged. The sign takes the reciprocal of size-th bits. For example: data = 1010 1010 1010 size = 0 output = 1111 1111 1111, sign = 1 In SGXMODE = DIFMAG, if the size-th bit is zero, all bits below the size-th bit are inverted, while All things remain unchanged. If the size-th bit is 1, all bits remain unchanged. In both cases, the sign takes the reciprocal of size-th bits. This is AC
Used to get the magnitude of the difference value.
For example: data = 0000 1010 1010 size = 2 output = 0000 1010 1101, sign = 1 data = 0000 1010 1010 size = 1 output = 0000 1010 1101;
All bits greater than (but not including, size-th bits) take the reciprocal of size-th bits, while all bits less than that remain unchanged. The sign takes the reciprocal of size-th bits. This is DC
Used to take two's complement values for the difference value. For example: data = 1010 1010 1010 size = 0 output = 1111 1111 1110, sign = 1 B. 3.5 “Condition code” 2 of the condition code used by Huffman block
There are three bytes (16 bits), of which certain bits are created by the ALU / register file. These are a sign condition code, a zero condition code, an extended condition code, and a change detection bit. The last two of these codes are not really condition codes because they are not used by parsers as others.

The sign, zero, and extended condition codes are updated when the parser issues a command to update, and for each of these commands, the condition code valid signal is sent only once with a high pulse.

The sign condition code is simply the sign extended sign output latched, while the zero condition code is set to one if the input to the A register is zero. Extended condition code is OU
Input extension bit latched independently of TSRC.

The condition code can be used to evaluate a particular condition type: the result is equal to a constant-using a subtract, zero condition the result is equal to the register value-using a subtract, zero condition register Is equal to a constant-using subtraction, zero condition-register bit set-using sign extension, sign condition-result bit set-using sign extension, sign condition using a combination of sign extension and sign condition code Note that it is only possible to evaluate one particular bit, rather than to evaluate multiple bits as in a conventional logical AND.

In the present invention, the change detection bits are created using the same logic as the zero condition code, but do not have an associated valid signal. The bits in the microinstruction are different from those in which the value recently written to the register file already exists (requires two clock cycles, first R
Set EG-MODE to READ, then REGMOD
E to WRITE) indicates that the change detection bit should be updated. Next, when the changed value is detected, an interrupt of the microprocessor is started. The change detection bit is reset by activating Change Detect in the normal manner, but REGMODE is READ
Is set to

(Forming part of the register file, see below) The hardwired macroblock counter structure also produces the following condition code: Mb
Start, Pattern Code, Resta
rt and Pic Start.

[1430] B. 3.6 “Register File” The address map for the register file is shown below. It is common to both ALU datapath and UPI7
Use bit address space. Many locations are not accessible by the ALU, these are typically counters in the hardwired macroblock structure and registers in the ALU itself. The latter register has dedicated access, but the UPI
Form part of the address map for (0 in the table
A multi-byte location is indicated by one ALU address and multiple U
Has a PI address. Similarly, a register group indexed by the component count, CC (indicated by I in the table), is treated as one location by the ALU. This facilitates microprogramming for initialization and resetting, and for block-level operation.

Except for the dedicated ALU register (UPI read only), all locations are read / write and all counters are reset to zero by bits in the command word. The pattern code register has the ability to shift right, with the least significant bit being Pa
Form a tern Code condition bit. All registers in the hardwired macroblock structure are denoted by M in the table, and a counter (n-bit)
Are annotated as Cn.

In the present invention, the specific location is the other part of the Huffman subsystem coding standard,
Two r-size locations and an ac huff table and dc huff for the Huffman decoder
It has content hardwired into one location (one bit word) for each of the tables.

The addresses in bold indicate that the locations are accessible in both ALU and UPI, otherwise they have only UPI access. AL
Register groups not indicated by the U through the CC can have one ALU address specified in the command word, and the CC will be a data token that selects a physical location within the group to access.
Conventionally, the ALU address should use the first address, but may be from any register in the group. This is true in the case of multi-byte locations to be accessed using the lower address of the pair, although either address is actually sufficient. Locations 2E and 2
F is the top level address map (indicated by T)
Note that it is accessible, not just through the keyhole register. These two locations are also reset to zero.

The register file is physically partitioned into four "banks" to improve access speed, but this does not affect addressing in any way. The main table shows the allocation for MPEG and two repeated sections are JPEG and H.264. 2
61 variations are provided.

[1435]

[Table 191]

[1436]

[Table 192]

[1437]

[Table 193]

[1438]

[Table 194]

[1439]

[Table 195]

[1440]

[Table 196]

[1441]

[Table 197]

[1442]

[Table 198]

[1443]

[Table 199]

[1444]

[Table 200] B. 3.7 "Microinstruction Word" According to the present invention, the ALU microinstruction word is divided into a number of fields, each of which controls a different aspect of the above structure. The total number of bits used in the command word is 36, a minimum encoding (plus one for extended bit input) and across the field is employed, maintaining maximum flexibility in hardware configuration Is done. The command word is partitioned as described in detail below. Default field values, ie, those that do not change the state of the ALU or register file, are shown in italics.

[1445]

[Table 201]

[1446]

[Table 202]

[1449]

[Table 203]

[1448]

[Table 204]

[1449]

[Table 205] Section B. 4 "Buffer manager" 4.1 Introduction This document describes the purpose, operation and implementation of a buffer manager according to the present invention (bman).

[1450] B. 4.2 “Prospects” The buffer manager uses 4
Provide two addresses. These addresses are
Is the page address within. The DRAM interface maintains two FIFOs in the DRAM, a coded data buffer and a token data buffer. Thus, for four addresses, there is a read address and a write address for each buffer.

[1451] B. 4.3 "Interface" The buffer manager is only connected to the DRAM interface and the microprocessor. The microprocessor is B.I. It only needs to be used to set the "initialization register" shown in 4.4. DRA
The interface with the M interface has a Request / ACKnowledg for each address.
Four 18-bit addresses controlled by the e-protocol. (Because the buffer manager is not in the data path, the buffer manager lacks a two-wire interface.) In addition, the buffer manager turns off the DRAM interface clock generator and turns on the DRAM interface scan chain.

B. [1452] 4.4 “Address Calculation” The read address and write address for each buffer are 9
Created from 18 18-bit registers:-Initialization register (RW from microprocessor)-BASECB-Base address of coded data buffer-LENGTHCB-Maximum size (in page of coded data buffer)-BASETB-Token data buffer Base address of LENGTHTB-Maximum size of token data buffer (in page) LIMIT-Size of DRAM (in page) Dynamic register (R from microprocessor)
O)-READCB-coded data buffer read pointer for BASECB-NUMBERCB-coded data buffer write pointer for READCB-READTB-token data buffer read pointer for BASETB-NUMBERTB-token data buffer write pointer for READTB To calculate the address :-Readaddr = (BASE + READ) mod L
IMIT writeaddr = (((READ + NUMBER)
mod LENGTH) + BASE) mod LIM
Since the IT buffer may wrap around the DRAM, m
The term od LIMIT is used.

[1453] B. 4.5 "Description of Block" In the present invention, the buffer manager
It consists of three top-level modules connected in a ring that monitors the interface junction. Modules are bmprize (priority), bm
instr (command) and bmrecalc (recalculation) is placed in the ring of that order, and omsn
The oop (snorper) is arranged above the address output.

[1454] The module, Bmprize is REQ /
ACK protocol, FULL / EMPT for buffer
The Y flag is processed, and the state of each address, i.e., i
sit a valid address? To maintain. From this information, it tells bminstr what address (if any) should be recalculated.
In addition, it contains a BUF indicating the FULL / EMPTY flag.
Buf, which manipulates CSR (status) microprocessor registers and controls microprocessor write access to buffer manager registers
Manipulates access microprocessor registers.

[1455] The module Bminstr is bmpr
When the command to calculate the address is issued, six commands (one for every two cycles) are issued to control bmcalc to calculate the address.

[1456] Module, Bmrecalc is bmin
Under the command of str, the address is recalculated. It runs commands every two cycles and includes all of the initialization and dynamic registers and a simple ALU capable of addition, subtraction and modulus. It is the FU it detects
It signals Sbmprize in the LL / EMPTY state, and upon completion, calculates the address.

[1457] B. 4.6 "Block implementation" 4.6.1 "Bmprize" On reset, the buf access microprocessor register is set to 1, allowing the initialization register to be set. While buf access is reading back 1, no address calculation is started. This is because without a valid initialization register, those calculations are meaningless.

Once the buf access is fully qualified (write zero to it), its purpose is to validate all four addresses, so mbprti
ze serves (validating them back) to make all addresses valid. At this stage, the buffer manager is "starting up" (i.e., all addresses have not yet been calculated), and thus no request is authorized. Once all addresses are valid once, the startup ends and all requests are certified. From this point, once the address becomes invalid (since it has been used and recognized), it will be recalculated.

It is not necessary to prioritize between addresses. Because the buffer manager can recalculate the address every 12 cycles while the DRA
This is because the M interface is at best able to use the address every 17 cycles. Thus, after startup, only one address at a time is invalid. Thus, bmprize will recalculate invalid addresses that are not currently calculated.

In the invention, the startup is buf ac
During a microprocessor access, no address is provided to the DRAM interface because the ESS is re-entered each time it is qualified.

[1461] B. 4.6.2 The "Bminstr" module, Bminstr, contains a MOD12 cycle counter (the number of cycles it takes to create an address). Note that the odd cycle ends the command while the even cycle starts the command. The upper three bits, along with whether it is a read or write calculation, are decoded into a command for bmrecalc as follows: for a read address:

[1462]

[Table 206] For the write address:

[1463]

[Table 207] Note: The result of the last operation is always kept in the accumulator.

If there are no addresses to be recalculated, the cycle counter will idle at zero, thus causing a command not to write to any of the registers. This has no effect.

1465. 4.6.3 "Bmrecalc" module, Bmrecalc performs one operation every two clock cycles. It is bmi on even counter cycle (start alu cyc)
nstr (and its buffer and io types), latch in the odd counter cycle (end al
u cyc) Latch the operation result. The operation result is always stored in the Accum register in addition to the register specified by the instruction. Furthermore, e
On the second alu cycle, bmrecalc informs bmprize as to whether the use of the address just computed will make the buffer full or empty, and when the address and full / empty are successfully computed (load addr).

[1466] Full / empty is calculated using the sign bit of the operation result.

The modulus operation is not a true modulus, but A mod B is implemented as follows: (A> B? (AB): A) However, this is only wrong in the following cases: Yes, A> (2B-1) This never happens.

1468. 4.6.4 Bmsnoop module, Bmsnoop, consists of four 18-bit super snoopers that monitor the address provided to the DRAM interface. Snorpa is an external DRA
M must be super (i.e., must be accessible by clock running) to enable on-chip testing of M. These snoopers are REQ
/ ACK system, and therefore
Different from the others on the device.

[1469] REQ / ACK is used on this interface as opposed to a two-wire protocol. This is because it is essential to send the information back to the sender (that is, to signal receipt), and Accept does not. Thus, it closely monitors the FIFO pointer.

[1470] B. 4.7 “Registers” To obtain microprocessor write access to the initial registers, one should write bufaccess and access is obtained when buf access reads back one. Conversely, to abandon the microprocessor write access, zero is used for buf access.
Should be written to. Access is gained when buf access reads back zero. buf acces
Note that s is reset to 1.

Although the dynamic and initialization registers of the present invention can be read at any time, write access must be obtained to ensure that the dynamic registers have not changed the microprocessor.

The initialization register is intended to be written only once. By rewriting them,
It may cause the buffer to be manipulated incorrectly. However, it is contemplated to increase the length of the on-the-fly buffer and have the buffer manager use the new length in a timely manner. No check has ever been made to see if the value in the initialization register feels, for example, that the buffers do not overlap. This is the user's responsibility.

[1473]

[Table 208] In the table, D indicates a register bit and x does not indicate any register bit.

[1474]

[Table 209]

[1475]

[Table 210]

[1476]

[Table 211] B. 4.8 "Match" Verification was performed in L-sim, with small FIFO's on the dummy DRAM interface, and in C-code as part of the top-level chip simulation.

[1478] B. 4.9 “Test” Test coverage for bman is through a snooper in bmsnoop, through a dynamic register (shown in B.4.4), and using a scan chain that is part of the DRAM interface scan chain. Section B. 5 "Reverse Modeler" 5.1 "Preface" This document describes the purpose, operation and implementation of the inverse modeler and token formatting (hsppk) according to the present invention.

Note: hsppk is a hierarchical part of the Huffman decoder, but is functionally part of the inverse modeler. Therefore, it should be discussed in this section.

[1479] B. 5.2 "Outlook" The token buffer is between imodel and hsppk and can contain a large amount of data all in off-chip DRAM. To ensure efficient use of this memory, the data must be in a 16-bit format. Token formatting "packs" the data from the Huffman decoder into this format for the token buffer. Thus, the inverse modeler "fetches" (unpacks) data from the token buffer format.

[1480] However, the main functions of the reverse modeler are:
Extending from a "run / level" code to a run of zero data and then to a level. In addition, the inverse modeler ensures that the data token has a coefficient of at least 64 and provides a "gate" for stopping streams that do not meet the startup criteria.

[1481] B. 5.3 "Interface" 5.3.1 Hsppk In the present invention, Hsppk has a Huffman decoder as input and a token buffer as output. Both interfaces are of the 2-wire type, with inputs of 17
Bit token port, output is 16 bit "packed data" plus FLUSH signal.
In addition, Hsppk is clocked from the Huffman clock generator and is connected to the Huffman scan chain. B. 5.3.2 "Imodel" Imodel has token buffer start-up output gate logic (bsogl) as input and inverse quantizer as output. Input from token buffer is 16-bit "packed data" plus block
end signal, and the input from bsogl is one w
irestream enable. Output is 11
Bit token port. All interfaces are controlled by a two-wire protocol. Imode
l has its own clock generator and scan chain.

[1482] Both blocks have microprocessor access to the snooper only at its output.

[1483] B. 5.4 “Description of Block” 5.4.1 “Hsppk” Hsppk receives 17-bit data from Huffman and outputs 16-bit data to a token buffer.
This is achieved by first truncating or splitting the input data into 12-bit words and then packing these words into a 16-bit format.

[1484] B. 5.4.1.1 "Splitting" Hsppk receives 17-bit data from inverse Huffman. This data is formatted into 17 bits using the following format.

F designates a format; E is an extension bit; R is a run bit; L is a length bit (shown in sign magnitude) or a non-data token bit; x is a don't care.

[1486] FLLLLLLLLLLLLLFormat 0 ELLLLLLLLLLLLFormat 0a FRRRRRRR00000000001 Normal tokens only occupy the bottom 12 bits,
Take the following form: ExxxxxxxLLLLLLLLLLLL However, the data token has a run and a level within each word in the following form: For zero format, 0 is used: E000000LLLLLLLLLLLL → FLLLLLLLLLLLLL Format 0 In format 0, it can be seen that the extension bits are lost and assumed to be 1. Thus, if the extension is zero, it cannot be used. In this case, format 1
Can be used unconditionally.

[1487] B. 5.4.1.2 "Packing" After splitting, all data words are 12 bits wide. All four 12-bit words consist of three 1
"Packed" into 6-bit words:

[1488]

[Table 212] B. 5.4.1.3 "Flushing Buffer" The DRAM interface of the present invention collects blocks of 32 16-bit "packed" words and writes them to the buffer. This means that if the block is only partially completed, the data can be stuck into the DRAM interface at the end of the stream. Therefore, a flushing mechanism is needed. Therefore,. Hsppk signals the DRAM interface to write the current partially completed block unconditionally.

[1489] B. 5.4.2.1 "Imup (Impacker)" Imup performs three functions: 4) 12 data from its 16-bit format.
Unpack to a bitword.

[1490]

[Table 213] 5) Maintain correct data during flushing of the token buffer.

By writing the current partially completed block unconditionally, useless data remains in the block when the DRAM interface flashes. Imup must delete useless data, that is, all data from the flash token, until the end of the block.

1492 Retain data until startup criteria are met. The data output from the block is conditional provided that a "stream enable" is accepted for each different stream from the buffer startup. Therefore, 12-bit data is output to hsppk. B. 5.4.2.2 "Imex (Expand
r) In the present invention, Imex extends all run length codes to zero runs and subsequent levels.

[1493] B. 5.4.2.3 "Impad (PA
Dder) "Impad ensures that every data token body contains 64 (or more) words. It does so by padding the last word of the token with zeros. Data token is 64 in the body
Not checked to have more words.

[1494] B. 5.5 "Block execution" 5.5.1 “Hsppk” Typically, splitting and packing are performed in one cycle.

1495. 5.5.1.1 “Splitting” First, the format is determined: IF (datatoken) IF (lastformat == 1) use fo
rmat 0a; ELSE IF (run == 0) use form
at 0; ELSE use format 1; and format bits are determined: format 0 format bit = 0; format 0a format bit = ex
format 1 format bit = 1; if format 1 is used, the new data should not be accepted in the next cycle since the code level must still be output. B. 5.5.1.2 "Packing" The packing procedure cycles through every four valid data entries. The output of the 16-bit word is formed from the last valid word held and the following word. If this is not valid, the output is not valid. The procedure is as follows:

[1496]

[Table 214] In the table, x indicates an undefined bit.

During valid cycle 0, no word is output since it is not valid.

A valid cycle number is maintained by the ring counter. It is incremented by valid data from the splitter and the accepted output.

1499 FLUSH (or picture en)
d) When the token is received and the token itself is ready for output, a flash signal is output to the DRAM interface, resetting the valid cycle to zero. When the flush token reaches something other than cycle 3, the flush signal must delay the valid cycle to ensure that the token itself outputs.

[1500] B. 5.5.2 "Imodel" 5.5.2.1 "Imup" As in the case of the packer, the last valid input is stored and combined with the next input to enable unpacking.

[1501]

[Table 215] In the table, x indicates an undefined bit.

A valid cycle number is maintained by the ring counter. The unpacked data includes the token data, the flash and the picture end decoded from it. In addition, the format and extension bits are decoded from the unpacked data.

[1503] formatbit is extn =
(Lastformat == 1) 11 dataobo
dy format = databody && (forma
tbit && lastformatbit) For token decoding and to be sent to imex.

[1504] FLUSH (or picture en)
d) The token is unpacked and output to imex,
All data is deleted until the block end signal is received from the DRAM interface (Val
id is lowered).

[1505] B. 5.5.2.2 "Imex (EX
According to the present invention, imex is a four state machine for extending run / level codes out. The state machines are as follows: State 0: Load run count from run code.

[1506] State 1: Decrease run count,
Outputs zero.

State 2: input data and output level; default state.

[1509] State 3: illegal state.

[1509] B.I. 5.5.2.3 "Impad (PA
Dder) "Impad is informed by imex about the data token header. Next, it counts the number of coefficients in the token body. If the token ends before it has 64 coefficients, a zero coefficient is inserted at the token end, completing it to be 64 coefficients. For example, 64 with unextended data headers inserted after them
Has a zero coefficient of Data tokens with coefficients greater than 64 are not affected by impad.

[1510] B. 5.6 “Registers” The models and hsppks of the present invention have no microprocessor registers, except for their snoopers.

[1511]

[Table 216] In the table, V = valid bit; A = accept bit; E = extended bit; D = data bit.

[1512] B. 5.7 "Match" The selected stream flows through the Lsim simulation.

B. [1513] 5.8 "Test" The test coverage for the imodel at the input is through the token buffer output snooper and at the output through the imodel's own snooper. The logic is covered by the scan chain of the model itself.

The output of hsppk is accessible through the Huffman output snooper. Logic can be viewed through the Huffman scan chain. Section B. 6
"Buffer startup" 6.1 Introduction This section describes the method and implementation of buffer startup according to the present invention.

B. [1515] 6.2 "Outlook" To ensure that the picture stream can be displayed smoothly and continuously, a certain amount of data must be collected before decoding can be started. This is called a start-up condition. Coding standards can be translated into almost the amount of data that needs to be collected.
Specify BV delay. The purpose of "buffer start-up" is to ensure that all streams have their data coming from the token buffer and meeting its start-up conditions before allowing decoding. It is held in the buffer by a conceptual gate (output gate) at the output of the token buffer (ie, the inverse modeler). This gate is only opened for the stream once its startup conditions are met.

B. [1516] 6.3 "Interface" The Bscntbit (Buffer Startup Bit Counter) is in the data path, communicates via a two-wire interface and is connected to the microprocessor. In addition, it branches to bsogl (buffer start-up output gate logic) with a two-wire interface.
Bsogl controls an imup (inverse modeler unpacker) that implements an output gate via a two-wire interface. B. 6.4 "Block Structure" Bscntbit is in the data path between the start code detector and the coded data buffer. This one cycle block counts the valid data words leaving the block and counts this number as the start-up condition (or target) that will be loaded from the microprocessor.
Compare with When the target is met, bsogl is signaled. Data is not affected by bscntbit. Bsogl is between bscntbit and imup (in the reverse modeler). Effectively, it is a sequence of indicators that indicate that the streams have met their targets. The column is driven by the stream leaving the buffer (ie, the flash token received in the data stream at the imup) when another "indicator" is accepted into the imup. If the column is empty (ie, if there are no streams in the buffer that filled its startup target), the stream in the imup is stalled.

The sequence has only a finite depth, but
This can be expanded indefinitely by destroying a column in bsogl, allowing the microprocessor to monitor that column. These row mechanisms are referred to as the inner row and the outer row, respectively.

B. [1518] 6.5 "Block execution" 6.5.1 "Bsbitcnt (Buffer Startup Bit Counter)" Bscntbit counts all valid words input to the buffer startup. Counter (bs
ctr) is a 16-24 bit wide programmable counter. In addition, bsctr has carry look ahead circuitry to give it sufficient speed. Bs
The width of ctr is programmed by ced bs prescale. It does so by raising the bit 8-16, so that a carry is always sent. Therefore, those bits remain effectively unused. The upper 8 bits of bsctr are used for comparison with the target (ced bs target).

[1519] Comparison (ced bs count ≧ ced)
bs target) is performed by bscmp.

The target is extracted from the stream when the stream is in a Huffman decoder and calculated by the microprocessor. Therefore, it will only be set after a stream start. Before startup, targetvalid is set low. Writing to ceds target is tar
Set get valid high so that the comparison in bscmp is performed. The comparison is ced bs co
When indicating that unt ≧ ced bs target, the target valid is set low. Target has been met.

When the target is satisfied, the count is reset. Note that it does not reset at the stream end. In addition, if it is before the end of the stream, counting is disabled after the target is satisfied. The count saturates at 255.

When the stream end (ie, flush) is detected at bsbitcnt, abs
A flush event is created. If the stream ends before the target is satisfied, an additional event (bs flush before target m
et event) is created. When these events occur, the block is stranded. This allows the user to redo the target search for the next stream, or bs flush bef
For an ore target met event, one of the following: 1) Write a zero target that will force the target met or 2) Until the target is not met and this combined with the last stream reaches the target Notice the progress of the next stream. The target for this next stream should be adjusted accordingly.

[1523] B. 6.5.2 BSOGL (Buffer Startup Output Gate Logic) As described above, Bsogl is a string of indicators that indicate that a stream has met its target.
The column type is set by ced bs queue (internal (0) or external (1)). This is a reset to select an internal column. The column depth determines the maximum number of filled streams that can exist in the coded data buffer, Huffman, and token buffer. When this number is reached (ie, when the column is full), bso
gl stalls the data path at bsbitcnt.

The use of an internal column does not require any action from the microprocessor. However, if it is necessary to increase the depth of the column, (ced to be set
ced bs to get access to bsqueue
Set access and target get ev
ent and stream end events are enabled and access is denied (external columns can be set).

The external columns (counts maintained by the microprocessor) are inserted into the internal columns. The outer column has two events: target_met_event and st
Maintained by the beam end event. These are simply servicequeue inputs, respectively.
service queue output, and register ced bs enable next stream
It is called m. In effect, target met even
nt is the upstream end of the internal column that supplies the column. Similarly, ced bs enable nxt
stream is the downstream end of the internal column that consumes the column. Similarly, stream end e
event is the request to supply the downstream stream; stream end event is ce
Reset the dbs enable next stream. The two events should be serviced as follows: / * TARGET MET EVENT * / j = micro read (CED BS ENABLE NXT STM): if (j == 0) / * Is next stream enabled? * / (/ * No, enable it * / micro write (CED BS ENABLE NXT STM, 1); printf ("enable next stream (queue = 0x% x) @n", (context->queueel)); / * Yes, increment of queuing of “target met” streams * / ｛queue ++; if (queue> 0) / * are there any “target mets” left? * / (/ * yes, decrement the queue and enable ano micro stream (CED BS ENABLE NXT STM, 1); printf ("enable next stream (queue = 0x% x) @n", (context-> queueel) (the context->queueel); the stream * / queue ----; que empty empty enable next stream (queue = 0x% x) ＼n ″, queue; micro write (CED EVENT 1,1 <<< BS STREAM END EVENT); Can be changed from internal to external, but the external column is (queue above)
== 0) ced to be reset when empty
ced to get access to the bs queue
bs access and set target met
By masking the event and stream end and giving up access, it is only possible to change from outside to inside.

On the other hand, the check of the stream start-up condition is disabled, the cedsqueue (external) is set, and the target
mask the end and end events and add ced bs
Set enable nxtstream. In this way, all streams are always enabled. B. 6.6 "Microprocessor Register"

[1527]

[Table 217]

[1528]

[Table 218] In the table: D is a register bit; x is a non-existent register bit; r is a reserved register bit; and to gain access to these registers, it must be in the case of an interrupt service routine. , Ced bs a
access is set to one and must be registered until it reads back one. ed bs access
Access is abandoned by setting to zero.

[1529] Section B. 7 "DRAM interface" 7.1 "Outlook" In the present invention, the spatial decoder, the temporal decoder, and the video formatting unit each include a DRAM interface block for its special chip. In all three devices, the function of the DRAM interface is:
Data transmission from the chip to the external DRAM and data transmission from the external DRAM to the chip via the block address supplied by the address generator.

The DRAM interface typically operates from a clock that is asynchronous to the address generator and to the clocks of the various blocks through which data is sent. However, this asynchrony can be easily handled because the clocks operate at approximately the same period.

The data is usually transmitted between the DRAM interface and the rest of the chip in a block of 64 bytes (the only exception being the prediction data in the temporal decoder). The transmission is generated by a device known as a "swing buffer". This is essentially a pair of DRAMs operated in a double buffered configuration,
The AM interface fills or empties one RAM, while another part of the chip empties or fills the other RAM. A separate bus carrying addresses from the address generator is associated with each swing buffer.

Each chip has four swing buffers, and the functions of these swing buffers are different in each case. In the case of a spatial decoder, one swing buffer was used to transmit coded data to DRAM, another swing buffer was used to read coded data from DRAM, and a third swing buffer was tokenized. A fourth swing buffer is used to transfer the data to the DRAM, and a fourth swing buffer is used to read the tokenized data from the DRAM. In the temporal decoder, one swing buffer is used to write intra or predicted picture data to the DRAM, a second buffer is used to read intra or predicted picture data from the DRAM, and the other two buffers are used. Two buffers are used to read the prediction data forward and backward. In the video formatting section, one swing buffer converts data to DR.
AM, and the other three swing buffers are used to read data from the DRAM, each with luminance (Y), red and blue color difference data (each C
r and Cb).

The following section describes a DRAM according to the present invention.
The operation of the interface will be described, which has one write swing buffer and one read swing buffer which are essentially the same as the operation of the spatial decoder DRAM interface. This is illustrated in the "DRAM interface" of FIG.

B. [1534] 7.2 “General DRAM Interface” In FIG. 140, the interface to the address generator and the interface to the block that supplies and takes data are all two-wire interfaces. The address generator may generate an address as a result of receiving the control token, or simply generate a fixed sequence of addresses. The DRAM interface handles the two-wire interface associated with the address generator in a special way. Instead of holding the accept line high when ready to receive an address, the DRAM interface provides the address generator with a valid address, processes that address,
The accept line is set high for one clock cycle. Thus, the request / acknowledge (REQ / A
CK) Execute the protocol.

A unique feature of the DRAM interface is the ability to communicate with blocks that provide / accept data completely separate from the address generator and other blocks. For example, an address generator can generate an address associated with data in a write swing buffer, but the write swing buffer is an external DRAM.
No action will be taken unless there is a signal that there is a data block ready to be written to. However, no action is taken unless the address is provided on the appropriate bus from the address generator.
Further, once one of the RAMs in the write swing buffer is filled with data, the other RAM is fully filled before the data input is stalled (the 2-wire interface accept signal is set low) and the DRAM is fully filled.
"Swing" to the interface.

It is important to note in understanding the operation of the DRAM interface of the present invention that, in a properly configured system, at least as much as the sum of all the average data rates between the swing buffer and the remaining chips. Faster, the DRAM interface can transfer data between the swing buffer and the external DRAM.

Each DRAM interface includes a way to determine which swing buffer to service next. In general, this is either a "round robin" or a priority encoder, where in the case of a round robin, the serviced swing buffer is the next available swing buffer that has been seldom out of order recently and the priority is In the case of an encoder, some swing buffers have higher priority than others. In both cases, additional requests will come from the refresh request generator which has a higher priority than all other requests. The refresh request is generated from a refresh counter that is programmable via a microprocessor interface.

B. [1538] 7.2.1 “Swing Buffer” FIG. 141 shows a write swing buffer. The operation is as follows: 1) Valid data is displayed at data in. As each piece of data is accepted, it is written to RAM1 and the address is incremented.

2) When RAM1 is full, the input data gives up control and sends a signal to the read side to indicate that RAM1 is ready to be read. This signal passes between two asynchronous clock regimes and therefore passes through three synchronous flip-flops.

1540) The next data item to arrive at the input side is written to the RAM2 which is still empty.

4) When the round robin or priority encoder indicates that it is time to read this swing buffer, the DRAM interface
1 and read them into the external DRAM. Then, as in (2), a signal is sent back across the asynchronous interface, indicating that RAM1 is ready to be written again.

1) The DRAM interface is RAM1
, And if the input side "swings" before filling RAM2, data can be continuously accepted by the swing buffer, otherwise, when RAM2 is full, RAM1 Until "swing back" to be used by the side,
The swing buffer will set its accept signal low.

6) This process is repeated indefinitely.

The operation of the read swing buffer is similar, but the input and output data buses are reversed.

B. [1545] 7.2.2 "Addressing External DRAM and Swing Buffer" The DRAM interface is designed to maximize the available memory bandwidth. Thus, each 8 × 8 data block is arranged to be stored in the same DRAM page. In this way, the DRAM fast page access mode can be fully used, where one row address is provided followed by many column addresses.
In addition, the data bus for the external DRAM is 8,
DRAM used can be 16 or 32 bits wide
Convenience is provided to allow the amount to meet the size and bandwidth requirements of the particular application.

In this example (showing how the DRAM interface on the spatial decoder works), the address generator provides the block address to the DRAM interface for each of the read swing buffer and the write swing buffer. . This address is DRA
Used as row address for M. The six bits of the column address are provided by the DRAM interface itself, and these bits are also used as addresses for the swing buffer RAM. The data bus for the swing buffer is 32 bits wide and therefore the external D
If the bus width for the RAM is less than 32 bits, before the next word is read from the write swing buffer or before the next word is written to the read swing buffer (read and write are related to the transfer direction to the external DRAM). ) Two to four external DRAM accesses must be made.

For the temporal decoder and the video formatting part, the situation is more complicated. These are described separately below.

[1548] B. 7.3 “DRAM Interface Timing” In the present invention, the DRAM interface timing block uses a timing chain to place the edge of the DRAM signal exactly ４ of the system clock period. Two quadrature clocks from the phase lock loop are used. These are combined to form a conceptual 2x clock. Any one chain is made up of two shift registers in parallel on opposite phases of the 2x clock.

First, there is one phase for the page start cycle and another for the read / write / refresh cycle. The length of each cycle is programmable via the microprocessor interface, after which the page start chain has a fixed length, and the length of the cycle chain changes appropriately during page start.

When reset, the chain is cleared and a pulse is created. This pulse travels along the chain and is directed by state information from the DRAM interface. The DRAM interface clock is generated by this pulse. Each DRAM interface clock cycle corresponds to one DRAM cycle. Thus, because the DRAM cycles have different lengths, the DRAM interface clock is not constant speed.

Further, the timing chain combines the pulses from the above chain with information from the DRAM interface, and outputs and strobes and enables (notca).
s, notras, notwe, notoe).

[1552] Section B. 8 "Inverse quantizer" 8.1 Introduction This document describes the purpose, operation and implementation of the inverse quantizer (iq) according to the present invention.

B. [1553] 8.2 “Outlook” The inverse quantizer reconstructs the coefficients from the quantized coefficients, the quantization weight, and the step size, all of which are transmitted in the data stream.

B. [1554] 8.3 "Interface" Iq lies between the inverse modeler and the inverse DCT in the data path and is connected to the microprocessor. The data path connection is made via a two-wire interface. Input data is 10 bits wide and output data is 11 bits wide.

[1555] B. 8.4 "Operation of inverse quantizer" 8.4.1 "H261 formula"

[1556]

(Equation 1) B. 8.4.2 "JPEG formula"

[1557]

(Equation 2) B. 8.4.3 "MPEG type"

[1558]

(Equation 3) B. 8.4.4 “JPEG variation formula”

[1559]

(Equation 4) B. 8.4.5 "All other tokens" All tokens except data tokens must pass through unquantized iq. Therefore: Floor (a) returns an integer as follows: (a-1) <floor (a) ≦ a a ≧ 0, a ≦ floor (a) <(a + i) a ≦ 0 Qi is a quantization coefficient.

[1560] Ci is the reconstructed coefficient.

[1560] Wi, j is a value in the quantization table matrix.

[1562] i is a coefficient index along the zigzag.

J is a quantization table matrix number (0 ≦ j ≦ 3).

B. [1564] 8.4.6 "Multiple Standards to be Combined" All of the above standards and their variations (further control data that must not be changed by iq)
Can be mapped to one expression: OUTPUT = (2INPUT + k) (xy) / 16 There are the following additional post-dequantizers: Add 1024 Convert sine magnitude to 2's complement representation Round to the nearest odd number towards zero. Saturate the result to +2047 or -2048.

The variables k, x, and y for each variation of the standard and the functions they use are shown in Tables 219 and 220.

[1566] B. 8.4.6 "Multiple Standards to be Combined"

[1567]

[Table 219]

[1568]

[Table 220] B. 8.5 “Block Structure” Paragraph B. From 8.4.6 and Tables 219 and 220, it can be seen that one structure can be used for the multi-standard dequantizer. The arithmetic block diagram is shown in FIG. 142 "Arithmetic Block": the control for the arithmetic block can be functionally divided into two sections: a token for loading into a status register or quantization table Decoding of the status register to the control signal.

The token is decoded in the next cycle, iqca, which controls the iqcb bank of registers. It also controls access to the four quantization tables in iqram . Arithmetic, the two multipliers and the post function, are in iqarith. A complete block diagram for iq is shown in FIG.

[1570] B. 8.6 "Block execution" 8.6.1 “Iqca” In the present invention, iqca converts tokens into igram and i
It is a state machine used for decoding into a register control signal in qcb. Since the state machine is reset by each new token, it should be described as a state machine for each token. For example: QUANT SCALE (B.8.7.
4. See QUANT SCALE) and QUANT
TABLE (B. 8.7.6 QUANT TABLE
Code) is as follows: if (tokenheader == QUANT SCALE) @sprintf (report, "QUANT SCALE"); reg addr = ADDR IQ QUANT SCALE; rnnow = write; entitle; (Tokenheader == QUANT TABLE) / * QUANT TABLE token * / switch (substate) ｛case 0: / * quantification table header * / spreadf (report, "QUANTA, QUANTA, QUANTA, QUANTA, QUANTA, QUANTA, QUANTA, QUANTA, QUANTA, QUANT TABLE) "(Empty)")); nextsubstate = 1; insertnext = (headerextn? 0: 1) Reg addr = ADDR IQ COMPONENT; rnoww = WRITE; enable = 1; break; case 1: / * quantification table body * / sprintf (report, "QUANT TABLE"% "???????????????????????????????? Insertsubstate = 1; insertnext = (headerextn? 0: (qtmaddr 63 == 0)); reg addr = USE QTM; rnow = (headerextn ?? reK; default: printf (report, ERROR in iq quantification table token) oder (substate% x) \n, substate); break; case}} substate is state in the token, QU
The ANT SCALE has, for example, only one substate. However, QUANT TABLE has two substates, one is the header and the other is the token body.

The state machine is implemented as a PLA. Unrecognized tokens do not generate any word lines and do not cause the PLA to output default (harmless) controls.

Therefore, iqca supplies the address from the BodyWord counter to iqram and inserts words into the stream, for example, in an unextended QUANT TABLE (see B.8.7.7.4). While this keeps enable output is achieved by Rukoto stop input. The word can be filled with the correct data in the following block (iqcb or iqarith).

[1573] iqca is one cycle in the data path controlled by the two-wire interface.

B.1574 8.6.2 "iqcb" In the present invention, iqcb holds an iq status register. Under the control of iqca, iqcb loads or unloads these from / to the data path.

The status register is iqarith for controlling the XY multiplier terms and the post-quantization function.
(See Table 219, Table 2)
20).

The sign bits of the data path are now separated and sent to the post-quantization function. Further, zero value words on the data path are detected here. Arithmetic is then ignored and zeros are maxed into the data path. This is the simplest way to follow iq's "zero in; zero out" specification.

[1577] The status register is the register iq a
access is set to 1 and is accessible from the microprocessor only when 1 is read back. In this situation, iqcb stalls the data path, so that the registers have a stable value and no data is converted in the data path.

Iqcb is one cycle in the data path controlled by the two-wire interface.

[1579] B.I. 8.6.3 "Iqram" Iqram must support for four quantization table matrices (QTMs), each of which is 648 bits. Therefore, it is a 2568-bit 6-transistor RAM, one read or one write per cycle. The RAM is surrounded by two-wire interface logic that receives its control and writes data from iqca. It reads data to iqarith. Similarly, iqram occupies the same cycle in the datapath as iqcb.

The RAM is read from and written to the microprocessor when iq access reads back 1. RAM is a keyhole register, iq qtm ke
put behind yhole, iq qtm keyho
addressed by le addr. iq qtm
Access to keyhole is iq qtm key
It will increment the address it points to, which is kept in the hole addr. Similarly, iq qtm ke
yhole addr can be written directly.

B.B. 8.6.4 "iqarith" Note that iqarith has three functions that are pipelined and split over three cycles. The function is discussed below (see FIG. 140).

B. [1582] 8.6.4.1 “XY Multiplier” This is the 5 (X) × 8 supplied to the datapath multiplier.
(Y) bit carry save unsigned multiplier. The multiplier and multiplicand are selected with control wires from iqcb. The multiplication is in the first cycle and the decomposition adder is in the second cycle.

At the input to the multiplier, the data from iqram can be maxed to the data path to read the QUANT TABLE to the data path.

B. [1584] 8.6.4.2 "(XY) * Datapath Multiplier" This 13 (XY) * 12 (datapath) bit carry-save unsigned multiplier is split over three cycles of the block. 3 partial products in the first cycle, 2nd
Seven in the cycle and the remaining two in the third cycle.

All outputs from the multiplier are less than 2047 (non-coefficient) or saturate to + 2047 / −2048, so the top 12
The bits need not be disassembled. Thus, the decomposition adder is only 2 bits wide. For the rest of the higher order bits, zero detection is sufficient as a saturation signal.

[1586] B. 8.6.4.3 Post-quantization function The post-quantization function adds: 1024 Converts sine magnitude to two's complement representation Rounds all even numbers to the nearest odd number toward zero • Saturate the result to +2047 or -2048. • Set the output to zero (see B.8.6.2).

The first three functions are performed in a 12-bit adder (pipelined in second and third cycles). From this, we know what each function needs and they are combined on one adder.

[1588]

[Table 221] Table B. 8.2 As will recognize if post-quantization adder functions those skilled in the art, since these functions mutually dependent on one another when coupled, to be careful when re profile Gurami <br/> ring these No.

The saturation values, zero and zero + 1024, are maxed into the data path at the end of the third cycle.

[1590] B. 8.7 "Dequantizer Token" The following description defines the dequantizer behavior for each token tp to which the dequantizer responds. In all cases, the token is sent to the output of the inverse quantizer. In most cases, tokens are not modified by the inverse quantizer, with the exceptions noted below. All unrecognized tokens are sent unmodified to the output of the inverse quantizer.

B. [1591] 8.7.1 "Sequence start" This token is stored in the register iq prediction.
mode [1: 0] and iq mpeg india
Let ction [1: 0] be set to zero.

B.1592. 8.7.2 “Coding Standard” This token is the current standard (M
PEG, JPEG or H.264. 261), iq
Let standard [1: 0] be loaded with the appropriate value.

[1593] B. 8.7.3 "Prediction mode" This token is in the iq prediction mode
Load [1: 0]. The prediction mode token possesses more than one bit, while the inverse quantizer only needs access to the two lowest order bits. These determine whether the block is intra-coded.

[1594] B. 8.7.4 "Quantization Scale" This token is called iq quant scale [4:
0].

[1595] B. 8.7.5 The data present invention, this token owning the actual quantized coefficients. The token head contains two bits that identify the color components, which are loaded into iq component [1: 0]. The next 64 token words contain the quantized coefficients. These are modified as a result of the inverse quantization process and are replaced by the reconstructed coefficients.

If exactly 64 extension words are not present in the token, the dequantizer behavior is unlimited.

The data token at the input of the inverse quantizer owns the quantized coefficients. These are represented by 11 bits (10 bits + sign bit) in the sign magnitude format. Value "minus zero"
Should not be used, but is interpreted exactly as zero.

The data token at the input of the inverse quantizer owns the reconstructed coefficients. These are represented by 12 bits (11 bits + sign bit) in 2's complement format. The data token at the input will have the same number of token extension words as at the input of the inverse quantizer.

[1599] B. 8.7.6 "Quantization table (QUA
ANT TABLE) This token can be used to load a new quantization table or to read the current table. In an inverse quantizer, the token will typically be used to load a new table decoded from the bitstream. The operation of reading the current table is useful in a quantizer in front of the encoder if the table is to be encoded in a bitstream.

The token head contains two bits that specify the table number to be used. These are placed in iq component [1: 0]. Note that this register now contains the "table number", not the color component.

If the extension bit of the token head is 1, the inverse quantizer expects there to be exactly 64 extension token words. Each is interpreted as a quantization table value and placed in successive locations in the appropriate table starting at location zero. The ninth bit of each extension token word is ignored. The token is also sent unmodified to the output of the inverse quantizer in the usual manner.

If the extension bit of the token head is zero, the inverse quantizer will read successive locations in the appropriate table starting at location zero. Each location becomes an extension token word (the ninth bit becomes zero). At the end of this operation,
The token will contain exactly 64 extended token words.

The operation of the inverse quantizer in answer to this token is not limited for all extended word numbers except zero and 64.

[1604] B. 8.7.7 “JPEG table select” This token is iq jpeg indirectio
Used to load / unload color component translations for table numbers to / from n. These translations are used in JPEG and other standards.

The token head contains two bits that identify the color component of current interest. These are iq comp
onent [1: 0].

If the extension bit of the token head is 1, the token is one extension word, iq jpeg i
ndirection [2iq component
[1: 0] +1: 2 iq component [1:
0]] contains the lowest two bits written to the location. The value just read becomes the token extension word (the upper 7 bits become zero). At the end of this operation, the token will contain exactly one token extension word.

[1607]

[Table 222] B. 8.7.8 "MPEG Table Select" This token is used during processing via the MPEG standard to define whether to use a default or user defined quantization table. The token head contains two bits. Bit 0 of the header is iq mpeg direction
Determines which bit is to be written. Bit 1 is written to that location.

[1608] iq mpeg direction
Since the [1: 0] register is cleared by the sequence start token, it will only be necessary to use this token if a user-limited quantization table was sent in the bitstream.

[1609] B.I. 8.8 “Microprocessor registers” 8.8.1 "iq access" To gain microprocessor access to any iq register, iqaccess must be set to 1 and registered until it reads back 1 (B.8 .6.2). Failure to do this will result in the register being read being still controlled by the data path and not stable. igram
If, access is locked out and reads back zero.

Writing 0 to iq access gives up control to the data path.

B. [1611] 8.8.2 “Iq coding
standard [1: 0] "This register holds the coding standard implemented by the inverse quantizer.

[1612]

[Table 223] This register is loaded by the coding standard value.

Although this is a 2 bit register, 8 bits are currently allocated to the memory map, and future implementations will be able to handle more than the above standards.

B.B. 8.8.3 “Iq mpeg in
direction [1: 0] "This 2-bit register is used to record which quantization table is to be used during the MPEG decoding operation.

[1615] Iq mpeg direction
[0] controls the table used for intra-coded blocks. If it is 0, quantization table 0 is used and is expected to include the default quantization table. If it is 1, quantization table 2
Is used and is expected to include a user-limited quantization table.

[1616] This register is an MPEG TABLE S
Loaded by the ELECT token and set to 0 by the sequence start token.

B. [1617] 8.8.4 “Iq jpeg in
direction [7: 0] "This 8-bit register determines which four quantization tables are used for each of the four possible color components that occur in a JPEG scan.

• Bits [1: 0] hold the table number used for component 0.

• Bits [3: 2] hold the table number used for component one.

• Bits [5: 4] hold the table number used for component two.

• Bits [7: 6] hold the table number used for component three.

[1620] This register is a JPEG TABLES
Affected by the ELECT token.

[1623] B. 8.8.5 “iq quants”
call [4: 0] "This register holds the current value of the quantization scale function. This register is loaded by the QUANT SCALE token.

[1624] B. 8.8.6 "iq component
nt [1: 0] "This register is a quantization table matrix (QTM)
Holds the value that is translated into a number. It is loaded by token number.

The data token header causes this register to be loaded with the color components of the block being processed. This information is used only in JPEG and JPEG variations to determine the QTM number, which is reference to iq j
Process with peg direction [7: 0]. In other standards, iq component
[1: 0] is ignored. The JPEG table select token causes this register to be loaded with a color component. Then it is accessed by the token body iq
Used as an index into jpeg_direction [7: 0].

The quantizer token causes this register to be loaded with the QTM number. This table is then loaded from the token (if an extended form of token is used) or read from the table to form a suitably expanded token.

B. [1627] 8.8.7 "iq predict
ion mode [1: 0] "This two-bit register holds the prediction mode used for the following block. The only way the dequantizer uses this information is to determine whether intra-coding is used. If both bits of the register are 0, the next block is intra-coded.

This register is loaded by the prediction mode token. This register is set to 0 by the sequence start token.

[1629] Iq prediction mode
[1: 0] has no effect on operation in JPEG and JPEG variation modes.

B.1630 8.8.8 “Iq jpeg in
direction [7: 0] "Iq jpeg direction is used as a look-up table to translate color components into QTM numbers. Therefore, as shown in Table 222, iq component is iq jpeg indirect
Used as an index to the Tion.

This register location is written directly by the JPEG table select token if an extended form of the token is used.

This register location is read directly by the JPEG table select token if a non-extended form of the token is used.

[1433] B. 8.8.9 “Iq quant t”
able [3: 0] [63: 0] [7: 0] "There are four quantization tables, each having 64 locations. Each location is an 8-bit value.
Value 0 should not be used at any location.

These registers are stored in B.C. 8.6.3 Ig
This is implemented as the RAM described in ram.

These tables can be loaded using quantization table tokens.

Note that the data in these tables is stored in a zigzag scan order. Many documents display quantization table values as a square 8 × 8 number array. Typically, the DC terms are in the upper left, with horizontal frequencies increasing from left to right and vertical frequencies increasing from top to bottom. Such tables must be read along a zig-zag scan path as the numbers are placed in a quantization table with consecutive i.

[1637] B. 8.9 "Microprocessor register map"

[1638]

[Table 224] B. 8.10 "Test" The test coverage for the inverse quantizer at the input is through the inverse quantizer's output sniper and at the output through the inverse quantizer's own snooper. The logic is covered by the scan chain of the inverse quantizer itself.

When the ramtest signal is recognized, iq
Access to the program is obtained regardless of the access. Section B. 9 “IDCT” B. 9.1 "Preface" The purpose of describing the Inverse Discrete Cosine Transform (IDCT) block here is to provide a source of engineering information for the IDCT. It contains the following information: The purpose and key features of the IDCT • How it was designed and demonstrated • Structure In addition, the purpose is to provide sufficient information to those skilled in the art to make such explanations easier or aid in: It is to be.

IDC as "silicon macro function"
Recognition of T ・ Integration of IDCT into another device ・ Development of test program for IDCT silicon ・ Modification, redesign or maintenance of IDCT ・ Development of forward DCT block 9.2 “Outlook” The Discrete Cosine Transform / Zigzag (DCT / ZZ) transforms on blocks of pixels, each block displaying a screen area of 8 pixels high by 8 pixels wide. The purpose of the transformation is to display pixel blocks in the frequency domain, which is classified by frequency. Since the eye is sensitive to DC components in the picture, but less sensitive to high frequency components, the frequency data causes each component to separately reduce magnitude according to the sensitivity of the eye. The magnitude reduction process is known as quantization. The quantization process reduces the information contained in the picture, ie the quantization process is lossy. Lossy processes provide overall data compression by removing certain information. The frequency data is classified so that high frequencies are easily quantized to zero, and all appear continuously. Consecutive zeros mean that run-length coding is generally not a lossy process, but coding data that is quantized by using a run-length coding scheme results in additional data compression. I do.

The IDCT block (which actually contains the inverse zigzag RAM or IZZ, and the IDCT) takes the frequency data to be classified and converts it to spatial data. This inverse classification process is a function of IZZ.

The picture decompression system of which the IDCT block forms a part specifies pixels as integers. This means that the IDCT block takes an integer value and must produce an integer value. However, since the IDCT function is not based on integers, the internal numbering uses a fractional part to maintain internal precision. Although full floating point arithmetic is preferred, the implementation described here uses fixed point arithmetic. There is a slight loss of precision when using fixed-point arithmetic, but the accuracy for this implementation is 261 and beyond the precision specified by IEEE.

[1643] B. 9.3 "Design Goals" According to the present invention, the main design goal was to design a functionally accurate IDCT block that uses minimal silicon area. Furthermore, while the design was required to run at a clock speed of 30 MHz under specified operating conditions, it was believed that it should have further applicability for the future. Higher clock rates will be needed in the future, and the structure of the design will allow this where possible.

[1644] B. 9.4 “Description of IDCT Interface” The IDCT block has the following interface.

Token data input port of 12-bit width Token data output port of bit width Microprocessor interface port System service input port Test interface Resynchronization signal Both token data ports are the standard two-wire interface described above. Type. The width shown refers to the number of bits in the data representation, not the total number of wires in the port.
In addition, associated with the input token data port are the clock and reset signals used for resynchronization to the output of the previous block. In addition, there are two resynchronization clocks associated with the output token data port and used by subsequent blocks.

The microprocessor interface is standard and uses a 4-bit address. In addition, there are three externally decoded select inputs, which are used to select the address space for events, internal registers, and test registers. This mechanism provides the flexibility to map the IDCT address space to different locations in different chips. In addition, one event output, idcevent
And two i / o signals, n derrd and n serrd
And are event tri-state data wires that are externally connected to the appropriate bits of the non-data bus of the IDCT and microprocessor.

The service port of the system consists of a standard clock signal and a reset input signal, as well as a two-phase override clock and an associated clock override mode select input.

The test interface is composed of JTAG clock signal and reset signal, scan path data, control signal, ramtest and chiptest inputs.

In normal operation, the microprocessor port is inactive because the IDCT does not require microprocessor access to perform its designated function. Similarly, the test interface is only active when testing or confirmation is required.

[1650] B. 9.5 "Computational basis for discrete cosine transform" In video bandwidth compression, the input data represents a rectangular part of the picture. Therefore, the transformation applied must be two-dimensional. Two-dimensional transforms are difficult to calculate effectively, but two-dimensional DCTs have separable properties. Separable transforms can be calculated along each dimension separately from the other dimensions. To do this, a one-dimensional I, specifically designed for mapping to hardware,
Use the DCT algorithm; the algorithm is not appropriate for software models. One-dimensional algorithms are applied continuously to obtain two-dimensional results.

2D DC for N × N pixel block
The operational definition of T is as follows:

[1652]

(Equation 5) The above definition is operationally equivalent to performing matrix compatibility between multiplications and multiplying two N × N matrices twice in succession. One-dimensional DCT is equivalent to arithmetically multiplying two NN matrices. Operationally, in the two-dimensional case: Y = [XC] TC where C is a matrix of cosine terms.

Thus, DCT is sometimes described in the section on matrix operations. While the description of the matrix is useful for the arithmetic reduction of the transformation, it must be emphasized that this only simplifies the notation. Note that the 2 / N term dominates the DC level. The constants c (j) and c (k) are known as normalization functions.

[1654] B. 9.6 "IDCT Transform Algorithm" As will be described in more detail below, the algorithm used to calculate the actual IDCT transform is "fast"
Should be an algorithm. The algorithm used is optimized for efficient hardware structure and implementation. The main features of the algorithm are the use of 〓2 scaling to remove one multiplication, and the transformation of the algorithm designed to produce greater symmetry between the upper and lower sections. This symmetry allows many of the most expensive arithmetic units to be efficiently reused.

In the diagram showing the algorithm (FIG. 145), the symmetry between the upper half and the lower half is evident in the middle part. The last column of the adder and the subtractor also has a symmetrical part, and the adder and the subtractor can be combined at a relatively low price (four adders / subtractors have four adders and four Considerably smaller than a subtractor).

Note that all outputs of the one-dimensional transform are approximated by 〓2. This means that the last two-dimensional answer is approximated by two. This can be easily corrected in the final saturation and shifting rounding stage.

The illustrated algorithm was coded in double precision floating point C, and the results were compared (using explicit matrix multiplication) to a reference IDCT. The next stage is used to encode a bit-exact integer version of the algorithm in C (no timing information is included), which verifies the performance and accuracy of the algorithm as it will be implemented on silicon Could have been used to Acceptable conversion errors are described in As specified in the H.261 standard, this method is used to implement a bit accurate model and measure the reported accuracy.

FIG. 146 shows the overall IDCT structure in a way that illustrates the commonality between the upper and lower sections, and also shows the points where intermediate results need to be stored. The circuit is time division multiplexed so that the upper and lower sections are calculated separately.

[1659] B. 9.7 "IDCT Transform Structure" As mentioned above, the IDCT algorithm is optimized for efficient structure. The key features of the resulting structure are as follows: significant reuse of expensive arithmetic operations; a small number of multipliers, all of which are constant rather than versatile (reducing multiplier size, Eliminates the need for coefficient storage) Fewer latches, slightly required to pipeline structures Pipelined operations are arranged so that only one decomposition operation is required per pipeline stage • Can be arranged to produce results in natural order • No complex crossbar switching or significant multiplexing (both are expensive in the final implementation) • Two carry-save operations (one add, 1
Advantages derived from the decomposition result to eliminate the (subtraction) one: A structure that allows each stage to take four clock cycles, thus eliminating the need for very fast (large) arithmetic operations. A structure that would support much faster operation than the current 30 MHz pixel clock operation by simply changing the decomposition operation from a slow ripple carry to a large and fast carry look ahead version. Since decomposing operations require the largest part of the time required at each stage, speeding up only these operations has a significant effect on the overall operation speed, while increasing the overall size of the transform Relatively small. Furthermore, an increase in speed can also be achieved by increasing the depth of the pipe lining.

The control of the conversion data flow is very clear and efficient.

[1661] Diagram of one-dimensional conversion fine structure (FIG. 150)
Shows how the algorithm maps to a small set of hardware resources to achieve the required performance. Control of this structure is achieved by adapting the "control shift register" to the data flow pipeline. This control is clear to the design and efficient in silicon layout.

The control signal (lat) designated on FIG.
ch, sel by, etc.) are various enable signals used to control the latch, through which the signals flow. The clock signal for the latch is not shown.

While the transform structure minimizes the transform size,
Some implementation details are important in terms of being able to meet the required accuracy standards. Commonly used techniques fall into two main classes.

By maintaining the fixed point positions individually, maintaining the maximum dynamic range with a fixed word width in each intermediate state.

Use of the statistical definition of the accuracy requirement to achieve accuracy through the selection of arithmetic operations (rather than simply increasing the word width of the entire transform).

An obvious way to design a transform would consist of simply running a fixed point with a fixed word width large enough to achieve accuracy. Unfortunately, this approach results in a larger word width and therefore a large conversion. The approach used in the present invention is to maximize the dynamic range available for a particular intermediate value,
Allow the fixed-point position to change through the conversion to achieve the maximum possible accuracy.

As the available results are specified statistically, selective adjustments can be made to any intermediate values to improve overall accuracy. The adjustment chosen is just an operation of the LSB calculation, which is almost inexpensive. An alternative to this technique is to increase the word width, but at a significant cost. The adjustment is to effectively weight the result in a given direction if the end result has previously been found to be in the opposite direction. By adjusting the fractional parts of the results, the overall average of these results can be effectively shifted.

1668. 9.8 Description of the IDCT block diagram The IDCT block diagram shows all the blocks involved in the processing of the token stream. This diagram, FIG. 147, does not show the clocking, test and microprocessor access, and event mechanisms in detail. The snorper blocks used to provide test access are not shown in the diagram.

B.1669. 9.8.1 Data Error Checker The first block is a data error checker and collector, called a decheck that selects / creates a 12-bit wide token stream, analyzes this stream, and checks for data tokens. All other tokens are ignored and sent directly. The check performed is performed for data tokens with an extension number not equal to 64. Possible error is significant (deficient)
(<64 extension), i dct too few even
t and supernumerary (excess) (> 64)
Extension), referred to as an idct to many event. Such errors are signaled by standard event mechanisms, but blocks also attempt simple error recovery by manipulating the token stream. In the case of a missing error, the data token is padded with "0" value extensions (stop accepting inputs and perform insertions), making up the exact 64 extensions. In case of excess error, the extension bit is forced to "0" for the 64th extension and all extra extensions are removed from the token stream.

[1670] B. 9.8.2 "Inverse zigzag" The next block of the spatial decoder is the inverse zigzag RAM, iz
z, which also selects / creates a 12 bit wide token stream. As with all other blocks, the stream is analyzed, but only data tokens are recognized.
All other tokens are sent unchanged. A data token is also sent, but the extension order is changed. This block relies on accurate data tokens (ie, only 64 extensions). If this is not true, no operation is specified. The rearrangement is performed according to a standard inverse zigzag pattern and by default to provide horizontally scanned data at the IDCT output. It is also possible to change the ordering to provide a vertically scanned output. Standard IZ
In addition to Z-ordering, this block performs an extra relocation of each 8-word row. This is done because of the special requirements of the IDCT one-dimensional transform block, (0,1,2,
Instead of the order 3, 4, 5, 6, 7), (1,
3,5,7,0,2,4,6).

[1671] B. 9.8.3 “Input Formatting Unit” The next block is the input formatting unit, ip fm
t, which forms the data input for the first dimension of the IDCT transform. This block has a 12 bit wide token stream input and a 22 bit wide token stream output. Data token is IDCT conversion standard 22
To move the integer part to the correct validity in the bit-width word, it is shifted left and the fraction part is set to zero. This means that there is a 10-bit fraction at this point. All other tokens are not shifted,
The extra unused bits are simply set to zero.

[1672] B. 9.8.4 "One-dimensional transformation-first
The next block shown is the first one-dimensional IDCT transform block, oned. It inputs / outputs a 22 bit wide token stream, and the stream is analyzed and data tokens are recognized as usual . All other tokens are sent unchanged. The data token passes through a pipelined data path that performs a one-dimensional implementation of an 8x8 inverse discrete cosine transform.
At the output of the first dimension, there are 7 bit fractions in the data word. All other tokens simply fit the data conversion latency and pass through a simple shift register data path that is recombined into a token stream before output.

[1673] B. 9.8.5 Transpose RAM The transpose RAMtram is similar in many ways to the inverse zigzag RAM in the way it processes the token stream. The width of the token being processed (22 bits) and the relocation performed are different, but otherwise behave the same and actually share much of its control logic. Again, the row (Row) is the row (Row) of the column (Column ).
With the basic swapping to, it is additionally rearranged for the next IDCT dimension requirement.

[1679] B. 9.8.6 "One Dimension Transform-Second Dimension" The next block shown is another example of a one dimensional IDCT transform block, which is the same in all aspects as the first dimension. The output of this dimension has a 4-bit fraction. B. 9.8.7 "Round and saturation" The round saturation block, ras, selects a 22-bit wide token stream containing a data extension in 22-bit fixed-point format and outputs a 9-bit wide token stream, in which case the data The extension is rounded to an integer (towards + ve infinity), saturated to a 9-bit two's complement representation, and all other tokens are sent directly.

B.1675 9.9 "Block hardware description" 9.9.1 "Standard block structure" For all blocks processing the token stream, there is a standard conceptual structure as shown in FIG.
This separates the two-wire interface latch from the section that performs the operation of the token stream. This structural variation includes extra internal blocks (RA
M core). In some of the blocks shown, the structure is not very clear in the schematic diagram (even though it still exists) due to the requirement that all "datapath" logic be grouped together, Separate this from all standard cell logic.
In the case of a very simple block such as ras, the latched outaccept is directly input without logical operation.
Can be placed on a wire latch.

B. 1676 9.9.2 "Decheck-Data Error Checking / Recovery" The first block in the token stream performs data checking and correction as specified in the block diagram perspective section. The detected error is handled by a standard event mechanism, which can be masked to the event, and the block can either continue with the recovery procedure when the error is detected, or stop depending on the event mask status. Since the IDCT should not see the incorrect data token, the recovery it attempts is only a fairly simple attempt to include what might be a serious problem.

This block is two stages deep in the pipeline and runs completely in zcells. Input 2-wire interface latch is "front"
Type, and when this block (before the IDCT) is on a different power supply than the one before it, so that all inputs can reach the transistor gates for safe operation It means to do. This block works by analyzing the token stream and sending non-data tokens directly. When a data token is found, counting starts with the extension number found after the header. When the extension bit is found to be "0" when the count is not 63, an error signal is generated (it goes to the event logic) and
Dech depends on the state of the mask bit for the event
Eck is stopped (i.e. no longer accepts input or emits output) or initiates error recovery. The recovery mechanism for the differential error uses a counter to control the insertion of the correct extension number into the token stream (the value inserted is always "0"). Obviously, the input is not accepted, while the insertion continues. If the extension bit of the 64th extension is not found to be "0", a supernumerary error is issued and the data token is completed by forcing the extension bit to "0" and the extension bit set to "1". All subsequent words with are removed from the token stream by continuing to accept data but invalidating the output.

[1678] The two error signals are not (block is not if stopped) permanent, i.e. the error signal, from the point where the error is detected, until the recovery is complete, only remain active. This is one complete cycle of minimum, Ru can survive forever in the case of excessive data token to infinity.

[1679] B. 9.9.3 "Izz and tram-R
Relocation of AM "izz (inverted zigzag RAM) and tram (transposed RA)
M) perform the same variation of the function and have more similarities than differences, and are considered together here. These blocks choose a token stream,
Relocate data token extensions while sending all other tokens unchanged. Although the expansion width and the relocation sequence processed are different, the large section of control logic for each RAM is the same and is actually organized into "common control" blocks illustrated in the schematic for each RAM. . Since width differences have no effect on this control section, it is only necessary to use a different "sequence address generator" for each RAM, with a RAM core and a two-wire interface block of appropriate width. is there.

[1680] The overall behavior of each RAM is essentially a FIFO
Same as O. This is true at the token level, and special modifications to the output order are made for the expansion words of the data token. FIFO
Has a depth of 128 stages. This is necessary to meet the requirement for 30 MHz that can be sustained through the system since the output of the FIFO is supported after the start of output of the data token is detected. This is because the features of the relocation sequence used require that the complete 64 extension blocks be collected in the FIFO before relocation output can begin. More precisely, the required minimum number for the inverse zigzag and the transposition sequence is different, somewhat less than 64 in both cases. However, the complexity of controlling FIFOs with non-power lengths of two means that small savings in the RAM core will be more significant than the additional complexity of the required control logic. RAM core is one 30M
It is implemented in a design that allows reading and writing (to the same address or another address) in Hz cycles. This means that the RAM operates effectively with an internal 60 MHz cycle time. The relocation operation is in the range 0-63, but not in the natural order, but by generating a special sequence of read addresses (sequenceaddress g).
eneration is performed. The required sequence is specified by a standard zigzag sequence (for eight horizontal or vertical scannings) or by the required sequence for normal matrix transposition.
These standard sequences require the requirement to output each row in odd / even format (ie, (0,1,2,3,4,
(1, 3, 5, 7, 0, 2, 4,
6)) and then rearranged further.

The generation of the transposed address sequence is quite clear algorithmically. Direct transposition sequence generation simply requires separate generation of row and column addresses, both of which are performed by counters. The requirement of row relocation simply means that the row address is not generated by a natural counter, but rather by a simple special state machine.

The inverse zigzag sequence is not very clear because it occurs algorithmically. Because of this fact,
A small ROM is used to hold the full 64-bit value of the address, which is addressed with a row and column counter that can be swapped to change between horizontal and vertical scan modes. ROM-based generators are designed very quickly and also have the advantage that performing forward zigzag (ROM reprogramming) or adding other alternative sequences in the future is trivial.

[1683] B. 9.9.4 “Oned” —one-dimensional IDCT transformation This block has a pipeline depth of 20 stages, and the pipeline becomes rigid when stopped . This stiffness greatly simplifies the design and the depth of the pipeline is not very large, so it should not unduly affect the overall force and both dimensions take over RAM providing a certain amount of buffering .

The block follows the standard structure, but has separate paths internally for data token extensions (to be processed) and all other items to be sent unchanged. Note that the schematic is drawn in a special way. First, because of the requirement that all datapath logic be grouped together, and then, because of the requirement to enable automatically compiled code generation, which describes control logic at the top level.

The token is analyzed as usual, and then the data extensions and other values are each sent through two different parallel paths before being recombined at the multiplexer in front of the output 2-wire interface latch block. . A parallel path is required because values cannot be sent unchanged through the transformation data path. The latency of the transform data path is matched with a simple shift register to handle the rest of the token stream.

The oned control section needs to analyze the token stream and control token splitting and recombination. The other main sections control the conversion data path. The primary mechanism for controlling this data path is a control shift register that adapts the data path pipeline, and taps are removed to provide the necessary control signals for each stage of the data path pipeline.

The oned block has the requirement that it can only start a complete row of data extensions, ie, operations on groups of eight. Although it is not possible to handle invalid data (Gaps) in the middle of a row, in effect the operation of izz and trm guarantees that a complete data block is output as an uninterrupted sequence of 64 valid extension values. I do.

B.1688. 9.9.4.1 “Transform Data Path” The fine structure of the transform data path, t dp, was previously illustrated in FIG. Some details (such as clocking,
Note that shifts are not shown. However, the diagram illustrates how the datapath operates on four values simultaneously at any stage of the pipeline. The basic datapath substructure, the three main sections (eg, pre-common, common, and post-common), can also be seen as computing and latching resources are needed. The nominated control signal is an enable for the pipeline latch (and the add / subtract selector) which is ordered in decoding the control shift register state. Note that each pipeline stage is actually four clock cycles in length.

There are many latch stages in the transform datapath that need to collect inputs, store intermediate results in a pipeline, and order the outputs. Some latch Mack single type (muxing type), i.e. they can be loaded from a number of sources than one conditionally. All latches are of the enabling type,
That is, there are separate clock and enable inputs. This means that it is easier to generate the enable signal at the right time, rather than having to consider the problem of asymmetry that would occur when the created clock scheme is applied.

The main operation elements required are as follows.

[1691] Many fixed coefficient multipliers (Carry-save output)-Carry-save adder-Carry-save subtractor-Decomposition adder-Decomposition adder / subtractor All operations are performed in two's complement notation. This is the normal (disassembled) or carry-save form (ie, two numbers whose sum represents the actual value)
It may be. All numbers are broken down before memory, which is the most expensive operation in terms of time,
Only one disassembly operation is performed per pipeline stage. The disassembly operation is performed here, and all operations use simple ripple carry.
This means that the decomposer is very small but relatively slow. Since the decomposition dominate the overall time at each stage, there is clearly an opportunity to use a fast decomposition arithmetic unit to speed up the overall transformation.

[1692] B. 9.9.5 - The "" Ras "rounding and saturation" present invention, ras blocks necessary second dimension select a fixed point numbers 22 bits from the output of oned, it was these Re et accurately rounded saturated fulfill task of obtaining conversion into a 9-bit coded integer result. This block further performs the inherent required divide by 4 operation in the scheme (2 / N term), and further divides by 2 required to compensate for = 2 prescaling performed in each of the two dimensions. Perform This divide-by-8 operation is interpreted as three bits left beyond the expected fixed-point position,
This implies that the result is processed as a 15-bit integer representation and a 7-bit fraction (rather than a 4-bit fraction). The rounding mode implemented is "round to positive infinity", that is, adding 1 to a fraction of exactly 0.5. This is basically done because this is the easiest rounding mode to execute. After the rounding (conditional increment of the integer part) is completed, the 9-bit signed result is checked to see if it needs to be saturated to the maximum or minimum value within this range . This is done by checking the increments performed with the high order bits of the original integer value .

As usual, the token stream is analyzed and round and saturation operations are applied only to data token extension values. The block has a pipeline with a depth of 2 stages and is completely z
Executed in cells.

[1694] B. 9.9.6 “Idctsels −
IDCT Register Select Decoder "This block is a simple decoder that decodes the four microprocessor interface address lines and sel test input into select lines (snooper and RAM) for individual block test access.
The block is composed of only zcells combination logic. The select to be decoded is shown in Table 227.

[1695]

[Table 225]

[1696]

[Table 226] B. 9.9.7 "Idctregs-IDCT Control Registers and Events" This block of the invention provides data under and over errors,
And an example of a standard event logic block that processes a single memory mapped bit, vscan, that can be used to make an izz relocation change so that the IDCT output is scanned vertically. This bit is reset to the value "0", that is, the default mode is horizontally scanned out. The two possible events are ORed together to form an idcevent signal that can be used as an interrupt. For register and event addresses and bit locations, see Section B.3. See 9.10.

[1697] B. 9.9.8 "Clock generator" Two "standard" types (clkge) in the IDCT
n) clock generator is used. This is implemented so that there are two separate scan paths. The clock generators are called idctcga and idctcgb. Functionally, the only difference is that idctcgb is nottrstl
There is no need to generate a signal. The amount of buffering for each of the clock and reset outputs in the two clock generators is individually adjusted to match the actual load driven by each clock or reset. The adapted load was actually measured from the gate and track capacitance of the final layout.

[1698] IDCT Top Level Block Pl
The advantage when ace and Route (BPR) is performed is that these tracks carry active current, so the heavier loaded clocks (ph0b and ph1b)
Derived from the ability of the interactive global routing feature to increase the track width of the first section of the clock distribution tree for the system.

[1699] B. 9.9.9 JTAG control block Since the IDCT has two separate scan chains and two clock generators, the standard JTAG control block, j
There are two cases of the spectrum. These connect the test port with the two scan paths.

[1700] B. 9.10 Event and Control Register The IDCT can generate two events,
It has two control bits. The two events are d before the IDCT if an incorrect data token is detected.
dct t generated by the check block
oo few and Id too many
event. One control bit is vscan, which is set when it is necessary to operate the IDCT with a vertically scanned output. Therefore, this bit is
Control the block. All events logic and MEMO <br/> Lee map control bit is placed in the block Idctregs.

From an IDCT point of view, these registers are located at the following locations: The tristate i / o wires are n derrd and n serrd is used to read and write these locations as appropriate.

[1702]

[Table 227]

[1703]

[Table 228] B. 9.11 "Execution" 9.11.1 "Logic Design Approach" In the design of all IDCT blocks, according to the invention, there is a unified and simple logic design strategy,
That would have meant that it was possible to make a "safe" design in a quick and clear way. For many control logics, a simple scheme using only master-slave was adopted. Only the asynchronous set / reset input was connected to the correct system reset. It might have been possible to provide a clever non-standard circuit configuration to perform the same function more efficiently,
This scheme has the following advantages:

[1704]-Conceptually simple-Easy to design-Operation speed is quite obvious (latch → logic →
Latch → see logic style design), follow automatic analysis ・ Glitch is not a problem (see SR latch) ・ Use only system reset for initial setting ・ Enable scan path to work properly ・ Automatically follow There are a number of locations where transparent d-type latches that allow C code generation have been used, and are described below.

[1705] B. 9.11.1.1 Two-wire interface latch The standard block structure uses latches for input and output two-wire interfaces. There is no logic between the output 2-wire latch and the subsequent input 2-wire latch.

[1706] B. 9.11.1.2 ROM Interface Due to the timing requirements of the ROM circuit, latches are used in the IZZ sequence generator at the output of the ROM.

[1707] B. 9.11.3. Conversion Datapath and Control Shift Registers It is possible to implement any pipeline storage stage as a complete master-slave device, but use latches because of the amount of storage required There are significant savings gained by doing so. However, this scheme requires the user to consider several factors.

The control shift register is used as an enable, so control signals for both phases must be created (ie, the use of latches in this shift register). Timing analysis is complicated by the use of latches. T postc will no longer automatically produce edited code because one latch outputs to another latch in the same phase (this is not a circuit problem due to the timing of the enable). The area saved by the use of latches makes it valuable to accept these elements in the present invention.

[1709] 9.11.1.4 Microprocessor interface Due to the nature of this interface, there is a requirement for latches (and resynchronizers) in the event and register block idctregs and keyhole logic for the RAM core.

[1710] B. 9.11.1.5 "JTAG test control" These standard blocks use latches.

B. [1711] 9.11.2 "Circuit Design Issues" Apart from the work done in the design of library cells used in IDCT designs (standard cells, data path libraries, RAM, ROM, etc.)
There are no requirements for transistor level circuit design in IDCT. Circuit simulation (using Hspice) is performed from among several known critical paths in the transformation data path, and Hspice further evaluates the results of the critical path analysis (CPA) tool for paths near the maximum allowed length. It was also used to confirm.

The IDCT is completely static in normal operation (ie we can stop the system clock indefinitely), but when the test clock is stopped (or very slow) Note that there is a dynamic node in the scannable latch that will fade. Due to the non-regenerative nature of some nodes exhibiting a Vt drop (eg, max output), the IDCT will not be "micro-power" when static.

[1713] B. 9.11.3 “Layout Approach” The overall approach to layout implementation of the present invention is:
The use of BPR (some manual interference) to lay out a complete IDCT composed of many zcells and a few macroblocks. These macroblocks were either manually edited layouts (eg, RAM, ROM, clock generator, datapath) or, in the case of oned blocks, additional z
It was built using BPR from cell and datapath.

The datapath was built from KDPRIB cells. In addition, a locally limited layout variation of the kdpriv cell was defined and used when it was found to provide a valuable size benefit. Each oned block, oned
The data path used in d is
Rukani the largest first element, considerable effort has been expended to optimize the size (height) of this datapath.

The organization of the transform data path, t dp, is rather crucial, because the exact ordering of the elements in the data path affects the way interconnects are handled. Minimize the number of overs (vertical wires that do not connect to sub-blocks) that occur at the most dense points because there is a maximum allowed value (ideally 8, very inconvenient but 10 is possible) is important. The datapath is logically split into three main subsections, thus implementing the datapath layout. In each subsection there are currently four parallel data flows (which are combined at various points)
Thus, there are many ways to organize the data flow (and the location of all elements) within each subsection. Ordering of blocks within each subsection,
And the assignment of the logical buses to the physical bus pitch was carefully calculated before the layout started to allow achieving a layout that would be connected correctly.

[1716] B. 9.12 "Match" IDCT matches were made at many levels, from the top-level match of the algorithm to the final layout check.

The initial work on the transform structure was done in C and a full precision and bit exact integer model was developed. H. Various tests were performed on the bit-accurate model to verify compliance with the H.261 accuracy standard and measure the dynamic range of calculations within the transform structure.

By writing M in many cases, the design has advanced the operation of the sub-block (eg, control of data path and RAM). Such an explanation is provided before moving on to the design of the schematic description of the block, Lsim
Was simulated. In some cases (for example, RA
The M) clock generator) Operation was also used for the simulation of the top level.

The strategy for performing logic simulation was to simulate schematics for anything that would simulate properly at that level. Low-level library cells (ie, zce
ll and kdlib) were primarily simulated using their operational description, as the result is a much smaller and faster simulation. In addition, operational library cells provide a feature of timing checking that can highlight structural issues in certain circuits. As a reliability check, a simulation was performed using the transistor description of the library cell. All logic simulations are performed using the zero delay method.
Therefore, it was intended to verify functional performance.
Verification of real-time behavior was performed using other techniques.

As a partial comparison of timing performance, (R
Lsim switch-level simulations were performed (using C Timing mode), but still provide checks for other potential transistor-level issues (eg, glitch sensitive circuits).

The main collation techniques for checking timing problems are CPA tools, path for datechk
Was the use of options. This is used to identify longer signal paths (some were already known), and to check CPA analysis in certain critical cases.
spice was used.

Since the bulk of the IDCT action is trained by the flow of tokens through the device, most L
Sim simulation was performed using the standard source → block → sink methodology. Additional simulations are also needed to test features accessed through the microprocessor interface (configuration, events and test logic) and test features accessed via JTAG / scan.

Edited code simulation can be easily accomplished by one of ordinary skill in the art for the full IDCT, again using many of the same source-to-block-to-sink methods and the same token streams used in Lsim matching.

[1724] B. 9.13 Testing and test support This section deals with the mechanisms provided for testing and for analyzing how each block is tested.

The three mechanisms provided for test access are: microprocessor access to the RAM core microprocessor access to the snooper block scan path access to the control and data path logic For the IDCT There are two "Snowpa" blocks and one "Super Snopa" block. FIG. 149 shows the location of the snooper block and the test access of another microprocessor.

Using these and two RAM blocks,
It is possible to isolate each major block for the purpose of testing their behavior on the token flow.
With microprocessor access, it is possible to control the token input for any block and observe the token port output of that block in isolation. In addition, there are two separate scan paths that go through (almost) all flip-flops and latches in the control section of each block, and in the case of the oned converted data path pipeline, a part of the data path latch. The two scan paths are labeled a and b, the former moving from the decheck block to the ipfmt block, and the latter moving from the first oned block to ra.
Move to s block.

Access to the snooper is possible by accessing the appropriate memory-mapped location in the usual manner. (Ramt as appropriate
The same is true for the RAM core (using the est input). The scan path is accessed through the JTAG port in the usual way.

Each block is discussed in connection with various test questions.

[1729] B. 9.13.1 “Decheck” This block has a standard structure (see FIG. 148) with two latches for the input and output two-wire interface surrounding the processing block. As usual , these two
Since wire latches simply pass data whenever enabled and have no logic depth to be tested,
No scanning is performed on the two-wire latch. In this block, the "control" section consists of a one-stage pipeline of zcell all above scanpath a. The logic in the control section is relatively simple, and most of the complex paths are probably in generating a data extension count where a 6-bit incrementer is used.

B.1730 9.13.2 "Izz" This block is a variant of the standard structure and includes a RAM core block added to the 2-wire interface latch and control section. The control section is implemented with a zcell and a small ROM used for address sequence generation. All zcells are on scan path a and have access to ROM addresses and data through the zcell latch. Further, there is logic, for example, logic for the generation of numbers plus the ability to increment or decrement. In addition, there is a 7-bit full adder used for read address generation. The RAM core is accessible via a microprocessor interface through a keyhole register. Table 225,
See Table 226.

[1731] B. 9.13.3 "lp fmt" This block also has a standard structure. The control logic is implemented with fairly simple zcell logic (all on scan path a), but since the logic here is very shallow and simple, data latching and shifting / maxing is straightforward. Performed in the data path without any significant access.

[1732] B. 9.13.4 “Oned” Again, this block follows a standard structure and is divided into random logic and datapath sections. zcell
The logic is relatively straightforward, with all zcells on scan path a. The control signal for the conversion pipeline datapath is derived from a long shift register consisting of a zcell latch on the scanpath. In addition, some pipeline latches are on the scan path, because the logic between some stages of the pipeline (eg, multipliers and adders) is quite deep. Non-data tokens are sent along the shift register and implemented as a data path, with no test access to any of these stages.

[1733] 9.13.5 "Tram '" This block is very similar to the izz block. However, in this case, no ROM is used in address sequence address generation. This is performed algorithmically. All zcell control states are on data path b.

B.1733 9.13.6 "Rras'" This block follows the standard structure and is executed entirely in zcell. The most complex logic function is the 8-bit incrementer used during rounding up. All other logic is fairly simple. All states are on scan path b.

[1735] B. 9.13.7 "Other top-level blocks" There are several other blocks that appear at the top level of the IDCT. The snooper is obviously part of the test access logic as well as the JTAG control block.
In addition, there are two clock generators without special test access (although they support various test features). Block idctsels is a combination z for decoding microprocessor addresses.
cell logic, block idctregs is a microprocessor accessible event, and IDC
Includes T-related control bits.

[1736] Section B. 10 "Introduction" 10.1 “Prospect of temporal decoder” FIG. 151 shows the internal structure of the temporal decoder according to the present invention.

All data flow between chip blocks (and many data flows within blocks) is controlled by a two-wire interface (see technical reference and section for details) and each arrow in FIG. Represents a two-wire interface. The incoming token stream passes through an input interface that synchronizes data from the external system clock to an internal clock derived from the phase lock loop (ph0 / ph1). The token stream is then split into two passes via the top fork; one stream goes to the address generator and the other stream goes to the 256 word FIFO. The FIFO buffers the data while the data from the previous I or P frame is pulled from the DRAM and processed in a prediction filter before being added to the input error data from the spatial decoder in the prediction adders (P and B frames). Is done. During MPEG decoding, frame relocation data must be derived for I and P frames so that the output frames are in the correct order. The rearranged data is inserted into the stream in the read ladder block.

The address generator generates separate addresses for forward and backward prediction, relocation, read and write back, and the data to be written back is split from the stream in the write ladder block. Finally, the data is resynchronized to the external clock in the output interface block.

[1739] All major blocks in the temporal decoder are connected to an internal microprocessor interface (UPI) bus. It is derived from the external microprocessor interface (MPI) in the microprocessor interface block. This block has an address decode for the various blocks in the chip associated with it. Also associated with the microprocessor interface is the event logic.

The remaining logic of the temporal decoder is basically test related. First, IEEE 1149.1 (JT
AG) interface provides an interface to the internal scan path as well as to the JTAG boundary scan feature. Second, during the test mode,
A two-wire interface stage that allows intrusive access to the data flow via the microprocessor interface is included at strategic points in the pipeline structure.

[1741] Section B. 11 "Clocking,
Testing and Related Issues "B. 11.1 "Clock Styles" Before considering the individual functional blocks in a chip, it may be useful to recognize the clock styles in the chip and their relationships.

During normal operation, most blocks of the chip move in synchronization with the signal pllsysclk from the phase lock loop (PLL). The exception to this is the DRAM interface, whose timing is governed by the need to synchronize to the iftime sub-block, which sub-block is controlled by the DRAM control signals (notwe, notoe, notcas, notra).
s). The core of this block is two phases
Clocked by non-overlapping clocks clk0 and clk1, which are PLL cki0, cki
1 and derived from a quadrature 2 phase clock supplied separately from clkg0 and ckg1.

Clk0, clk1 Since the DRAM interface clock is synchronized with the clock in the remaining chip, the interface between the DRAM interface and the remaining chip (as far as practically possible) is used to eliminate the possibility of metastable behavior. Countermeasures have been taken. Synchronization occurs in two areas: at the output interface of the address generator (addrgen / predre
ad / psgsync, addrgen / ip wrt
2 / sync18 and addrgen / iprd2 / s
ync18), and in the block that controls the "swinging" of the swing buffer RAM in the DRAM interface (see section on DRAM interface). In each case, the synchronization process is achieved by three series metastable hard flip-flops. Note that this is clk0 / cl
This means that k1 is used in the output stage of the address generator.

In addition to these fully synchronized clock schemes, there are a number of separate clock generators that generate a two-phase non-overlapping clock (ph0, ph1) from pllsysclk. Address generator,
The prediction filter and the DRAM interface each have their own clock generator; the remaining chips are moved away from the common clock generator. There are two parts to this reason. First, it reduces the capacitive load on individual clock generators, allowing for smaller clock drivers and reduced clock routing width.
Second, each scan path is controlled by a clock generator, thus increasing the number of clock generators allows the use of shorter scan paths.

It is necessary to resynchronize signals that are moved across these clock style boundaries. This is because insignificant skew between non-overlapping clocks derived from different clock generators would mean that an underlap occurred at the interface. Circuits built into each "snooper" block (see section B.11.4) ensure that this does not occur, and the snooper block is an address generator that is resynchronized in the token decode block. Except at the front of the clock.

[1746] B. 11.2 Clock Control Each standard clock generator generates a number of different clocks that allow it to operate in normal mode and scan test mode. The control of the clock in scan test mode is described in detail in another section, but it should be noted that the clock generators (tph0, tph0)
Some of the clocks emitted by ph1, tckm, tcks) are not normally added to the primitive symbols in the schematic.
This is because the scan path is automatically created by a post processor that accurately connects these clocks. From a functional point of view, the fact that the post-processor has connected a different clock than the one shown in the schematic can be neglected; the act is the same.

During normal operation, the master clock can be derived in many different ways. Table 2
Reference numeral 29 denotes a state in which various modes can be selected depending on the state of the pin "pllselect" and the override state.

[1748]

[Table 229] B. 11.3 "2-wire interface" The overall functionality of the 2-wire interface is described in detail in the technical reference book. However, the two-wire interface is used for communication between all blocks in the temporal decoder, most blocks are made up of many pipeline stages, all of which are two-wire interface stages. Therefore, it is important to understand the internal implementation of the two-wire interface in order to be able to interpret many schematics. Generally, these internal pipeline stages are configured as shown in FIG.

FIG. 152 shows a latch-logic-latch display, which is a commonly used arrangement. However, when many stages are put together, it is useful to think of a "stage" as latch-latch-logic (a mode well known to many engineers). The use of a latch-logic-latch arrangement means that all inter-block communication, whether sending or receiving blocks,
It can be a latch-to-latch without any intervening logic.

Referring again to FIG. 152, the logic block is removed and the data and valid signal are directly connected between the latches, and out valid and out accept are gated in the same manner as in valid which is latched directly to the NOR gate on the input. Is connected to the accept latch to provide a simple two-wire interface
O stage can be constructed. The data and valid signals propagate when the next corresponding accept signal is high. Logical and in valid in out acceptreg In the illustrated method
By taking the logical sum , the data is out accept
Even if reg is low, it is accepted if in valid is low. In this way, whenever a stall (accepting a low signal) occurs, gaps (data with low valid bits) are removed from the pipeline.

As shown in FIG. 152, a logic block is inserted, and in accept and out valid can depend on data or the state of the block. In the arrangement shown, every state in the block is ph
It is standard to be kept in a master-slave device with a master enabled by 1 and a slave enabled by ph0.

B. [1752] 11.4 "Snooper Block" The snooper block allows access to the data stream via a microprocessor interface at various points within the semiconductor chip. There are two types of snooper blocks. Ordinary snoopers can only be accessed in a test mode where the clock can be controlled directly. The "super snooper" is accessible while the clock is running and includes circuitry that synchronizes asynchronous data from the microprocessor bus to the internal chip clock. Table 230 lists the location and type of all snoopers in the temporal decoder.

[1753]

[Table 230] Details on the use of both snoopers are provided in the test section. Details of the operation of the JTAG interface are described in the JTAG document.

[1754] Section B. 12 “Function block” 12.1 Top Fork According to the invention, the top fork performs two different functions. First, the data stream is split into two different streams: one for the address generator, one for the FIFO, and second, the means for starting and stopping the chips so that the chips can be located. Provide a means.

The aspect of the fork portion of the component is very simple. The same data is displayed in the address generator and in the FIFO and must be accepted by both blocks before the accept is sent back to the previous stage. Thus, the vari of the two branches of the fork
ds is dependent on accepts from other branches. If the chip is in a halt state, the valid for both branches
ds is kept low. Until the arrangement bit is set to high , the semiconductor chip has a low in accept.
In a state of being kept in, power up (power up,
Power increase) . This ensures that no data is accepted until the user places the chip. If the user needs to place the chip at another time, the user must set the placement bit and wait until the chip has completed the current stream. The stopping process is as follows: 1) If the configuration bit is set, no data is accepted after the flash token is detected by the top fork.

2) When the flush token reaches the read ladder, the chip will have completed processing the stream. This causes the signal seq done to go high.

3) When seq_done goes high, set an event bit that can be read by the microprocessor. The event signal may be masked by the event block.

[1758] B. 12.2 Address Generator In the present invention, the address generator (addrgen) is responsible for counting the number of blocks in a frame and generating the correct address sequence for DRAM data transmission. The input of the address generator is a token stream from the token input port (via the top fork) and its output to the DRAM interface consists of the address and other information controlled by the request / acknowledge protocol.

The basic sections of the address generator are as follows: Token decode Block count and generation of DRAM block addresses Conversion of motion vector data to address offset Request and address generator for predictive transmission -Relocation read address generator-Write address generator B. 12.2.1 “Token Decode (tokde
c) "In the token decoder, tokens, frames, block information and motion vectors associated with the coding standard are decoded. The information extracted from the stream is stored in a series of registers, which
i. Detection of the data token header is signaled to the next block, enabling block counting and address generation. Nothing happens when running JPEG.

[1760] Token list to be decoded • Coding standard • Data • DEFINE MAX SAMPLING • DEFINE SAMPLING • HORIZONTAL MBS • MVD BACKWARDS • MVD FORWARDS • Picture start • Picture type • Prediction mode This block further combines information from the request generator. Control the toggling of the frame pointer to stall the input stream. When a new frame appears at the input (in the form of a picture start token), the stream is stalled, but the writeback or relocation read associated with the previous frame is incomplete.

[1761] B. 12.2.2 Macroblock Counter (mblkcntr) The macroblock counter of the present invention consists of four basic counters that point to the horizontal and vertical position of a macroblock within a frame. At the beginning of time and at the start of each picture, all counters are set to zero. When the data token header arrives, the counter is incremented and reset according to the token header and the color component number in the frame structure. This frame structure is described by the sampling register in the token decoder.

[1762] For a given color component, counting proceeds as follows. The horizontal block count is incremented for each new data token of the same component until the macroblock width is reached, and then reset. The vertical block count is incremented by this reset until the macroblock height is reached, and then reset. When this occurs, it waits for the next color component. Thus, this sequence is repeated for each of the components in the horizontal and vertical size of the macroblock—perhaps different for each component. If fewer blocks than expected are received for one component, the count will proceed to the next component without error.

If the color component of the data token is less than the expected value, the horizontal macroblock count is incremented. (This would also occur when more blocks than expected for a given color component appeared, since the counter expects a higher component index.) Reset when the picture width in the macroblock is reached. This reset causes the vertical macroblock count to be incremented.

[1764] Further, H. H.261 is capable of counting macroblocks in the CIF format. In this case, there is a special level of hierarchy between macroblocks and pictures called block groups. This is 11 macroblocks wide and 3 macroblocks deep, and a picture is always 2 groups wide. The token decoder derives the CIF bit from the picture type token and sends it to the macroblock counter, instructing it to count block groups. If the number of blocks per component is too low or too high, a reaction as described above will occur.

[1765] B. 12.2.3 “Block calculation (bl
kcalc) "block calculation converts the coordinates of a macroblock and macroblock in a block position coordinates for the block in the picture, i.e. collapse a hierarchy level (knockout)
I do. Of course, this must take into account the sampling rates of the different color components. B. 12.2.4 “Base block address (bsb
lkadr) "The information from blkcalc, along with the color component offset,
Used to calculate block addresses in the linear DRAM address space. In essence, for a given color component, the linear block address is the number of vertical blocks times the width of the picture plus the number of horizontal blocks. This is added to the color component offset to form the base block address.

[1766] B. 12.2.5 "vector offset" The motion vector information displayed by the token decoder is in the form of horizontal and vertical pixel offset coordinates. That is, for each of the forward and backward vectors, give the transposition of half a pixel from the block formed in the block in which it is predicted (x,
y). Note that these coordinates can be positive or negative. They are first approximated according to a sampling of each color component and used to form blocks and new pixel offset coordinates. FIG. 154 shows a block in which a shadow portion is being formed. The dotted outline is the block from which it is expected to come. The large arrows indicate the block offset-the horizontal and vertical vector to the DRAM block containing the origin of the prediction block, in this case (1, 4). The small arrow indicates the new pixel offset-the location of the predicted block origin within that DRAM block. 8 DRAM blocks
X8 bytes, so the pixel offset is (7,
It looks like 2).

The multiplier array vmarrla then converts the block vector offset to a linear vector offset. Pixel information is represented by (x, y) coordinates (pix inf
sent to the prediction request generator as o).

[1768] B. 12.2.6 “Prediction Request” The frame pointer, the base block address, and the vector offset are added to the DRAM (Inblka
Form the address derived from d3). If the pixel offset is 0, only one request is issued. If there is an offset in either the x or y dimension, two requests-the original block address, and either immediately right or directly below-
Is issued. If there are offsets in both x and y, then
Four requests are issued. The synchronization between the chip clock mode and the DRAM interface clock mode is the first.
(Inblkad3) and the state machine issuing the appropriate request. Thus, the state machine (psgstate) is clocked by the DRAM interface clock, and the scanned elements form part of the DRAM interface scan chain.

[1768] B. 12.2.7 “Relocation Read and Write Requests” Since no pixel offset is included here, each address is formed by adding the base block address to the associated frame pointer. Relocation reads use the same frame store because predictions and data are written back to other frame stores. Each block has a short FIFO to store the address because the transmission of read and write data tends to delay the predicted transmission at the corresponding address. (This is because the read / write data interacts with the stream along the chip data flow more than the prediction data.) Further, each block includes synchronization between the chip clock and the DRAM interface clock.

[1770] B. 12.2.8 “Offset” The DRAM is arranged as two frame stores, each containing three color components. The frame store pointer and the color component offset within each frame must be programmed via upi.

[1771] B. 12.2.9 "Snowpa" In the present invention, the snooper is arranged as follows: between blkcalc and bsblkadr-this interface uses horizontal and vertical block coordinates, appropriate color component offsets, and (for that component) ) Consists of the width of the picture in the block.

[1772] After bsblkadr-the base block address.

After vec pipe-linear block offset, prediction mode, color component and H.264 Pixel offset within the block, along with information about the H.261 operation.

After Inblkad3-As described in the "Predicted Request" section, the physical block address super snooper is used in the relocated read and write request generator for use during testing of the external DRAM. Is placed. See DRAM Interface section for details.

[1775] B. 12.2.10 "Scan" The addrgen block has its own scan chain and its clocking is controlled by its own clock generator (adclgen). Note that the request generator at the end of the block is within the DRAM interface clock format.

[1776] 12.3 “Prediction Filter” The overall structure of the prediction filter according to the present invention is shown in FIG. The forward and backward filters are the same and filter the MPEG forward / backward prediction block. H. In the H.261 mode, only the forward filter is used (the h261 on input of the backward filter should be permanently low because the H.261 stream does not include backward prediction). The overall prediction filter block consists of a two-wire interface stage pipeline.

[1777] B. 12.3.1 "Predictive Filters" Each predictive filter operates completely independently of the other predictive filters and processes the data as soon as valid data appears at its input. As can be seen from FIG. 156, the prediction filter consists of four separate blocks, two of which are the same. The operation of these blocks is described in MPEG and H.264. It would be better to describe it separately for the operation of H.261. H. 261 is the most complicated and will be described first.

B. [1778] 12.3.1.1 H.261 Operation The one-dimensional filter equation used is as follows: Fi = (xi + 1 + 2xi + xi-1) / 4 (i≤i≤6) Fi = xi (Others) I) This is applied to each row of the 8 × 8 block by the x prediction filter and to each column by the y prediction filter. The mechanism by which this is achieved is illustrated in FIG. 157, which basically represents a pfltldd schematic. The filter consists of three two-wire interface pipeline stages. For the first and last pixel of the row,
Registers A and C are reset, and data is stored in register B,
Pass D and F unchanged (the contents of B and D are added to 0). The control of Bx2 mux is set such that the output of register b is shifted left by one. This shifting is always shifted 1 in any event
In one place. Thus, all values are multiplied by 4 (and more later). For all other pixels, xi + 1 is loaded into register C, xi is loaded into register B, and xi-1 is loaded into register A. As can be seen from FIG. The H.261 filter expression is executed. Since vertical filtering is performed in the three horizontal groups (see note on dimension buffers below), there is no need to process the first and last pixels in a row separately. Control and counting of pixels in a row is performed by control logic associated with each one-dimensional filter. Note that the result is not divided by four. After horizontal and vertical filtering have been performed, the prediction filter adder (section
B. In the input of 12.4.2), a task of dividing by 16 (shifting right by 4) is performed. Registers DA, D
D and DF send control information to the pipeline. This is h2
Includes 61 on and last byte.

[1781] Among other blocks found in the prediction filter, the function of formatting is simply to ensure that the data is displayed in the x-filter in the correct order. As can be seen from the above, this simply requires a three-stage shift register, the first stage connected to the input of register C, the second stage to register B, and the third stage to register A. Connected.

[1780] Between the x and y filters, a dimension buffer buffers the data so that three groups of vertical pixels are displayed in the y-filter. Although these three groups are still processed horizontally, no transposition occurs in the prediction filter. Tables 231 and 232 show the sequence in which pixels are output from the dimension buffer in relation to FIG.

[1781]

[Table 231]

[1782]

[Table 232] B. 12.3.1.2 MPEG Operation During the MPEG operation, the prediction filter performs a simple half-pixel interpolation: Fi = (xi + xi + 1) / 2 (0≤i≤8, half pixel) Fi = xi (0 ≦ i ≦ 7, integer pixel) h261 on If input is not low, this is the default filter operation. If the signal dim to the one-dimensional filter is low, integer pixel interpolation will be performed. Thus, if h261 on is low and xdim and ydim are low, all pixels are sent directly without filtering. Dim to one-dimensional filter
It is a clear requirement that the row (or column) be 8 pixels wide (or more) when the signal is high. This is summarized in Table 233.

[1783]

[Table 233] In FIG. 157, “One-dimensional prediction filter”, the operation of the one-dimensional filter MPEG as well as for the first and last pixel in the H.261 row
For inter-pixel. For MPEG half-pixel operation, register A is permanently reset and the output of register C is shifted left by one (the output of register B is always shifted left by one). Thus, after two clocks, register F stores (2B + 2
C), which is four times the required result, which is processed at the input of the prediction filter adder where the number passed by the x and y filters is shifted right by four.

The functions of the formatting and the dimension buffer are simple in MPEG. Formatting must collect two valid pixels and send them to the x-filter for half-pixel interpolation; the dimension buffer need only buffer one row. It is worth noting that after the data has passed the x-filter, there are only eight pixels in the row as the filtering operation converts the 9-pixel rows to 8-pixel rows. "Lost" pixels are replaced by gaps in the data stream. When performing half-pixel interpolation, the x-filter at the end of each row (8
Insert a gap) (after 8 pixels); the y-filter inserts 8 gaps at the end of the block. This means that at the end of the block, 8 or 9 gap groups will contain a data token header and a FIFO.
Important because it aligns with other tokens between data tokens in the incoming stream. This minimizes the worst case through chip that occurs when a 9x9 block is filtered.

[1785] B. 12.3.2 Predictive Filter Adder During MPEG operations, predictions are formed using early pictures, late pictures, or an average of both. Prediction formed from early frames is called forward prediction, and prediction formed from late frames is called backward prediction. Prediction filter adder (pfa
The function of dd) is to determine which filtered prediction value to use (forward, backward or both) and whether to pass forward or backward filtered prediction or the average of both. (Rounded toward positive infinity).

The prediction mode can only be changed between blocks, ie at power-up, or after the fwd 1st byte and / or bwd 1st byte signals indicating the last byte of the current prediction block have been activated. If the current block is forward predicted, only the fwd 1st byte is examined.
If it is backward prediction, bwd 1st
Only bytes are examined. If it is a bidirectional prediction, fwd 1st byte and bwd 1
The st byte is checked.

The signals fwd on and bwd on determine which prediction to use. At any time, both of these signals may be active or both may not be active. If there is a gap at start-up or when there is no valid data at the input of the block, the block enters the state when neither signal is active.

[1790] Two criteria are used to determine the prediction mode for the next block: a signal fwd indicating which of the forward or backward blocks is part of the bidirectional prediction pair. imat
win and bwd ima twin and bus fwd
p num [1: 0] and bwd p num [1:
0]. These buses contain a number that increments by one for each new prediction block or prediction block pair. These blocks are needed, for example, if there are two forward prediction blocks followed by a bidirectional prediction block, so that the input of the prediction filter adder arrives before the second forward prediction block. This is because the DRAM interface can retrieve the backward block of the bidirectional prediction long enough. Similarly, the backward and forward predictions of other sequences can also leave the sequence at the input of the prediction filter adder. Thus, the next prediction mode is determined as follows: 1) Valid forward data is present and fwd ima
If twin is high, the block stalls until valid backward data arrives with the bwd ima twin set and then passes through the block averaging each predicted value pair.

[1789] 2) Valid backward data exists and b
If wd ima twin is high, the block stalls until valid forward data arrives with the fw ima twin set, and then proceeds as described above. If both the forward and backward data are valid, no stall is performed.

[1790] 3) Although valid forward data exists,
If fwd ima twin is not set, fwd
p num is checked. This is (pred num
If the prediction mode is equal to the number from the previous prediction +1 (stored in), the prediction mode is set to forward.

[1791] 3) Although valid backward data exists, if bwd ima twin is not set, b
wd p num is checked. This is (pred n
If equal to the number from the previous prediction +1 (stored in um), the prediction mode is set to backward.

[1792] e from the back of one stage in the pipeline
Note that the early valid signal is used and the prediction filter adder mode can be set before the first data from the new block arrives. This ensures that no stalls are introduced into the pipeline.

The ima twin and pred num signals are not sent along with the filtered data along the forward and backward prediction filter pipelines. This is for the following reasons: 1) These signals are fwd 1st byte and / or
Or, it is checked only when bwd 1st byte is valid. This saves about 25 3-bit pipeline stages in each prediction filter.

2) Since the signal remains valid throughout the block, it is valid when fwd 1st byte and / or bwd 1st byte arrives at the prediction filter adder.

3) The signal is checked one clock before the data arrives in any case.

[1796] B. 12.4 “Predictive Adders and FIF
O "The prediction adder (padder) forms a predicted frame by adding the data from the prediction filter to the error data. To compensate for the delay from the input through the address generator, DRAM interface and prediction filter, the error data is 256 words FI before reaching the padder.
Passes through the FO (sfifo).

The coding standard token, prediction mode token, and data token are decoded to determine when a prediction block is formed.
The 8-bit prediction data is added to the 9-bit two's complement error data in the data token. The result is 0-25
It is limited to the range of 5 and proceeds to the next block. Note that this data restriction also applies to all intra-coded data, including JPEG.

The prediction adder of the present invention further includes a mechanism for detecting inconsistencies in the data arriving from the FIFO and the prediction filter. Theoretically, the amount of data from the filter must exactly correspond to the number of data tokens from the FIFO, including the prediction. In the event of a major malfunction, the padder will attempt recovery.

The end of the data block from the FIFO and filter is marked by the inextn and f1 last inputs, respectively. If the end of the filter data is detected before the end of the data token, the remaining tokens will continue to be output unchanged. On the other hand, if the filter block is longer than the data token, the input is stalled until all excess filter data is accepted and discarded.

1800 Since the chip is configured to send data from the token input port directly to these blocks and to send these outputs directly to the token output port,
There is no snooper in either the IFO or the prediction adder.

[1801] B. 12.5 "Write and read ladders" 12.5.1 “Light ladder (wrudde)
r) The write ladder sends all tokens coming from the prediction adder to the lead ladder. In addition, it is the MPEG I or P
All data blocks in the picture; Since all data blocks in the DRAM interface are sent to the external frame store under the control of the address generator. Although the write-back data passes through a snooper en route to the DRAM interface, all the basic functionality is contained within one two-wire interface stage.

[1802] The light ladder decodes the following tokens:

[1803]

[Table 234] After the data token header is detected, all data bytes are output to the DRAM interface. The end of a data token is detected by a low inextn, which causes a flash signal to be sent to the DRAM interface swing buffer. In normal operation, this will be aligned with the point where the swing buffer will swing anyway, but if the data token does not contain 64 bytes of data,
This provides a recovery mechanism (however,
3 may be incorrect).

B. [1804] 12.5.2 "Lead ladder (rr
udder)] The read ladder of the present invention has the following three functions, two of which are mainly related to picture sequence rearrangement in MPEG: 1) Data read back from an external frame storage device is stored in a correct position. To be inserted into the token stream.

2) Rearranging the picture header information in the I picture and the P picture.

3) Detect the end of the token stream by detecting the flush token (see Section B.12.1 “Top Fork”).

The structure of the lead ladder is shown in FIG. The entire block is made from standard two-wire interface technology. The tokens in the input interface latch are decoded, and these decodes determine the block operation:

[1808]

[Table 235] The relocation function is initiated via the microprocessor interface, but is forbidden unless the coding standard is MPEG, regardless of the state of the register. The same MPI register controls whether the address generator is generating a relocation address, and thus the relocation is an output from this block. To understand how the read ladder works, consider the input and output control logic separately, keeping in mind that the sequence of tokens is as follows: coding standard sequence start picture start Temporal standard Picture type Picture including data token and other token Picture end . .・ Picture start ・． . . B. 12.5.2.1 Input Control Logic From power-up, all tokens go to FIFO1 (referred to as current input FIFO) until the first picture type token for an I or P picture is encountered. Next, FIFO2 becomes the current input FIFO and I
Alternatively, all inputs are directed to it until the next picture type for the P picture is encountered, and FIFO1 becomes the current input FIFO again. Within I and P pictures, all tokens between the picture type and picture end are discarded, except for data tokens. This prevents motion vectors from associating with the wrong picture in a relocated stream that would have no meaning.

A 3 bit code is inserted into the FIFO along with the token stream to indicate the presence of a particular token header. This eliminates the need to perform token decoding on the output of the FIFO.

[1810] B. 12.5.2.2 Output Control Logic From power-up, until a picture start code is encountered, the token is accepted as FIFO1 (referred to as the current output FIFO), after which FIFO2 receives the current FIFO.
Becomes an IFO. Section B. In 12.5.2.1, at this stage, three picture header tokens, picture start, time standard, and picture start
It can be seen that it is held at 1. The current output FIFO is swapped each time a picture start code is encountered in an I or P frame. Thus, the three picture header tokens will be stored until the next I or P frame, and in the next I or P frame they will be associated with the correctly relocated data. B
The pictures are not rearranged and pass through without any tokens being discarded. All tokens in the first picture including the picture end are discarded.

During the I and P pictures, the data contained in the data token of the token stream is replaced by the rearranged data from the DRAM interface. During the first picture, the "relocated" data is present in the relocated data input. This is because the address generator requests the DRAM interface to pull it out. This is considered a hash,
Discarded.

[1812] Section B. 13 "DRAM interface" 13.1 "Outlook" In the present invention, the spatial decoder, the temporal decoder and the video formatting each have a DR for their particular chip.
An AM interface block is provided. In all three devices, the function of the DRAM interface is to transfer data from the chip to the external DRAM and to transfer data from the external DRAM into the chip via block addresses provided by the address generator. It is.

Typically, the DRAM interface operates from an address generator and a clock that is asynchronous to the clocks of the various blocks through which data is sent. However, this desynchronization is easily handled because the clocks operate at approximately the same frequency.

Normally, data is transmitted between the DRAM interface and the remaining chips in a 64-byte block (the only exception being the prediction data in the temporal decoder). The transmission is performed by a device known as a "swing buffer". This is essentially a set of RAMs operating in a double buffered configuration,
While the AM interface is packing or emptying one RAM, another chip portion is emptying or packing another RAM. A separate bus carrying addresses from the address generator is associated with each swing buffer.

Each chip has four swing buffers, and the functions of these swing buffers are different in each case. In the spatial decoder, the coded data is
M, one swing buffer is used to transfer the encoded data from the DRAM, and another swing buffer is used to read the encoded data from the DRAM.
A third swing buffer for transmitting to
A fourth swing buffer is used to read the tokenized data from RAM. In a temporal decoder,
Intra or predicted picture data in DRAM
One swing buffer is used to write to
A second swing buffer is used to read intra or predicted picture data from DRAM,
The other two are used to read forward and backward prediction data. In video formatting, one swing buffer is used to transfer data to the DRAM, and the other three are used to read data from the DRAM, each of which is a luminance (Y) and a red and blue color difference. Data (Cr and Cb, respectively). D
The operation of the general features of the RAM interface is described in the spatial decoder documentation. The next section describes features specific to the temporal decoder.

B. [1816] 13.2 "Time Decoder DRAM Interface" Section B. As described in 13.1, the temporal decoder has four swing buffers: two are used to read / write decoded intra and predicted (I and P) picture data, which are as described above. To operate. The other two are used to derive prediction data.

[1817] In general, prediction data, position of Tei Ru block is processed as specified by motion vectors in x and y, it is placed al offset. Thus, the data block to be retrieved will generally not correspond to a block boundary of data as it was encoded (and written to DRAM).
This is illustrated in FIG. 160, where the shaded area represents the block being formed. The dotted outline indicates the block from which it is predicted. The address generator translates the address specified by the motion vector for the block offset (total number of blocks) as indicated by the large arrow and the address specified by the motion vector for the pixel offset as indicated by the small arrow. .

At the address generator, the frame pointer, base block address, and vector offset are added to form the address of the block derived from DRAM. If the pixel offset is 0, only one request is issued. If there is an offset in either the x or y dimension, two requests are issued-the original block address and either immediately right or directly below. x and y
If both have offsets, four requests are issued. For each block to be derived, the address generator calculates the start / stop address parameters and sends them to the DRAM interface. The use of these start / stop addresses may be better illustrated by example, as outlined below.

As shown by the shaded area in FIG.
Consider the (1,1) pixel offset. The address generator makes four requests labeled A through D in the figure. The problem to be solved is how to quickly provide the required sequence of row addresses. The solution is to use a "start / stop" technique, which will be described.

Consider block A in FIG. The reading starts at position (1, 1) and at position (7,
It must end in 7). For a moment, assume that one byte is read at a time (ie, an 8-bit DRAM interface). The x value of the coordinate pair forms the 3 LSBs of the address, and the y value is three MSs.
Form B. The start values of x and y are both 1, giving address 9. Data is read from this address and the x value is incremented. The process is repeated until the x value reaches its stop value.
At this point, the y value is incremented by one and the x start value is reloaded, giving address 17. As each byte of data is read, the x value is incremented again until the stop value is reached. The process is repeated until both the x and y values have reached their stop values. Thus, 9, 10, 11, 12, 1
3, 14, 15, 17,. . . 23, 25,. . . , 3
1, 33,. . . ,. . . , 57,. . . , 63 are generated.

Similarly, the start / stop coordinates for block B are: (1, 0) and (7, 0), and for block C: (0, 1) and (0, 7). , For block D: (0,0) and (0,0).

The next question is where to write this data. Obviously, looking at block A, the data read from address 9 should be written to address 0 of the swing buffer, the data read from address 10 should be written to address 15 of the swing buffer, and so on. Similarly, address 8 of block B
Data read from address 15 of the swing buffer
And the data read from address 16 should be written to address 15 of the swing buffer. This function proves to be a very simple implementation, as outlined below.

Consider block A. At the start of reading, the swing buffer address register is opposite a stop value is loaded, y inverse stop value forms the three MSB, x inverse stop value forms the three LSB. In this case, DRAM
The swing buffer address is 0 while the interface is reading address 9 in the external DRAM. Thereafter, as the external DRAM address register is incremented, the swing buffer address register is incremented, as shown in Table 236:

[1824]

[Table 236] The discussion so far has centered on an 8-bit DRAM interface. For a 16 or 32 bit interface, some modifications have to be made. First, the pixel offset vector is 16 or 3
Must be "clipped" to point to a 2-bit binary. In the example used so far, for block A, the first DRAM read points to address 0,
The data in addresses 0-3 will be read. Next, the unwanted data must be discarded. This is accomplished by writing all the data to the swing buffer (which must now be physically larger than needed for the 8-bit case) and reading at the offset. When performing MPEG half-pixel interpolation, 9 bytes in x and / y must be read from the DRAM interface. in this case,
The address generator provides the proper start and stop addresses, and some additional logic in the DRAM interface is used, but there is no fundamental change in the way the DRAM interface operates.

The last thing to note about the temporal decoder DRAM interface is that additional information must be provided to the prediction filter to indicate what processing is required for the data. This includes: a "last byte" signal indicating the last byte of the transmission (of 64, 72 or 81 bytes); 261 flag Bidirectional prediction flag 2 bits indicating the dimension of the block (8 or 9 bytes in x and y) 2 bit number indicating the order of the block The last byte flag indicates that the data is a swing buffer. Generated when read from. Other signals are derived from the address generator and piped through the DRAM interface as they are read from the swing buffer by the predictive filter block so that they associate with the correct data block.

[1826] Section B. 14 "UPI documentation" 14.1 Introduction This document is intended to give the reader a proper understanding of the operation of a microprocessor interface according to the present invention. The interface is basically the same as for the spatial and temporal decoders, the only difference being the number of address lines.

The logic described here is purely microprocessor internal logic. The related schematics are as follows: UPI UPI101 UPI102 DINLOGIC DINELL UPIN TDET MONOVRLP WRTGEN READGEN VREFCKT Circuit UPI, UPI101, UPI102 are UPI0
All are the same except that one has a 7-bit address input and the eighth bit is hardwired to ground, while the other two have an 8-bit address input. Input / Output Signals The signals described here are U (defined in terms of UPI)
A list of all inputs and outputs to the PI module, with a note detailing the source or destination of these signals: NOTRSTInputGlob
From al chip reset, active low, pad input driver.

E1InputEnable signal 1, active low, from pad input driver (Schmitt).

E2InputEnable signal 2, active low, from pad input driver (Schmitt).

[1830] RNOTWInputRead not
Write signal from the pad input driver (Schmi
tt).

[1831] ADDRIN [7: 0] InputAdd
less bus signal from the pad input driver (Sc
hmitt).

[1832] NOTDIN [7: 0] InputInp
out data bus, from the input pad driver of the bidirectional microprocessor data pin (TTLin).

[1833] INT RNOTWOutputThe
Read not Write signal to internal circuitry accessed by the microprocessor interface (see memory map).

[1834] INT ADDR [7: 0] Output
The Internal Address Bus,
To all circuits accessed by the microprocessor interface (see memory map).

[1835] INTDBUS [7: 0] Input / O
inputThe Internal Data bu
s, to all circuits accessed by the microprocessor interface (see memory map) and to the microprocessor data output pad. The internal data bus carries data that is the reverse of the data on the pins of the chip.

[1590] READ STROutputAn is an internal timing signal that directs the reading of a location in the device memory map.

[1837] WRITE STROutputAn is an internal signal instructing writing of a location in the internal memory map.

[1838] TRISTATEDDPOutputA
n is an internal signal connected to the microprocessor data output pad indicating that they should be tri-stated. General Comments: The UPI schematic consists of six small modules: NONOVRLP, UPIN, DI
NLOGIC, VREFCKT, READGEN, WR
TGEN. It should be noted from the overall list of signals that there is no clock signal associated with the microprocessor interface other than the microprocessor bus timing signals that are synchronized with all other timing signals on the chip. Therefore, no timing relationships should be assumed between the operation of the microprocessor and the operation of the remaining devices, other than those that can be forced by external control. For example, stopping the external system clock for accessing the microprocessor interface on the test system.

Another close relationship without clocks in UPI is that some internal timing is self-timed. In other words, the delay of a signal is UPI
Controlled internally for the block.

The overall function of UPI is to take address, data, enable, and read / write signals from the outside world and format them so that they can properly operate internal circuits. The internal signal that defines access to the memory map is INT
RNOTW INT ADDR [. . . ], INTD
BUS [. . . ], And READ STR and WRITE
STR. The timing relationship between these signals is shown below for a read cycle and a write cycle. Although the data sheet definitions and the diagrams below always show the chip enable cycle, circuit operations are held low enabled and addresses can be cycled to perform a continuous read or write operation. You should be careful. This function is possible because of the address transition circuit.

[1841] Further, INT RNOTW and READ
The presence of STR, WRITE STR reflects some redundancy. It is a separate READ ST
Use either R or WRITE STR (and ignore INT RNOTW) or INT R
NOTW and a separate strobe signal (strobe signal is R
(Derived from the OR of EAD STR and WRITE STR).

The internal data bus is precharged high during a read cycle, and it further has a resistive pull-up to default to the 0XFF state for an extended period when the internal data bus is not driven. This translates to 0x00 on the external pins when they are enabled, since the internal data bus is the inverse of the data on the pins. This means that when an external cycle accesses a register or a register bit that is a hole in the memory map, the output data is limited and is low.

Circuit Details: UPIN-This circuit is the overall change detection block. It includes a sub-circuit called TDET which is a 1-bit change detection circuit. UPIN has a TDET module for each address bit and rnoww for each enable signal. UPIN also includes some combination logic to gate the outputs of the change detection circuit together. This gating generates the following signals: TRAN--indicates a transition to one of the input signals, and UPD DONE--indicates that the transition is complete and the cycle can be performed.

1844 CHIP EN--Indicates that a chip has been selected.

1845-TDET- This is a one bit change detection circuit. Two latches and two
Consists of two dedicated OR gates. The first latch is the signal SA
Clocked by MPLE, the second latch
Clocked by PDATE. These two non-overlapping signals are connected to the module NONOVRLP
come from. The general operation is that the input transition is CHA
NGE is generated, which is then performed to generate SAMPLE. When all input changes are accepted while SAMPLE is HIGH and input changes stop,
CHANGE goes LOW , SAMPLE goes LOW, which causes UPDATE to go HIGH , which in turn transmits data to the output latch, indicating UPD DONE.

[1846] NONOVRLP- This circuit basically inputs TRAN,
And a non-overlapping clock generator for generating UPDATE. External gating on the output of UPDATE means that the
Stop ATE from going high .

DINLOGIC-This module consists of eight stages of the data input circuit DINCELL and some gating to drive the TRISTATEPAD signal. This is because the output data port or Enable is LOW and Enable2 is L
OW , RnotW is HIGH , internal read
Indicates that it will only drive if dstr is HIGH .

DINCELL- This circuit consists of a data input latch and a tri-state driver for driving the internal data bus. Signal DATAH
OLD is HIGH, Enable and Enable1
When both e2 are LOW, data from the input pad is latched. The tri-state driver drives the internal data bus whenever the internal signal INT RNOTW is LOW . An internal data bus precharges the transistors, and a bus pull-up is also included in this module.

[1849] WRTGEN-This module is a WRIT
E STR and a latch signal DAT for data latch
Generate AHOLD. The write strobe is a self-time signal, but the self-time delay is VREFC
Defined in KT. Timing circuit RESETW
The output from RITE is used to terminate the WRITE STR signal. Note that the actual write pulse writing to the register only occurs after the end of the access cycle. This is because the data input to the chip is sampled only on the back edge of the cycle. Therefore, the data is valid only after the normal access cycle ends.

READGEN-This circuit, as the name implies, generates a READ STR and also PREC which is used to precharge the internal data bus.
Generate an H signal. The PRECH signal is also a self-time signal, and its period depends on VREFCKT and the voltage of the internal data bus. READ STR is not self-timed, but lasts from the end of the precharge period to the end of the cycle. The precharge circuits use inverters, but their transmission features are biased such that they require approximately 75% of the supply voltage before going out of phase. This circuit ensures that the internal bus is properly precharged before the READ STR begins. If the internal bus is already precharged, the timing circuit guarantees a minimum width via the signal RESETREAD to stop PRECH pulses that tend to be zero width.

[1851] VREFCKT-VREFCKT is the only circuit that controls the self-timing of the interface. Both delays, 1 / Widt of WRITE STR
The 2 / Width of h and PRECH is controlled by the current through the P transistor. The gate of this P-transistor is controlled by the signal VREF,
It is set by a diffusion transistor of kΩ.

[1852] Section C. 1 "Prospects" 1.1 Introduction The structure of the image formatting unit according to the present invention is shown in FIG. Two address generators, one for writing, one for reading, a buffer manager that manages the two address generators and provides frame rate conversion, and a data processing pipeline that includes vertical and horizontal unsamplers. There is a final control block that adjusts the output of the color space conversion and gamma correction, and the processing pipeline.

[1853] C.I. 1.2 "Buffer Manager" Tokens arriving at the input of the image formatting unit are buffered in the FIFO and transmitted to the buffer manager. This block detects the arrival of new pictures and determines the availability of a buffer to store each picture. If a buffer is available, it is assigned to the arriving picture and its index is transmitted to the write address generator. If no buffer is available, the incoming picture will be stalled until any buffer becomes available. All tokens are sent to the write address generator.

Each time the read address generator receives a VSYNC signal from the display system, a request is made to the buffer manager for a new display buffer index. If there is a buffer containing the complete picture data, and if the picture is deemed ready for display, the buffer's index is sent to the display address generator. Otherwise, the buffer manager sends the last buffer index to be displayed. At startup, 0 is sent as an index until the first buffer is full. If the number of pictures (calculated as each picture is input) is greater than or equal to the number of pictures expected on the display (number of presentations) given the encoding frame rate, the picture is ready for display. I have. The expected number is determined by counting the picture clock pulses, in which case the picture clock can be generated locally by a clock distributor or externally. This technique allows for frame rate conversion (eg, 2-3 pulldown).

An external DRAM is used for the buffer, and the number may be two or three. If frame rate conversion is to be performed, three are required.

[1856] C.I. 1.3 "Write Address Generator" The write address generator receives tokens from the buffer manager and detects the arrival of each new data token. As each data token arrives, the address generator uses a DRAM to store the arriving block.
Calculate a new address for the interface. The raw data is then sent to the DRAM interface, where it is written to the swing buffer. A DRAM address is a block address and a picture organized as a raster of pictures or blocks in the DRAM. However, since the incoming picture data is actually a sequence of microprocessors organized, the address generation algorithm must account for (intra-block) line width offsets for the lower rows of the blocks in the microprocessor. .

The arrival buffer index provided by the buffer manager is used as an address offset for the entire stored picture. In addition, component offsets are used in the calculations as each component is stored in a separate area in the designated buffer.

[1858] C.I. 1.4 "Read Address Generator" The read address generator (dispaddr) does not receive and generate tokens, but only generates addresses.
Answer VSYNC and the address generator will use field in
A buffer index is requested from the buffer manager according to fo, read start, sync mode, and lsb invert. Upon receiving the index, three sets of addresses are generated, one for each component, one for the current picture read in raster order. The different setups allow: interlaced / progressive displays, and / or vertical unsampling, and field synchronization (for interlaced displays). At the lower level, the read address generator translates the base address into a block address and a sequence of byte counts for each of the three components that are compatible with the page structure of the DRAM. The addresses provided to the DRAM interface are page and line addresses along with block start and block end counts.

[1859] C.I. 1.5 "Output Pipeline" Data from the DRAM interface is provided to the output pipeline. The three component streams are first interpolated vertically and then horizontally. After interpolation, the three components must be in equal proportions (4: 4: 4) and sent to a color space converter and color look-up table / gamma correction. Output interface is HS
At this point the stream can be held until YSC is reached. The output controller then multiplexes the three components as needed and directs them to one, two or three 8-bit buses.

[1860] C.I. 1.6 “Timing style” Basically associated with the image formatting unit 2
There are three main timing styles. First, there is a system clock that provides timing for the front end of the chip (address generator and buffer manager, plus the front end of the DRAM interface). Second, there is a pixel clock that drives all timing for the back end (DRAM interface output, and the entire output pipeline).

[1861] Each of the two aforementioned clocks drives a number of on-chip clock generators. The FIFO, buffer manager, and read address generator operate from the same clock (DΦ), and the write address generator uses a similar but separate clock (WΦ). Data is clocked into the DRAM interface on the internal DRAM interface clock (outΦ). DΦ,
WΦ and outΦ are all generated from syscik.

The read and write addresses are clocked into the DRAM interface by the clock of the DRAM interface itself.

Data is read from the DRAM interface on bifRΦ and transmitted to a section of the output pipeline called bushy ne (north east because of its physical location) that operates on the clock represented by NEΦ. . Forward gamma R
The pipeline section from the AM is clocked on a separate but similar clock (RΦ). bifR
Φ, NEΦ, RΦ are all pixel clocks, pixin
Drawn from.

For testing, all of the major interfaces between the blocks have either an attached snooper or a super snooper. This depends on the timing scheme and the type of access required. Block boundaries between separate but similar timing modalities have associated retiming latches.

[1865] Section C. 2 "Buffer management" 2.1 Introduction The purpose of the buffer management block according to the present invention is to provide an index to the address generator specifying two or three external buffers for writing and reading of picture data. The assignment of these indices is affected by three major factors, each representing one impact of the timing modality in operation.
These are the rate at which picture data arrives at the input to the image formatting unit (coded data rate), the rate at which data is displayed (display data rate), and the frame rate of the encoded video sequence (presentation rate).

[1866] C.I. 2.2 “Functional Perspective” The three-buffer system, given the timing constraints of the system, ensures that frames are repeated or skipped as needed to achieve the best possible frame sequence. The presentation rate and the display rate can be different (for example, 2-3 pull-down). If the picture takes longer than the available display time to decode,
Pictures representing difficulties in decoding can be accommodated in a similar manner so that previous frames are repeated while all others "catch up". In a two-buffer system, three timing modalities must be locked-a third buffer that provides flexibility to handle slack.

The buffer manager operates by maintaining specific status information associated with each external buffer. This is a flag that indicates whether the buffer is busy, full, or ready for display, and a flag that indicates the number of pictures in the picture sequence currently stored in the buffer. including. A presentation count is also recorded, which increments each time a picture clock pulse is received, and represents the number of pictures currently expected to be displayed based on the frame rate of the encoded sequence.

An arrival buffer (a buffer into which incoming data is written) is allocated each time a picture start token is detected at the input. This buffer is then flagged IN USE.
When the picture end is reached, the arrival buffer is deallocated (reset to 0) and becomes a buffer that is flagged as FULL or READY, depending on the relationship between the number of pictures and the number of presentations.

The display address generator requests a new display buffer via the two-wire interface once every vsync. READY
If any buffers are flagged, they will be allocated for display by the buffer manager. If there is no READY buffer, the previously displayed buffer is repeated.

Each time the number of presentations changes, it is detected,
By examining the relationship between that picture number and the number of presentations, the RE of any buffer containing a complete picture
ADY-ness is tested. The buffers are considered in order. When a buffer appears to be READY, this automatically cancels the READY-ness of the buffer previously flagged as READY. Thereafter, the previous buffer is flagged as EMPTY. In the buffer to be considered later,
This works because the allocation plan stores the number of later pictures.

When a skipped picture in the input stream is indicated, H.187 The time standard token in 261 causes the number of pictures in the buffer to be modified. However, such features, although contemplated, are not currently included. Similarly, the time standard in MPEG has no effect.

[1872] The flush token has all buffers E
Stall the input until it is MPTY or allocated as a display buffer. Thereafter, the number of presentations and the number of pictures are reset, and a new sequence can be started.

[1873] C.1873. 2.3 "Architecture C.2.3.1 Interface" 2.3.1.1 "Interface to bm front" All data is input to the buffer manager from the input FIFO, bm front. This transmission takes place via a two-wire interface, the data being 8 bits wide plus extension bits. All data arriving at the buffer manager is guaranteed to be a complete token. This is a requirement for continuous processing of the number of presentations, and for display buffer requests when there is a valid gap in the data stream.

[1874] C.1874 2.3.1.2 "Waddrgen"
The token (8-bit data, 1-bit extension) is transmitted to the write address generator via the 2-wire interface. As soon as the picture start token arrives at waddrgen, the arrival buffer index is also transmitted on the same interface so that the correct index is available for the address generator.

[1875] C.1875. 2.3.1.3 "dispaddr"
Interface to the Read Address Generator The interface to the read address generator consists of two separate two-wire interfaces that are thought to act as "request" and "acknowledge" signals, respectively. However, single wire is not suitable because of the two two wire based state machines at either end.

The sequence of events is usually associated with the dispaddr interface as follows. First,
dis-paddr is drq to the buffer manager
By validating the valid input, v
Call a request that answers sync. Then, when the buffer manager reaches the appropriate point in its state machine, it accepts the request and strives to allocate a buffer to be displayed. Thereafter, the disp valid wire is qualified and the buffer index is transmitted, which is typically
Immediately accepted by paddr. Further, this last two-wire interface (rst) indicates that the number of fields associated with the current index must be reset independent of the number of previous fields.
There is an additional wire associated with fld).

[1877] C.I. 2.3.1.4 Microprocessor Interface The buffer manager block uses a 4-bit microprocessor address space with an 8-bit data bus and read / write strobe. There are two select signals, one indicating a user accessible location and the other indicating a test location that should not require access under normal operating conditions.

[1878] C.I. 2.3.1.5 Events The buffer manager can create two different events, index found and late arrival. The first of these is identified when the picture arrives, and its picture start extension byte (picture index) is set during setup by BU BM TARG.
Matches the value written to the ET IX register. Second
Is less than the current number of presentations, that is, processing in the system pipeline up to the buffer manager has not been processed to meet the presentation requirements.

[1879] C.1879 2.3.1.6 "Picture Clock" In the present invention, the picture clock is the clock signal for the presentation counter and is generated on-chip or derived from an external source (usually a display system). The buffer manager accepts both of these signals and selects one based on the value of pclk ext (a bit in the buffer manager's control register). This signal also serves as an enable for the pad picoutpad so that if the image formatting unit is generating its own picture clock, this signal is also available as an output from the chip.

[1880] C.I. 2.3.2 "Main Blocks" The following section is a buffer manager schematic (bml
The various hardware blocks that make up the omic) will be described.

[1881] C.I. 2.3.2.1 "input / output block (bm input)" This module consists of four 2-wire interfaces (input data and output data, drq v
valid / accept and disp valid / a
ccept). The input data register is shown with some token decoding hardware attached to it. bm to
The signal vheader at the input to kdec is used to ensure that the token decoder output is qualified only at points where the header will be valid (ie, not in the middle of the token). The rtmd block acts as an output data register adjacent to the dual input data register for the next block in the pipeline. This explains the timing difference due to the different clock generators. The signals go and ngo are data valid, ac
It is based on the AND of ccept and notstopped and is used somewhere in the state machine to indicate when something has been "wrecked" at the input or output. The display index portion of this module consists of a two-wire interface, with an equivalent " go " signal for the data. rst fld
A bit also occurs here, which, if set, dis
A signal that remains high until p_valid goes high for one cycle. Then it is reset. In addition, after the flash token causes the display buffer to flag all external buffers as EMPTY or IN USE, the rst f
ld is reset. This is the same point at which both the number of pictures and the number of presentations are reset.

There is a small amount of additional circuitry associated with the input data register that appears at the next level in the hierarchy. This circuit has a value equal to what the input data register is written to BU BM TARGIX and produces a signal indicating that it is used for event generation.

[1883] C. 2.3.2.2 "bm index" The index block consists mainly of a 2-bit register indicating the various strategic buffer indices.
These are arr buf, the buffer into which the arriving picture data is written, the disp buf, the buffer from which the picture data is read out for display, and the rdy buf, most up to now that the buffer can be displayed if requested by dispaddr Is a buffer index that contains the picture of. In addition, there is a register containing buf ix, which is used as a general pointer to the buffer. This register is incremented (D input to max), cycling through buffers to check their status, or if the status needs to be changed, arr buf,
One value of disp buf or rdy buf is specified. All of these registers (ph0 version) are accessible from the microprocessor as part of the test address space. old ix is a retimed version of buf ix and is used to enable buffer status and the number of pictures register in im stus block. buf ix
And old ix are both output from this block.
Decoded into two signals, each of which can hold the values 1-3. Other outputs are buf ix is arr b
indicates whether it has the same value as either uf or disp buf, and rdy buf and d
Indicates whether any of the isp buf has the value 0. 0 is not a reference code for the buffer.
It is simply the arrival / dis currently assigned
It only indicates that there is no play / ready buffer.

The arr buf and the disp buf are enabled by respective two-wire interface output accept registers.

An additional circuit at the bmlogic level is used to determine if the current buffer index (buf ix) is equal to the highest index in use, as limited by the value written to the control register during setup. You. "1" in the control register is 3
Indicates a buffer system, "0" indicates a two-buffer system.

[1886] C.I. 2.3.2.3 "Buffer Status" The main components in the buffer status are the status and the picture number register for each buffer. Each of the three groups is a master-slave arrangement, where the slave is a bank of three registers and the master outputs (using registers enables,
One register directed to one of the slaves (switched by old ix). One of the possible inputs to the master (buf at bmlogic level
multiplexed between different slave outputs (indexed by ix). Since the buffer status decoded at the bmlogic level is used in the state machine logic, it can take any of the values shown in Table 237, or the previous value can be recirculated. The number of pictures can take the previous value or the previous value incremented by one (or 1 + delta, the difference between the actual and predicted time reference in H.261). This value is provided by the 8-bit adder present in the block. The first input to this adder is this pnum, the number of pictures of the currently written data.

[1888]

[Table 237] Table C. 2.1 Buffer status value Any of the three buffer picture number registers (almost always
Outdated) rather than the number of pictures preceding their own, so that it can be easily updated based on the current (or previous) picture number, which is the separately (itself master
Need to be stored). this p
num is reset to -1 and added to the output from the adder when the first picture arrives, so the input to the first buffered picture number register is zero.

In the current version, the delta is connected to zero due to the lack of a time reference block to supply its value.

[1889] C.I. 2.3.2.4 Presentation Number The 8-bit presentation number register has an associated presentation flag used in the state machine to indicate that the presentation number has changed since the last time it was examined. This is necessary because the picture clock is inherently synchronous and can be active in any state, not because they are related to the number of presentations. The rest of the circuitry in this block detects that a picture clock pulse has occurred and "remembers" this fact.
Related to In this way, the number of presentations can be updated when it is valid. A representative sequence of events is shown in FIG. Signal incr prn
Becomes active one cycle after the retimed picture clock rising edge and persists until the state enters, during which time the number of presentations can be modified. This is indicated by the signal en prnum. The reason that we can only update the offer count during certain states is
Standard for which it provides the signal rdyst
This is because it is used to drive a significant amount of logic, including d-cell, not-very-fast 8-bit adders. Therefore, it must only be changed during states where the following state is not using the result.

[1890] C.I. 2.3.2.5 Temporal Reference The temporal reference block according to the present invention has been omitted from the current aspect of the image formatting unit, but its operation is described here for completeness of description.

[1891] The function of this block is Delta, H .; 261 to calculate the difference between the time reference value received at the token in the data stream and the "predicted" time reference (1 + the previous value). Thereby, H. At 261, a frame can be skipped. The time reference token is all non-H. 261 stream. The calculated value is used in the status block to calculate the number of pictures for the buffer. bml
The effect of omitting the block from the original is described in H.O. 261
Even though the stream indicates that some number of pictures should be skipped, the number of pictures is always continuous in any sequence.

The main components of the block (seen in schematic bm tref) are the registers for tr, exptr and delta. In the present invention, tr is reset to zero and loaded from the input data register when appropriate. Similarly, exptr is -1
And incremented by one or delta during the sequence of time reference states. In addition, delta is reset to 0 and the difference between the other two registers is loaded. All three registers are reset after a flush token. The adders in this block are used for both delta and exptr calculations, ie for subtraction and addition operations, respectively, and the signal del
controlled by ta calc.

[1893] C.I. 2.3.2.6 "Control register (b
m uregs) "The control register for the buffer manager is block bm
urges. These are the access bit register,
A setup register (which limits the maximum number of external buffers and internal / external picture clocks), and a target index register. The access bits are synchronized as expected. Signal stop0, stop
pd 1 and nstop 1 are the access bits O
Derived from R and the two event stop bits. Upi address decoding for all bmlogic is performed by block bm udec, which, together with the two select signals from the top level address decode of the image formatting unit, upi.
Take the lower 4 bits of the data bus.

[1894] C.I. 2.3.2.7 "State machine for control" State machine logic is originally a block of its own,
occupied bm state. However, for code generation reasons, it is now flattened and bmlogic
It is on sheet 2 of the schematic.

The main section of this logic is the same. This is a flag used to decode, generate logic signals for control of other bmlogic blocks, and select a route through the state machine, f
Includes new state encodings including rom ps and fromfl. bm stus and bmind
There is a separate block for creating max control signals for ex.

Signals in state machine hardware have been given simple alphabetic names for ease of typing and reference. All of them are listed in Tables 238-241 along with the logic representation they represent. In addition, they are the behavior of bmlogic.
It also appears as a comment in the commentary (bmlogic.M).

[1897]

[Table 238]

[1898]

[Table 239]

[1899]

[Table 240]

[1900]

[Table 241] C. 2.3.2.8 "Monitoring Operation (bminfo)" The present invention includes a module, bminfo, so that the buffer status information, index value, and number of presentations can be observed during the simulation. It is written into M, producing an output each time one of its inputs changes.

C. [1901] 2.3.3 "Register Address Map" The buffer manager address space is split into two areas, user accessible and test. Thus, there are two separate enable wires derived from range decoding at the top level. Table 242 shows the user accessible registers.
43 indicates the contents of the test space.

[1902]

[Table 242]

[1903]

[Table 243] C. 2.4 "State Machine Operation" As detailed in Table 244, there are 19 states in the buffer manager state machine. These are shown in FIG.
As shown in FIG. 66, the behavior description bmlogic. M interacts as described.

[1904]

[Table 244] C. 2.4.1 "Reset State" The reset state is PRES0, and the flag is set to 0 so that the main loop is cycled initially.

[1905] C.I. 2.4.2 "Main Loop" The main loop of the state machine is composed of the states shown in FIG. 167 (the main diagram-highlighted in FIG. 166). States PRES0 and PRES1 are signals pre
Relating to detecting the picture clock via sflg. The two cycles are all rdyst,
C. Since it depends on the value of the adder output signal described in 2.3.2.4, it can be included for testing. If a presentation flag is detected, all buffers are checked for possible "readiness"; otherwise, the state machine proceeds to state DRQ. PRE
Each cycle around the S0-PRES1 loop examines a different buffer and checks for full and ready conditions. When these are satisfied, the previous ready buffer (if any) is cleared, a new ready buffer is allocated, and its status is updated. This process looks at all buffers (index == ma
x buf) until the state advances. A buffer is considered ready to be displayed if any of the following are true: (pic num> pres num) && (pic num-pres num)> = 128) or (pic num <pres num) && (pres num-pic num) <= 128) or pic num == pres num The state DRQ is a request for the display buffer (drq validreg && disp acc).
Check reg). If there are no requests, the state proceeds (typically to state TOKEN, as described below). Otherwise, the display buffer index is emitted as follows: If there is no ready buffer, the previous index is reissued, or if there is no previous display buffer,
A zero index (zero) is emitted. If the buffer is ready to be displayed, its index is issued and its state is updated. If necessary, the previous display buffer is cleared. The state machine then proceeds as before.

The state TOKEN is a typical option for completing the main loop. If there is a valid input and the output is not stalled, the token is examined for strategic value (described in a later section); otherwise, control returns to state PRES0.

Control only branches from the main loop when certain conditions are met. These are described in the following sections.

[1908] C.I. 2.4.3 Assignment of Ready Buffer Index During the PRES0-PRES1 loop, if the buffer is determined to be ready, the previous ready buffer is emptied. Only one buffer can be designated ready at any time. State VACATE R
DY clears the old ready buffer by setting its state to VACANT, and control goes to PRES0.
When returning to the state, reset the buffer index to 1 so that the readiness of all buffers is tested. The reason for doing this is that the index now points to the previous ready buffer (to clear it) and there is no record of the new ready buffer index we intended. Therefore, it is necessary to retest all buffers.

[1909] C.I. 2.4.4 “Assignment of display buffer index”
State V that clears the old display buffer state directly from RQ (state USERDY) or
This is performed via the ATE DISP. The selected display buffer is flagged as IN USE, the value of rdy buf is set to 0, and the index is reset to 1 to return to state DRQ. Further, the necessary index is given to the disp buf, and the two-wire interface wire (disp v
alid and drq acc) are controlled accordingly. Control returns to state DRQ only so that decisions between states TOKEN, FLUSH, ALLOC need not be made in state USE RDY.

[1910] C.I. 2.4.5 "Operation when picture end is received" Upon receipt of the picture end token, control transfers from state TOKEN to state picture end, where if the index does not already point to the current arrival buffer, it is set there. Set to point and its state can be updated. out acc reg and en
Assuming full is true, the status can be updated as described below. Otherwise,
Control remains at the state picture end until they apply together. The en full signal is supplied by the write address generator and indicates that the swing buffer has swung, that is, that the last block has been successfully written and thus it is safe to update the buffer status.

The readiness of the just completed buffer is tested and the status FULL
Or READY is given. If it is ready, rdy buf is given the value of that index and the set_la_ev signal (late arrival event) is set high (indicating that the predicted display has advanced ahead of the decoding in a timely manner). Do). The new value of arr buf is now 0, and if the previous ready buffer needed to clear its status, the index is set to point there and control moves to state VACATE RDY.
If not, the index is reset to 1 and control returns to the start of the main loop.

[1912] C.I. 2.4.6 “Operation when picture start is received (arrival buffer allocation)” When a picture start token arrives during state TOKEN, flag froms is set, and state ALLOC is inspected instead of state TOKEN. To change the basic state machine loop. State ALLOC involves the allocation of an arrival buffer (in which picture data arriving therein can be written) and cycles through the buffer until it finds one whose status is VACANT. Since the buffer is output on the data two-wire interface, it is allocated only when out acc reg is high. Thus, the circulation around the loop will continue until this is the case. If a suitable arrival buffer is found, the index is arrb
uf and its status is IN USE
Is attached. The index is set to 1, the flag from ps is reset, and the state is set to go to NEW EXP TR. The index of the picture (contained in the word following the picture start) is checked to determine if it is the same as the target ix (the target index specified in the setup), and if so, set i
f + ev (index found event) is set high.

[1913] Three statuses NEW EXP TR,
SET ARR IX and NEWPIC NUM set the newly predicted time reference and the number of pictures for incoming data. The intermediate state sets the index to arr b so that the correct picture number register is updated (note that thispnum is also updated).
Set to uf. Control then proceeds to state OUTPUTTAIL which outputs data (assuming the preferred two-wire interface signal) until a low expansion is encountered. At this point, the main loop is restarted. This means that all data blocks (64 items) are output, during which no test is performed for presentation flags or display requests.

[1914] C.I. 2.4.7 "Action when flash is received" The flash token in the data stream indicates that the sequence information (number of presentations, number of pictures, rst fld) should be reset. This can only occur when all data leading to FLUSH has been correctly processed. Thus, after receiving the FLUSH, all frames have been handed to the display, ie all but one buffer have status EMPTY and one of them is IN USE (as a display buffer) It is necessary to monitor all the statuses of the buffer until is certain.
At that point, the "new sequence" can be used safely.

When a flash token is detected in the state token, a flag from fl is set, causing the basic state machine loop to be changed so as to patrol the state flash instead of the state token. State FLUSH examines the status of each buffer in order and waits until it becomes VACANT or IN USE as a display. The state machine simply cycles around the loop until the condition is true, then increments its index and repeats the process until all buffers have been visited. If the last buffer satisfies the condition, it is assumed that the number of presentations, number of pictures, and all time reference registers have their reset value rst fld set to one. The flag fromfl is reset and normal main loop operation is restarted.

[1916] C.I. 2.4.8 "Action when time standard is received" When a time standard token is encountered, When a check of 261 bits is performed and set, four state TEMs are set.
It patrols P REF0 to TEMP REF3. They perform the following operations:

[1917] TEMP REF0: temp ref =
in data reg; TEMP REF1: delta = temp ref−
index tr; index = arr buf; TEMP REF2: exp tr = delta + ex
p tr; TEMP REF3: pic num [i] = this
pnum + delta; index = 1. C. 2.4.9 "Other Tokens and Tail" State tokens send control to state OUTPUT TAIL in all cases except those outlined above. Encounter the last token word (in
Control remains here until extn reg is low) and the main loop is then re-entered.

[1918] C.I. 2.5 "Application Notes" 2.5.1 "State Machine Stalling Buffer Manager Input" This requirement repeatedly checks the picture clock and the "synchronous" timing events of the display buffer request. The need to stall the buffer manager input during these checks means that there is a limited rate of data passing through the buffer manager when there is a continuous data feed at the buffer manager input. A typical state sequence is PRES0, PRE
S1, DRQ, TOKEN, and OUTPUT TAIL, each of which lasts one cycle except OUTPUT TAIL. This is because the input is stalled for each block of 64 data items (state PRES).
There is an overhead of 3 cycles (between 0, PRES1, DRQ), which means slowing down the write speed by 3/64 or almost 5%. This number of overheads can be increased, sometimes up to 13 cycles, when the auxiliary branches of the state machine are executed under worst case conditions. Note that so much overhead can only be applied once per frame.

[1919] C.I. 2.5.2 "Presentation act during access" Bm illustrated by the schematic shown in 2.3.2.4
A special aspect of pres means that the number of presentations moves freely during an upi access. If the number of presentations when discarding access is required to be the same as the number of presentations when access was obtained, this should read the number of presentations after access has been granted and read it immediately before access is discarded. Achieved by writing back. Note that this is asynchronous, so it is desirable to repeat the access several times to further confirm its effectiveness.

[1920] C.I. 2.5.3 “H261 time reference number” module bm tref (not shown) is bmlogi
c. H. The 261 hour reference value is the delta input from bmtref
It is processed correctly by directing it to the stus module. The delta input can be tied to zero if the frames are always consecutive.

[1921] Section C. 3 "Write address generation" 3.1 Introduction The function of the write address generation hardware according to the present invention is to create a block address for the data to be written to the buffer. This takes into account the base address of the buffer, the components indicated in the stream, the horizontal and vertical sampling in macroblocks, picture dimensions and coding standards. The data arrives in the form of macroblocks, but must be stored so that the lines can be easily retrieved for display.

[1922] C.I. 3.2 Functional Perspective Each time a new block arrives in the data stream (indicated by the data token), the write address generator is requested to create a new block address. It is not necessary to create an address immediately because up to 64 data words can be stored by the DRAM interface (in the swing buffer) before the address is actually needed. This means that the various address components can be added to the running sum in successive cycles, thus eliminating the need for any hardware multiplier. The macroblock counter function is accomplished by storing important terminal values and moving a count in the register file, which is an operand for comparison and conditional update after each block address calculation.

Considering the picture format shown in FIG. 170, the expected address sequence is the standard data stream and H.264. 261 can be derived from both. These are shown below. Although the slices are not wide enough (three macroblocks rather than eleven), we use the same "half picture width slice" concept here for convenience and the sequence is of the "H.261 type" Format, the format is actually H.264. Note that it does not conform to 261 rules. Data is full macroblock,
In the example shown, it arrives at 4: 2: 0, and each component is stored in its own area of the designated buffer. Standard address sequence: 000,001,00C, 00D, 100,200; 002,003,00E, 00F, 101,201; 004,005,010,011,102,202; 006,007,012,013,103, 203; 008, 009, 014, 015, 104, 105; 00A, 00B, 016, 017, 105, 205; 018, 019, 024, 025, 106, 107; 01A, 01B, 226,. . . . . . . . . . H. 080, 081, 08C, 08D, 122, 222; 082, 083, 08E, 08F, 123, 223; 261 type sequence: 000,001,00C, 00D, 100,200; 002,003,00E, 00F, 101,201; 004,005,010,011,102,202; 018,019,024,025,106, 107; 01A, 01B, 026, 027, 107, 207; 01C, 01D, 028, 029, 108, 208; 030, 031, 03C, 03D, 10C, 20C; 032, 033, 03E, 03F, 10D, 20D; 006,007,012,013,103,203; 008,009,014,015,104,105; 00A, 00B, 016,017,105,205; 01E, 034,035,040,041,10E, 20E; 01F, 02A, 02B, 109, 209; 022,023,02E, 02F, 10B, 20B; 036,037,042,043,10F, 20F; 038,039,044,045,110,210; 03A, 03B, 046 048, 049, 054, 055, 112, 212; 04A, 04B, 056,. . . . . . . . . . B. 06A, 06B, 076, 077, 11D, 21D; 07E, 07F, 08A, 08B, 121, 221; 080, 081, 08C, 08D, 122, 222; 082, 083, 08E, 08F, 123, 223; 3.3 "Architecture" 3.3.1 "Interface" 3.3.1.1 Interface to Buffer Manager The buffer manager outputs data and buffer index directly to the write address generator. This is done under the control of a two-wire interface. In one way,
The write address generator block can be considered an extension of the buffer manager. Because they are very closely connected. However, they operate from two separate (but similar) clock generators.

[1924] C.I. 3.3.1.2 "Interface to dramif" The write address generator provides data and addresses for the DRAM interface. Each of these has its own two-wire interface, and dramif uses each in a different clock style. In particular,
The address is clocked dramif on a clock that is not related to the write address generator clock. Therefore,
It is synchronized at the output.

[1925] C.I. 3.3.1.3 Microprocessor Interface The write address generator uses a 3-bit microprocessor address space with an 8-bit data bus and read / write strobe. There is one select bit for register access.

[1926] C.I. 3.3.1.4 "Event" The write address generator can create five different events. Two respond to picture size information appearing in the data stream (hmbs and vmbs) and three respond to DEFINE SAMPLING tokens (one event for each component).

[1927] C.I. 3.3.2 "Basic structure" Schematic diagram of the structure of the write address generator waddrge
n. sch. It consists of a data path, some control logic, and a snooper and synchronization.

[1928] C.I. 3.3.2.1 “Data path (bw
adpath) "data path is defined in C.I. 18-bit adder / subtractor, of the type described in Chapter 5,
And a register file (see C.3.3.4) to create a zero flag (based on the output of the adder) for use in the control logic.

[1929] C.I. 3.3.2.2 "Control Logic" The control logic of the present invention is composed of hardware to generate all of register file load and drive signals, adder control signals, and two-wire interface signals, and further includes a writable control register. including.

[1930] C.I. 3.3.2.3 "Snorper and Synchronization" Super Snorper is present on both data and address ports. The snoopers in the data path are controlled as snoopers from zcells. The address has synchronization between the write address generator clock and the dramif clk style. Syncifs is used in zcells for two-wire interface signals, and a simplified synchronizer is used in the data path for addresses.

[1931] C.I. 3.3.3 "Control logic and state machine" 3.3.3.1 “Input / Output Block (wa i
nout) "This block contains a latch for input data (for token decoding) and a (for decoding in four ways)
Includes a two-wire interface of input and two outputs, along with an arrival buffer index.

[1932] C.I. 3.3.3.2 "Two Cycle Control Block (wa fc)" Flag fc (first cycle) is maintained here and state machine is in the middle of a two cycle operation (i.e. an operation involving addition) Indicate whether.

[1933] C.I. 3.3.3.3 “Component count (w
a comp) "A separate address is needed for the data block in each component, which keeps the current component under consideration based on the type of data header received in the input stream.

[1934] C.I. 3.3.3.4 “Modulo-3 Control (wa mod 3)” When generating the address sequence for the H.261 data stream, it is necessary to count three rows of the macroblock along the screen up to half (C.3.
2). This is achieved by maintaining a modulo-3 counter that is incremented each time a new row of the macroblock is visited.

[1935] C.I. 3.3.3.5 “Control register (w
a uregs) The module wa uregs includes a step-up register and a coding standard register, the latter being loaded from the data stream. The setup register uses 3 bits: QCIF (1sb) and the largest amount of components (bits 1 and 2) expected in the data stream. Further, the access bits are in this block (synchronized as usual) and the "stopped" bit is derived at the next higher level in the hierarchy as the OR of the access bit and the event stop bit. Microprocessor address decoding is performed by the block waudec, which takes the lower two bits of the read and write strobes, select wires, and address bus.

[1936] C.I. 3.3.3.6 "control state machine" The logic in this block is divided into several distinct areas. State decoding, new state encoding, origin of "intermediate" logic signals, data path control signals (drive, drive, load, adder control and select signals), multiplier control, 2-wire interface control, and five event signals. .

[1937] C.I. 3.3.3.7 "Event Occurrence" Five event bits are generated as a result of a particular token reaching the input. The important thing is that in each case,
Because the event service routine makes calculations based on the newly received value, all tokens are received before the event occurs. Thus, each bit is delayed by a full cycle before entering the event hardware.

[1938] C.I. 3.3.4 “Register Address Map” The write address generator block has two sets of registers. These are top-level setup-type registers located in the standard cell section, and are keyhole datapath registers. These are listed in Table 245 and Tables 246 to 256, respectively.

[1939]

[Table 245]

[1940]

[Table 246]

[1941]

[Table 247]

[1942]

[Table 248]

[1943]

[Table 249]

[1944]

[Table 250]

[1945]

[Table 251]

[1946]

[Table 252]

[1947]

[Table 253]

[1948]

[Table 254]

[1949]

[Table 255]

[1950]

[Table 256] Keyhole registers fall into two broad categories. It includes what must be loaded with the picture size parameter prior to address calculation, and the current sum of various (horizontal and vertical) block and macroblock counts. The picture size parameter may be loaded in response to an interrupt generated by the write address generator, ie, loaded when either the picture size or the sampling token appears in the data stream. Alternatively, if the picture sizes are known before receiving the data stream, they can be written after reset. See Section C. for an example of the setup. 13, the picture size parameter register is defined in the next section.

[1951] C.I. 3.4 Programming the Write Address Generator The next datapath register must contain the correct picture size information before the address calculation can proceed. They are illustrated in FIG.

[1952] 1) WADDR HALF WIDTH
IN BLOCKS: This defines, in blocks, half the width of the incoming picture.

[1953] 2) WADDR MBS WIDE: This defines the width of the incoming picture in a macroblock.

1954) WADDR MBS HIGH: This defines the height of the incoming picture in a macroblock.

[1955] 4) WADDR LAST MB IN
ROW: This defines the block number of the upper left block of the last macroblock in one full width row of the macroblock. Block numbering starts at 0 in the upper left corner of the leftmost macroblock, increases for each block across the frame, and continues to the next block row in the macroblock row.

[1956] 5) WADDR LAST MB IN
HALF ROW: This is the same as the previous item, but defines the number of blocks in the upper left of the last macroblock in the half width row of the macroblock.

[1957] 6) WADDR LAST ROW IN
MB: This defines the block number of the leftmost block in the last block row in the macroblock row. 7) WADDR BLOCKS PER MB RO
W: This defines the total number of blocks contained in one full width row of the macroblock.

[1958] 8) WADDR LAST MB RO
W: This defines the upper left block address of the leftmost macroblock in the last row of the macroblock in the picture.

9) WADDR HBS: This defines the width of the incoming picture block.

[1960] 10) WADDR MAXHB: This is 1
Defines the number of rightmost blocks in a row of blocks within one macroblock.

19) WADDR MAXVB: This defines the height-1 of one macroblock in the block.

[1962] In addition, the registers that define the organization of the DRAM must be programmed. These registers are three-buffer-based registers and n-component offset registers, where n is the number of components expected in the data stream (which can be defined in the data stream, 1 min and 3 max Limit).

Note that many parameters specify the number of blocks or block address. This is because the last address is expected to be a block address and the calculation is based on an accumulation algorithm.

The screen configuration shown in FIG. 171 yields the following register values: 1) WADDR HALF WIDTH IN BLO.
CKS = 0x16 2) WADDR MBS WIDE = 0x16 3) WADDR MBS HIGH = 0x12 4) WADDR LAST MB IN ROW = 0x
2A 5) WADDR LAST MB IN HALF R
OW = 0x14 6) WADDR LAST ROW IN MB = 0x
2C 7) WADDR BLOCKS PER MB ROW
0x58 8) WADDR LAST MB ROW = 0x5D8 9) WADDR HBS = 0x2C 10) WADDR MAXVB = 1 11) WADDR KAXHB = 1 3.5 State Machine Operation The buffer manager state machine has 19 states, details of which are shown in Tables 257 and 258. These are, as shown in FIG. 173, an action explanation and bmlogi.
c. Interact as described in M.

[1965]

[Table 257]

[1966]

[Table 258] C. 3.5.1 Address Calculation The main section of the write address generator state machine is illustrated on the left side of FIG. When the data token is received, the state machine sets the state ID
LE to state ADDR1 and then state A
It moves to DDR5, from which it outputs an 18-bit block address under the control of the 2-wire interface. The calculations performed by states ADDR1 to ADDR5 are as follows: BU WADDR SCLATCH = BU BUFFE
Rn BASE + BU COMPm OFFSET; BU WADDR SCLATCH = BU WADDR
SCRATCH + BU WADDR VMBADD
R; BU WADDR SCLATCH = BU WADDR
-SCRACTH + BU WADDR HMBADD
R; BU WADDR SCLATCH = BU + WADDR
SCRACTH + BU WADDR VBADDR; out addr = BU WADDR SCRACTH
+ BU WADDR HB; 1) BU WADDR VMBADDR: the block address of the leftmost macroblock in the macroblock row (upper left block), which includes the block whose address is calculated.

[1967] 2) BU WADDR HMBDDR:
The block address of the upper macroblock (upper left block) of the column of the macroblock, which includes the block whose address is calculated.

[1968] 3) BU WADDR VBADDR: The block address in the macroblock row at the left end of the row of the block, which includes the block whose address is calculated.

[1969] 4) BU WADDR HB: The number of horizontal blocks in the macro block of the block whose address is calculated.

[1970] 5) BU WADDR SCLATCH:
Scratch register used for temporary storage of intermediate results.

[1971] Considering FIG. 172, for example, taking the calculation of a block whose address is 0x62D, the following calculation sequence occurs: Scratch = BUFFERn BASE + COMPm
OFFSET; (assumed to be 0) Scratch = 0 + 0x5D8; Scratch = 0x5D8 + 0x28; Scratch = 0x600 + 0x2C; Block Address = 0x62C + 1 = 0x62D; The contents of various registers are shown in the figure.

[1972] C.I. 3.5.2 Calculation of New Screen Location Parameters Once the address is output, the state machine continues to perform calculations to update the various screen location parameters described above. State HB and MB0-MB
6 performs the calculation and transfers control to the state data at some point, from which the rest of the data token is output.

[1973] These states proceed in pairs, the first pair calculating the difference between the current count and its terminal value,
Generate a flag. The second pair resets the registers or adds a fixed offset (based on the value in the setup register derived from the screen size). In either case, when the count under consideration reaches its end value (ie, the 0 flag is set), control continues down the MB sequence of states. Otherwise, all counts are considered correct (ready for next address calculation) and control transmits state data.

All states, including the use of addition or subtraction, take two cycles to complete (allowing use of the standard ripple carrier), which is between 1 and 0 for adder-based states. Flag to be replaced by
This is achieved by using fc (first cycle).

The address calculation and screen location calculation states all assume that the preferred two-wire interface conditions allow data to be output.

[1976] C.I. 3.5.2.1 "Calculation for the standard
(MPEG-style) sequence "The sequence of the operation is as follows (0 flag is based on the output of the adder): State HB and MB0: Scratch = hb-maxhb; if (z) hb = 0; else ｛hb = hb + 1 new state = DATA;｝ state MB1 and MB2: scratch = vb addr-last row in mb; if (z) vb addr = 0; else ｖ vb addr = vb addr + width in block; ＭＢ states MB3 and MB4: scratch = hmb addr-last mb in row; if (z) hmb addr = 0; else ｈ hmb addr = hmb addr + maxhb; new state = DATA ｝ States MB5 and MB6: scratch = vmb addr-last mb row; if (! Z) vmb addr = vmb addr + blocks per mb row; (vmb addr is a picture start from the time when the picture end is inferred from the calculation. Reset after a token is detected.) 3.5.2.2 “H.261 calculation sequence” The H.261 calculation sequence branches off from the standard sequence in state MB4: state HB and MB0: as described above state HB1 and MB2: as described above state HB3 and MB4: scratch = hmb addr-last mb in row; if (z & (mod3 == 2)) / * end of slice on right of screen * / ｈhmb addr = 0; new state = MB5; ｅｌelse if (z) / * end of low on fresh * border / bright in blocks; new state = MB4A; {else} scratch = hmb addr -last mb in half row; new state = MB4B; {state MB4A: v b addr = vmb addr + blocks per mb row; new state = DATA; state (MB4) and MB4B: (scratch = hmb addr−last mb in half row;) if (z & (mod 3 == 2) slice on left of screen * / ｛hmb addr = hmb addr + maxhb; new state = MB4C; ｅｌelse if (z) / * end of left on screen / available; else {hmb addr = hmb addr + maxhb; new state = DATA;} state MB4C and MB4D: vmb addr = vmb addr -blocks er mb row; vmb addr = vmb addr -blocks per mb row; new state = DATA; state MB5 and MB6: as above C. 3.5.3 Operation on Picture Start Token Upon receipt of the picture start token, control proceeds to state PIC ST1, where the vb addr register (BU WADDR VBADDR) is reset to zero. State PIC ST2 and PIC ST3
Are patroled once for each component, and hmb a
Reset ddr and vmb addr, respectively. Control then proceeds to state IDLE via state OUTPUT TAIL.
Return to C. 3.5.4 Operation on DEFINE SAMPLING Token Upon receipt of a DEFINE SAMPLING token, the component registers are loaded with the least significant two bits of input data. In addition, state HSAM
Via P and VSAMP, the maxhb and maxvb registers for that component are loaded. Furthermore,
The appropriate defined sampling event bit is triggered (delayed by one cycle to ensure that all tokens are written).

[1977] C.I. 3.5.5 "HORIZONTAL
Operation on MBS and VERTICAL MBS "HORIZONTAL MBS and VERTICAL
As each MBS arrives, the 14-bit value contained in the token is written to the appropriate register in two cycles. The associated event bit is triggered and delayed by one cycle.

[1978] C.I. 3.5.6 "Other Tokens" Coding standard tokens are detected and input data is written to the top-level BU WADDR COD STD register. This is decoded and the nh261 flag (rather than H261) is hardwired to the buffer manager block. All other tokens control state OUTPUT TAI
Move to L and the state accepts data until the token is completed. Note, however, that it does not actually output any data.

[1979] Section C. 4 "Read address generator" 4.1 "Outlook" The read address generator of the present invention consists of four state machine / data path blocks. First, dline generates line addresses and distributes them to the other three (one for each component), the same page / block address generator, dramctls. All blocks are 2
Connected by a line interface. The operation modes include all combinations of jump / forward, first field upper / lower, and upper / lower / both frame start. Table 259 and Table 260 are dispa
dr control register name, address, and reset state. 13 shows an example of programming for both address generators.

[1980] C.I. 4.2 "Line address generator (d
line) "This block computes a line address generator for each component. Table 259 and Table 260 show 1 in dline.
8 shows an 8-bit data path register.

[1981] DISP register name and ADDR register name DISP
The distinction of the name register is only in dispaddr, which means that the register is special for the display area read from the DRAM. ADDR
name means that the register describes something about the structure of the external buffer.

Operation The basic operation of dline, ignoring all modes such as repeat, is: if (vsync start) / * first active cycle of vsync * / ｛comp = 0 DISP VB CNT COMP [comp] = 0; LINE [Comp] = BUFFER BASE [comp] + 0; LINE [comp] = LINE [comp] + DISP COMP OFFSET [comp]; while (VB CNT COMP [comp] <DISP VBS COMP [comp]) ｗ while (line count [comp) ] <8) ｛｛while (comp <3) ｛→ OUTPUT LINE [comp] to dramctl [comp] line [comp] = LINE [ comp] + ADDR HBS COMP [comp]; comp = comp + 1;｝ line count [comp] = line count [comp] +1; Ｖ VB CNT COMP [comp] = VB CNT COMP [comp] +1; line count [comp] == 0;｝｝

[1983]

[Table 259]

[1984]

[Table 260] C. 4.3 "Dline control register" The above operation is performed by the dispaddr shown in the table below.
Modified by control register.

[1985]

[Table 261] C. 4.3.1 “LINES IN LAST RO”
W [Component] These three registers determine, for each component, the number of lines in the last row of the block that is to be read. Thus, the height of the lead window may be any number of lines. Since the top, left and right edges of the window are on block boundaries, the output controller can clip (discard) extra lines,
This is a feature of backup.

[1986] 4.3.2 "DISPADDR A"
CCESS "This is the access bit for the entire dispaddr. When "1" is written to this location, dis
The paddr is stopped in synchronization with the clock. Once this state is reached, it is safe to perform an asynchronous upi access to all the dispaddr registers. Note that the upi is actively locked out of the datapath register until the access bit goes to "1". In order to achieve access to dispaddr without disrupting the current display or datapath operation, access is granted and released only under the following circumstances:

[1987] Stopping: The data path is
Access will only be granted if the cycle operation has been completed (one operation has been performed) and if the "safe" signal from the output controller is high. This signal represents the area on the screen below the display window and the output controller (dispaddr).
Not). Therefore, dis
Note that it is necessary to program the output controller before attempting to gain access to paddr.

The starting access will be released only when "secure" is high or during vsync. This ensures that the display does not start too close to the active window.

[1989] In this scheme, the control software accesses, registers up to the display end, and dispaddr.
, And allow access to request release, etc. Software is too slow, vsync
If the access bit is not released until after
paddr will not start until the next safe period. Border colors will be displayed during this "lost" picture (rather than boring ). C. 4.3.3 "DISPADDR CTLO [7:
0] "When reading the following description, it is important to understand the distinction between interlaced data and interlaced display.

The skip data can have two forms. The top-level register supports field pictures (each buffer contains one field) and frames (whether or not skipped, each buffer contains the entire frame).

[1991] DISPADDR CTL0 [7: 0] contains the following control bits: SYNC MODE [1: 0] In the interlaced display, the vsyncs referring to the top to bottom fields are distinguished by the field info pin. In such a situation, the fieldinfo
= HIGH means the top field. These two control bits determine which vsyncs dispaddr
Determines whether to request a new display buffer from the buffer manager, thus synchronizing the fields in the buffer (if data is skipped) with the fields on the display: 0: new display buffer on top field 1: Bottom field 2: Both fields 3: Both fields At startup, dispaddr is
It will request a buffer from the buffer manager on the ync. Dispadd until buffer is ready
r will receive a 0 (no display) buffer. When you finally receive a good buffer index,
dispaddr has no knowledge of where it is on the display. Therefore, it may be necessary to synchronize the display startup with the correct vsync.

[1992] READ START For jump display at startup, this bit determines on which vsync display to actually start. Further, after receiving the display buffer index, dispaddr may "leave" the current vsync to align the fields on the display with the fields in the buffer.

[1993] INTERLACED / PROGRESS
IVE 0: Progressive 1: Interlaced In forward mode, all lines are read from the display area of the buffer. In the jump mode, alternating lines are read. Whether reading starts from the first line or the second line is f
It depends on the field info. Note that in a (interlaced) field picture, the setting of this bit will be progressive, since the system wants to read all lines from each buffer. field
The mapping between info and the first / second line is lsb
invert (named so for historical reasons)
May be inverted.

LSB INVERT When set, this bit inverts the field info signal seen by the line counter. In this way, reading may start on the correct line of the frame and be aligned to the display regardless of the convention employed by the encoder, display, or top-level register.

[1995] LINE RPT [2: 0] When set, each bit causes the line of the corresponding component to be read twice (bit 0 affects component 0, etc.).
This forms the first part of the vertical unsampling. It is used for the eight color unsamplings required for the QFIF to 601 conversion.

[1996] COMPOHOLD This bit sets the number of lines for components 1 and 2 to component 0.
Used to program the ratio of the number of lines read (as opposed to what is displayed).

0: The same number of lines, that is, 4: 4: 4 data in the buffer 1: Double the 0-component line, that is, 4: 2: 0.

[1998] page / block address generator (dra
mctls) When passing a line address, these blocks generate a series of page / line addresses and blocks to read along the line. A minimum page width of 8 blocks is always assumed and the resulting output is the page address,
3-bit line number, 3-bit block start, and 3
It is composed of a bit block stop address. (The number of lines is calculated by dline and the unmodified dram
sent through ctls. Thus, reading 48 pixels on line 5 forms page 0xaa starting from the third block from the left (any point along any line), and the address sent to the DRAM interface is: Would be: page = 0xaa line = 5 block start = 2 block stop = 7 Each of these three machines has five datapath registers. These are shown in Tables 259 and 260. Each dr
The basic behavior of amct1 is as follows: block start = 2 block stop = 7 Each of these three machines has five datapath registers. These are shown in Tables 259 and 260. Each dr
The basic actions of amct1 are as follows: while (true) ｛CNT LEFT = 0; GET A NEW LINE ADDRESS from dline; BLOCK ADDR = input block addr + 0; PAGE ADDR + EpTDp = EpntFlogin; (CNT LEFT> BLOCKS LEFT) ｛BLOCKS LEFT = 8-BLOCK ADDR; → output PAGE ADDR, start = BLOCK ADDR, stop = 7. PAGE ADDR = PAGE ADDR + 1; BLOCK ADDR = 0; CNT LEFT = CNT LEFT-BLOCKS LEFT:｝ / * Last Page of line * / CNT LEFT = CNT LEFT + BLT C TFT TFT TFT T FLT TFT TFT TFT TFT TFT TFT TFT TFL T CFT TFT = BLOCK ADDR, stop = CNT LEFT｝

[1999]

[Table 262]

[2000]

[Table 263] Programming The next fifteen dispaddr registers must be programmed before starting operation.

[2001] BUFFER BASE0,1,2 DISP COMP OFFSET0,1,2 DISP VBS COMP0,1,2 ADDR HBS COMP0,1,2 DISP COMP0,1,2 Use of reset state of HBS dispaddr control register is 4: 2n Line repeats are not synchronized and the top field (field
d info = HIGH). Figure 168, "Buffer 0 with SIF (22x18 macroblock) picture" shows a buffer setup for a typical SIF picture. (For this example,
C. This will be described in detail in Chapter 13.) In this example, the DI
SP HBS COMPn is ADDR HBS COM
The register DISP VBS equal to Pn and also vertical
Note that COMPn and the equivalent write address generator register are equal, that is, the area to be read is the entire buffer.

[2002] Window processing using the read address generator dis so as to read only a part (window) of the buffer
It is possible to program the paddr. The window size is determined by the registers DISP HBS, DISP
VBS, COMPONENT OFFSET, and L
Programmed for each component by INES INLAST ROW. FIG. 169, "SIF Component 0 with Display Window" shows how this is achieved (for component 0 only).

In this example, the register settings would be as follows: BUFFER BASE0 = 0x00 DISP COMP OFFSET0 = 0x2D DISP VBS COMP0 = 0x22 ADDR HBS COMP0 = 0x2C DISP HBS COMP0 = 0x2A Notes: You can only start and stop. In this example, LINES IN equal to 7
The LAST ROW was left (meaning all 8).

This example is not practical for data other than 4: 4: 4 data. To reconcile, window edges for the other two components would not be able to lie on block boundaries.

The color space conversion will stop if the data it receives is not 4: 4: 4. This means that these lead windows, along with the ensampler, must be programmed to achieve this. Section C. 5 "Data path for address generation" The data paths used in dispaddr and waddrgen have the same structure and width (18 bits), but differ only in the number of registers, some masking, and the flags returned to the state machine. is there. A circuit of one slice is shown in FIG. 174, "Slice of Data Path". The registers are only assigned to the drive A or B bus, and they are fully utilized in the controller,
Used (specified). All registers can be loaded from the C bus, but not all "load" signals are driven. All operations, including adders, cover two cycles that make the adder have a normal ripple carry. FIG. 175, "Two-Cycle Operation of the Data Path", shows the timing for the sum of two cycles of the two registers loaded back into the A bus register. Various flags are ph0ed in the datapath to enable ccode generation. For the same reason, the structure of the datapath schematic is a bit unusual.
The tristate for all registers (on the A and B buses) allows for better ccode generation because it is in one block that eliminates the coupling path in the cell. To get upi access to the data path,
The access bit must be set such that the upi is locked out without this. Upi access is different from read and write: Writing: When the access bit is set, all load signals are disabled and one of a series of three-byte addressed write strobes is moved to one appropriate byte of a register. . The Upi data bus goes vertically through the data path (copied, 2-8-8 bits) and the 18-bit register is written as three separate byte writes.

Reading: This is done using A and B buses. Again, the access bit must be set. The address register is moved onto the A or B bus and the upi byte select picks up a byte from the associated bus and moves it onto the upi bus.

A double cycle data path operation requires the A and B buses to hold their values,
The access is broken before the start of any datapath operation, since the up access disrupts them.
It must only be given by controlling the state machine.

All data path registers in both address generators are passed through a 9-bit wide keyhole at top level address 0x28 (msb) and 0 for the keyhole.
x29 (lsb), addressed through 0x2A for data. Table 282 to Table 300 show the keyhole addresses.

Note: 1) Address generators (dispaddr and waddrg)
All address registers in en) contain the blocked address. Pixel addresses are never used,
The only register containing the line address is the three L
INES INLAST ROW register.

2) Some registers are duplicated between address generators, eg, BUFFER BASE0 is d
Occurs in the address space for ispaddr and waddrgen. These are two separate registers that both require loading. This enables display window processing (reading only a part of the display storage device), and facilitates display of formats other than three-component video.

[2011] Section C. 6 "DRAM interface" 6.1 Perspective In the present invention, the spatial decoder, the temporal decoder, and the video formatting unit each include a data token block for its special chip. In all three devices, the function of the DRAM interface is to transmit data from the chip to the external DRAM and from the external DRAM to the chip via block addresses provided by the address generator.

The DRAM interface typically operates from a clock that is asynchronous to the address generator and to the clocks of the various blocks through which data is sent. However, this asynchrony is easily handled because the clocks operate at approximately the same frequency.

Data is usually transmitted between the DRAM interface and the remaining chips in a block of 64 bytes (the only exception being the prediction data in the temporal decoder). The transmission is performed by a device known as a "swing buffer". This is essentially a pair of RAMs that are operated in a double buffered arrangement, while the DRAM interface packs or empties one RAM while the other part of the chip empties the other RAM. I'm packed. A separate bus carrying addresses from the address generator is associated with each swing buffer.

Each chip has four swing buffers, and the functions of these swing buffers are different in each case. In the spatial decoder, one swing buffer is used to transmit the coded data to the DRAM, another swing buffer is used to read the coded data from the DRAM, and
A third swing buffer to transfer to RAM
A fourth swing buffer is used to read tokenized data from the DRAM. In a temporal decoder, intra or predicted picture data is
One swing buffer is used to write to RAM, a second swing buffer is used to read intra or predicted picture data from DRAM, and the other two are used to read forward and backward predicted data. used. In the video formatting section, one swing buffer is used to transfer data to the DRAM, and the other three are used to read data from the DRAM, which are respectively luminance (Y), and red and blue. Color difference data (Cr and Cb respectively)
It is.

The operation of the general features of the DRAM interface is described in the spatial decoder documentation. The next section describes the DR according to the invention.
The features of the AM interface, particularly the features unique to the video formatting unit, will be described.

[2016] C. 6.2 "Video Formatting Unit DRAM Interface" In the video formatting unit, data is written to the external DRAM in blocks, but is read out in raster order. The lighting is exactly the same as that already described for the spatial decoder, but the reading is a bit more complicated.

Video Formatting Unit The data in the external RAM is organized so that at least eight blocks of data fit on one page. These eight blocks are eight consecutive horizontal blocks. When rasterizing, 8
It is necessary to read 8 bytes from each of the contiguous blocks and write it to the swing buffer (ie, the same row for each of the 8 blocks).

Considering the top flow (and assuming a byte-wide interface), the x address (3
LSB) is set to 0, and the same applies to the y address (3MSB). The x address is then incremented as each of the first eight bytes are read. At this point, the upper part of the address (bits 6 and above—LSB = bit 0) is incremented, and the x address (3LSB) is reset to zero. This process is repeated until 64 bytes have been read. For a 16 or 32 bit wide interface to an external DRAM, the x address is simply incremented by 2 or 4 instead of 1.

The address generator can send a signal to the DRAM interface that multiples of 8 bytes are always read, but no more than 64 bytes should be read (this is required at the beginning or end of a raster line). it can. This is done using start and stop values. The start value is used for the upper part of the address (6 bits or more), the stop value is compared to this and a signal is issued indicating that reading should be stopped.

[2020] Section C. 7 "Vertical upsampling" 7.1 Introduction If a raster scan of a pixel of one color component is at its input, a vertical ensampler according to the invention can provide an output scan that is twice as high. With mode selection, the output pixel value can be formed in many ways.

C. [2021] 7.2 "Port" Input 2-wire interface: in valid-in accept-in data [7: 0]-in lastpel-in lastline Output 2-wire interface:-out valid-out accept-out data [9: 0] ・ out last mode [2: 0] nupdata [7: 0], upaddr, upsel
[3: 0], upstrr, upwstr ramtest tdin, tdout, tph0, tckm, tcks ph0, ph1, notrst0 C.I. 7.3 “Mode” Selected by input bus mode [2: 0].

The mode register values 1 and 7 are not used.

In each of the above modes, the output pixels are displayed as 10 bit values, not as bytes. No rounding or censoring is done in this block. If necessary, the values are shifted left to use the same range.

[2024] C.I. 7.3.1 "Mode 0: Fifo" The block acts simply as a FIFO storage device. The number of output pixels is exactly the same as the number of input pixels. The value is shifted left by two.

[2025] C.I. 7.3.2 “Mode 2: Repea
t "Every line in the input scan is repeated to make an output scan twice the height. Again, the pixel value is shifted left by two.

A → ABACBDBCDCD C.A. 7.3.3 Mode 4: Lower Each input line produces two output lines. In this "lower" mode, the second of these two lines (the lower one on the display) is the same as the input line. The first of the pair is the average of the current input line and the previous input line. For the first input line when the previous line is not used, the input line is repeated.

This should select where the chroma samples will be placed along with the lower luminance samples.

A → ABAC (A + B) / 2DB (B + C) / 2C (C + D) / 2D 7.3.4 "Mode 5: Upper" Similar to the "lower" mode, except that the input lines form the upper side of the output pair and the lower side is the average of adjacent input lines. The last output line is a repeat of the last input line.

This should select where the chroma samples will be placed along with the higher luminance samples.

A → AB (A + B) / 2CBD (B + C) / 2C (C + D) / 2DD 7.3.5 “Mode 6: Central” This “center” mode corresponds to the situation where the chroma sample is halfway with the luminance sample. An output line is formed using weighted averaging to place the output chroma pixels along with the luminance pixels.

A → AB (3A + B) / 4C (A + 3B) / 4D (3B + C) / 4 (B + 3C) / 4 (3C + D) / 4 (C + 3D) / 4D 7.4 "How to operate" There are two line stores virtually designated by a and b. In FIFO and repeat modes, only line store a is used. Each store can accommodate lines up to 512 pixels (vertical upsampling should occur before horizontal upsampling). FI
The FO mode has no restrictions on the line length.

[2032] in lastpel and in last
The input signal in the line is used to indicate the end of the input line and the end of the picture. in las
At tpel, the input signal should strongly match the last pixel of each line. in lastline
In, the input signal should strongly match the last pixel of the last line of the picture.

The output signal out last strongly matches the last pixel of each output line. In repeat mode, each line is written to store a. The line is then read twice. When reading for the second time, writing of the next line may be started.

[2034] lower, upper and centra
In the l mode, lines are written alternately to stores a and b. The first line of the picture is always written to store a. Two small state machines, one for each store, remember what is in each store and which output lines are being formed. From these states, read and write requests and signals determining when to overwrite the next line with the current data are issued to the line store RAM.

When in lastpel is high, a register (lastaddr) stores the write address, thereby providing a line length for the formation of the output line. C. 7.5 "UPI" This block contains two 512x8 bit RAM arrays, which can be accessed via a microprocessor interface in a typical manner. No register has microprocessor access.

[2036] Section C. 8 "Horizontal Up Sampler" 8.1 "Outlook" In the present invention, the top level register comprises three identical horizontal up samplers, one for each color component. Since all three are controlled separately, only one will be described here. From a user perspective, the only difference is that each horizontal upsampler is mapped to a different set of addresses in the memory map.

The horizontal up sampler performs an operation that combines duplication and filtering. In all, there are four modes of operation.

[2038]

[Table 264] C. 8.2 Use of Horizontal Up Sampler The address map for each horizontal up sampler consists of 25 locations corresponding to 12 13-bit coefficient registers and one 2-bit mode register. The number written to the mode register determines the operation mode, as outlined in Table 264. Depending on the mode, some or all of the coefficient registers can be used. The equivalent FIR filter will be described below.

[2039] Depending on the operation mode, input, X
n is held constant for one, two, or four clock periods. The actual coefficients programmed for each mode are as follows:

[2040]

[Table 265]

[2041]

[Table 266]

[2042]

[Table 267] Coefficients not used in a particular mode need not be programmed when operating in that mode.

The first and last pixels of each line are repeated before filtering in order to provide a smooth filtering. For example, when up-sampling by 2, the first and last pixels of each line are 2
It is duplicated four times, not degrees. Since the residual data in the filter is discarded at the end of each line, the output of the number of pixels is always exactly one, two or four times the number in the input stream.

Depending on the coefficient values, the output samples are placed either coincident with the input samples or shifted out of the input samples. Some examples of coefficient values in a certain sample mode are described below. "-" Indicates that the coefficient value is "don't care". All values are shown in hexadecimal.

[2045]

[Table 268] C. 8.3 "Description of Horizontal Up Sampler" FIG. 177 shows the data path of the horizontal up sampler.

The operation takes the case of x4 up samples and is outlined below. In addition, × 2
Up-sampling and x1 filtering (mode 2
And 1) are a perturbation case of this, bypassing all filters (mode 0) and data going directly from the input latches to the output latches through the last max as shown.

1) If valid data is latched at the input Latch (L), it is held for four clock periods.

2) Each of the coefficient registers (labeled C / OE / FF) has four (PI
Two sets of pipeline registers (labeled PE) are clocked and simultaneously multiplexed onto the multiplier for one clock period. Thus, for the input data Xn, the value c00. X
n, c01. Xn, c02. Xn, c03. Xn will be packed.

3) Similarly, a second multiplier would in turn multiply that coefficient by Xn and a third multiplier would in turn multiply all its coefficients by Xn.

It will be appreciated that the output will be of the form shown in Table 269.

[2051]

[Table 269] From an output perspective, each clock period produces an individual pixel. This can be thought of as implementing a 12-tap filter on the x4 up-sampled input pixels, since each output pixel depends on the weighted value of the 12 input pixels (though there are only three different values). .

For x2 upsampling, the operation is essentially the same, except that the input data is held for only two clock periods. Furthermore, 2
Only coefficients are used and the PIPE block is shortened by the multiplier shown. For × 1 filtering,
The input is held only for one clock period. As expected, one coefficient and one PIPE stage are used.

Next, the specificity of the implementation in the present invention will be described a little.

1) Datapath width and coefficient width (13 bit 2's complement) as designed for the color space converter
And the same multiplier can be used. These widths are no more suitable for a horizontal up sampler.

2) A multiplexer that multiplexes coefficients onto a multiplier is shared with UPI readback. This introduces some complexity in the schematic structure (essentially due to the difficulty in CCODE generation), but the actual circuit is smaller.

3) As in the color space converter, a carry-save multiplier is used, the result of which is only resolved at the end.

The control for the entire horizontal up sampler can be viewed as a two-wire interface stage that, when on its input, can produce twice or four times the amount of data at the input. The mode programmed through the UPI determines the length of the programmable shift register (bob). The mode selected produces an output pulse every clock period, every two clock periods, or every four clock periods. It then controls the main state machine, whose state is further (2
In valid, out (for wire interface)
Accept and the signal in last. This signal is sent from the vertical up sampler,
Raised for the last pixel in each line. This causes the first and last pixel of each line to be duplicated twice,
Clear the pipeline between the lines (immediately after the line is completed, the pipeline contains partially processed redundant data).

[2058] Section C. 9 "Color space converter" 9.1 “Outlook” The color space converter (CSC) in the present invention multiplies incoming 9-bit data by a 3 × 3 matrix and then adds:

[2059]

(Equation 6) When x0-2 is input data, y0-2 is output data, and cnm is a coefficient. Some unconventional naming should be used with care for the matrix coefficients, since the names correspond to the signal names in the schematic.

The CSC can perform conversions between many different color spaces, but a limited set of these conversions is used in the top-level registers. The design color space conversion is as follows: ER, EG, EB → Y, CR, CBR, G, B → Y, CR, CB Y, CR, CB → ER, EG, EB Y, CR, CB → R, G, B where R, G and B are in the range (0.511);
All other quantities are in the range (32.470). The inputs to the top level register CSC are Y, CR, CB
Therefore, only the third and fourth of these equations are relevant.

In the CSC design, the precision of the coefficients is, for 9-bit data, +1 of the value created by all floating point simulations of the algorithm for all outputs.
Or within -1 bit (this is the best accuracy that can be achieved). This provided a 13-bit two's complement coefficient for cx0-cx3 and a 14-bit two's complement coefficient for cx4. All design conversion coefficients are listed below in both decimal and hexadecimal.

[2062]

[Table 270]

[2063]

[Table 271] All these numbers are calculated from the following basic formula: Y = 0.299 ER + 0.587 EG + 0.0114 EB and the following color difference formula: CR = ER-Y CB = EB-Y The formulas in R, G and B are It is derived from these after considering the full range of quantities.

[2064] C. 9.2 “Use of color space converter” After reset, c01, c12, and c23 are set to 1,
All other coefficients are set to zero. Thus, y0 = x
0, y1 = x1, y2 = x2, and all data is sent unchanged. To select a color space conversion, one simply writes the appropriate coefficients (eg, from Table 270, Table 271) to the locations specified in the address map.

In the schematic diagram, x0. . 2 is in da
ta0. . 2, corresponding to y0. . 2 is out data
0. . Corresponds to 2. It should be remembered that the user must upsample 4: 4: 4 input data to the CSC. Failure to do this will not only make the color space conversion meaningless, but will also lock the chip.

Note that each output can be formed from a possible combination of coefficients and input plus (or minus) constants. Thus, for a given color space conversion, the output order can be changed by swapping the rows in the conversion matrix (the address where the coefficients are written).

For all the conversions in Tables 270 and 271, the CSC is guaranteed to work. When using other transforms, the user must remember the following: 1) If the intermediate result of the calculation requires more than 10 bits of precision (except for the sign bit), the hardware will not work .

2) The output of the CSC is saturated to 0 and 511. That is, numbers less than or equal to 0 are replaced with 0,
Numbers greater than or equal to 511 are replaced with 511. The execution of the saturation logic assumes that the result is slightly above 511 or slightly below zero. If the CSC were programmed incorrectly, it would be a common signal that the output always (or in most cases) appears to saturate.

C. [206] 9.3 "Description of CSC" The structure of the CSC is illustrated in FIG. 178, but only two of the three "components" are shown due to space constraints. In the figure, "register" or R indicates a master / slave register, and "latch" or L indicates a transparent latch.

All coefficients are loaded into read / write UPI registers not explicitly shown in the figure. To understand the operation, the leftmost "component"
For (creating output out data0), consider the following sequence: 1) Data arrives at input x0-2 (in data0-2). It represents one pixel in the input color space. This is latched.

2) Multiply x0 by c01 and latch it in the first pipeline register. x1 and x2 move on one register.

3) Multiply x1 by c02 and multiply it by (x1.
c01) and latch the result in the next pipeline register. x2 moves on one register.

4) Multiply x2 by c03 and add it to the result of (3) to obtain (x1.c01 + x2.c02 + x3.
c03). The result is latched in the next pipeline register.

5) The result of (4) is added to c04. This adder is also used to decompose the data from the multiplier chain since the data is held in carry-save format through the multiplier. The result is latched in the next pipeline register.

20) The final operation is to saturate the data. To do this, the partial result is sent from the decomposition adder to the saturating block.

It can be seen that the result is y0, as specified in the matrix equation at the beginning of this section. Similarly, y1 and y2 are formed in the same way.

[2077] The coefficient is a multiplicand, and the data is a multiplier.
Three multipliers were used. This allowed an efficient layout to be achieved, with partial results going down the data path and the same input data being sent across three parallel, identical data paths, one for each output. Section C. To achieve the reset state described in 9.2, each of the three "components" must be reset in a different way. To avoid having three sets of schematics and three slightly different layouts, this is achieved by having inputs to UPI registers that are tied high or low at the top level.

The CSC has little control associated with it. Nevertheless, since each pipeline stage is a two-wire interface stage, their associated controls (in accept = out accept)
There is a chain of valid latches and accept latches with tr + lin validr). Therefore, the CSC is a two-wire interface with a depth of 5 stages and can hold 10 levels of data when stalled.

The output of the CSC includes a resynchronization latch, as the next function in the output pipe departs from a different clock generator.

[2080] Section C. 10 "Output controller" 10.1 Introduction The output controller according to the invention performs the following functions: provides data in one of three modes: 24 bits 4: 4: 4 16 bits 4: 2: 2 8 bits 4: B. 2: Align data by vsync and hsync pulses and in video display window defined by programmed timing register. Add border around video window, if needed. 10.2 "Port" Input 2-wire interface: -in valid -in accept -in data [23: 0] Output 2-wire interface: -out valid -out accept -out data [23: 0] -out active- out window out comp [1: 0] invsync, inhsync nupdata [7: 0], upaddr [4: 0],
upsel, rstr, wstr, tdin, tdou
t, tph0, tckm, tcks chips
t, ph0, ph1, notrst0, notrst1 C.I. 10.3 "Out mode" The format of the output is selected by writing to the opmode register.

[2081] C.I. 10.3.1 "Mode 0" This mode is a 24-bit 4: 4: 4 RGB or Y
CrCb. Input data goes directly to output.

C. [2082] 10.3.2 "Modes 1 and 2" These modes represent 4: 2: 2 YCrCb. In
Assuming that data [23:16] is Y, i
n data [15: 8] is Cr, and indata
[7: 0] is Cb.

C. [2083] 10.3.2.1 "Mode 1" In 16-bit YCrCb, Y is out data.
a is displayed on [15: 8]. Cr and Cb are out
Time division multiplexing is performed on data [7: 0], with Cb first. Out data [23:16] is not used.

C.2084 10.3.2.2 "Mode 2" In 8-bit YCrCb, Y, Cr and Cb are C
out data in the order of b, Y, Cr, Y
Time division multiplexing is performed on [7: 0]. Out data
[23:16] is not used.

C.2085 10.3.3 "Output timing" To put data in the video display window,
The following registers are used:

Vdelay-hsync following the vsync pulse, before the first line of video or border
c-pulse number-number of clock cycles between hdlay-hsync and the first pixel of the video or border-height of the video window in height-line-width of the video window in width-pixel-north, south-line Height of each border above and below the video window at, west, east-each border width to the left and right of the video window in pixels. The minimum vdelay is zero. The first hsync is the first active line. The minimum value that can be programmed into hdlay is 2. However, inhsyn
Note that the actual delay from c to the first active output pixel is hdlay + 1 cycles.

The border edge can have a value of zero. The color of the border is border r, b in the register
It is selected by writing order g and border b. The color of the area outside the border is blank r, blank g, blank in the register.
Selected by writing b. Output mode 1 and 2
The multiplexing performed in will also affect border and blank components. In other words, the value of these registers is in data [2
3:16], in data [15: 8], and in
data [7: 0].

C.2088 10.4 "Output Flag" outactive indicates that the output data is part of an active window, ie video data or a border.

• out window indicates that the output data is part of a video window.

[0201] out comp [1: 0] indicates that the color component is present on output data 1 and 2 out data [7: 0]. In mode 1, 0 =
Cb, 1 = Cr. In mode 2, 0 = Y,
1 = Cr, 2 = Cb. C. 10.5 Two-Wire Mode The two-wire mode of the present invention is selected by writing a one to a two-wire register. It is not selected following a reset. In the two-wire mode, the output timing register and the sync signal are ignored, and the data flow through the block is controlled by out accept.
Note that in normal operation, out accept should be tied to both.

[2091] C.I. 10.6 "Snooper" There is a super snooper on the output of the block that contains access to the output flag. C. 10.7 How It Works Two identical down counters remember the current position on the display. Vcount decrements on hsyncs and loads from the appropriate timing register on vsync or at its terminal count. Hc
The count decrements on every pixel and loads on hsync or at its terminal count. Note that in output mode 2, one pixel corresponds to two clock cycles.

[2092] Section C. 11 “Clock divider” 11.1 “Prospects” The top-level register in the present invention is
One is AUDIO to generate TURE CLK
To generate CLK, it includes two identical clock dividers. The clock divider is the same and is controlled separately. Therefore, only one will be described here.
From the user's point of view, the only difference is that the divisor register of each clock divider is mapped to a different set of addresses in the memory map.

[2093] The function of the clock divider is 4Xsysclk
It is to provide a distribution clock frequency and there is no requirement for an even mark to space ratio.

Since the divisor is required to be in the range of ０0 to １６16,000,000, it can be represented using 24 bits with the restriction that the minimum divisor is 16. This is because the clock divider will use a divisor / 2 to approximate equal mark-to-space ratios (within one sysclk cycle). Since the maximum clock frequency available is sysclk, the maximum distribution frequency available is sysclk / 2. In addition, since 4 counters are used in cascade, the divisor / 2 is never 8
Should not be less, or the clock output distributed would be driven to the positive power rail.

[2095] C.I. 11.2 Use of Clock Divider The address map for each clock divider consists of four locations corresponding to three 8-bit divisor registers and one 1-bit access register. The clock divider powers up the inactive one and is activated upon completion of access to its divisor register.

The divisor register may be written in the order according to the address map in Table 272. The clock divider is activated by sensing a synchronized 0-1 transition on its access bit. When a transition is sensed for the first time, the clock divider exits the reset state and generates a distributed clock. Subsequent transitions (assuming the divisor has also been changed) will simply cause the clock divider to lock to its new frequency on-the-fly. Once activated, there is no other way to stop the clock divider than chip RESET.

[2097]

[Table 272] Divisor values in the range 16-16, 777, 216 can be used.

[2098] C.I. 11.3 Description of Clock Divider The clock divider, as one counter carries,
It is implemented as four 22-bit counters cascaded to sequentially activate the next counter. Since the counters count down the divisor / 4 value before carry, each counter will take it in turn and generate a pulse at the distribution clock frequency.

After the carry, the counter reloads the divisor / 8, which is counted down to produce approximately equal mark-to-space ratio distribution clocks. As each counter is activated by the previous counter, as it reloads from the divisor register, this allows the distribution clock frequency to be changed on the fly by simply changing the divisor contents. To

Each counter is clocked by its own independent clock generator to precisely control the clock skew between the counters and to enable each counter to be clocked by a separate clock set.

The state machines are divisor / 4 and divisor / 8.
It controls the value generator and multiplexes the correct source clock from the PLL to the clock generator. The counter is clocked by a different clock depending on the value of the divisor. This is because different divisor values will use different combinations of clocks provided by the PLL to create a distributed clock whose edges are located.

[2102] C.I. 11.4 Testing the Clock Divider The clock divider can be tested by powering up the chip with CHIPEST High. This has the effect of forcing all of the clocking logic in the clock divider clocked by sysclk as opposed to the clock generated by the PLL.

Since the clock divider is designed to have full scan, it can still be tested using standard JTAG access as long as the chip is moved as described above.

If the device is operating in normal operation while CHIPTEST is held high,
The functionality of the clock divider is not guaranteed.

[2105] Section C. 12 "Address map" 12.1 "Top Level Address Map" Notes: -1) The registers for the top level address map described in Tables 273 to 281 are names used in the design. They need not be the names that appear in the data sheet.

2) Because this is a full address map, many of the locations listed here include locations for testing only.

[2107]

[Table 273]

[2108]

[Table 274]

[2109]

[Table 275]

[2110]

[Table 276]

[2111]

[Table 277]

[2112]

[Table 278]

[2113]

[Table 279]

[2114]

[Table 280]

[2115]

[Table 281] C. 12.1 “Address Generator Keyhole Space” Notes on the Address Generator Keyhole Table: 1) All registers in the address generator keyhole are
Regardless of their width, they take up 4 bytes of address space. The default address (0x00, 0x04, etc.) is always 0
Read back.

[211] 2) The access bit of the associated block (dispaddr or waddrgen) must be set before accessing this keyhole.

[2117]

[Table 282]

[2118]

[Table 283]

[2119]

[Table 284]

[2120]

[Table 285]

[2121]

[Table 286]

[2122]

[Table 287]

[2123]

[Table 288]

[2124]

[Table 289]

[2125]

[Table 290]

[2126]

[Table 291]

[2127]

[Table 292]

[2128]

[Table 293]

[2129]

[Table 294]

[2130]

[Table 295]

[2131]

[Table 296]

[2132]

[Table 297]

[2133]

[Table 298]

[2134]

[Table 299]

[2135]

[Table 300]

[2136]

[Table 301]

[2137]

[Table 302]

[2138]

[Table 303]

[2139]

[Table 304]

[2140]

[Table 305]

[2141]

[Table 306]

[2142]

[Table 307] Section C. 13 "Picture size parameter" 13.1 Introduction The following stylized code fragment illustrates the processing required to respond to a picture size interrupt from the write address generator. The picture size parameter is HO
RIZONTAL MBS Token, VERTICAL
MBS token, and (for each component)
Note that this can be changed on-the-fly by sending a DEFINE SAMPLING token, which in turn causes a write address generator interrupt. These tokens may arrive in any order, and generally, each should require a full recalculation of the picture size parameter. However, during setup, it may be more efficient to detect the arrival of all events before performing the calculations.

At the time of setup, a special value can be written to the picture size parameter register, so that there is no need to rely on interrupt processing for answering a token. Therefore, an appropriate register value for the SIF picture is also provided.

[2144] C.I. 13.2 Interrupt Handling for Picture Size Parameter There are 5 picture size events, the main ones of each response are described below: In addition, to maintain consistent picture size parameters, the following calculations are required: if (hmbs event || vmbs event || def samp0 event || def samp1 event || def samp2 event) ｏｒ for (I = 0; i <max component; i ++) ｈ hbs [i] = addr hbs [i] = (maxhb [i] +1) mbs wide; half width in blocks [i] = ((maxhb [i] +1) mbs wide) / 2; last mb in row [i] = hbs [i]-(maxhb [i] +1); last mb in half row [i] = half width in blocks [i]-(maxhb [i] +1 ); Las blocks in mb [i] = hbs [i] maxvb [i]; blocks per mb row [i] = last row in mb [i] + hbs [i]; last mb row [i] = blocks per mbro (Mbs high-1); It is strictly necessary to modify the dispaddr register value (such as the display window size) in response to the picture size parameter, but this should be dependent on the requirements of the application .

[2145] C.I. 13.3 “Register Value for SIF Picture” After the above interrupt processing for SIF, the values contained in all picture size registers, 4: 2: 0 streams are as follows: 13.3.1 "Primary value" BU WADDR MBS WIDE = 0x16 BU WADDR MBS HIGH = 0x12 BU WADDR COMP0 MAXHB = 0x01 BU WADDR COMP X1 MAXHB = 0x00 BUDXBMP 0MBOOBUX 0 B. 0x00 BU WADDR COMP2 MAXVB = 0x00 13.3.2 "Secondary Value-After Calculation" BU WADDR COMP0 HBS = 0x2C BU WADDR COMP1 HBS = 0x16 BU WADDR COMP2 HBS = 0x16 BU ADDR COMP0 HBS = 0x2C BU ADDR0x0B0x0B0x0B0x0B0x16 WADDR COMP0 HALF WIDTH
IN BLOCKS = 0x16 BU WADDR COMP1 HALF WIDTH
IN BLOCKS = 0x03 BU WADDR COMP2 HALF WIDTH
IN BLOCKS = 0x03 BU WADDR COMP0 LAST MB IN
ROW = 0x2A BU WADDR COMP1 LAST MB IN
ROW = 0x15 BU WADDR COMP2 LAST MB IN
ROW = 0x15 BU WADDR COMP0 LAST MB IN
HALF ROW = 0x14 BU WADDR COMP1 LAST MB IN
HALF ROW = 0x0A BU WADDR COMP2 LAST MB IN
HALF ROW = 0x0A BU WADDR COMP0 LAST ROW I
N MB = 0x2C BU WADDR COMP1 LAST ROW I
N MB = 0x0 BU WADDR COMP2 LAST ROW I
N MB = 0x0 BU WADDR COMP0 BLOCKS PER
MB ROW = 0x58 BU WADDR COMP1 BLOCKS PER
MB ROW = 0x16 BU WADDR COMP2 BLOCKS PER
MB ROW = 0x16 BU WADDR COMP0 LAST MB RO
W = 0x5D8 BU WADDR COMP1 LAST MB RO
W = 0x176 BU WADDR COMP2 LAST MB RO
W = 0x176 Note that if these values are to be written explicitly during setup, the multi-byte nature of most locations must be taken into account.

The pipeline system of the present invention described above fulfills a long-felt need, and an improved pipeline system comprises a plurality of processing stages between an input, an output, and an input and an output. A plurality of processing stages are interconnected by a two-wire interface that transmits tokens along the pipeline, control tokens and data tokens interface with all processing stages in the pipeline, And in the form of a universal adaptation unit that interfaces with selected processing stages in the pipeline, the processing stages of the pipeline being characterized by increased flexibility in construction and processing. According to the invention, the processing stage is configured to respond to recognition of at least one token. One processing stage is a start code detector that receives input and generates / converts a token.

The token of the present invention includes a picture start code token indicating that a picture starts after a next data token, a picture end token indicating the end of an individual picture, and a flash for clearing a buffer and resetting a system. Token, a coding standard token that adjusts the system to perform processing according to a selected one of a plurality of picture compression / decompression standards. Further, the invention comprises a Huffman decoder, an index / data (ITOD) stage, an arithmetic logic unit (ALU), and data buffer means immediately following the system, for video pictures of varying data size. The present invention relates to a pipeline system for decoding video data, wherein a time interval is controllable. According to the invention, the processing stage comprises means for receiving an input data stream and recognizing a particular bit stream pattern, the processing stage facilitating random access and error recovery. Further, the present invention comprises means for achieving a clear end to picture data decoding, indicating the end of a picture, and performing a picture stop after operation to clear the pipeline. The improved pipeline system comprises a fixed size and fixed width buffer and means for padding the buffer to pass any number of bits through the buffer. The invention further has a data stream comprising a run length code, and is activated by the data stream from the token to extend the run level code to one run of zero data followed by one level. It has an inverse modeler, and each token is represented by a specified number of values. Further, the present invention comprises an inverse modeler stage, an inverse discrete cosine transform stage, and a processing stage located between the inverse modeler stage and the inverse discrete cosine transform stage and responsive to a token table for data processing.

Furthermore, the present invention relates to an improved pipeline system, comprising: 261, JPEG or MPE
Huffman decoding means for decoding a data word coded based on any of the Huffman coding conditions of the G standard, wherein the data word has an identifier for identifying a Huffman code standard in which the data word is coded based on the Huffman decoding means. Means for receiving a Huffman coded data word; means for reading an identifier to determine which standard governed the Huffman coding of the received data word; and optionally, a Huffman coded data word. To H. In response to reading an H.261 or MPEG Huffman coded identifier, the Huffman coded data word is operatively connected to the Huffman coded data word receiving means for receiving an exponent from the exponent generation means, Means for generating an associated index, and a JPE to convey JPEG Huffman table information
Means for operating a look-up table including a Huffman code table having a format used in accordance with the G standard and outputting a decoded data word corresponding to the received exponent.

The multi-standard video decompression device of the present invention has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine, wherein control tokens and data tokens are in token format for both control and data. Through one two-wire interface to carry The token decode circuit is located at a particular stage to recognize the particular token as a control token for that stage and send unrecognized control tokens along the pipeline. The relocation processing circuit is placed on the selected stage,
React to a recognized control token to rearrange such stages to process the identified data token. A wide range of unique sub-support system circuits and processing techniques are disclosed to implement such a system.

[2150] While the specific embodiments of the invention have been illustrated and described, as noted above, it will be apparent that various modifications can be made without departing from the spirit and scope of the invention.
Accordingly, the invention is not limited by the illustrated embodiments, except for the limitations imposed by the appended claims.

[2151]

As described above, according to the present invention,
A pipe comprising a plurality of processing stages and a universal adaptation unit in the form of an interaction interface control token for performing control and data functions in the processing stages, the processing stages being provided with increased flexibility in construction and processing A line system is provided.

[Brief description of the drawings]

FIG. 1 shows six cycles of a six-stage pipeline for different combinations of two internal control signals.

FIG. 2 shows a pipeline in which each stage includes a secondary data store to show how the pipeline stages can compress and decompress in response to delays in the pipeline.

FIG. 3 shows a pipeline in which each stage includes a secondary data store to show how the pipeline stages can compress and decompress in response to delays in the pipeline.

FIG. 4 illustrates the control of data transfer between stages in a preferred embodiment of a pipeline using a two-wire interface and a multi-phase clock.

FIG. 5 illustrates the control of data transfer between stages in a preferred embodiment of a pipeline using a two-wire interface and a multi-phase clock.

FIG. 6 illustrates the control of data transfer between stages in a preferred embodiment of a pipeline using a two-wire interface and a multi-phase clock.

FIG. 7 illustrates the control of data transfer between stages in a preferred embodiment of a pipeline using a two-wire interface and a multi-phase clock.

FIG. 8 is a block diagram illustrating a basic embodiment of a pipeline stage incorporating a two-wire interface and two consecutive pipeline processing stages having two-wire transfer control.

FIG. 9 is an example of a timing chart showing a relationship among timing signals, input / output data, and internal control signals used in the pipeline stage shown in FIG. 8;

10 is an example of a timing diagram showing a relationship among timing signals, input / output data, and internal control signals used in the pipeline stage shown in FIG. 8;

FIG. 11 is a block diagram showing an example of a pipeline stage that maintains its state under control of an extension bit.

FIG. 12 is a block diagram of a pipeline stage that decodes a stage activation data word.

FIG. 13 is a block diagram illustrating the use of two-wire transfer control in one example of a data duplication pipeline stage.

FIG. 14 is a block diagram illustrating the use of two-wire transfer control in one example of a data duplication pipeline stage.

FIG. 15 is an example of a timing diagram showing a two-phase clock, a two-wire transfer control signal, and other internal data and control signals used in the embodiments illustrated in FIGS. 13 and 14;

FIG. 16 is an example of a timing diagram showing a two-phase clock, a two-wire transfer control signal, and other internal data and control signals used in the embodiments illustrated in FIGS. 13 and 14;

FIG. 17 is a block diagram of a reconfigurable processing stage.

FIG. 18 is a block diagram of a spatial decoder.

FIG. 19 is a block diagram of a temporal decoder.

FIG. 20 is a block diagram of a video formatter.

FIG. 21 is a memory map showing a first configuration of a macro block.

FIG. 22 is a memory map showing a second configuration of a macro block.

FIG. 23 is a memory map showing another configuration of a macro block.

FIG. 24 is a Venn diagram of possible table selection values.

FIG. 25 is a diagram showing a variable length of image data used in the present invention.

FIG. 26 is a block diagram of a temporary decoder including a prediction filter.

FIG. 27 is a diagram illustrating a prediction filter process by a picture;

FIG. 28 is a general diagram showing the structure of a macroblock.

FIG. 29 is a general block diagram of a start code detector.

FIG. 30 is a diagram exemplifying a start code in a data stream.

FIG. 31 is a block diagram showing a relationship among a flag generator, a decoding index, a header generator, an additional word generator, and an output latch.

FIG. 32 is a block diagram of a spatial decoder DRAM interface.

FIG. 33 is a block diagram of a write swing buffer.

FIG. 34 is an illustration showing a predicted data offset from a block being processed.

FIG. 35 is a diagram showing a predicted data offset of (1, 1).

FIG. 36 is a block diagram showing a split state device of a Huffman decoder and a spatial decoder.

FIG. 37 is a block diagram of a prediction filter.

FIG. 38 illustrates an exemplary decoder system.

FIG. 39 is a view showing a JPEG still image decoder.

FIG. 40 is a diagram showing a JPEG video decoder.

FIG. 41 is a diagram showing a multi-standard video decoder.

FIG. 42 is a view showing the start and end of a token.

FIG. 43 shows a token address and a data field.

FIG. 44 shows a token on an interface wider than 8 bits.

FIG. 45 is a diagram showing a macro block.

FIG. 46 is a diagram showing a two-wire interface protocol.

FIG. 47 is a diagram showing positions of external two-wire interfaces.

FIG. 48 is a diagram showing clock propagation.

FIG. 49 is a diagram showing the timing of a two-wire interface.

FIG. 50 illustrates an access structure.

FIG. 51 is a diagram showing a read transfer cycle.

FIG. 52 is a diagram showing access start timing.

FIG. 53 is a diagram showing an access example of two write transfers.

FIG. 54 is a diagram showing a read transfer cycle.

FIG. 55 is a diagram showing a write transfer cycle.

FIG. 56 shows a refresh cycle.

FIG. 57 is a diagram showing an example of a DRAM (9-bit address) having a 32-bit data bus and a depth of 256 k bits.

FIG. 58 is a diagram showing timing parameters for a strobe signal.

FIG. 59 is a diagram showing timing parameters between any two strobe signals.

FIG. 60 is a view showing timing parameters between a bus and a strobe signal.

FIG. 61 is a view showing timing parameters between a bus and a strobe signal.

FIG. 62 is a diagram showing MPI read timing.

FIG. 63 is a diagram showing MPI write timing.

FIG. 64 is a diagram showing an arrangement of large integers in a memory map.

FIG. 65 shows a typical decoder clock configuration.

FIG. 66 is a diagram showing input clock requirements.

FIG. 67 shows a spatial decoder.

FIG. 68 illustrates input and output of an input circuit.

FIG. 69 shows an encoding port protocol.

FIG. 70 shows a start code detector.

FIG. 71 is a view showing a detected start code and a converted token.

FIG. 72 shows a start code detector passing a token.

FIG. 73 is a view showing overlapping of MPEG start codes (byte alignment).

FIG. 74 is a view showing an overlap of MPEG start codes (non-byte alignment).

FIG. 75 is a view showing a jump between two video sequences.

FIG. 76 is a view showing insertion processing of an additional token.

FIG. 77 is a view showing decoder activation control;

FIG. 78 shows an enabled stream queued before output.

FIG. 79 is a view showing a spatial decoder buffer;

FIG. 80 shows a buffer pointer.

FIG. 81 is a diagram showing a video demultiplexer.

FIG. 82 is a view showing an image structure.

FIG. 83 is a view showing the structure of a 4: 2: 2 macro block.

FIG. 84 is a view showing a method of calculating the size of a macroblock from the size of a pixel;

FIG. 85 shows a spatial decoder.

FIG. 86 is a view showing an overview of H.261 inverse quantization;

FIG. 87 is a view showing an overview of JPEG inverse quantization;

FIG. 88 is a view showing an overview of MPEG inverse quantization.

FIG. 89 is a view showing a quantization table memory map;

FIG. 90 is a view showing an overview of a JPEG baseline sequence structure.

FIG. 91 is a view showing a tokenized JPEG image.

FIG. 92 shows a temporal decoder.

FIG. 93 is a view showing image buffer specifications.

FIG. 94 is a view showing an MPEG image sequence (m = 3).

FIG. 95 is a view showing how an “I” image is stored and output;

FIG. 96 is a view showing how a “P” image is stored and output;

FIG. 97 is a view showing how a “B” image is stored and output;

FIG. 98 is a view showing a picture buffer.

FIG. 99 is a diagram showing an H.261 prediction format.

FIG. 100 is a diagram showing an H.261 sequence.

FIG. 101 is a view showing a hierarchy of H.261 syntax.

FIG. 102 is a diagram showing an H.261 image layer.

FIG. 103 is a diagram showing an H.261 arrangement of a block group.

FIG. 104 is a diagram showing an H.261 “slice” layer.

FIG. 105 is a diagram showing an H.261 arrangement of macro blocks.

FIG. 106 is a diagram showing an H.261 block sequence.

FIG. 107 is a diagram showing an H.261 macroblock layer.

FIG. 108 is a diagram showing an H.261 arrangement of pixels.

FIG. 109 is a view showing a hierarchy of MPEG syntax.

FIG. 110 is a view showing an MPEG series layer.

FIG. 111 is a diagram showing an image layer of an MPEG group.

FIG. 112 is a diagram showing an MPEG image layer.

FIG. 113 shows an MPEG “slice” layer.

Fig. 114 is a diagram showing MPEG sequence blocks.

FIG. 115 is a diagram showing an MPEG macro block layer.

FIG. 116 is a view showing an example of “open GOP”;

FIG. 117 is a diagram showing an example of an access structure.

FIG. 118 is a diagram showing access start timing.

FIG. 119 is a diagram showing a high-speed page read cycle.

FIG. 120 is a diagram showing a high-speed page write cycle.

FIG. 121 is a diagram showing a refresh cycle.

FIG. 122 is a diagram showing how a row and column address is extracted from a chip address.

FIG. 123 is a view showing timing parameters for a strobe signal.

FIG. 124 is a view showing a timing parameter between any two strobe signals.

FIG. 125 is a diagram showing timing parameters between a bus and a strobe signal.

FIG. 126 is a view showing timing parameters between a bus and a strobe signal.

FIG. 127 is a view showing a Huffman decoder and a parser.

FIG. 128 is a view showing a flowchart of H.261 and MPEG AC coefficient decoding.

Fig. 129 is a block diagram of JPEG (AC and DC) coefficient decoding.

FIG. 130 is a view showing a flowchart of JPEG (AC and DC) coefficient decoding.

FIG. 131 is a view showing an interface of the Huffman token formatter.

FIG. 132 is a block diagram of a token formatter.

FIG. 133 is a view showing H.261 and MPEG AC coefficient decoding.

FIG. 134 is a view showing an interface of the Huffman ALU.

FIG. 135 is a view showing a basic structure of a Huffman ALU.

FIG. 136 is a view showing a buffer manager.

Fig. 137 is a block diagram of imodel and hsppk.

FIG. 138 is a view showing an imex state;

FIG. 139 is a view showing buffer startup.

FIG. 140 shows a DRAM interface.

FIG. 141 is a diagram showing a write swing buffer.

FIG. 142 is a diagram showing an operation block.

FIG. 143 is a block diagram of iq;

FIG. 144 is a view showing an iqca state machine;

FIG. 145 is a diagram showing an IDCT 1-D conversion algorithm.

FIG. 146 is a view showing an IDCT 1-D conversion structure;

Fig. 147 is a block diagram of a token stream.

Fig. 148 is a standard block diagram.

FIG. 149 is a block diagram illustrating microprocessor test access.

FIG. 150 shows a 1-D conversion microstructure.

FIG. 151 is a block diagram of a time decoder.

FIG. 152 is a view showing the structure of a two-wire interface stage.

FIG. 153 is a block diagram of an address generator.

FIG. 154 is a diagram showing offsets between blocks and pixels.

FIG. 155 is a diagram showing a plurality of prediction filters.

FIG. 156 is a diagram showing a prediction filter.

FIG. 157 is a diagram showing a 1-D prediction filter.

FIG. 158 is a diagram showing one block of pixels.

FIG. 159 is a diagram showing a structure of a read ladder.

FIG. 160 is a diagram showing offsets between blocks and pixels.

FIG. 161 is a diagram showing a prediction example.

FIG. 162 is a view showing a read cycle;

FIG. 163 is a diagram showing a write cycle.

FIG. 164 is a block diagram of a top-level register group capable of referring to timing;

FIG. 165 is a view showing control for increasing a presentation number.

FIG. 166 is a view showing a buffer manager state machine.

FIG. 167 is a diagram showing a main loop of the state machine.

FIG. 168 is a view showing a buffer 0 including an SIF (a macro block of 22 × 18).

FIG. 169 is a view showing SIF component 0 having a display window.

FIG. 170 is a view showing an example of an image format indicating a storage block address.

FIG. 171 is a view showing a buffer 0 including an SIF (a macro block of 22 × 18);

FIG. 172 is a view showing an example of an address calculation.

FIG. 173 is a view showing a write address generation state;

FIG. 174 is a view showing a slice of a data path.

FIG. 175 is a diagram showing a two-cycle operation of the data path.

FIG. 176 is a view showing a filtering process in mode 1;

FIG. 177 is a diagram showing a horizontal upsampler data path.

FIG. 178 is a view showing the structure of a color-space converter.

[Explanation of symbols]

33: token decoder, 34: input latch, 36: processing unit, 39: action identification unit, 41
... output latches, 43, 44 ... registers.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI H03M 7/30 H03M 7/30 Z 7/40 7/40 H04N 1/41 H04N 1/41 B Z 7/015 7/00 A 7/24 7/13 Z 7/30 7/133 Z (72) Inventor Helen Rosemary Finch UK, G127 127 N, Gloucester Shear, Wootton Under Edge, Combe, Tylay (no address) (72) Inventor William Philip Robbins UK, GL 115 PEE, Gloucester Shear, Kam, Springhill 19 (72) Inventor Kevin James Boyd England, BS 79 Diesel, Bristol, Lancashire Road 21 (72) Inventor Martin William Sozaran UK, GL 116 Biddy, Gloucester Shear, Darzley, Stinchcomb, Wikleyn, The Rady Gus (no address) (56) References JP-A-5-191652 (JP, A) JP-A-4-294684 (JP, A) JP-A-4-56548 (JP, A) JP-A-3-245281 ( JP, A) JP-A-1-306927 (JP, A) JP-A-64-66740 (JP, A) JP-A-64-18849 (JP, A) JP-A-63-271549 (JP, A) 1987-254550 (JP, A) Kannan Ramchandran, Martin Vetterli, Rate-Distribution Optimal Fast Threshold with the Complete ICON IJ PEG / MPEG Deco ICON, PEG / MPEG Deco. Pages: 700-704 Subroto Bose, Steve Purcell, T on Chiang, ASINGLE CHIP MULTI STANDARD VIDEO CODEC, Proceedings of IEEE 1993 CUSTOM INTEGRATED CIRCUITS CONFERENCE, IEV ERSV e. HORIZONS, ELECTRONIC DESIGN, November 11, 1993, Vol: 41, No: 23, Pages: 69, 70, 72, 74, 76, 78, 80-82 Stefan Mole, Komp akt and Flexibel, Elektronik, September 21, 1993, Vol: 42, No: 19, Pages: 102-108, 114-115 Dave Bursky, IMAGE-PROCESSING CHIP SET ANDLES FULL-MOTION VIDEO, ELECTRO NIC DESIGN, May 3, 1993, Vol: 41, No: 9, Pages: 117-120 Jack Shandle, ISSC CADVANCED TECHNOLOGY, ELECTRONIC DESIGN, 1993 Date Vol: 41, No: 5, Pages: 73, 74, 76, 78, 80 Mark Querol, MPEG / H261-Videodecoder mit wenigen Chips, Elektronik, November 9, 1992, Vol: 41, No: 23, Page. s: 72-75 Doug Baley, Matthew Cressa, Jan Fundrianto, Doug Neubauer, Hedley K. J. Rainnie, Chi-Shin Wang, Programmable Vision Processor / Controller, IEEE Micro, IEEE, Vol: 12, No: 5, Pages: 33-39 Milt Leonicon, Scan Electronics Regiment, Scan Electronics Recon. DESI GN, July 9, 1992, Vol: 40, No: 14, Pages: 40, 42-44, 46 Kiichi Matsuda, Osamu Kawai, Special Issue on Multimedia and Computer Element Technology 3-4 LSI , Journal of the Television Society, Japan, The Television Society of Japan, November 20, 1993, Vol. 47, No. 11, p. 1483-1487 Tsuneo Katsuyama, Ability of Broadband Multimedia Workstation Monster, Electronics, Japan, Ohm Co., Ltd., July 1, 1993, Vol. 38, No. 7, p. 30-34 Keiji Matsumoto and 6 others, Data flow type processor LSI aimed at the image processing field, Nikkei Electronics, Nikkei McGraw-Hill, Japan, April 9, 1984, No. 340, p. 181−218 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 17/10 G06T 1/20 G06T 9/00-9/40 H03M 7/00-7/50 H04N 1/41-1 / 419 H04N 7/00-7/68 G06F 15/82 G06F 13/38-13/42 G06F 15/16-15/177 G06F 15/80

Claims (1)

(57) [Claims] 1. A pipeline system having an inverse modeler stage and an inverse discrete cosine transform stage, comprising: a processing stage disposed between the inverse modeler stage and the inverse discrete cosine transform stage for processing data in response to a token. And including a processing stage for decoding the token according to a standard corresponding to the token, wherein each of the tokens includes a plurality of data words, each of which is an extension indicating the presence or absence of an additional word in the token. An indicator, wherein the length of the token is determined by the extended indicator, whereby the length of the token can be unlimited; the token is transmitted from the inverse modeler stage to the processing stage. Pipeline system characterized in that .