CN111722581B - Method for improving communication transmission and data processing efficiency of PLC and upper computer - Google Patents
Method for improving communication transmission and data processing efficiency of PLC and upper computer Download PDFInfo
- Publication number
- CN111722581B CN111722581B CN202010466104.7A CN202010466104A CN111722581B CN 111722581 B CN111722581 B CN 111722581B CN 202010466104 A CN202010466104 A CN 202010466104A CN 111722581 B CN111722581 B CN 111722581B
- Authority
- CN
- China
- Prior art keywords
- data packet
- data
- upper computer
- flag bit
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/547—Remote procedure calls [RPC]; Web services
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1101—Remote I-O
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/15—Plc structure of the system
Abstract
The invention provides a method for improving the communication transmission and data processing efficiency of a PLC (programmable logic controller) and an upper computer, which is adopted in the application occasions of large monitored data quantity and less data change of the PLC. In the PLC controller, open up the space, place the data package of keeping in, the register that keeps in the data package of keeping in compares with the register that current data package corresponds, sets its state bit to the current data package that changes the data, reaches to the data package that changes the data and carries out focus reading, has obviously improved the reading speed and the processing speed of host computer to changing the data. In addition, the storage and reading states of the data packet are set, and the consistency of the data packet and the state bits is ensured.
Description
Technical Field
The invention relates to a method for improving PLC transmission and processing efficiency, and belongs to the field of PLC application.
Background
The PLC has a wide range of applications in which the monitored data volume is large and the data change is small, for example, a subway station wind-water-power System, and the monitoring of wind-water-power is based on a BAS (Building Automation System, hereinafter abbreviated as BAS) System and uses a PLC (Programmable Logic Controller, hereinafter abbreviated as PLC).
Data monitored by the PLC is stored and transmitted using registers, one register typically occupying two bytes. PLC communication is usually based on MODBUS communication protocol, and a packet of normal message data has 125 registers, i.e. 250 bytes. Digital quantity input data monitored by a subway station PLC usually has three packets, analog quantity input data usually has more than ten packets, one packet of data query needs 300 milliseconds, the current PLC adopts full data uploading, the time consumption of all data transmission needs more than 3 seconds, the polling period is long, and the data refreshing in an upper computer system is slow. And the upper computer screens the change data when the change data needs to be deleted. If the number of registers included in the data packet is increased, although the number of data packets can be reduced, the number of times of establishing communication links is correspondingly reduced, and the time of the links is reduced, the message length is increased, the probability of communication failure is greatly improved, repeated communication is needed, and the communication time is wasted.
In the traditional method, an upper computer reads each data packet in sequence even if the data packet has no change, time is wasted, if sudden change data occurs, the upper computer polls the data packet which has the change data, and under the worst condition, the upper computer just reads one data packet, the data packet has data change, the upper computer needs to poll a circle of data packet to read the change data which is the data packet, and if more than ten data packets exist, the time delay of the upper computer feeding back the change data is the time for reading more than ten data packets, so that the change data is refreshed slowly.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a new technical scheme for improving the reading speed and the processing speed of an upper computer on change data.
The technical scheme is as follows: in order to solve the technical problem, the invention provides a method for improving the communication transmission and data processing efficiency of a PLC and an upper computer, which comprises the following steps:
the PLC is divided into two types, namely a PLC controller and a remote IO module;
the remote IO module has input and output functions of analog quantity and digital quantity and is used for measurement and control, and also has a function of communicating with the subsystem PLC;
the PLC has a communication function and a data processing function;
the communication function of the PLC controller is used for completing various communication tasks, including communication with an upper computer and communication with a lower computer, and the communication with the lower computer includes communication with a remote IO module, communication with a subsystem PLC and communication with a subsystem communication module, the communication tasks are not controlled by a user program of the PLC controller, after the communication configuration of the PLC controller is completed, the communication tasks are independently communicated, and the communicated data are accessed in a register for communication in the PLC controller;
the data processing function of the PLC is controlled by a user program, the data in the register for communication read by the communication function is logically judged, a decision is made, the data is written into the register for communication, and the communication function of the PLC is used for communication so as to achieve the purpose of control;
the register for communication of the PLC is filled according to a point table appointed with opposite communication side equipment, the opposite communication side equipment comprises an upper computer and a lower computer, and the lower computer comprises a remote IO module, a subsystem PLC and a subsystem communication module;
the PLC is communicated with an upper computer, data are stored in a plurality of communication data packets, the length of each data packet is limited by the length of a message communicated with the upper computer, the communication data packets are divided into three types, namely a digital quantity data packet, an analog quantity data packet for representing the digital quantity and a pure analog quantity data packet, the digital quantity data packet is used for placing the digital quantity, the analog quantity data packet for representing the digital quantity is used for placing the analog quantity for representing the digital quantity, and the pure analog quantity data packet is used for placing the pure analog quantity data; setting variables of each communication data packet, which are expressed as digital quantity, digital analog quantity and pure analog quantity, are stored in a PLC (programmable logic controller) and an upper computer;
the digital value is the switching value of the external contact, has two states of connection and disconnection, and is respectively represented by 0 and 1;
the analog quantity representing digital data is data for counting, is represented as an analog quantity, and is processed as a digital quantity;
the pure analog quantity refers to the value of the fluctuation of the measured voltage, current, temperature, humidity and the like;
the aforementioned digital quantity and analog quantity representing the digital quantity are collectively referred to as a non-pure analog quantity;
the communication data packet consists of a plurality of data registers which are called communication registers;
each communication data packet comprises input data of a plurality of remote IO modules or input data of a plurality of subsystems;
a first communication data packet communicated with the upper computer by the PLC is used as a special data packet, and a plurality of data registers are occupied as state registers according to the total amount of the data packets and are used for transmitting information with the upper computer;
communication data packets except the first communication data packet for communication between the PLC and the upper computer are called subsequent data packets:
each bit of the status register is used for indicating that the PLC controller data packet of each subsequent data packet has a changed data flag bit, the PLC controller is storing the data packet flag bit, the upper computer is reading the data packet flag bit and the upper computer data packet reading completion flag bit;
definition of 'PLC controller data packet has change data flag bit': the number of the data packets is '1' and respectively and correspondingly indicates that at least one data in the data packets stored by the corresponding PLC controller is changed; the data packets are respectively and correspondingly represented as '0' and none of the data stored in the corresponding PLC controller is changed;
definition of "PLC controller is storing packet flag bit": the data packets are respectively and correspondingly represented as '1' and are stored by the PLC controller of the corresponding data packet; the data packets are respectively and correspondingly represented as '0' and are not stored in the PLC;
definition of "upper computer is reading flag bit of data packet": the data packets are respectively and correspondingly represented as '1' and are read by the upper computer of the corresponding data packet; the data packets are respectively and correspondingly indicated as '0' and the corresponding data packet upper computer is not reading;
definition of a reading completion flag bit of an upper computer data packet: the data packets are respectively and correspondingly read by the upper computer of the corresponding data packet with the number of 1; the data packets are respectively and correspondingly represented as '0' and are not read by the upper computer of the corresponding data packet;
opening a storage space in the PLC, and storing temporary storage data packets of subsequent data packets, wherein data registers in the temporary storage data packets are called temporary storage registers, each temporary storage register in the temporary storage data packets is completely consistent with the definition of a corresponding communication register in the communication data packets for communicating with the upper computer, and the data packets for communicating with the upper computer corresponding to the temporary storage data packets are called corresponding data packets; the register in the data packet for communicating with the upper computer corresponding to the temporary storage register is called as a corresponding data register;
when the PLC controller is initialized, the following operations are sequentially carried out: all subsequent data packets are 'the upper computer is reading the flag bit' position '0' of the data packet ', and all subsequent data packets are' the PLC controller is storing the flag bit 'position' 1 'of the data packet'; copying the data of the lower computer, which is obtained by the communication corresponding to each data packet and is stored in the register, into the data register corresponding to each data packet; all subsequent data packets with a changed data flag bit of '1' of the PLC controller data packet; all subsequent data packets "PLC controller is storing data packet flag bit" position "0";
when the PLC controller starts a normal processing flow, firstly copying data stored in a register of a lower computer obtained by communication and stored in the register corresponding to a first data packet into a data register corresponding to the first data packet; then copying the data of the lower computer obtained by the communication stored in the register corresponding to the subsequent data packet into the data register corresponding to the temporary storage data packet corresponding to the subsequent data packet;
the variable of the current data packet processing number of the PLC is set to be 2, and the variable of the current data packet processing number of the PLC is arranged in the PLC and is used for representing the number of a data packet currently processed by a program of the PLC;
the following enters the processing flow of the subsequent data packet: the variable of the current data packet register processing number of the PLC is set to be 1, and the variable of the current data packet register processing number of the PLC is arranged in the PLC and is used for indicating the number of a register in a data packet currently processed by a program of the PLC;
the PLC sequentially compares and processes the temporary storage data packets with the corresponding data packets one by one according to the pure analog quantity data packets and the non-pure analog quantity data packets for the subsequent data packets;
when the register of the current data packet has changed data, if the flag bit of the current data packet is '0' read by an upper computer, and the 'upper computer data packet reading completion flag bit' is '1', the 'PLC controller is storing the' position '1' of the data packet flag bit in the current data packet, the PLC controller data packet of the current data packet has a changed data flag bit of 1, the upper computer data packet of the current data packet has a reading completion flag bit of 0, the subsequent data of the data packet are not compared any more, all the data in the current temporary storage data packet are copied to the data register corresponding to the current data packet, after the copying operation is completed, adding 1 to the current data packet 'the PLC controller is storing the data packet flag bit' position '0', and entering the next cycle until the comparison of the data of all the subsequent data packets is completed; if the flag bit of the current data packet, which is being read by the upper computer, is '1' or the flag bit of the upper computer data packet read completion is '0', the flag bit setting and copying operation is abandoned, the current data packet processing number of the PLC controller is added with 1, and the next cycle is entered until the comparison of the data of all the subsequent data packets is completed;
when the comparison is completed and no changed data is found, if the flag bit of the current data packet that the upper computer is reading the data packet is '0' and the flag bit of the current data packet that the upper computer is reading the data packet is '1', the flag bit of the current data packet that the PLC controller is storing the data packet is '1', the flag bit of the current data packet that the PLC controller has the changed data is '0', and the flag bit of the current data packet that the upper computer is reading the data packet is '0'; for a pure analog quantity data packet, copying all data in the current temporary storage data packet to a data register corresponding to the current data packet, and for a non-pure analog quantity data packet, not performing the copying operation; then adding 1 to the flag bit ' position ' 0 ' of the data packet currently stored by the PLC controller of the current data packet, and entering the next cycle until the comparison of the data of all the subsequent data packets is completed;
the data registers are compared one by one to judge whether changes occur, including the comparison of pure analog quantity data packets and non-pure analog quantity data packets;
the comparison of the non-pure analog quantity, i.e. the comparison of the digital quantity or the analog quantity representing the digital quantity, means that the temporary storage registers are compared with the corresponding registers one by one, and when the temporary storage registers are inconsistent, the current temporary storage register is considered to be the change data;
the comparison of the pure analog quantities means that variables corresponding to the pure analog quantities are configured in the PLC, and are used for setting change threshold values and amplitude threshold values corresponding to the pure analog quantities, the numerical values of the temporary storage registers of the pure analog quantities are compared with the corresponding amplitude threshold values one by one, and when the numerical values exceed the amplitude threshold values, the current temporary storage registers are considered to be change data; subtracting the values of the temporary storage registers of the pure analog quantity and the corresponding register values one by one, and when the values exceed a change threshold value, considering that the current temporary storage registers are changed data;
the data packet "PLC controller data packet has changed data flag bit" position "0", which means that the data packet has no changed data, and for digital quantity data packet or analog quantity data packet representing digital quantity, each temporary storage register has the same value as the corresponding register, i.e. has no change; for a pure analog quantity data packet, the value of each temporary storage register does not exceed a set change threshold and an amplitude threshold;
in the upper computer, a variable of 'change data packet flag' of the upper computer is set, wherein the variable is '1', which indicates that a subsequent data packet with 'a change data flag bit' of '0' exists in the data packet processing of one round of the upper computer, and the 'PLC controller data packet has a change data flag bit' of '1', namely the subsequent data packet with change data needing to be processed by the upper computer;
in the upper computer, a variable of 'the upper computer records that the data packet reads a changed bit' of each subsequent data packet is set, wherein the variable of '1' indicates that the subsequent data packet has changed data, is used for marking the subsequent data packet with the changed data and is used for the upper computer to perform subsequent processing on the changed data packet; after the upper computer finishes processing the changed data packet, reading the changed position ' variable position ' 0 ' of the data packet ' recorded data packet of the upper computer ';
the upper computer of the first round of fingers processes all data packets in sequence once;
in the upper computer, a variable of 'the current data packet processing number of the upper computer' is set for recording the number of the data packet processed by the upper computer;
when the upper computer is initialized, setting a variable of 'circularly reading a data packet number' to '2';
when the upper computer starts a new round of data processing, unconditionally reading the data of the first data packet so as to respectively process the subsequent data packets in sequence according to the state register in the first data packet; setting the ' changed data packet mark ' of the upper computer to ' 0 ', reading the changed position ' 0 ' of the data packet recorded by the upper computer and ' 2 ' of the current data packet processing number of the upper computer ' of all subsequent data packets;
the upper computer does not process the subsequent data packet with the flag bit of the data packet being stored by the PLC controller being 1, adds 1 to the current data packet processing number of the upper computer and processes the next data packet;
for a subsequent data packet with a flag bit of '0' stored by a PLC (programmable logic controller) and a changed data flag bit of '0' of a data packet of the PLC, the upper computer reads the flag bit of '1' of the data packet, reads the flag bit of '0' of the data packet, adds 1 to the processing number of the current data packet, and processes the next data packet;
the upper computer carries out the following operations in sequence for the subsequent data packet with the flag bit of the data packet being stored by the PLC controller being 0 and the flag bit of the data packet of the PLC controller having changed data being 1: the method comprises the steps that a current data packet 'upper computer is reading a data packet flag bit' position '1', all data of the current data packet are read, the current data packet 'upper computer data packet reading completion flag bit' position '1', the current data packet 'upper computer is reading a data packet flag bit' position '0', 'the upper computer has a changed data packet flag' position '1', the current data packet 'upper computer records a data packet reading changed position' 1 ',' the upper computer current data packet processing number 'is added with 1', and then the next data packet is processed;
after the upper computer finishes the reading processing of the three data packets in all the subsequent data packets, when the changed data packet mark of the upper computer is '1', entering the cycle of processing the data packets in the next round; when the data packet flag of the upper computer is changed to be '0', circularly reading a data packet;
the above-mentioned circulation reads a data packet, the step is as follows sequentially: setting a count of reading one data packet circularly for 2, and assigning the value of the variable of reading one data packet circularly for the variable of processing the number of the current data packet of the upper computer;
when the current data packet 'PLC controller data packet has changed data flag bit' is '0' and the 'PLC controller is storing data packet flag bit' is '0', the following operations are performed in sequence: reading all data of a current data packet by using a flag bit position '1' of the data packet which is being read by an upper computer of the current data packet, reading a flag bit position '1' of the data packet reading completion of the upper computer of the current data packet, reading a flag bit position '0' of the data packet by the upper computer of the current data packet, adding 1 to a data packet number in a circulating manner, and entering the next cycle of processing the data packet by circularly reading a data packet number '2' when the data packet number in the circulating manner is larger than the data packet number; entering the next cycle of processing the data packets when the number of the data packets read circularly is not more than the number of the data packets; when the flag bit of the changed data of the current data packet 'PLC controller data packet' is '1' or the flag bit of the data packet 'being stored by the PLC controller' is '1', the following operations are sequentially carried out: adding 1 to the current data packet processing number of the upper computer, and when the current data packet processing number of the upper computer is greater than the number of the data packets, setting the current data packet processing number of the upper computer to be 2, and adding 1 to the round counting of circularly reading one data packet; when the current data packet processing number of the upper computer is not more than the number of the data packets, adding 1 to the count of circularly reading one data packet in one round; when the ' one-round counting for circularly reading one data packet ' is not more than the number of the data packets ', processing the next data packet until the ' one-round counting for circularly reading one data packet ' is more than the number of the data packets, ending the circulation and entering the circulation for processing the data packets in the next round;
the upper computer is provided with a variable of 'cyclically reading a data packet number', and is used for reading a data packet without change data in each round in sequence when the upper computer does not read a change data packet after processing a round of data packets; the cyclic reading refers to sequential reading;
the variable of 'reading one data packet in a cycle and counting' is arranged in the upper computer and used for ensuring that one data packet in all subsequent data packets is read in a cycle.
Further, the data register in the first packet of the PLC controller stores frequently changing pure analog data and fills up the packet as much as possible.
Further, the status register set in the first packet of the PLC controller is selected to be two registers, one register, or three registers according to the data capacity to be stored, and the status register is placed at the beginning of the first packet or at the end of the first packet.
Furthermore, the first data packet of the PLC controller is only used as a data status packet, that is, only the status register is stored, and no data is stored, so that the data of the original first data packet is stored in the second data packet, the total number of the data packets is increased by one, and the subsequent data packets include the original first data packet.
Further, the PLC controller indicates the status of the subsequent data packet by using bits, or indicates the status by using a register, that is, "the PLC controller data packet has a changed data flag bit", "the PLC controller is storing the data packet flag bit", "the host computer is reading the data packet flag bit", or "the PLC controller data packet has a changed data flag register", "the PLC controller is storing the data packet flag register", "the host computer is reading the data packet flag register", or "the host computer data packet has a read completion flag register".
Furthermore, the current data packet 'upper computer data packet reading completion flag bit' is not set in the PLC, namely the PLC does not judge that the upper computer reads, and the storage is updated, so that the storage speed of the PLC is increased.
In the technical scheme provided above, the temporary storage data packets are added in the PLC controller, and the temporary storage data packets are compared and processed with the corresponding data packets one by one, and then the status register set in the first data packet transmits information with the upper computer, indicating that "the PLC controller data packet has a changed data flag bit", "the PLC controller is storing the data packet flag bit", "the upper computer is reading the data packet flag bit", and "the upper computer data packet reading completion flag bit" of each subsequent data packet. Therefore, the invalid transmission of the data packet without any change data in the traditional method is avoided under most conditions, and the communication transmission and data processing efficiency of the PLC and the upper computer are greatly improved.
In the process of comparing the change data of a certain subsequent data packet, once the change data is found, the PLC does not compare the data, marks the data packet as the data packet with the change data so as to be communicated and transmitted with an upper computer, and aims to reduce the CPU overhead of the PLC and increase the data processing rate.
The data register in the first data packet of the PLC controller stores frequently-changing pure analog data and occupies the data packet as full as possible. Because the first data packet is a special data packet, each round needs to be transmitted, and even if the pure analog quantity does not exceed the threshold value, the fluctuation lower than the threshold value can occur, and the upper computer can preferably reflect the fluctuation in time.
The method comprises the steps that data which are traditionally distinguished according to digital quantity and analog quantity are changed into data which are distinguished according to digital quantity, analog quantity which represents the digital quantity and pure analog quantity, namely the analog quantity is divided into the analog quantity which represents the digital quantity and the pure analog quantity, the analog quantity which represents the digital quantity, such as the starting times of a fan and the failure times of the fan, are regarded as the digital quantity to be compared and processed, and the times are regarded as the same when the data of the current time and the data of the last two times are the same; when the data is different, the times are considered to be changed, thereby simplifying the comparison and processing of analog quantities representing the numbers.
In most cases, the upper computer does not have the following data packets with changed data to be communicated, so a variable of circularly reading a data packet number is set in the upper computer, and when the upper computer does not process a changed data packet after processing a round of data packets, the upper computer sequentially reads a data packet without changed data in each round. For reading data packets of digital quantity and analog quantity representing digital quantity, although data is not changed, the reading is used for refreshing the data so as to prevent the data in the upper computer from being tampered due to memory leakage and the like; for the reading of the pure analog quantity data packet, although the pure analog quantity does not exceed the threshold value, the pure analog quantity still fluctuates slightly below the threshold value, and the purpose of the reading is to update the data. In this case, there is also an advantage that even if a subsequent packet of data, which has no change in the upper computer, needs to be read, a subsequent packet of data is still read.
And a variable of circularly reading a data packet and counting for one round is set in the upper computer for counting, a data packet which has no change and is not stored is searched and read, and when the count is greater than the number of the data packets, namely the PLC does not have the data packet, the PLC does not search the data packet any more and enters the judgment and processing of a new round of data packets.
The state register is arranged in the first data packet of the PLC, so that the efficiency of data transmission and processing is improved. The status register occupies several registers originally used for storing data in a data packet, and since a packet has 125 or more registers, the influence on the storage amount of the data is small.
Advantageous effects
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
by adopting the invention, in the first communication data packet, a plurality of data registers are occupied as the status registers for transmitting information with the upper computer. In the PLC controller, open up the space, place the data package of keeping in, the register that keeps in the data package of keeping in compares with the register that current data package corresponds, sets its state bit to the current data package that changes the data, reaches to the data package that changes the data and carries out focus reading, has obviously improved the reading speed and the processing speed of host computer to changing the data. In addition, the storage and reading states of the data packet are set, and the consistency of the data packet and the state bits is ensured.
Drawings
Fig. 1 is a logic diagram of PLC controller data processing.
FIG. 2 is a logic diagram of data processing of the upper computer.
Detailed Description
Referring to fig. 1 and 2, the present invention provides a method for improving communication transmission and data processing efficiency between a PLC controller and an upper computer, including a PLC controller data processing logic shown in fig. 1 and an upper computer data processing initialization logic shown in fig. 2.
In the application of PLC monitoring with large data volume and less data change, such as a subway station wind and water power system, the invention is preferably used for a short data packet, such as 125 registers of one data packet, and is not preferably used for a long data packet, such as 2000 registers of one data packet, because the number of registers contained in one data packet is increased, although the number of data packets can be reduced, if an analog quantity exceeding a threshold value exists in the long data packet or a variable digital quantity exists, the whole data packet must be transmitted for the data, so that the efficiency is low, and the use of the long data packet is inferior to the use of the short data packet.
In the PLC controller, a space is opened up, a temporary storage data packet is placed, a temporary storage register in the temporary storage data packet is compared with a register corresponding to the current data packet, and a 'PLC controller data packet has a changed data zone bit' is marked on the current data packet with changed data.
In addition, a flag bit of 'a data packet is being stored by a PLC controller', 'a data packet flag is being read by an upper computer', and 'an upper computer data packet reading completion flag' is set for each subsequent data packet, and the flag bit is used for limiting data storage of the data packet by the PLC controller and data packet reading completion of the upper computer so as to prevent one part of one data packet read by the upper computer from being old data and the other part from being new data, and further avoid possible inconsistency between the data packet and the state bit.
In some occasions where the storage speed of the PLC is sought to be improved and the upper computer is not sought to read each time of data, the storage can be updated without setting a current data packet 'upper computer data packet reading completion flag bit' in the PLC, namely the PLC does not judge that the upper computer reads the data completely.
The conventional method is not adopted, the conventional method for reading the PLC controller by the upper computer is not adopted, the upper computer reads each data packet in sequence whether the data packet has changed data or not, time is wasted, if sudden change data occurs, the upper computer does not necessarily exactly read the data packet with the changed data because the upper computer polls the data packet with the changed data, and under the worst condition, the upper computer just reads one data packet after the data packet has changed, the upper computer needs to poll the data packet once to read the data packet with the changed data, and if the total number of the data packets is more than ten, the time delay for feeding back the change data by the upper computer is the time for reading more than ten data packets, so that the change data is updated slowly. However, if the method of the invention is adopted:
in most cases, no subsequent data packet with changed data needs to be read, and the upper computer reads only one data packet without changed data in each round in sequence. If a changed data appears in the process of polling and reading a data packet without the changed data once, the upper computer can immediately read the data packet corresponding to the changed data in the next round of data packet processing, the time delay is the time for reading one data packet, and the reading speed is far higher than that of the traditional method.
When a subsequent data packet with changed data needs to be read, the upper computer immediately reads the data packet. If another data packet with changed data appears in the process of reading the data packet with changed data, the data packet with changed data can be immediately read in the next round of processing of the data packet, the time delay is the time for reading one data packet, and the reading speed is much higher than that of the traditional method.
When a subsequent data packet with changed data needs to be read, the upper computer immediately reads the data packet. If a plurality of other data packets with changed data appear in the process of reading the data packet with changed data, the data packets with changed data can be immediately read in the next round of processing of the data packet, the time delay is the time for reading one data packet, and the reading speed is much higher than that of the traditional method.
When a subsequent data packet with changed data needs to be read, the upper computer immediately reads the data packet. If an extreme condition occurs during the process of reading the data packet with changed data, namely, the changed data occurs in each data packet, each data packet is read in turn in the next round of processing of the data packet, and the reading speed is the same as that of the traditional method.
In addition, in the conventional method, it is very time-consuming for the upper computer to find changed data to perform subsequent processing in each round of reading of the data packet, but according to the method provided by the invention, a variable of 'the upper computer records the reading of the data packet with changed bits' of each subsequent data packet is set in the upper computer, and the variable is '1' to indicate that the subsequent data packet has changed data and is used for marking the subsequent data packet with changed data, so that the upper computer can perform subsequent processing on the changed data packet conveniently.
Claims (6)
1. A method for improving the communication transmission and data processing efficiency of a PLC and an upper computer is characterized in that,
the PLC is divided into two types, namely a PLC controller and a remote IO module;
the remote IO module has input and output functions of analog quantity and digital quantity and is used for measurement and control, and also has a function of communicating with the subsystem PLC;
the PLC has a communication function and a data processing function;
the communication function of the PLC controller is used for completing various communication tasks, including communication with an upper computer and communication with a lower computer, and the communication with the lower computer includes communication with a remote IO module, communication with a subsystem PLC and communication with a subsystem communication module, the communication tasks are not controlled by a user program of the PLC controller, after the communication configuration of the PLC controller is completed, the communication tasks are independently communicated, and the communicated data are accessed in a register for communication in the PLC controller;
the data processing function of the PLC is controlled by a user program, the data in the register for communication read by the communication function is logically judged, a decision is made, the data is written into the register for communication, and the communication function of the PLC is used for communication so as to achieve the purpose of control;
the register for communication of the PLC is filled according to a point table appointed with opposite communication side equipment, the opposite communication side equipment comprises an upper computer and a lower computer, and the lower computer comprises a remote IO module, a subsystem PLC and a subsystem communication module;
the PLC is communicated with an upper computer, data are stored in a plurality of communication data packets, the length of each data packet is limited by the length of a message communicated with the upper computer, the communication data packets are divided into three types, namely a digital quantity data packet, an analog quantity data packet for representing the digital quantity and a pure analog quantity data packet, the digital quantity data packet is used for placing the digital quantity, the analog quantity data packet for representing the digital quantity is used for placing the analog quantity for representing the digital quantity, and the pure analog quantity data packet is used for placing the pure analog quantity data; setting variables of each communication data packet, which are expressed as digital quantity, digital analog quantity and pure analog quantity, are stored in a PLC (programmable logic controller) and an upper computer;
the digital value is the switching value of the external contact, has two states of connection and disconnection, and is respectively represented by 0 and 1;
the analog quantity representing digital data is data for counting, is represented as an analog quantity, and is processed as a digital quantity;
the pure analog quantity refers to the value of fluctuation of measured voltage, current, temperature and humidity;
the aforementioned digital quantity and analog quantity representing the digital quantity are collectively referred to as a non-pure analog quantity;
the communication data packet consists of a plurality of data registers which are called communication registers;
each communication data packet comprises input data of a plurality of remote IO modules or input data of a plurality of subsystems;
a first communication data packet communicated with the upper computer by the PLC is used as a special data packet, and a plurality of data registers are occupied as state registers according to the total amount of the data packets and are used for transmitting information with the upper computer;
communication data packets except the first communication data packet for communication between the PLC and the upper computer are called subsequent data packets:
each bit of the status register is used for indicating that the PLC controller data packet of each subsequent data packet has a changed data flag bit, the PLC controller is storing the data packet flag bit, the upper computer is reading the data packet flag bit and the upper computer data packet reading completion flag bit;
definition of 'PLC controller data packet has change data flag bit': the number of the data packets is '1' and respectively and correspondingly indicates that at least one data in the data packets stored by the corresponding PLC controller is changed; the data packets are respectively and correspondingly represented as '0' and none of the data stored in the corresponding PLC controller is changed;
definition of "PLC controller is storing packet flag bit": the data packets are respectively and correspondingly represented as '1' and are stored by the PLC controller of the corresponding data packet; the data packets are respectively and correspondingly represented as '0' and are not stored in the PLC;
definition of "upper computer is reading flag bit of data packet": the data packets are respectively and correspondingly represented as '1' and are read by the upper computer of the corresponding data packet; the data packets are respectively and correspondingly indicated as '0' and the corresponding data packet upper computer is not reading;
definition of a reading completion flag bit of an upper computer data packet: the data packets are respectively and correspondingly read by the upper computer of the corresponding data packet with the number of 1; the data packets are respectively and correspondingly represented as '0' and are not read by the upper computer of the corresponding data packet;
opening a storage space in the PLC, and storing temporary storage data packets of subsequent data packets, wherein data registers in the temporary storage data packets are called temporary storage registers, each temporary storage register in the temporary storage data packets is completely consistent with the definition of a corresponding communication register in the communication data packets for communicating with the upper computer, and the data packets for communicating with the upper computer corresponding to the temporary storage data packets are called corresponding data packets; the register in the data packet for communicating with the upper computer corresponding to the temporary storage register is called as a corresponding data register;
when the PLC controller is initialized, the following operations are sequentially carried out: all subsequent data packets are 'the upper computer is reading the flag bit' position '0' of the data packet ', and all subsequent data packets are' the PLC controller is storing the flag bit 'position' 1 'of the data packet'; copying the data of the lower computer, which is obtained by the communication corresponding to each data packet and is stored in the register, into the data register corresponding to each data packet; all subsequent data packets with a changed data flag bit of '1' of the PLC controller data packet; all subsequent data packets "PLC controller is storing data packet flag bit" position "0";
when the PLC controller starts a normal processing flow, firstly copying data stored in a register of a lower computer obtained by communication and stored in the register corresponding to a first data packet into a data register corresponding to the first data packet; then copying the data of the lower computer obtained by the communication stored in the register corresponding to the subsequent data packet into the data register corresponding to the temporary storage data packet corresponding to the subsequent data packet;
the variable of the current data packet processing number of the PLC is set to be 2, and the variable of the current data packet processing number of the PLC is arranged in the PLC and is used for representing the number of a data packet currently processed by a program of the PLC;
the following enters the processing flow of the subsequent data packet: the variable of the current data packet register processing number of the PLC is set to be 1, and the variable of the current data packet register processing number of the PLC is arranged in the PLC and is used for indicating the number of a register in a data packet currently processed by a program of the PLC;
the PLC sequentially compares and processes the temporary storage data packets with the corresponding data packets one by one according to the pure analog quantity data packets and the non-pure analog quantity data packets for the subsequent data packets;
when the register of the current data packet has changed data, if the flag bit of the current data packet is '0' read by an upper computer, and the 'upper computer data packet reading completion flag bit' is '1', the 'PLC controller is storing the' position '1' of the data packet flag bit in the current data packet, the PLC controller data packet of the current data packet has a changed data flag bit of 1, the upper computer data packet of the current data packet has a reading completion flag bit of 0, the subsequent data of the data packet are not compared any more, all the data in the current temporary storage data packet are copied to the data register corresponding to the current data packet, after the copying operation is completed, adding 1 to the current data packet 'the PLC controller is storing the data packet flag bit' position '0', and entering the next cycle until the comparison of the data of all the subsequent data packets is completed; if the flag bit of the current data packet, which is being read by the upper computer, is '1' or the flag bit of the upper computer data packet read completion is '0', the flag bit setting and copying operation is abandoned, the current data packet processing number of the PLC controller is added with 1, and the next cycle is entered until the comparison of the data of all the subsequent data packets is completed;
when the comparison is completed and no changed data is found, if the flag bit of the current data packet that the upper computer is reading the data packet is '0' and the flag bit of the current data packet that the upper computer is reading the data packet is '1', the flag bit of the current data packet that the PLC controller is storing the data packet is '1', the flag bit of the current data packet that the PLC controller has the changed data is '0', and the flag bit of the current data packet that the upper computer is reading the data packet is '0'; for a pure analog quantity data packet, copying all data in the current temporary storage data packet to a data register corresponding to the current data packet, and for a non-pure analog quantity data packet, not performing the copying operation; then adding 1 to the flag bit ' position ' 0 ' of the data packet currently stored by the PLC controller of the current data packet, and entering the next cycle until the comparison of the data of all the subsequent data packets is completed;
the data registers are compared one by one to judge whether changes occur, including the comparison of pure analog quantity data packets and non-pure analog quantity data packets;
the comparison of the non-pure analog quantity, i.e. the comparison of the digital quantity or the analog quantity representing the digital quantity, means that the temporary storage registers are compared with the corresponding registers one by one, and when the temporary storage registers are inconsistent, the current temporary storage register is considered to be the change data;
the comparison of the pure analog quantities means that variables corresponding to the pure analog quantities are configured in the PLC, and are used for setting change threshold values and amplitude threshold values corresponding to the pure analog quantities, the numerical values of the temporary storage registers of the pure analog quantities are compared with the corresponding amplitude threshold values one by one, and when the numerical values exceed the amplitude threshold values, the current temporary storage registers are considered to be change data; subtracting the values of the temporary storage registers of the pure analog quantity and the corresponding register values one by one, and when the values exceed a change threshold value, considering that the current temporary storage registers are changed data;
the data packet "PLC controller data packet has changed data flag bit" position "0", which means that the data packet has no changed data, and for digital quantity data packet or analog quantity data packet representing digital quantity, each temporary storage register has the same value as the corresponding register, i.e. has no change; for a pure analog quantity data packet, the value of each temporary storage register does not exceed a set change threshold and an amplitude threshold;
in the upper computer, a variable of 'change data packet flag' of the upper computer is set, wherein the variable is '1', which indicates that a subsequent data packet with 'a change data flag bit' of '0' exists in the data packet processing of one round of the upper computer, and the 'PLC controller data packet has a change data flag bit' of '1', namely the subsequent data packet with change data needing to be processed by the upper computer;
in the upper computer, a variable of 'the upper computer records that the data packet reads a changed bit' of each subsequent data packet is set, wherein the variable of '1' indicates that the subsequent data packet has changed data, is used for marking the subsequent data packet with the changed data and is used for the upper computer to perform subsequent processing on the changed data packet; after the upper computer finishes processing the changed data packet, reading the changed position ' variable position ' 0 ' of the data packet ' recorded data packet of the upper computer ';
the upper computer of the first round of fingers processes all data packets in sequence once;
in the upper computer, a variable of 'the current data packet processing number of the upper computer' is set for recording the number of the data packet processed by the upper computer;
when the upper computer is initialized, setting a variable of 'circularly reading a data packet number' to '2';
when the upper computer starts a new round of data processing, unconditionally reading the data of the first data packet so as to respectively process the subsequent data packets in sequence according to the state register in the first data packet; setting the ' changed data packet mark ' of the upper computer to ' 0 ', reading the changed position ' 0 ' of the data packet recorded by the upper computer and ' 2 ' of the current data packet processing number of the upper computer ' of all subsequent data packets;
the upper computer does not process the subsequent data packet with the flag bit of the data packet being stored by the PLC controller being 1, adds 1 to the current data packet processing number of the upper computer and processes the next data packet;
for a subsequent data packet with a flag bit of '0' stored by a PLC (programmable logic controller) and a changed data flag bit of '0' of a data packet of the PLC, the upper computer reads the flag bit of '1' of the data packet, reads the flag bit of '0' of the data packet, adds 1 to the processing number of the current data packet, and processes the next data packet;
the upper computer carries out the following operations in sequence for the subsequent data packet with the flag bit of the data packet being stored by the PLC controller being 0 and the flag bit of the data packet of the PLC controller having changed data being 1: the method comprises the steps that a current data packet 'upper computer is reading a data packet flag bit' position '1', all data of the current data packet are read, the current data packet 'upper computer data packet reading completion flag bit' position '1', the current data packet 'upper computer is reading a data packet flag bit' position '0', 'the upper computer has a changed data packet flag' position '1', the current data packet 'upper computer records a data packet reading changed position' 1 ',' the upper computer current data packet processing number 'is added with 1', and then the next data packet is processed;
after the upper computer finishes the reading processing of the three data packets in all the subsequent data packets, when the changed data packet mark of the upper computer is '1', entering the cycle of processing the data packets in the next round; when the data packet flag of the upper computer is changed to be '0', circularly reading a data packet;
the above-mentioned circulation reads a data packet, the step is as follows sequentially: setting a count of reading one data packet circularly for 2, and assigning the value of the variable of reading one data packet circularly for the variable of processing the number of the current data packet of the upper computer;
when the current data packet 'PLC controller data packet has changed data flag bit' is '0' and the 'PLC controller is storing data packet flag bit' is '0', the following operations are performed in sequence: reading all data of a current data packet by using a flag bit position '1' of the data packet which is being read by an upper computer of the current data packet, reading a flag bit position '1' of the data packet reading completion of the upper computer of the current data packet, reading a flag bit position '0' of the data packet by the upper computer of the current data packet, adding 1 to a data packet number in a circulating manner, and entering the next cycle of processing the data packet by circularly reading a data packet number '2' when the data packet number in the circulating manner is larger than the data packet number; entering the next cycle of processing the data packets when the number of the data packets read circularly is not more than the number of the data packets; when the flag bit of the changed data of the current data packet 'PLC controller data packet' is '1' or the flag bit of the data packet 'being stored by the PLC controller' is '1', the following operations are sequentially carried out: adding 1 to the current data packet processing number of the upper computer, and when the current data packet processing number of the upper computer is greater than the number of the data packets, setting the current data packet processing number of the upper computer to be 2, and adding 1 to the round counting of circularly reading one data packet; when the current data packet processing number of the upper computer is not more than the number of the data packets, adding 1 to the count of circularly reading one data packet in one round; when the ' one-round counting for circularly reading one data packet ' is not more than the number of the data packets ', processing the next data packet until the ' one-round counting for circularly reading one data packet ' is more than the number of the data packets, ending the circulation and entering the circulation for processing the data packets in the next round;
the upper computer is provided with a variable of 'cyclically reading a data packet number', and is used for reading a data packet without change data in each round in sequence when the upper computer does not read a change data packet after processing a round of data packets; the cyclic reading refers to sequential reading;
the variable of 'reading one data packet in a cycle and counting' is arranged in the upper computer and used for ensuring that one data packet in all subsequent data packets is read in a cycle.
2. The method as claimed in claim 1, wherein the data register in the first packet of the PLC controller stores frequently-changing pure analog data and fills the packet as full as possible.
3. The method as claimed in claim 1, wherein the status register set in the first packet of the PLC controller is selected to be two registers, one register, or three registers according to the data capacity to be stored, and the status register is placed at the beginning of the first packet or at the end of the first packet.
4. The method as claimed in claim 1, wherein the first data packet of the PLC controller is only used as a data status packet, i.e. only stores the status register and does not store data, so that the data of the original first data packet is stored in the second data packet, the total number of the data packets is increased by one, and the subsequent data packets include the original first data packet.
5. The method as claimed in claim 1, wherein the PLC controller is configured to indicate the status of the subsequent data packet by using a bit, or indicated by a register, that is, the subsequent data packet is indicated by "PLC controller data packet has changed data flag bit", "PLC controller is storing data packet flag bit", "upper computer is reading data packet flag bit", "upper computer data packet reading completion flag bit", or indicated by "PLC controller data packet has changed data flag register", "PLC controller is storing data packet flag register", "upper computer is reading data packet flag register", or "upper computer data packet reading completion flag register".
6. The method as claimed in claim 1, wherein the PLC controller selects not to set the "upper computer data packet reading completion flag" of the current data packet, that is, the PLC controller updates the storage without determining that the upper computer has completed the reading, so as to increase the storage speed of the PLC controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010466104.7A CN111722581B (en) | 2020-05-28 | 2020-05-28 | Method for improving communication transmission and data processing efficiency of PLC and upper computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010466104.7A CN111722581B (en) | 2020-05-28 | 2020-05-28 | Method for improving communication transmission and data processing efficiency of PLC and upper computer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111722581A CN111722581A (en) | 2020-09-29 |
| CN111722581B true CN111722581B (en) | 2021-10-22 |
Family
ID=72565252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010466104.7A Active CN111722581B (en) | 2020-05-28 | 2020-05-28 | Method for improving communication transmission and data processing efficiency of PLC and upper computer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111722581B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113325798B (en) * | 2021-07-08 | 2021-11-02 | 宜科(天津)电子有限公司 | Sensor data processing system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1973279A (en) * | 2004-06-22 | 2007-05-30 | 横河电机株式会社 | Mutual access method of data and mutual access system of data |
| CN109960242A (en) * | 2017-12-25 | 2019-07-02 | 欧姆龙株式会社 | Control system and control device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2288957B (en) * | 1994-03-24 | 1998-09-23 | Discovision Ass | Start code detector |
| AUPR459801A0 (en) * | 2001-04-24 | 2001-05-24 | Canon Kabushiki Kaisha | A multi-agent system for digital home/office |
| US7152942B2 (en) * | 2002-12-02 | 2006-12-26 | Silverbrook Research Pty Ltd | Fixative compensation |
| US7334123B2 (en) * | 2003-05-02 | 2008-02-19 | Advanced Micro Devices, Inc. | Computer system including a bus bridge for connection to a security services processor |
| CN103885376A (en) * | 2012-12-19 | 2014-06-25 | 施耐德电器工业公司 | Programmable logic controller and event-driven programming method thereof |
-
2020
- 2020-05-28 CN CN202010466104.7A patent/CN111722581B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1973279A (en) * | 2004-06-22 | 2007-05-30 | 横河电机株式会社 | Mutual access method of data and mutual access system of data |
| CN109960242A (en) * | 2017-12-25 | 2019-07-02 | 欧姆龙株式会社 | Control system and control device |
Non-Patent Citations (2)
| Title |
|---|
| 《Design of Force Loading Monitor and Control System Based on LabVIEW》;Quan Bai;《2013 Fourth International Conference on Digital Manufacturing & Automation》;20131231;第466页-第469页 * |
| 《基于 PLC 的多工位刷光线加工机床控制系统设计》;缪泽宇;《组合机床与自动化加工技术》;20160930(第9期);第40页-第42页，第46页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111722581A (en) | 2020-09-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108197181B (en) | Compression storage method of time sequence data, electronic equipment and storage medium | |
| CN101853207B (en) | Storage device | |
| CN111722581B (en) | Method for improving communication transmission and data processing efficiency of PLC and upper computer | |
| CN101341450A (en) | Method, communication network, and control unit for the cyclical transmission of data | |
| CN105759679B (en) | Power down protection controller and its power-down retaining method | |
| CN105280222A (en) | Lower power consumption refresh system and method for improving resistive memory reliability | |
| CN108897577A (en) | A kind of server backplane CPLD state self-adaption system and method | |
| CN109254839A (en) | It determines the method in task triggered time, construct the method and system of task timer | |
| CN111291022B (en) | Data storage system based on block chain | |
| CN106776104A (en) | A kind of method of Nand Flash controllers and terminal and control Nand Flash | |
| CN111665778B (en) | Method for rapid communication transmission and data processing between PLC and upper computer | |
| WO2021007698A1 (en) | Memory device providing bad column repair and method of operating same | |
| CN100471175C (en) | Message storage forwarding method and message storage forwarding circuit | |
| US7685333B2 (en) | Method and system for communicating with memory devices utilizing selected timing parameters from a timing table | |
| CN103019302B (en) | Temperature variation-based dynamic time sequence adjustment method and device and network equipment | |
| CN106547716B (en) | A kind of expansion bus configuration system and method towards low pin number | |
| CN100394384C (en) | Method and system for on-line updating of network | |
| CN102393672A (en) | Programmable logic controller and expansion module thereof | |
| CN219041804U (en) | Dual Ethernet expansion module | |
| CN104077198A (en) | Doorbell (DB) recovery method and device and input/output (I/O) device comprising DB recovery device | |
| CN209591533U (en) | A kind of NOR Flash test macro based on FPGA | |
| CN116866852A (en) | NB-ioT network transmission method based on low-power consumption data record | |
| CN219551578U (en) | Networked environment temperature and humidity monitoring system | |
| KR100274644B1 (en) | Apparatus for interfacing data | |
| CN206946470U (en) | Flash controller with signal calibration device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221129 Address after: No. 19, Jiangning District, Jiangning District, Nanjing, Jiangsu Patentee after: NARI TECHNOLOGY Co.,Ltd. Patentee after: NARI Rail Transit Technology Co.,Ltd. Address before: No. 19, Jiangning District, Jiangning District, Nanjing, Jiangsu Patentee before: NARI TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right |