CN100471175C - Message storage forwarding method and message storage forwarding circuit - Google Patents
Message storage forwarding method and message storage forwarding circuit Download PDFInfo
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- CN100471175C CN100471175C CNB2006100615800A CN200610061580A CN100471175C CN 100471175 C CN100471175 C CN 100471175C CN B2006100615800 A CNB2006100615800 A CN B2006100615800A CN 200610061580 A CN200610061580 A CN 200610061580A CN 100471175 C CN100471175 C CN 100471175C
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Abstract
The disclosed message store and forward method and circuit can overcome the reading bandwidth loss as delay, and improves bandwidth utility and circuit performance greatly.
Description
Technical field
The present invention relates to store retransmission technique, especially relate to method and corresponding message storage repeat circuit that a kind of message storage is transmitted.
Background technology
The mechanism that in the application of network processes ASIC (application-specific integrated circuit (ASIC)), has handle packet, usually earlier data are stored by whole message, these messages use mass storage to store, these memories are independent of asic chip, as SRAM, DDR SRAM, according to certain scheduling mode, again data are read by putting in order message one by one then, be transmitted to next node or equipment.
Generally, network node has N logical channel, these logical channels are transmitted data by the time slot that takies physical link, storage-forwarding mechanism according to above-mentioned this whole message, at each logical channel, all be provided with an independently buffer area at this node, utilize the complete message of this buffer area storage, this buffer area is realized with memory device usually, the address that is about to memory is divided into several, each logical channel takies wherein one, can only visit one of them logical channel at each time slot.It is above-mentioned that to give the condition of next node or equipment with data forwarding be that at least one whole message must be arranged in the buffer area, therefore the key problem in technology point is how to judge whether at least one whole message is arranged in the memory, and can make does not waste the clock cycle of read operation in the data procedures of scheduling memory, guarantees that the data of at every turn reading all are useful.
In the prior art, message data is write in the external memory storage comprise: read write address when prepass from the write address memory cell; Judge whether current to write permission effective; If current writing allows effectively after write address adds 1 so, to be then written in the write address memory cell; If current writing allows invalidly, write address is constant so; Write enable signal according to written allowance signal with imitating the signal generation; Produce the address signal of reference to storage according to write address.
Wherein, whole message is that the form with one group of group data writes in the buffer area, and promptly the message data that writes in a clock cycle is a grouping, and wherein every group of data comprise several fields, the tail field is end-of-packet sign EOP (End Of Packet), whether this EOP is used for identifying message finishes, when EOP is effective, as EOP=1, the expression ENMES, when EOP was invalid, as EOP=0, the expression message did not have end.
When message data is read from external memory storage, whether be 1 to decide the read operation of a complete message whether to finish according to eop signal in the data of reading.
In existing message store and forward mode, a part of EOP end-of-packet sign being used as message data writes in the external memory storage, and the EOP counter is set in the logic of ASIC, when N logical channel, N EOP counter need be set, come to put in order having or not of message in the instruction memory by the value that reads this EOP counter; As shown in Figure 1, when going into a complete message to outside memory write, when promptly writing an effective EOP, this EOP counter is done to add 1 and is handled; When reading a complete message from external memory storage, when promptly reading an effective EOP, this EOP counter is done to subtract 1 and is handled; When having simultaneously when writing and reading a complete message, the value of this EOP counter is constant; Judge the value of EOP counter again, when the value of EOP counter was 0, expression did not have message in the buffer area, current read to allow invalid; When the value of EOP counter is not 0, also have message in the expression buffer area, currently read to allow effectively;
Wherein, read from external memory storage and also comprise before the effective EOP: reading of data and judge whether the EOP of these data is effective from external memory storage if EOP is effective, is only and reads an effective EOP from external memory storage.
Yet there is following problem in above-mentioned message store and forward mode:
One, read data loss of bandwidth
The asic chip access external memory postpones big, calculates by the clock cycle, from reading data to whether logical requirement of judgment data, needs the clock cycle more than 2 or 2 usually.If do continuous read operation, be that it is excessive that read pointer has been read, and mutiread has been got data from external memory storage when wrapping tail when judging the data of reading, at this moment read pointer needs rollback, and the hash that mutiread is come out filters out.Therefore the clock cycle that postpones and the time of read pointer rollback just are equivalent to slattern, and can not carry out the active data read-write, have therefore caused the read data loss of bandwidth;
Two, the confusion of logic and endless loop
Because need read in data from the asic chip outside carries out logic determines in the asic chip and judges promptly whether eop signal is 1, and the outer signal of asic chip is vulnerable to outside interference, for example EOP=1 becomes EOP=0 after disturbed, signal after disturbed like this enters into logic inside when judging, will cause the confusion and the endless loop of logic.
Summary of the invention
The method and the message storage repeat circuit that the object of the present invention is to provide a kind of message storage to transmit are to improve the wide utilance of tape reading of memory.
To achieve these goals, the invention provides following technical scheme:
The method that a kind of message storage is transmitted is provided with one and is used to store the required memory module of reading the last bag tail address of address and write address and each logical channel of each logical channel access external memory, and this method comprises the steps:
Write address according to the logical channel that receives with this passage of imitating signal and from memory module, reading, produce and export to write and enable and write address, and when receiving effective eop signal, export described effective eop signal corresponding condition information and this write address is write memory module as bag tail address; Described conditional information comprises control signal or write address information;
Read address and bag tail address according to the read request of the logical channel that receives and this passage of from memory module, reading, produce and export and read to enable and read the address, and when receiving described conditional information, read address and bag tail address according to this conditional information and this, the generation next one clock cycle read to allow signal;
Enable external memory storage is carried out read-write operation according to read/write address that receives and read-write.
A kind of message storage repeat circuit, described circuit comprises message storage transmitting controller and memory control unit;
Described message storage transmitting controller comprises writing module, memory module and read through model; Wherein,
Described writing module is according to the write address with this passage of imitating signal and reading from memory module of the logical channel that receives, produce and export to write and enable to give memory control unit with write address, and when receiving effective eop signal, export described effective eop signal corresponding condition information and give read through model and this write address is write memory module as bag tail address; Described conditional information comprises control signal or write address information;
Described memory module is used to store the required last bag tail address of reading address and write address and each logical channel of each logical channel access external memory;
Described read through model is read address and bag tail address according to the read request of the logical channel that receives and this passage of reading from memory module, produce and export and read to enable and read the address to memory control unit, and when receiving described conditional information, read address and bag tail address according to this conditional information and this, the generation next one clock cycle read to allow signal;
Described memory control unit enables external memory storage is carried out read-write operation according to the read/write address and the read-write that receive.
Owing to adopted such scheme, the present invention to have following beneficial effect:
The present invention utilizes the EOP address storaging unit of message storage repeat circuit inside to store the bag tail address of each logical channel, bag tail address by reading circuit of the present invention inside and read the address and compare in real time again, if two addresses are identical and the current mantissa of not wrapping according to writing, then think externally whole message in the memory of current logical channel, and determine the next clock cycle read to allow invalid, when the next clock cycle arrives, then switch to other logical channel immediately, solved the problem of prior art read data loss of bandwidth, thereby situation for multi-logical channel, can improve the wide utilance of tape reading of memory greatly, greatly improve the performance of message storage repeat circuit;
The present invention by decision circuitry inside the address rather than memory in data, can evade the big shortcoming of memory read operation time-delay, thereby, reach the purpose that shortens time-delay by making full use of the little advantage of circuit internal storage unit read-write time-delay;
The present invention program does not need the outer signal of message storage repeat circuit is judged in addition, has avoided the confusion or the endless loop of the internal logic that causes owing to external disturbance in the prior art, thereby has strengthened the robustness of circuit of the present invention.
Description of drawings
Fig. 1 judges in the existing message store and forward mode that memory has or not the flow chart of message;
Fig. 2 is the structure chart of first embodiment of message storage repeat circuit provided by the invention;
Fig. 3 is the structure chart of second embodiment of message storage repeat circuit provided by the invention;
Fig. 4 is Fig. 2 and shown in Figure 3ly reads to read in the judging unit enable state transition diagram;
Fig. 5 is the write operation flow chart in the message store and forward mode of the present invention;
Fig. 6 is that the judging unit of reading shown in Figure 2 produces the flow chart of reading to allow signal;
Fig. 7 is the read operation flow chart in the message store and forward mode of the present invention;
Fig. 8 is a sequential schematic diagram of the present invention.
Embodiment
The invention provides a kind of message store and forward mode and corresponding message storage repeat circuit, external memory storage is carried out the problem that the read data Time Bandwidth is lost to solve prior art.For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Core concept of the present invention is: in message storage repeat circuit, corresponding each logical channel all is provided with a memory cell, this space is used for preserving the address that each logical channel writes last bag mantissa certificate of external memory storage and promptly wraps the tail address, when this circuit receives read request, read the bag tail address of reading address and current logical channel of current logical channel in the memory module from this circuit, both are compared, again according to comparative result and the current bag mantissa certificate that whether writes, determine having or not of message in the external memory storage, the corresponding next clock cycle of output read to allow signal, when the next clock cycle arrives, read to allow signal whether effective by judgement, thereby realize the forwarding of reading message data in the external memory storage.
Below in conjunction with accompanying drawing message storage repeat circuit of the present invention is described, see also Fig. 2 and shown in Figure 3, message storage repeat circuit provided by the invention comprises: message storage transmitting controller 100 and memory control unit 200, wherein, memory control unit 200 is as a control unit relevant with plug-in type of memory, and the read/write address and the read-write that are used for message is stored transmitting controller 100 outputs enable to be converted into the required sequential of external memory storage and external memory storage is carried out read-write operation.Consider that memory control unit 200 is prior art, is not described in detail at this.
Message storage transmitting controller 100 comprises: writing module 300, memory module 400 and read through model 500, wherein, writing module 300 is according to the write address with this passage of imitating signal and reading from memory module 400 of the logical channel that receives, produce and export to write and enable to give memory control unit 200 with write address, and when receiving effective eop signal, output corresponding conditions information is given read through model and this write address is write memory module 400 as bag tail address;
Read through model 500 is read address and bag tail address according to the read request of the logical channel that receives and this passage of reading from memory module 400, produce and export and read to enable and read the address to memory control unit 200, and when receiving conditional information, according to this conditional information and read read address and bag tail address, generation reads to allow signal.
As shown in Figure 2, first embodiment for message storage transmitting controller, wherein memory module 400 comprises EOP address storaging unit 401, reads address storaging unit 402 and write address memory cell 403, this EOP address storaging unit 401 is used for storing each logical channel and promptly wraps the tail address to the address that external memory storage writes last bag mantissa certificate, be specially in this EOP address storaging unit 401 the up-to-date bag tail address that each logical channel is stored this passage to there being memory block, an EOP address to be used to; This is read address storaging unit 402 and is used to store the needed address of reading of each logical channel access external memory, be specially at this and read in the address storaging unit 402, each logical channel is used to store the needed address of reading of this channel access external memory storage to a memory block should be arranged; This write address memory cell 403 is used to store the needed write address of each logical channel access external memory, be specially in this write address memory cell 403, each logical channel is used to store the needed write address of this channel access external memory storage to a memory block should be arranged;
Wherein, this EOP addressed memory 401 can be last two parts that logic is separate of a physical storage (writing the side memory) with write address memory 403, and this reads addressed memory 402 is another independently physical storage (reading the side memory); Also can be with this EOP address storaging unit 401, read address storaging unit 402 and write address memory cell 403 is configured to three independently physical storages.
Writing module 300 comprises EOP address updating block 301 and write operation module 304, wherein write operation module 304 is read address and write address according to what receive logical channel with this passage of imitating signal and reading from memory module 400, output is write and is enabled to give memory control unit 200 with write address, and write address output information and index signal are given EOP address updating block 301 simultaneously;
As shown in Figure 2, write operation module 304 specifically comprises to be write judging unit 302 and writes control unit 303, when receive when imitating signal, in present clock period:
Write the write address of reading the address and from write address memory cell 403, reading that 302 pairs of judging units read and compare from read address storaging unit 402, produce and the corresponding next clock cycle written allowance signal of output is given and write control unit 303 according to comparative result when prepass when prepass; Because of considering it is prior art, be not described in detail at this;
Write control unit 303 and judge whether the current written allowance signal that receives (write on the judging unit 302 a clock cycle output) is effective, according to judged result and from write address memory cell 403, read when the write address of prepass, output is write accordingly and is enabled to export corresponding indicating signals simultaneously for memory control unit 200 with write address and write address information is given E0P address updating block, and the write address when prepass in the write address memory cell 403 is correspondingly processed; Specific as follows: if write permission effectively, then output is effectively write and is enabled to memory control unit 200, sends effective index signal to EOP address updating block 301, and to after the write address of prepass does to add 1 processing, writing in the write address memory cell 403; Allow invalidly if write, then export invalid writing and enable, send invalid index signal to EOP address updating block 301 to memory control unit 200, when the write address of prepass constant.
EOP address updating block 301 is used for when receiving effective index signal, judge whether the eop signal that receives is effective, if EOP is effective, then export effective control signal and give and to read judging unit 501 in the read through model 500, and the write address that receives is write in the EOP address updating block 401 as bag tail address; If EOP is invalid, then exports invalid control signal and give and to read judging unit 501 in the read through model 500, and write address is not dealt with; Perhaps, EOP address updating block 301 is used for when receiving effective index signal, judge whether the eop signal that receives is effective, if EOP is effective, then the write address that receives is sent to and read judging unit 501 in the read through model 500, and the write address that receives is write EOP address updating block 401 as bag tail address; If EOP is invalid, then do not deal with.
For example eop signal is a logical one, and write address is write memory module 400 or covers original bag tail address in the memory module 400 as bag tail address, and making the content in the memory module 400 is the up-to-date bag tail address of each logical channel; Eop signal is a logical zero, keeps original bag tail address in the memory module, does not do to upgrade and handles.
As shown in Figure 2, read through model 500 comprises and reads judging unit 501 and read control unit 502; When receiving the read request of logical channel, in present clock period:
Read the read request of judging unit 501 according to the logical channel that receives, the address of reading to the bag tail address of this passage of reading from EOP address storaging unit 401 and this passage of reading from read address storaging unit 402 compares, if current EOP address updating block 301 is sent conditional information, then according to comparative result and the conditional information that receives, the next clock cycle of output reads to allow signal to give and reads control unit 502;
As shown in Figure 3, second embodiment for message storage transmitting controller is with first embodiment difference: in present clock period:
Write control unit 303 be used for when receive logical channel when imitating signal, judge the current written allowance signal receive (write on the judging unit clock cycle output) whether effectively and the write address of reading the address and from write address memory cell 403, reading when prepass that will from read address storaging unit 402, read when prepass send into and write judging unit 302, and write accordingly according to judged result output and to enable to give memory control unit 200 with write address, export corresponding indicating signals and write address information simultaneously and give EOP address updating block 301 and the write address when prepass in the write address memory cell 403 is correspondingly processed; Be specially: if judged result allows effectively for writing, then output is effectively write and is enabled to memory control unit 200, send effective index signal to EOP address updating block 301, and to after the write address of prepass does to add 1 processing, writing in the write address memory cell 403; If judged result allows invalidly for writing, then export invalid writing and enable to memory control unit 200, send invalid index signal to EOP address updating block 301, when the write address of prepass constant;
Write judging unit 302 according to the logical channel that receives with imitating signal, to receive read the address and write address compares, give according to the written allowance signal of corresponding next clock cycle of comparative result output and write control unit 303; Consideration is a prior art, is not described in detail at this.
In read through model 500, in present clock period:
Read control unit 502, be used for when receiving the read request of logical channel, judge that receive current read to allow signal (read on the judging unit 501 a clock cycle output) whether effective, and will from EOP address storaging unit 401, read send to and read judging unit 501 when the bag tail address of prepass and the address of reading that from read address storaging unit 402, reads when prepass, and output reads accordingly to enable and read that memory control unit 200 is given in the address and the address of reading when prepass is correspondingly processed in the address storaging unit 403 to reading according to judged result; Be specially: if judged result is currently to read to allow effectively, then output effectively reads to enable to memory control unit 200, and the address of reading that will work as prepass is done to add to write after 1 processing again and studied in the address storaging unit 402; If judged result is currently to read to allow invalid, then export and invalidly read to enable to memory control unit 200, when prepass to read the address constant;
Reading judging unit 501 is used for when receiving the read request of logical channel, to receive read the address and bag tail address compares, if current EOP address updating block 301 is sent conditional information, then according to comparative result and the conditional information that receives, the reading of corresponding next clock cycle of output allows signal to give and reads control unit 502.
In first and second embodiment of message storage transmitting controller, can also export to simultaneously by the written allowance signal of writing the next clock cycle that judging unit 302 will produce and write control unit 303 and EOP address updating block 301, when the next clock cycle arrives, oneself judge by EOP address updating block 301 whether the written allowance signal that receives is effective; Can also write address information be sent to EOP address updating block 301 by writing judging unit 302.
Reading judging unit 501 is emphasis of the present invention, below introduce in detail and read judging unit 501 and produce the process of reading to allow signal, see also shown in Figure 4ly, Fig. 4 has disclosed various state exchanges and the control corresponding condition of reading to read in the judging unit to allow signal:
To receive the control signal that EOP address updating block sends be example to read judging unit, read to allow the various state exchanges of signal to describe in the judging unit to reading below, when system reset (condition 1), read state machine in the judging unit and enter and read to allow disarmed state (state 1); Allow under the disarmed state reading, the control signal that EOP address updating block sends judged, if control signal for effectively promptly writing a bag tail address (condition 3) the next clock cycle enter and read to allow effective status (state 2); Write (condition 2) then next clock cycle and remain on and read to allow disarmed state (state 1) if control signal is the invalid tail address of promptly not wrapping;
Allow under the effective status (state 2) reading, the bag tail address of reading address and current logical channel of the current logical channel that obtains is compared, if current EOP address updating block is sent control signal, then simultaneously the control signal that receives is judged, when reading the address with bag tail address when inequality (condition 4), the then next clock cycle remains on reads to allow effective status (state 2); The address is identical with bag tail address when reading, and control signal is for effectively being current when having new bag tail address to write (condition 5), and the then next clock cycle remains on reads to allow effective status (state 2); The address is identical with bag tail address when reading, and control signal be invalid be current when not having new bag tail address to write (condition 6), the then next clock cycle enters reads to allow disarmed state (state 1).
For reading the example that judging unit receives the write address that EOP address updating block sends, be not described in detail at this.
See also shown in Figure 5ly, Fig. 5 has disclosed the write operation flow process of current logical channel, describes below in conjunction with Fig. 2,3.
When receive current logical channel when imitating signal,
Step S101 reads the write address when prepass from the write address memory cell, and judges whether current to write permission effective; If current writing allows effectively then to go to step S102; If current writing allows invalidly, then go to step S103.
Step S102 utilizes this write address, message data is write in the external memory storage, and this write address is done to add 1 write in the write address memory cell after handling; Judge simultaneously whether the eop signal in the message data that receives is effective, if eop signal is effective, then goes to step S1021; If eop signal is invalid, then go to step S1022.
Step S1021 writes this write address in the EOP address storaging unit when the prepass corresponding storage as bag tail address, exports corresponding condition information simultaneously; This information can be control signal, also can be this write address.
Wherein, before writing, if working as the prepass corresponding storage in the EOP address storaging unit is non-NULL, then this write address is covered original bag tail address as up-to-date bag tail address, make that what store in the EOP address storaging unit is up-to-date bag tail address in the prepass corresponding storage, just the bag tail address of last message.
Step S1022 keeps original EOP address in the memory block, EOP address, does not do to upgrade and handles.
Step S103 does not make data writing operation.
See also Fig. 6 and shown in Figure 7, disclosed the read operation flow process of current logical channel, describe below in conjunction with Fig. 2.
Before introducing the read operation flow process, need to introduce earlier the flow process of reading to allow the signal generation, that is judge that external memory storage has or not method of message, memory wherein to be judged can be one, also can be a plurality of; When being a memory, this memory is divided into a plurality of buffer areas, and each buffer area is disposed respectively gives relative logic channel; When being a plurality of memory, each logical channel disposes a memory respectively.
When receiving the read request of current logical channel:
Step S201 from read address storaging unit, read current logical channel read the address time, the bag tail address of from the EOP address storaging unit, reading current logical channel;
Step S202 relatively this whether read the address identical with bag tail address, if identical, execution in step S203 then; If inequality, execution in step S204 then.
Step S203 determines currently whether receive the conditional information that EOP address updating block sends, if receive conditional information, and this information is control signal, then execution in step S2031a; If receive conditional information, and this information is write address, then execution in step S2031b; If do not receive conditional information, execution in step S2032 then;
Step S2031a judges whether this control signal is effective, if effectively, and execution in step S2031a1 then; If invalid, execution in step S2031a2 then;
Step S2031a1 determines that whole message is arranged in the external memory storage, and the next clock cycle of generation reads to allow useful signal;
Step S2031a2 determines not have whole message in the external memory storage, and the next clock cycle of generation reads to allow invalid signals;
Step S2031b determines that whole message is arranged in the external memory storage, and the next clock cycle of generation reads to allow useful signal;
Step S2032 determines not have whole message in the external memory storage, and the next clock cycle of generation reads to allow invalid signals;
Step S204 determines that whole message is arranged in the external memory storage, and the next clock cycle of generation reads to allow useful signal;
Then introduce the read operation flow process of current logical channel below:
When the read request that receives when prepass,
Whether step S301 reads the address of reading when prepass from read address storaging unit, and judge and currently read to allow signal effective, if currently read to allow effectively, and execution in step S302 then; If current read to allow invalid, execution in step S303 then;
Step S302 utilizes this to read the address, and message data is read forwarding from external memory storage, and this is read the address do to add 1 and write after handling and study in the address storaging unit;
Step S303 stops when the read operation of prepass or switches to other logical channels carrying out read operation immediately;
With reference to figure 8, it is sequential schematic diagram of the present invention, wherein the up-to-date EOP address of logical channel 0 is 5, reading address signal represents current just in the address of reading of read channel 0, read the message data of 5 logical channels 0 among the figure continuously, when the value of reading the address with when the up-to-date E0P of prepass address equates (all being 5 among the figure), passage switches index signal and becomes high level, passage 0 has or not the bag index signal to become low level, represent that this logical channel 0 read message empty (last bag mantissa of this logical channel 0 is according to reading), switch to logical channel 1 simultaneously and promptly read the address that address signal switches to logical channel 1, proceed read operation, wherein passage 1 has or not the bag index signal to be in high level indication logical channel 1 message, the EOP address of logical channel 1 is 7, from Fig. 8, can see and read to enable to be high level always, therefore not waste a clock cycle.
The present invention utilizes the EOP address storaging unit of message storage repeat circuit inside to store the up-to-date bag tail address of each logical channel, bag tail address by reading circuit of the present invention inside and read the address and compare in real time again, if two addresses are identical and the current mantissa of not wrapping according to writing, then think externally whole message in the memory of current logical channel, it is invalid that definite next clock cycle reads to allow, when the next clock cycle arrives, then switch to other logical channel immediately, solved the problem of prior art read data loss of bandwidth, thereby situation for multi-logical channel, can improve the wide utilance of tape reading of memory greatly, greatly improve the performance of message storage repeat circuit;
The present invention by judging message storage repeat circuit inside the address rather than external memory storage in data, can evade the big shortcoming of external memory storage read operation time-delay, thereby, reach the purpose that shortens time-delay by making full use of the little advantage of circuit internal storage unit read-write time-delay;
The present invention program does not need the outer signal of message storage repeat circuit is judged in addition, has avoided the confusion or the endless loop of the internal logic that causes owing to external disturbance in the prior art, thereby has strengthened the robustness of circuit of the present invention.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (20)
1, a kind of method of message storage forwarding, it is characterized in that, be provided with one and be used to store the required memory module of reading the last bag tail address of address and write address and each logical channel of each logical channel access external memory, this method comprises the steps:
Write address according to the logical channel that receives with this passage of imitating signal and from memory module, reading, produce and export to write and enable and write address, and when receiving effective eop signal, export described effective eop signal corresponding condition information and this write address is write memory module as bag tail address; Described conditional information comprises control signal or write address information;
Read address and bag tail address according to the read request of the logical channel that receives and this passage of from memory module, reading, produce and export and read to enable and read the address, and when receiving described conditional information, read address and bag tail address according to this conditional information and this, the generation next one clock cycle read to allow signal;
Enable external memory storage is carried out read-write operation according to read/write address that receives and read-write.
2, the method for claim 1 is characterized in that, described method also comprises: when receiving invalid eop signal,
Keep original bag tail address in the memory module, do not do to upgrade and handle.
3, the method for claim 1 is characterized in that, described method also comprises: when not receiving conditional information, read address and bag tail address according to this, what produce the next clock cycle reads to allow signal.
4, method as claimed in claim 3 is characterized in that, this reads address and bag tail address described basis, produce the next clock cycle read allow the step of signal to comprise:
Read the address when identical with bag tail address when this, what produce the next clock cycle reads to allow invalid signals;
Read the address with bag tail address when inequality when this, what produce the next clock cycle reads to allow useful signal.
5, the method for claim 1, it is characterized in that, described write address with this passage of imitating signal and from memory module, reading according to the logical channel that receives, produce and export to write and enable and write address, and when receiving effective eop signal, output corresponding conditions information also comprises this write address as the step that bag tail address writes memory module:
According to the logical channel that receives with this passage of imitating signal and from memory module, reading read address and write address, output is write and is enabled and write address, simultaneously write address output information and index signal or the written allowance signal of next clock cycle;
When the written allowance signal that produced when a last clock cycle of judging the index signal that receives or receive is effective for eop signal effective and that receive, sends corresponding conditions information and the write address that receives is write memory module as bag tail address.
6, the method for claim 1, it is characterized in that, described according to the logical channel that receives read request and this passage of from memory module, reading read address and bag tail address, produce and export and read to enable and read the address, and when receiving conditional information, read address and bag tail address according to this conditional information and this, the reading of generation next one clock cycle allows the step of signal to comprise:
Allowed signal and reading of from memory module, reading to produce also output and read to enable and read the address accordingly in the address according to reading of producing of the read request of the logical channel that receives and last clock cycle of receiving;
When receiving conditional information, according to this conditional information and to the bag tail address that from memory module, reads with read address result relatively, produce and the next clock cycle of output read to allow signal.
7, the method for claim 1, it is characterized in that, described according to the logical channel that receives read request and this passage of from memory module, reading read address and bag tail address, produce and export and read to enable and read the address, and when receiving conditional information, read address and bag tail address according to this conditional information and this, the reading of generation next one clock cycle allows the step of signal to comprise:
According to the read request of the logical channel that receives, the bag tail address that will from memory module, read and read address output, and in conjunction with a last clock cycle that receives produce read to allow signal, output reads to enable and read the address accordingly;
When receiving conditional information, according to this conditional information and to the bag tail address that receives with read address result relatively, produce and the next clock cycle of output read to allow signal.
As claim 6 and 7 described methods, it is characterized in that 8, described according to this conditional information and to wrapping the tail address and reading address result relatively, the step of reading to allow signal also to export that produces the next clock cycle comprises:
When this passage to read the address identical with bag tail address, and this conditional information is when being effective control signal or write address information, produces the next clock cycle to read to allow useful signal and output;
When passage read address and bag tail address when inequality, produce the next clock cycle to read to allow useful signal and output;
When this passage read the address when identical with bag tail address, and this conditional information is when being invalid control signal, produces the next clock cycle to read to allow invalid signals and output.
9, as claim 4 and 8 described methods, it is characterized in that, described produce the next clock cycle read also comprise step after allowing the step of invalid signals:
Stop immediately working as prepass or switching to other logical channels.
10, a kind of message storage repeat circuit is characterized in that described circuit comprises message storage transmitting controller and memory control unit;
Described message storage transmitting controller comprises writing module, memory module and read through model; Wherein,
Described writing module is according to the write address with this passage of imitating signal and reading from memory module of the logical channel that receives, produce and export to write and enable to give memory control unit with write address, and when receiving effective eop signal, export described effective eop signal corresponding condition information and give read through model and this write address is write memory module as bag tail address; Described conditional information comprises control signal or write address information;
Described memory module is used to store the required last bag tail address of reading address and write address and each logical channel of each logical channel access external memory;
Described read through model is read address and bag tail address according to the read request of the logical channel that receives and this passage of reading from memory module, produce and export and read to enable and read the address to memory control unit, and when receiving described conditional information, read address and bag tail address according to this conditional information and this, the generation next one clock cycle read to allow signal;
Described memory control unit enables external memory storage is carried out read-write operation according to the read/write address and the read-write that receive.
11, circuit as claimed in claim 10 is characterized in that, described writing module also is used for when receiving invalid eop signal, keeps original bag tail address in the memory module, does not do to upgrade and handles.
12, circuit as claimed in claim 10 is characterized in that, described read through model also is used for when not receiving conditional information, reads address and bag tail address according to this, and what produce the next clock cycle reads to allow signal.
13, circuit as claimed in claim 12 is characterized in that, described read through model is used for reading the address when identical with bag tail address when this, and what produce the next clock cycle reads to allow invalid signals.
14, circuit as claimed in claim 10 is characterized in that, described writing module comprises write operation module and EOP address updating block;
Described write operation module is read address and write address according to the logical channel that receives with this passage of imitating signal and reading from memory module, generation and output are write and are enabled to give memory control unit with write address, and write address output information and index signal or the written allowance signal of next clock cycle are to EOP address updating block simultaneously;
Described EOP address updating block is used for the written allowance signal that produces when clock cycle on the write operation module of judging the index signal that receives or receiving for effectively and the eop signal that receives when being effective, sends corresponding conditions information and gives read through model and the write address that receives is write memory module as bag tail address.
15, circuit as claimed in claim 10 is characterized in that, described read through model comprises to be read judging unit and read control unit;
Described read control unit according to reading of producing of the read request of the logical channel that receives and last clock cycle of receiving allow signal and from memory module, read read the address, output reads to enable and read the address accordingly;
The described judging unit of reading is used for when receiving conditional information, according to this conditional information and to the bag tail address that from memory module, reads with read address result relatively, produce and the next clock cycle of output read allow signal to give to read control unit.
16, circuit as claimed in claim 10 is characterized in that, described read through model comprises to be read judging unit and read control unit;
The described read request of reading control unit according to the logical channel that receives, the bag tail address that will from memory module, read and read the address and export to and read judging unit, and in conjunction with reading on the judging unit of receiving a clock cycle produces reads to allow signal, output is read to enable and read the address accordingly and is given memory control unit;
The described judging unit of reading is used for when receiving conditional information, according to this conditional information and to the bag tail address that receives with read address result relatively, produce and the next clock cycle of output read allow signal to give to read control unit.
17, as claim 15 and 16 described circuit, it is characterized in that, the described judging unit of reading is used for when comparative result is effective control signal or write address information for reading address and conditional information identical with bag tail address, produce and the next clock cycle of output read allow useful signal to give to read control unit.
18, as claim 15 and 16 described circuit, it is characterized in that, described read judging unit be used for when comparative result for reading address and bag tail address when inequality, produce and the next clock cycle of output read allow useful signal to give to read control unit.
19, as claim 15 and 16 described circuit, it is characterized in that, the described judging unit of reading is used for when comparative result is invalid control signal for reading address and conditional information identical with bag tail address, produce and the next clock cycle of output read allow invalid signals to give to read control unit.
20, circuit as claimed in claim 10 is characterized in that, described memory module specifically comprises:
The EOP address storaging unit is used to store the last bag tail address of each logical channel;
Read address storaging unit, be used to store each logical channel access external memory required read the address;
The write address memory cell is used to store the required write address of each logical channel access external memory.
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| CNB2006100615800A CN100471175C (en) | 2006-07-10 | 2006-07-10 | Message storage forwarding method and message storage forwarding circuit |
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| CNB2006100615800A CN100471175C (en) | 2006-07-10 | 2006-07-10 | Message storage forwarding method and message storage forwarding circuit |
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| CN101246460A (en) | 2008-03-10 | 2008-08-20 | 华为技术有限公司 | Caching data writing system and method, caching data reading system and method |
| CN105242768B (en) * | 2015-10-09 | 2018-09-18 | 天津国芯科技有限公司 | The Biodge device that the low-power consumption high speed ahb bus of clock control can be divided to access polylith SRAM |
| CN108268238A (en) * | 2018-01-24 | 2018-07-10 | 深圳市风云实业有限公司 | Data processing method, device, computer storage media and FIFO device |
| CN114449030B (en) * | 2021-12-27 | 2024-03-12 | 天翼云科技有限公司 | Internet service system, method, electronic equipment and storage medium |
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