CN109285580A - Data prediction device, method and asynchronous double-end randon access memory system - Google Patents
Data prediction device, method and asynchronous double-end randon access memory system Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
Abstract
The present invention provides a kind of data prediction device, method and asynchronous double-end randon access memory systems；Wherein, which includes sequentially connected first read-write control circuit, the first data caching circuit, the second data caching circuit and the second read-write control circuit；First data caching circuit is for receiving and caching the first write request；First read-write control circuit is used to be stored the first write-in data into asynchronous double-end random access memory according to the first data address；Second data caching circuit is for receiving and caching the first write request；Second read-write control circuit reads request for receiving first, and according to the internal data of the write request of the preset quantity cached in the second data caching circuit and asynchronous double-end random access memory, output first, which is read, requests corresponding data.The present invention improves the working efficiency of asynchronous double-end random access memory.
Description
Technical field
The present invention relates to field of computer technology, more particularly, to a kind of data prediction device, method and asynchronous double-end
Randon access memory system.
Background technique
Dual port RAM (Random Access Memory, random access memory)) it is in a SRAM (Static Random
Access Memory, Static RAM) on have two sets of completely self-contained data lines, address wire and read-write control line, and
Two independent systems are allowed to carry out the access of randomness, i.e., shared multiport memory to the memory simultaneously
Dual port RAM in use it is noted that the problem of be how to avoid both ends to the contention of same ram memory cell；Usually
The problem is solved using the anti-collision mode of insertion wait state, signal lamp anti-collision mode or interruption anti-collision mode
Certainly.However, being directed to asynchronous double-end RAM, the working efficiency of above-mentioned several anti-collision modes is lower.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of data prediction device, method and asynchronous double-ends to deposit at random
Access to memory system, to improve the working efficiency of asynchronous double-end random access memory.
In a first aspect, the embodiment of the invention provides a kind of data prediction device, which deposits at random with asynchronous double-end
Access to memory connection；The device includes that sequentially connected first read-write control circuit, the first data caching circuit, the second data are slow
Deposit circuit and the second read-write control circuit；The first port of first read-write control circuit and asynchronous double-end random access memory connects
It connects；Second read-write control circuit is connect with the second port of asynchronous double-end random access memory；First data caching circuit is used
In receiving and cache the first write request；First write request includes the first write-in data and the first data address；First read-write
Control circuit is used to be stored the first write-in data into asynchronous double-end random access memory according to the first data address；The
Two data caching circuits are for receiving and caching the first write request；Second read-write control circuit is asked for receiving the first reading
It asks, and according to the write request of the preset quantity cached in the second data caching circuit and asynchronous double-end random access memory
Internal data, output first, which is read, requests corresponding data；First, which reads request, includes the second data address.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein on
Stating the first data caching circuit includes the first logic control element and the first data buffer storage unit for setting space size；First patrols
Control unit is collected for receiving the first write request, the first data buffer storage list is written into the first write-in data and the first data address
In member；First logic control element is also used to the first write request being sent to the second read-write control circuit.
The possible embodiment of with reference to first aspect the first, the embodiment of the invention provides second of first aspect
Possible embodiment, wherein above-mentioned second data caching circuit includes the second logic control element and setting space size
Second data buffer storage unit；Second logic control element is for receiving the first write request, by the first write-in data and the first number
It is written in the second data buffer storage unit according to address.
With reference to first aspect, the embodiment of the invention provides the third possible embodiments of first aspect, wherein on
Stating the first read-write control circuit includes first selector and first control unit；First control unit is asked for ought not receive read-write
When asking, the second write request is generated, the second write request is sent to first port by first selector, so that asynchronous double-end
According to the caching sequence of default write-in data preset data address is written in default write-in data by random access memory；It is default to write
Enter data and preset data address is cached in the first data caching circuit sequentially in time.
The third possible embodiment with reference to first aspect, the embodiment of the invention provides the 4th kind of first aspect
Possible embodiment, wherein when asynchronous double-end random access memory will be preset according to the caching sequence of default write-in data
After data write-in preset data address is written, the first read-write control circuit is also used to send first to the first data caching circuit clear
Except instruction；First data caching circuit is also used to remove the default write-in data and preset data of the first data buffer storage unit caching
Address；First data caching circuit is also used to send the second clearance order to the second data caching circuit；Second data buffer storage electricity
Road is also used to remove default write-in data and the preset data address of the second data buffer storage unit caching.
The 4th kind of possible embodiment with reference to first aspect, the embodiment of the invention provides the 5th kind of first aspect
Possible embodiment, wherein above-mentioned second read-write control circuit includes second selector and the second control unit；Second control
Unit is used for when receiving the first reading request, and the write request of the preset quantity cached in the second data caching circuit is looked into
Look for the corresponding data of the second data address, if found, which is exported；If do not found, pass through second selector
Request is read by first and is sent to second port, so that the second data address of asynchronous double-end random access memory output is corresponding
Data.
Second aspect, the embodiment of the present invention also provide a kind of data preprocessing method, and it is pre- that this method is applied to above-mentioned data
Processing unit, the device are connect with asynchronous double-end random access memory；This method comprises: the first data caching circuit receives simultaneously
Cache the first write request；First write request includes the first write-in data and the first data address；First read-write control circuit
According to the first data address, the first write-in data are stored into asynchronous double-end random access memory；Second data buffer storage electricity
Road receives and caches the first write request；Second read-write control circuit receives first and reads request, and according to the second data buffer storage
The write request of the preset quantity cached in circuit and the internal data of asynchronous double-end random access memory, output first are read
Request corresponding data；First, which reads request, includes the second data address.
In conjunction with second aspect, the embodiment of the invention provides the first possible embodiments of second aspect, wherein on
Stating the first data caching circuit includes the first logic control element and the first data buffer storage unit for setting space size；Above-mentioned
The step of one data caching circuit receives and caches the first write request, comprising: the first logic control element receives the first write-in
First write-in data and the first data address are written in the first data buffer storage unit for request.
In conjunction with the first possible embodiment of second aspect, the embodiment of the invention provides second of second aspect
Possible embodiment, wherein after above-mentioned first data caching circuit receives and caches the first write request, this method is also wrapped
Include: the first write request is sent to the second read-write control circuit by the first logic control element.
The third aspect, the embodiment of the present invention also provide a kind of asynchronous double-end randon access memory system, including above-mentioned number
Data preprocess device further includes asynchronous double-end random access memory.
The embodiment of the present invention bring it is following the utility model has the advantages that
The embodiment of the invention provides a kind of data prediction device, method and asynchronous double-end random access memory systems
System；First data caching circuit receives and caches the first write request；First read-write control circuit, will according to the first data address
First write-in data are stored into asynchronous double-end random access memory；Second data caching circuit receives and caches the first write-in
Request；After second read-write control circuit receives the first reading request, according to the preset quantity cached in the second data caching circuit
Write request and asynchronous double-end random access memory internal data, output first, which is read, requests corresponding data；The party
Formula improves the working efficiency of asynchronous double-end random access memory.
Other features and advantages of the present invention will illustrate in the following description, alternatively, Partial Feature and advantage can be with
Deduce from specification or unambiguously determine, or by implementing above-mentioned technology of the invention it can be learnt that.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, better embodiment is cited below particularly, and match
Appended attached drawing is closed, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of data prediction device provided in an embodiment of the present invention；
Fig. 2 is that another data prediction device and asynchronous double port RAM provided in an embodiment of the present invention are cooperative
Functional block diagram；
Fig. 3 is the functional block diagram of Rw_ctl module provided in an embodiment of the present invention；
Fig. 4 is the functional block diagram of Reg_buf module provided in an embodiment of the present invention；
Fig. 5 is a kind of flow chart of data preprocessing method provided in an embodiment of the present invention；
Fig. 6 is the flow chart of another data preprocessing method provided in an embodiment of the present invention；
Fig. 7 is a kind of asynchronous double-end randon access memory system provided in an embodiment of the present invention, structural schematic diagram.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, shall fall within the protection scope of the present invention.
Dual port RAM provides two completely self-contained ports, and there are control line, address wire and the data of oneself in each port
Line.Usual dual port RAM is possible same address read operation, but is written and read to same address or double write operations, is not fair
Perhaps.Dual port RAM in use it is noted that the problem of be how to avoid both ends to the contention of same ram cell, in general, can
In a manner of using following three kinds of anti-collisions:
(1) it is inserted into the anti-collision mode of wait state.When left and right port simultaneously carries out the ram memory cell of same address
When access, the arbitration unit of RAM will provide BUSY signal.The normal condition of BUSY signal is high level, when left port is to one
When storage unit is accessed, if right output port also operates the storage unit, the arbitration unit of chip interior can make letter
Number BUSY be it is low, BUSY is reverted into high level again after the completion of left port operation.Both ends are avoided to carry out simultaneously to dual port RAM
Operation.
(2) signal lamp anti-collision mode.Dual port RAM is grasped by applying with the signal lamp (also referred to as token) of release port
Making storage unit can be to avoid clashing.One signal lamp corresponds to the storage unit of respective numbers.The both ends of dual port RAM
Signal lamp is accessed.When " 0 " read back waveform lamp again is written to signal lamp in left port, if signal lamp is also that " 0 " indicates left
Port possesses the control to storage unit, otherwise indicates that right output port possesses the control to storage unit.
(3) anti-collision mode is interrupted.Two storage units of highest address can be used as mailbox use in dual port RAM, left
Right both ends can simultaneously operate it.Wherein highest address is the mailbox of right output port, and secondary high address is left port mailbox.It is right
When left port mailbox is written in port, the signal INTL of left port will become low, and when left port reads the mailbox of oneself, signal INTL will
It again is height；Similarly, when left port write-in right output port mailbox, the signal INTR of right output port will be lower, and right output port reads the letter of oneself
When case, signal INTR will be again height.It can be transmitted certainly by mailbox to other side using signal INTL and IN TR as interrupt source
Oneself reaches the purpose for preventing conflict using the state of storage unit.
The method of above-mentioned two-port RAM anti-collision is several general methods, and in certain specific applications, in use
Stating general anti-collision processing method but might not be suitable.With the switch or router largely used in the network device
For, in some applications, their forwarding table look-up module largely uses RAM to realize, needs preferentially to guarantee data in design
The forwarding of frame, therefore the read rate of RAM needs preferential guarantee.Secondly, with the promotion and application of SDN network, network service is fixed
Inhibition and generation demand is higher and higher, this also requires the write request to forwarding ram table to be also required to quick response simultaneously.If it is synchronous random access memory
If design, solving can be fairly simple, but if if being asynchronous RAM, solution will be relatively difficult.
Based on this, the embodiment of the invention provides a kind of data prediction device, method and asynchronous double-end arbitrary accesses to deposit
Reservoir system can be applied to asynchronous double-end random access memory and other data storage field of storage.
For convenient for understanding the present embodiment, first to a kind of data prediction device disclosed in the embodiment of the present invention
It describes in detail.
The embodiment of the invention provides a kind of data prediction device, the device and asynchronous double-end random access memory connect
It connects；The device includes sequentially connected first read-write control circuit 100, the first data caching circuit 110, the second data buffer storage electricity
Road 120 and the second read-write control circuit 130, structural schematic diagram is as shown in Figure 1；First read-write control circuit 100 with it is asynchronous double
Hold the first port connection of random access memory；Second read-write control circuit 130 and asynchronous double-end random access memory
Second port connection；First data caching circuit 110 is for receiving and caching the first write request；First write request includes the
One write-in data and the first data address；First read-write control circuit 100 is used for according to the first data address, and number is written by first
According to storing into asynchronous double-end random access memory；Second data caching circuit 120 is asked for receiving and caching the first write-in
It asks；Second read-write control circuit 130 reads request for receiving first, and according to caching in the second data caching circuit 120
The write request of preset quantity and the internal data of asynchronous double-end random access memory, output first, which is read, requests corresponding number
According to；First, which reads request, includes the second data address.
Above-mentioned first data caching circuit and the second data caching circuit are mainly used for caching the write-in number in write request
According to and corresponding data address, when to prevent first port and second port from having data write request, write operation without
Method is completed；Write request is executed when the free time of port, then through above-mentioned data prediction device；First data caching circuit
And second data caching circuit can have identical structure.
Specifically, the first data caching circuit can be by the first data of the first logic control element and setting space size
Cache unit is constituted；When write request (hereinafter referred to as the first write request) that oriented first port issues, the first logic control
The first data buffer storage unit is written for receiving the first write request, by the first write-in data and the first data address in unit processed
In；First logic control element is also used to the first write request being sent to the second read-write control circuit.
Specifically, above-mentioned second data caching circuit can by the second logic control element and set space size second
Data buffer storage unit is constituted；After first write request is sent to the second read-write control circuit by the first logic control element, second
The second data buffer storage is written for receiving the first write request, by the first write-in data and the first data address in logic control element
In unit；Similarly, when the write request that oriented second port issues, the first data caching circuit and the second data buffer storage electricity
The operation of road execution other side.
In write operation, above-mentioned first read-write control circuit is mainly used for writing what is cached in the first data buffer storage unit
Enter data to be written in due course in asynchronous double-end random access memory.First read-write control circuit can be by first selector and first
Control unit is constituted；Specifically, first control unit is used for when not receiving read-write requests, generates the second write request, by the
Two write requests are sent to first port by first selector, so that asynchronous double-end random access memory is according to default write-in
Preset data address is written in default write-in data by the caching sequence of data；Default write-in data and preset data address according to when
Between order buffer in the first data caching circuit.
When default write-in data are written according to the caching sequence of default write-in data for asynchronous double-end random access memory
Behind preset data address, the first read-write control circuit can be also used to send the first clearance order to the first data caching circuit；
First data caching circuit is also used to remove default write-in data and the preset data address of the first data buffer storage unit caching, i.e.,
The data for having been written into asynchronous double-end random access memory and corresponding address are deleted；First data caching circuit is also used to
The second clearance order is sent to the second data caching circuit；Second data caching circuit is also used to remove the second data buffer storage unit
The default write-in data of caching and preset data address, i.e., will have been written into the data and phase of asynchronous double-end random access memory
It deletes the address answered.
Above-mentioned second read-write control circuit can be with the first read-write control circuit structure having the same；Above-mentioned second read-write
Control circuit can be made of second selector and the second control unit.When oriented first port issue reading request (below
Referred to as first reads request) when, the second control unit is used for when receiving the first reading request, in the second data caching circuit
The write request of the preset quantity of middle caching searches the corresponding data of the second data address and exports the data if found；
If do not found, request is read for first by second selector and is sent to second port, so that asynchronous double-end arbitrary access
Memory exports the corresponding data of the second data address.
The embodiment of the invention provides a kind of data prediction devices；First data caching circuit receives and caches first and writes
Enter request；First read-write control circuit stores the first write-in data to asynchronous double-end arbitrary access according to the first data address
In memory；Second data caching circuit receives and caches the first write request；Second read-write control circuit receives first and reads
After request, according to the write request of the preset quantity cached in the second data caching circuit and asynchronous double-end random access memory
Internal data, output first, which is read, requests corresponding data；Which improves the work of asynchronous double-end random access memory
Make efficiency.
The embodiment of the invention also provides another data prediction device, the bases of device device shown in Fig. 1
Upper realization；The device includes that two Reg_buf modules (are equivalent to above-mentioned first data caching circuit and the second data buffer storage electricity
Road) and two Rw_ctl modules (being equivalent to above-mentioned first read-write control circuit and the second read-write control circuit)；The device with it is different
It is as shown in Figure 2 to walk the cooperative functional block diagram of two-port RAM；The device and asynchronous double port RAM are also shown in Fig. 2 simultaneously
Connection relationship, similar with Fig. 1, a Reg_buf module is connect with a Rw_ctl module, the connection of two Reg_buf modules,
Two Rw_ctl modules are connect with the port of the two sides a, b of asynchronous double port RAM respectively.
RAM module is the asynchronous double port RAM core of standard, and different clock domains is read and write in segmentation at left and right sides of dotted line.Its a, b
The port receiving interface signal of two sides；Wherein En_a_in, En_b_in are respectively the interface enable signal of two ports；Rd_a_
In, Rd_b_in are respectively the interface read-write control signal of two ports；Addr_a_in, addr_b_in are respectively two ports
Interface address bus；Din_a_in, din_b_in are respectively the write data bus of two ports, dout_a_in, dout_
B_in is the read data bus of interface.
Reg_buf module realizes the caching of data to be written, and in the present embodiment, which can at most deposit
Address and the data of ram to be written are clapped in storage 4.Address in 4 ram to be written of its addr signal designation, data signal designation 4
Data in ram to be written.Set_ab, clr_ab, addr_ab, data_ab, ack_ab and Set_ba, clr_ba, addr_
Ba, data_ba, ack_ba are used to realize the content synchronization of two reg_buf in the left and right sides.Wr_rjct_a, wr_rjct_b are
The back-pressure of write order indicates.
Rw_ctl module is the Read-write Catrol module of RAM, which realizes the control of the every side read-write requests of RAM,
On the one hand major function will realize the scheduling to RAM reading and write order, on the other hand realize the selection for reading RAM data.It closes
In the detailed design of the module, will be introduced in following description.
The external interface and the standard interface of RAM of entire block diagram are very similar, only increase wr_rjct_a and wr_
The two signals of rjct_b；Wr_rjct_a and wr_rjct_b is respectively a, and Reg_ is worked as in the back-pressure instruction of the write order of the two sides b
When buf module caching has been expired, refuse the write-in of write order.
Specifically, the functional block diagram of Rw_ctl module is as shown in figure 3, because being symmetrical in the principle of the left and right sides, therefore only
Depict the schematic diagram of wherein side.Rw_ctl module is mainly by two selectors (B1 and B2) and a Wr_gen module (phase
When in above-mentioned first control unit or the second control unit) composition, the wherein effect of Wr_gen module is, if being currently read operation
When, whether Wr_gen module compares addr_a equal with addr,, will by Rd_sel signal control selections device B2 if equal
The data data of Reg_buf module export, while controlling Wr_sel signal, so that read request can't be transparent to the interface of RAM
On.If unequal, dout_a_in is output on dout_a by Rd_sel signal control selections device B2, while controlling Wr_
Sel signal is transparent to read request on the interface of RAM.In other words, when read operation, if data to be read are in Reg_
Exist in buf module, then reads data from Reg_buf module, data are otherwise just read from RAM.
When for the read-write requests free time, Wr_gen module generates a write request, and controls Wr_sel signal, this is write and is asked
Ask on the interface for passing to RAM, at the same time generate Wr_done and Wr_sel signal, notify Reg_buf module, it is a certain caching to
Write-in data have been successfully written in RAM.
Specifically, the functional block diagram of Reg_buf module is as shown in figure 4, the logical construction of two sides is consistent with principle, figure
In illustrate only the logical construction of wherein side.Reg_buf module includes that reg_buf_ctl module (is equivalent to above-mentioned first to patrol
Volume control unit or the second logic control element) and depth be 4 cache unit；Reg_buf_ctl module is used for to be written
Data carry out logic control and first pass through En_a, Rd_a, addr_a, data_a when this side has data to need to be written in RAM
Interface is written in the caching that a depth is 4, such as addr1~4 in figure, the write-in data buffer storage that the bit depth of data1~4 is 4,
And the address and data are written to the Reg_buf mould of opposite side by signals such as Set_ab, addr_ab, data_ab, Ack_ab
In block, then by the rw_ctl module of this side of addr, data interface notification, which is inserted into the operating of RAM,
After the completion of write operation, Rw_ctl module notifies reg_buf_ctl module by Wr_done and Wr_sel signal, will correspond to
Address and data postpone deposit in group delete after, reg_buf_ctl module pass through again clr_ab, data_ab, addr_ab and
Ack_ab will delete corresponding address and data in the reg_buf of opposite side.
When opposite side has data to need to be written, write-in treatment process it is similar, by Set_ba, addr_ba,
Data_ba, Ack_ba are written into address and data are stored in the address date caching of this side, after the completion of the write-in of opposite side, then
It will be deleted from the address date of this side caching with writing address and data by clr_ba, addr_ba, data_ba, Ack_ba
It removes.
A write buffer reg_buf is respectively arranged in the two sides of asynchronous dual port RAM in the embodiment of the present invention, ensure that writing for two sides
Operation at all will not influence the progress of read operation；And it is provided with the synchronization process interface between two sides write buffer reg_buf, it ensure that
Even if two sides write operation carries out simultaneously, the write operation of RAM will not conflict, and data will not malfunction.
The embodiment of the present invention also provides a kind of data preprocessing method, and this method is applied to above-mentioned data prediction device,
The device is connect with asynchronous double-end random access memory；The flow chart of this method is as shown in Figure 5, comprising the following steps:
Step 500, the first data caching circuit receives and caches the first write request；First write request is write including first
Enter data and the first data address；
Step 502, the first read-write control circuit stores the first write-in data to asynchronous double-end according to the first data address
In random access memory；
Step 504, the second data caching circuit receives and caches the first write request；
Step 506, the second read-write control circuit receives first and reads request, and caches according in the second data caching circuit
Preset quantity write request and asynchronous double-end random access memory internal data, output first read request it is corresponding
Data；First, which reads request, includes the second data address.
Specifically, above-mentioned first data caching circuit includes the first logic control element and the first number for setting space size
According to cache unit；The step of above-mentioned first data caching circuit receives and caches the first write request, comprising: the first logic control
Unit receives the first write request, and the first write-in data and the first data address are written in the first data buffer storage unit.
After above-mentioned first data caching circuit receives and caches the first write request, the first logic control element is by
One write request is sent to the second read-write control circuit.
Data preprocessing method provided in an embodiment of the present invention has with data prediction device provided by the above embodiment
Identical technical characteristic reaches identical technical effect so also can solve identical technical problem.
The embodiment of the invention also provides another data preprocessing method, the basis of this method step shown in Fig. 5
Upper realization；This method is applied to the read-write operation process of above-mentioned apparatus, and flow chart is as shown in fig. 6, detailed process is as follows:
(1) the received request in the port first is write operation or read operation；
(2) when carrying out read operation, judge the degree address in read operation whether with 4 ground being stored in reg_buf module
Any of location is equal；
(3) if so, being returned using its corresponding data as data are read；If it is not, read address is sent into RAM, and by RAM
Reading result as data return；
(4) when carrying out write operation, judge whether the spatial cache of reg_buf module is full；
(5) if full, mean that write operation needs to refuse, wr_rjct_a/b is set into height；
(6) if it is discontented, judge whether that this sidelights on operates, if so, by write address, writing data and being stored in this side and opposite side
In reg_buf module.
(7) after the completion of waiting this sidelights on to operate, the corresponding entry in this and opposite side reg_buf is removed.
(8) if it is opposite side write operation, this side only responds the write-in of reg_buf module and clear operation of opposite side.
Data prediction device provided in an embodiment of the present invention may be implemented the asynchronous RAM's required in certain ASIC designs
Write operation cannot at all influence read operation；It especially tables look-up and is waited in application scenarios in forwarding, effectively ensured rate full gear of tabling look-up
It carries out；Furthermore the write operation of two sides will not influence each other, and when ensure that the same ram space of how main access, not will cause write-in
The mistake of data.
Corresponding to above-described embodiment, the embodiment of the present invention also provides a kind of asynchronous double-end randon access memory system,
Structural schematic diagram is as shown with 7, including above-mentioned data prediction device 70, further includes asynchronous double-end random access memory 71.
Data preprocessing method, device provided by the embodiment of the present invention and asynchronous double-end randon access memory system
Computer program product, the computer readable storage medium including storing program code, the finger that said program code includes
Order can be used for executing previous methods method as described in the examples, and specific implementation can be found in embodiment of the method, and details are not described herein.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
And/or the specific work process of device, it can refer to corresponding processes in the foregoing method embodiment, details are not described herein.
In addition, in the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for description the present invention and simplify description, rather than the device or element of indication or suggestion meaning must have a particular orientation,
It is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
Finally, it should be noted that embodiment described above, only a specific embodiment of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, those skilled in the art should understand that: anyone skilled in the art
In the technical scope disclosed by the present invention, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover in protection of the invention
Within the scope of.Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. a kind of data prediction device, which is characterized in that described device is connect with asynchronous double-end random access memory；It is described
Device includes sequentially connected first read-write control circuit, the first data caching circuit, the second data caching circuit and the second reading
Write control circuit；First read-write control circuit is connect with the first port of the asynchronous double-end random access memory；Institute
The second read-write control circuit is stated to connect with the second port of the asynchronous double-end random access memory；
First data caching circuit is for receiving and caching the first write request；First write request is write including first
Enter data and the first data address；
First read-write control circuit is used to be stored the first write-in data to described according to first data address
In asynchronous double-end random access memory；
Second data caching circuit is for receiving and caching first write request；
Second read-write control circuit reads request for receiving first, and caches according in second data caching circuit
Preset quantity write request and the asynchronous double-end random access memory internal data, export it is described first read asks
Seek corresponding data；Described first, which reads request, includes the second data address.
2. the apparatus according to claim 1, which is characterized in that first data caching circuit includes the first logic control
Unit and the first data buffer storage unit for setting space size；
First logic control element is for receiving the first write request, by the first write-in data and first data
Address is written in the first data buffer storage unit；
First logic control element is also used to first write request being sent to second read-write control circuit.
3. the apparatus of claim 2, which is characterized in that second data caching circuit includes the second logic control
Unit and the second data buffer storage unit for setting space size；
Second logic control element is for receiving first write request, by the first write-in data and described first
Data address is written in the second data buffer storage unit.
4. the apparatus according to claim 1, which is characterized in that first read-write control circuit include first selector and
First control unit；
The first control unit is used for when not receiving read-write requests, generates the second write request, and second write-in is asked
It asks and the first port is sent to by the first selector, so that the asynchronous double-end random access memory is according to default
Preset data address is written in the default write-in data by the caching sequence that data are written；Default write-in data and described pre-
If data address is cached in first data caching circuit sequentially in time.
5. device according to claim 4, which is characterized in that when the asynchronous double-end random access memory is according to default
The caching sequence of data is written by behind the default write-in data write-in preset data address, first read-write control circuit is also
For sending the first clearance order to first data caching circuit；
First data caching circuit is also used to remove the default write-in data of the first data buffer storage unit caching
And the preset data address；
First data caching circuit is also used to send the second clearance order to second data caching circuit；
Second data caching circuit is also used to remove the default write-in data of the second data buffer storage unit caching
And the preset data address.
6. device according to claim 5, which is characterized in that second read-write control circuit include second selector and
Second control unit；
Second control unit is used to delay in second data caching circuit when receiving the first reading request
The write request for the preset quantity deposited searches the corresponding data of second data address, if found, the data are defeated
Out；If do not found, request is read for described first by the second selector and is sent to the second port, so that institute
It states asynchronous double-end random access memory and exports the corresponding data of second data address.
7. a kind of data preprocessing method, which is characterized in that the method is applied to data described in any one of claims 1-6
Pretreatment unit, described device are connect with asynchronous double-end random access memory；The described method includes:
First data caching circuit receives and caches the first write request；First write request include first write-in data and
First data address；
First read-write control circuit stores the first write-in data to the asynchronous double-end according to first data address
In random access memory；
Second data caching circuit receives and caches first write request；
Second read-write control circuit receives first and reads request, and according to the present count cached in second data caching circuit
It is corresponding to export the first reading request for the internal data of the write request of amount and the asynchronous double-end random access memory
Data；Described first, which reads request, includes the second data address.
8. the method according to the description of claim 7 is characterized in that first data caching circuit includes the first logic control
Unit and the first data buffer storage unit for setting space size；
The step of first data caching circuit receives and caches the first write request, comprising:
First logic control element receives the first write request, by the first write-in data and first data address
It is written in first data buffer storage unit.
9. according to the method described in claim 8, it is characterized in that, first data caching circuit receives and caches first writes
After entering request, the method also includes:
First write request is sent to second read-write control circuit by first logic control element.
10. a kind of asynchronous double-end randon access memory system, which is characterized in that including any one of the claim 1-6 number
Data preprocess device further includes asynchronous double-end random access memory.
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