CN106951379A - A kind of high-performance DDR controller and data transmission method based on AXI protocol - Google Patents
A kind of high-performance DDR controller and data transmission method based on AXI protocol Download PDFInfo
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Abstract
The invention discloses a kind of high-performance DDR controller and data transmission method based on AXI protocol, AXI buses are connected including its data input pin, data output end then connects DDR memory, and its structure includes AXI interface modules, register configuration module, data cache module, control module, tfi module, data transmission module.A kind of the high-performance DDR controller and data transmission method based on AXI protocol are compared with prior art, complete the work of efficient memory access, improve the performance of total system, project demands can be better met simultaneously, the project budget is reduced, and the method for the present invention has then carried out good improvement to DDR controller internal logic and structure, effectively improve data transmission efficiency, it is practical, it is easy to accomplish, it is easy to promote.
Description
Technical Field
The invention relates to the technical field of computer application, in particular to a high-performance DDR controller with strong practicability and based on an AXI (advanced extensible interface) protocol and a data transmission method.
Background
With the progress of circuit design, production process and the like, the processing capacity of a CPU is continuously improved at high speed, the performance of the whole system is greatly reduced due to the fact that the difference between the working frequency of a processor and the working frequency of a DRAM is increased, and the key for improving the performance of the system is to improve the bandwidth of a bus and the working efficiency of each device. Due to the high performance of the AXI bus itself and the wide application of ARM microprocessors, AXI becomes a widely applied bus standard in SOC design. In the SOC design, because a cache with smaller capacity and a simplified storage system are used compared with a common computer architecture, the influence of the access performance on the whole system is more huge, and under the condition that the physical parameters of a storage are determined, the design of a storage interface directly influences the performance of a storage part, so that the performance of the whole system is influenced.
Therefore, the high-performance DDR controller based on the AXI protocol and the data transmission method are provided, and the DDR controller compatible with the AXI protocol is designed and used for connecting an AXI bus and a memory, so that efficient memory access is completed, and the performance of the whole system is improved.
Disclosure of Invention
The technical task of the invention is to provide the high-performance DDR controller and the data transmission method which have strong practicability and are based on the AXI protocol.
A high-performance DDR controller based on AXI protocol, the data input end of which is connected with AXI bus, the data output end of which is connected with DDR memory, the structure comprises AXI interface module, register configuration module, data buffer module, control module, time sequence module, data transmission module, wherein,
the AXI interface module is in communication connection with the AXI bus and generates a data transmission signal;
the register configuration module comprises a group of registers and is used for completing the setting of parameters of other modules in the DDR controller through the configuration of register values;
the data cache module is connected with the AXI interface module, caches the data signals transmitted from the AXI interface module and waits for the control signals of data transmission;
the control module generates a control signal for data transmission and sends the control signal to the data caching module;
the time sequence module is matched with the control signal of the control module to control the working state of the data transmission module;
and the data transmission module is used for completing data transmission between the AXI bus and the DDR memory, namely transmitting the data cached in the data cache module to the DDR controller based on the control signal of the control module.
Also comprises a state module and a refreshing module, wherein,
the status module records the current DDR controller status, records the current AXI bus and memory status through monitoring the sequential module command output, and reads the relevant status information from the status module as a reference when the control module generates a control signal;
the refreshing module comprises a counter with a set number function, and when the counter counts down to 0, a refreshing request signal is sent out, and the counter stops; when the refreshing process is finished, the time sequence module sends a response signal of the refreshing request, and the refreshing module can take values from the register configuration module and restart counting down.
The data transmission signals generated by the AXI interface module comprise handshaking signals for data transmission and response signals for data transmission, wherein the handshaking signals comprise handshaking signals of a read address channel, a read data channel, a write address channel, a write data channel and a write response channel; the data transfer response signal is generated based on the AXI bus specification.
The register configuration module is a register interface of the memory controller and comprises a group of registers, the configuration of the register value is completed through bus data transmitted by the AXI bus interface module, each register corresponds to other modules in the DDR controller, and the setting of the corresponding module parameter is completed after the value of the register is configured.
The data buffer module comprises a control buffer area and a storage buffer area, wherein each type of buffer area comprises a write command buffer area, a read command buffer area, a write data buffer area and a read data buffer area, and is responsible for judging and classifying data signals transmitted by the AXI interface module and distributing the data signals to the corresponding buffer areas to be transmitted.
The control module completes arbitration by receiving data from the data caching module and the state module, and generates a control signal, which specifically comprises the following steps: the control module arbitrates the read-write command and generates control signals, namely the transmission sequence and the transmission starting and ending time of the read-write request according to the priority of the signals and the state of the current memory.
The time sequence module is responsible for generating a specific storage bus time sequence, namely converting a command transmitted by the control module into actual storage bus time sequence operation and controlling the working state of the data transmission module; the control module is only responsible for carrying out arbitration of data transmission operation, and special operations including initialization operation and refresh operation of the DDR memory are controlled by the timing module.
When the data width of the AXI bus is different from the data bandwidth of the memory bus, the data transmission module completes the conversion between the data bit widths, and completes the data transmission between the AXI bus and the DDR memory on the premise of meeting respective transmission protocols.
Based on the DDR controller, the high-performance data transmission method based on the AXI protocol comprises the following implementation processes:
firstly, transmitting data to enter an AXI (advanced extensible interface) module through an AXT (advanced extensible transport) bus, wherein the AXI module generates data transmission signals, the data transmission signals comprise handshaking signals for data transmission and response signals for data transmission, and the handshaking signals comprise a read address channel handshaking signal, a read data channel handshaking signal, a write address channel handshaking signal, a write data channel handshaking signal and a write response channel handshaking signal; the data transmission response signal is generated based on the AXI bus specification;
the data transmission signals enter a data cache module for temporary storage, the data cache module judges and classifies the data signals transmitted by the AXI interface module and distributes the data signals to corresponding buffer areas for waiting transmission, the corresponding buffer areas comprise a control buffer area and a storage buffer area, and each buffer area comprises a write command buffer area, a read command buffer area, a write data buffer area and a read data buffer area;
the arbitration of the read-write command is carried out through the control module, namely, the arbitration is completed by receiving data from the data cache module and the state module, and a control signal is generated, wherein the control signal comprises the transmission sequence and the transmission starting and ending time of the read-write request;
the time sequence module converts a command transmitted by the control module into actual storage bus time sequence operation according to a control signal of the control module and controls the working state of the data transmission module;
and finally, completing the data transmission between the AXI bus and the DDR memory by the data transmission module.
The data transmission is periodically and automatically completed, and the periodic control is realized through a refreshing module, which specifically comprises the following steps: the refresh module is provided with a counter with a set number function, and when the counter counts down to 0, a refresh request signal is sent out, and the counter stops; when the refreshing process is finished, the time sequence module sends a response signal of the refreshing request, and the refreshing module can take values from the register configuration module and restart counting down.
The high-performance DDR controller based on the AXI protocol and the data transmission method have the following advantages that:
the DDR memory controller is used as an interface between an AXI bus and a memory and is used for finishing the work of efficient access and storage, the performance of the whole system is improved, meanwhile, the project requirements can be better met, the project budget is reduced, the method of the invention well improves the internal logic and structure of the DDR controller, the data transmission efficiency is effectively improved, the practicability is strong, the realization is easy, and the popularization is easy.
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In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of the implementation of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a high-performance DDR controller based on an AXI protocol is used as an interface between an AXI bus and a memory to complete efficient access. The invention provides the whole structure and module division of the DDR controller, and describes the function and design method of each submodule of the memory controller. The model structure mainly comprises the following modules: the device comprises an AXI interface module, a register configuration module, a data cache module, a control module, a time sequence module and a data transmission module.
Wherein,
the AXI interface module is in communication connection with the AXI bus and generates a data transmission signal;
the register configuration module comprises a group of registers and is used for completing the setting of parameters of other modules in the DDR controller through the configuration of register values;
the data cache module is connected with the AXI interface module, caches the data signals transmitted from the AXI interface module and waits for the control signals of data transmission;
the control module generates a control signal for data transmission and sends the control signal to the data caching module;
the time sequence module is matched with the control signal of the control module to control the working state of the data transmission module;
and the data transmission module is used for completing data transmission between the AXI bus and the DDR memory, namely transmitting the data cached in the data cache module to the DDR controller based on the control signal of the control module.
Also comprises a state module and a refreshing module, wherein,
the status module records the current DDR controller status, records the current AXI bus and memory status through monitoring the sequential module command output, and reads the relevant status information from the status module as a reference when the control module generates a control signal;
the refreshing module comprises a counter with a set number function, and when the counter counts down to 0, a refreshing request signal is sent out, and the counter stops; when the refreshing process is finished, the time sequence module sends a response signal of the refreshing request, and the refreshing module can take values from the register configuration module and restart counting down.
The data transmission signals generated by the AXI interface module comprise handshake signals for data transmission and response signals for data transmission, that is, the AXI interface module generates handshake signals on five independent channels defined by an AXI bus, respectively, and the handshake signals specifically comprise handshake signals of a read address channel, a read data channel, a write address channel, a write data channel and a write response channel; the data transfer response signal is generated based on the AXI bus specification.
The register configuration module is a register interface of the storage controller and comprises a group of registers, each register corresponds to other modules, and the setting of the corresponding module parameters can be completed by configuring the value of the register into a numerical value with a specific meaning. For example, the value in the refresh cycle register is a preset value of a counter required by a refresh module in the controller, and the refresh module will take out the value from the register again after each refresh is completed. The module completes the configuration of the register value through the bus data transmitted by the AXI bus interface module.
The data buffer module comprises a control buffer area and a storage buffer area, wherein each type of buffer area comprises a write command buffer area, a read command buffer area, a write data buffer area and a read data buffer area, and is responsible for judging and classifying data signals transmitted by the AXI interface module and distributing the data signals to the corresponding buffer areas to be transmitted.
The control module completes arbitration by receiving data from the data caching module and the state module, and generates a control signal according to the priority of the signal and the state of the current memory, specifically: the control module arbitrates the read-write command and generates control signals, namely the transmission sequence and the transmission starting and ending time of the read-write request according to the priority of the signals and the state of the current memory.
The time sequence module is responsible for generating a specific storage bus time sequence, namely converting a command transmitted by the control module into actual storage bus time sequence operation and controlling the working state of the data transmission module. The control module is only responsible for arbitrating data transmission operation, and special operations of the DDR memory, such as initialization operation, refresh operation and the like, are controlled and completed by the timing module.
When the data width of the AXI bus is different from the data bandwidth of the memory bus, the data transmission module completes the conversion between the data bit widths, and completes the data transmission between the AXI bus and the DDR memory on the premise of meeting respective transmission protocols.
Based on the DDR controller, the high-performance data transmission method based on the AXI protocol comprises the following implementation processes:
firstly, transmitting data to enter an AXI (advanced extensible interface) module through an AXT (advanced extensible transport) bus, wherein the AXI module generates data transmission signals, the data transmission signals comprise handshaking signals for data transmission and response signals for data transmission, and the handshaking signals comprise a read address channel handshaking signal, a read data channel handshaking signal, a write address channel handshaking signal, a write data channel handshaking signal and a write response channel handshaking signal; the data transmission response signal is generated based on the AXI bus specification;
the data transmission signals enter a data cache module for temporary storage, the data cache module judges and classifies the data signals transmitted by the AXI interface module and distributes the data signals to corresponding buffer areas for waiting transmission, the corresponding buffer areas comprise a control buffer area and a storage buffer area, and each buffer area comprises a write command buffer area, a read command buffer area, a write data buffer area and a read data buffer area;
the arbitration of the read-write command is carried out through the control module, namely, the arbitration is completed by receiving data from the data cache module and the state module, and a control signal is generated, wherein the control signal comprises the transmission sequence and the transmission starting and ending time of the read-write request;
the time sequence module converts a command transmitted by the control module into actual storage bus time sequence operation according to a control signal of the control module and controls the working state of the data transmission module;
and finally, completing the data transmission between the AXI bus and the DDR memory by the data transmission module.
The data transmission is periodically and automatically completed, and the periodic control is realized through a refreshing module, which specifically comprises the following steps: the refresh module is provided with a counter with a set number function, and when the counter counts down to 0, a refresh request signal is sent out, and the counter stops; when the refreshing process is finished, the time sequence module sends a response signal of the refreshing request, and the refreshing module can take values from the register configuration module and restart counting down.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The high-performance DDR controller based on the AXI protocol and the data transmission method provided by the present invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A high-performance DDR controller based on AXI protocol is characterized in that a data input end is connected with an AXI bus, a data output end is connected with a DDR memory, the structure of the DDR controller comprises an AXI interface module, a register configuration module, a data cache module, a control module, a time sequence module and a data transmission module, wherein,
the AXI interface module is in communication connection with the AXI bus and generates a data transmission signal;
the register configuration module comprises a group of registers and is used for completing the setting of parameters of other modules in the DDR controller through the configuration of register values;
the data cache module is connected with the AXI interface module, caches the data signals transmitted from the AXI interface module and waits for the control signals of data transmission;
the control module generates a control signal for data transmission and sends the control signal to the data caching module;
the time sequence module is matched with the control signal of the control module to control the working state of the data transmission module;
and the data transmission module is used for completing data transmission between the AXI bus and the DDR memory, namely transmitting the data cached in the data cache module to the DDR controller based on the control signal of the control module.
2. The AXI protocol based high performance DDR controller of claim 1 further comprising a status module, a refresh module, wherein,
the status module records the current DDR controller status, records the current AXI bus and memory status through monitoring the sequential module command output, and reads the relevant status information from the status module as a reference when the control module generates a control signal;
the refreshing module comprises a counter with a set number function, and when the counter counts down to 0, a refreshing request signal is sent out, and the counter stops; when the refreshing process is finished, the time sequence module sends a response signal of the refreshing request, and the refreshing module can take values from the register configuration module and restart counting down.
3. The AXI protocol-based high performance DDR controller of claim 2 wherein the AXI interface module generates data transfer signals comprising handshake signals for data transfer and response signals for data transfer, wherein the handshake signals comprise read address channel handshake signals, read data channel handshake signals, write address channel handshake signals, write data channel handshake signals, write response channel handshake signals; the data transfer response signal is generated based on the AXI bus specification.
4. The high-performance DDR controller according to claim 2, wherein the register configuration module is a register interface of the memory controller, and comprises a set of registers, the configuration of the register values is performed through bus data transmitted through the AXI bus interface module, each register corresponds to another module in the DDR controller, and the setting of the parameters of the corresponding module is performed after the register values are configured.
5. The AXI protocol-based high performance DDR controller as claimed in claim 2, wherein the data buffer module comprises two types, a control buffer and a storage buffer, each type of buffer comprises a write command buffer, a read command buffer, a write data buffer and a read data buffer, and is responsible for determining and classifying the data signals transmitted through the AXI interface module, and allocating the data signals to the corresponding buffers for transmission.
6. The high-performance DDR controller according to claim 2, wherein the control module performs arbitration by receiving data from the data buffer module and the status module, and generates the control signal, specifically: the control module arbitrates the read-write command and generates control signals, namely the transmission sequence and the transmission starting and ending time of the read-write request according to the priority of the signals and the state of the current memory.
7. The AXI protocol-based high-performance DDR controller as claimed in claim 2, wherein the timing module is responsible for generating specific memory bus timing, that is, converting the command transmitted from the control module into an actual memory bus timing operation, and controlling the operating status of the data transmission module; the control module is only responsible for carrying out arbitration of data transmission operation, and special operations including initialization operation and refresh operation of the DDR memory are controlled by the timing module.
8. The high-performance DDR controller according to any one of claims 1 to 7, wherein when the data width of the AXI bus is different from the data bandwidth of the memory bus, the data transfer module completes the conversion between the data bit widths, and completes the data transfer between the AXI bus and the DDR memory on the premise that the respective transfer protocols are satisfied.
9. A high-performance data transmission method based on AXI protocol is characterized in that based on the DDR controller, the realization process is as follows:
firstly, transmitting data to enter an AXI (advanced extensible interface) module through an AXT (advanced extensible transport) bus, wherein the AXI module generates data transmission signals, the data transmission signals comprise handshaking signals for data transmission and response signals for data transmission, and the handshaking signals comprise a read address channel handshaking signal, a read data channel handshaking signal, a write address channel handshaking signal, a write data channel handshaking signal and a write response channel handshaking signal; the data transmission response signal is generated based on the AXI bus specification;
the data transmission signals enter a data cache module for temporary storage, the data cache module judges and classifies the data signals transmitted by the AXI interface module and distributes the data signals to corresponding buffer areas for waiting transmission, the corresponding buffer areas comprise a control buffer area and a storage buffer area, and each buffer area comprises a write command buffer area, a read command buffer area, a write data buffer area and a read data buffer area;
the arbitration of the read-write command is carried out through the control module, namely, the arbitration is completed by receiving data from the data cache module and the state module, and a control signal is generated, wherein the control signal comprises the transmission sequence and the transmission starting and ending time of the read-write request;
the time sequence module converts a command transmitted by the control module into actual storage bus time sequence operation according to a control signal of the control module and controls the working state of the data transmission module;
and finally, completing the data transmission between the AXI bus and the DDR memory by the data transmission module.
10. The method for high-performance data transmission based on the AXI protocol as claimed in claim 1, wherein the data transmission is periodically and automatically completed, and the period control is implemented by a refresh module, specifically: the refresh module is provided with a counter with a set number function, and when the counter counts down to 0, a refresh request signal is sent out, and the counter stops; when the refreshing process is finished, the time sequence module sends a response signal of the refreshing request, and the refreshing module can take values from the register configuration module and restart counting down.
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| 贺理: "《AXI4-Stream总线的FPGA视频系统的开发研究》", 《单片机与嵌入式系统应用》 * |
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