CN113238974A

CN113238974A - Bus bandwidth efficiency statistical method, device, equipment and medium

Info

Publication number: CN113238974A
Application number: CN202110544807.1A
Authority: CN
Inventors: 刘铭; 李金亭
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2021-05-19
Filing date: 2021-05-19
Publication date: 2021-08-10

Abstract

The invention provides a bus bandwidth efficiency statistical method, a device, equipment and a medium, wherein the method comprises the following steps: triggering to carry out data statistics, and reading a current data transmission indication signal and a current transmission bit width indication signal on an AXI bus interface in real time; according to the current transmission indication signal, determining an effective bit width corresponding to the transmitted data according to the current transmission bit width indication signal when each data is transmitted on the data transmission channel; triggering a counter corresponding to the determined effective bit width, and counting the data of the effective bit width; and when the data statistics is finished, determining the bus bandwidth efficiency by using the data number counted by each counter and the corresponding effective bit width and the counting time. The invention realizes the calculation of the bus bandwidth efficiency by using the actual effective data bit width, so that the calculation result is more accurate.

Description

Bus bandwidth efficiency statistical method, device, equipment and medium

Technical Field

The invention relates to the field of data storage technology and SoC (system on chip) chips, in particular to a bus bandwidth efficiency statistical method, a device, equipment and a medium.

Background

In the SoC (System on Chip) field, the working efficiency and stability are important indexes of the Chip performance. The DDR SDRAM (Double Data Rate Synchronous Random Access Memory) is a critical storage unit in the SoC chip, and provides a storage function for functional modules of the chip, such as image quality modules of image quality chips including Motion Estimation and Motion Compensation (MEMC), Timing Controller (TCON), and CPU, so as to ensure normal operation of the entire SoC chip. The DDR work efficiency and stability play a very critical role in the whole chip. The operating efficiency of a DDR can be measured by the AXI (Advanced eXtensible Interface) Interface bus bandwidth efficiency of accessing the DDR controller. The method has the advantages that the bus bandwidth efficiency of the AXI interface during DDR access is accurately calculated, and the method has important significance for chip work efficiency assessment and efficiency improvement.

The existing calculation method for counting the bandwidth efficiency of the AXI bus is represented by the product of the total number of effective transmission data on each data channel of the AXI interface in unit time and the bit width of the effective data, the fixed data width is used, and the actual effective data width is generally smaller than or equal to the fixed data width of the interface, so that the bus bandwidth efficiency result calculated by the existing scheme is higher than the actual bandwidth efficiency result, and a more accurate bus bandwidth efficiency counting scheme is needed.

Disclosure of Invention

The application aims to provide a bus bandwidth efficiency statistical method, a device, equipment and a medium. The method is used for solving the problem that the prior bus bandwidth efficiency is calculated by utilizing the interface fixed bandwidth, and the actual effective data bandwidth is generally less than or equal to the interface fixed bandwidth, so that the calculation result is higher.

In a first aspect, an embodiment of the present application provides a method for bus bandwidth efficiency statistics, including:

triggering to carry out data statistics, and reading a current data transmission indication signal and a current transmission bit width indication signal on an AXI bus interface in real time;

determining an effective bit width corresponding to the transmitted data according to the current transmission bit width indication signal when determining that one data is transmitted on a data transmission channel according to the current transmission indication signal;

triggering a counter corresponding to the determined effective bit width, and counting the data of the effective bit width;

and when the data statistics is finished, determining the bus bandwidth efficiency by using the data number counted by each counter and the corresponding effective bit width and the counting time.

In some possible embodiments, according to that the data transmission channels include a read data transmission channel and a write data transmission channel, the counters include a first counter for counting data transmitted in the read data channel and corresponding to different effective bit widths, and a second counter for counting data transmitted in the write data channel and corresponding to different effective bit widths;

triggering a counter corresponding to the determined effective bit width, including:

when the transmitted data is determined to be data on a data reading channel, triggering a first counter corresponding to the determined effective bit width;

and triggering a second counter corresponding to the determined effective bit width when the transmitted data is determined to be the data on the data writing channel.

In some possible embodiments, the determining that each data is transmitted on the data transmission channel includes:

reading a first indication signal indicating whether data transmission is effective and a second indication signal indicating whether data can be transmitted;

when the data transmission of the data channel is determined to be effective and the data can be transmitted, determining that one data is transmitted on the data transmission channel;

enabling a counter corresponding to the determined valid bit width by a third indication signal.

In some possible embodiments, determining, according to the transmission bit width indication signal, an effective bit width corresponding to the transmitted data includes:

acquiring the coded values of transmission bit width indication signals corresponding to different effective bit widths of a data reading channel/a data writing channel in advance;

and determining the effective bit width corresponding to the transmitted data according to the coding value of the current transmission bit width indication signal.

In some possible embodiments, the determining the bus bandwidth efficiency by using the data number counted by each counter and the corresponding effective bit width and the counted time includes:

multiplying the data number counted by each counter by the corresponding effective bit width and then summing to obtain the bus bandwidth of the data channel;

the bus bandwidth efficiency is determined by dividing the bus bandwidth by the statistical time.

In some possible embodiments, when the data statistics is finished, determining the bus bandwidth efficiency by using the number of data counted by each counter and the corresponding effective bit width and the statistical time includes:

when the data statistics is finished, the number of the data counted by each counter is registered in a data register corresponding to the counter;

and reading the data number from the data register, and determining the bus bandwidth efficiency according to the corresponding effective bit width and the statistical time.

In some possible embodiments, the triggering performs data statistics, including:

acquiring the set counting starting time and the counting finishing time;

and triggering to carry out data statistics when the start time of the statistics is determined.

In a second aspect, an embodiment of the present application provides an apparatus for bus bandwidth efficiency statistics, including:

the indicating module is used for triggering data statistics and reading a current data transmission indicating signal and a current transmission bit width indicating signal on an AXI bus interface in real time;

a determining module, configured to determine, according to the current transmission indication signal, an effective bit width corresponding to transmitted data according to the current transmission bit width indication signal when each data is transmitted on a data transmission channel;

the counting module is used for triggering a counter corresponding to the determined effective bit width and counting the data of the effective bit width;

and the counting module is used for determining the bus bandwidth efficiency by utilizing the data number counted by each counter and the corresponding effective bit width and counting time when the data counting is finished.

In a third aspect, an embodiment of the present application provides a device for bus bandwidth efficiency statistics, including at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method of bus bandwidth efficiency statistics as provided in the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer storage medium, where a computer program is stored, where the computer program is used to enable a computer to execute a method for bus bandwidth efficiency statistics provided in the first aspect.

By utilizing the method, the device, the equipment and the medium for counting the bus bandwidth efficiency, the following beneficial effects are achieved:

the bus bandwidth efficiency is calculated by utilizing the actual effective data bit width, and the calculation result is more accurate.

Drawings

FIG. 1 is a schematic illustration of an application environment according to an embodiment of the present application;

FIG. 2 is a schematic diagram of application environment refinement according to one embodiment of the present application;

FIG. 3 is a flow diagram of a method of bus bandwidth efficiency statistics according to one embodiment of the present application;

FIG. 4 is a flow diagram of an apparatus for bus bandwidth efficiency statistics according to an embodiment of the present application;

FIG. 5 is a flow diagram of an apparatus for bus bandwidth efficiency statistics according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described in detail and clearly with reference to the accompanying drawings. In the description of the embodiments of the present application, "/" means "or" unless otherwise specified, for example, a/B may mean a or B; "and/or" in the text is only an association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: three cases of a alone, a and B both, and B alone exist, and in addition, "a plurality" means two or more than two in the description of the embodiments of the present application.

In the description of the embodiments of the present application, the term "plurality" means two or more unless otherwise specified, and other terms and the like should be understood similarly, and the preferred embodiments described herein are only for the purpose of illustrating and explaining the present application, and are not intended to limit the present application, and features in the embodiments and examples of the present application may be combined with each other without conflict.

To further illustrate the technical solutions provided by the embodiments of the present application, the following detailed description is made with reference to the accompanying drawings and the detailed description. Although the embodiments of the present application provide method steps as shown in the following embodiments or figures, more or fewer steps may be included in the method based on conventional or non-inventive efforts. In steps where no necessary causal relationship exists logically, the order of execution of the steps is not limited to that provided by the embodiments of the present application. The method can be executed in the order of the embodiments or the method shown in the drawings or in parallel in the actual process or the control device.

In view of the problem in the related art that in the bus bandwidth efficiency statistics of the AXI, a fixed data bit width is used, and an actual effective data width is generally smaller than or equal to an interface fixed data width, so that a calculated bus bandwidth efficiency result is higher than an actual bandwidth efficiency result, the present application provides a bus bandwidth efficiency statistics method, apparatus, device and medium, which calculate the bus bandwidth efficiency of the AXI using the actual effective data width, so that the calculated bus bandwidth efficiency is more accurate.

In view of the above, the inventive concept of the present application is: the effective bit width corresponding to the transmitted data is determined through the coded value of the transmission bit width indicating signal, and the number of the corresponding transmission data is counted through counters corresponding to different effective bit widths, so that the actual bus bandwidth can be determined.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

The following describes in detail a bus bandwidth efficiency statistical method in the embodiment of the present application with reference to the drawings.

Referring to fig. 1, a schematic diagram of an application environment applied to an embodiment of the present application is shown.

As shown in fig. 1, the application environment is an SoC system, and the SoC system includes: the system comprises an SoC system submodule 101, an AXI bus interface 102 and a DDR storage unit 103, and when the SoC system submodule 101 accesses the DDR storage unit 103, data interaction is achieved through the AXI bus interface 102.

The specific application environment of the embodiment of the present application is shown in fig. 2, and the application environment further includes a central processing unit CPU, and the SoC system sub-modules refer to sub-modules in the SoC system that have access requirements for the DDR memory unit, and include image quality modules such as MEMC (Motion estimation and Motion Compensation), TCON (Timing Controller), and the like. The DDR memory unit is responsible for the memory function of the system.

The BUS BUS is responsible for scheduling between SoC system sub-modules and requests of the CPU for accessing the DDR, and completes bidirectional forwarding between the DDR read-write data and the DDR controller; DDR CTRL (Double Data Rate Synchronous Random Access Memory Control) is responsible for the bidirectional conversion of the Data format of AXI on the BUS and the Data format of the DDR Memory unit; the data interaction interface between the DDR CTRL and the BUS is an AXI BUS interface; the AXI bus interface may be composed of a plurality of AXI PORTs, n AXI PORTs are schematically marked in fig. 2, a single AXI PORT is taken as an example for illustration in the present embodiment, and the present embodiment is also applicable to multiple PORTs.

The SoC system submodule forwards and stores data to be stored in a DDR storage unit through an AXI interface according to a data format of an AXI standard protocol. The bandwidth efficiency of the SoC system submodule 101 for accessing the DDR memory unit 103 is measured by counting the AXI bus bandwidth efficiency.

There are five channels in the AXI bus interface protocol standard, which are a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel. The bandwidth efficiency of the SoC system sub-module 101 accessing the DDR memory unit 103 may be measured by the bandwidth efficiency of the AXI bus interface, and the bandwidth efficiency of the AXI is calculated by the data number of the write data channel and the read data channel. Table 1 is referred to for a bandwidth efficiency-related AXI protocol interface signal list.

TABLE 1

WDATA is a write data signal, and RDATA is a read data signal; AXI _ CLK is an AXI interface protocol clock; WVALID is an indication signal for judging whether the write data is transmitted effectively on the write data channel, WREADY is an indication signal for judging whether the write address can accept the write data on the write data channel; RVALID is an indication signal that determines whether read data is valid for transmission on the read data path, and RREADY is an indication signal that determines whether read data can be accepted by the read address on the read data path.

The existing AXI bus interface data bandwidth efficiency can be expressed as the number of transmitted bits per unit time. Namely, the product of the total number of the read-write data on the AXI interface read-write data channel in unit time and the data bit width. Namely:

AXI bus bandwidth efficiency data bit width/time (in bps) total number of read and write data

In the related technology, the AXI bus bandwidth efficiency during DDR access is calculated according to a calculation formula and by using a fixed data bit width N, for example, 128 bits, and the influence of the effective data bit width of an AXI bus interface on the bus bandwidth efficiency is not considered. The actual valid data bit width is typically less than or equal to the interface fixed data bit width. Thus resulting in a higher bus bandwidth efficiency result calculated with the older scheme than the actual bandwidth efficiency result. A more accurate bus bandwidth efficiency statistical scheme is needed.

In view of this, an embodiment of the present application provides a bus bandwidth efficiency statistical method, which is applied to statistics of AXI bus bandwidth efficiency when an SoC system submodule accesses a DDR, and the method can accurately count a result, as shown in fig. 3, the method includes:

step 301, triggering data statistics, and reading a current data transmission indication signal and a current transmission bit width indication signal on an AXI bus interface in real time;

in the implementation, the data statistics may be triggered by a preset start time and an end time, or may be triggered by software or hardware, for example, by clicking a data statistics start button, which triggers the start of data statistics.

Reading a data transmission indication signal and a current transmission bit width indication signal on an AXI bus interface, judging whether current data transmission is effective or not according to the data transmission indication signal, namely, successfully transmitting the data, and determining the effective bit width of the transmission data according to the transmission bit width indication signal, so that the data is conveniently counted.

As an optional implementation, performing data statistics according to the trigger includes: acquiring the set counting starting time and the counting finishing time; and triggering to carry out data statistics when the start time of the statistics is determined.

The method comprises the steps of automatically triggering data statistics when the starting time is reached through the preset starting time and ending time, automatically stopping the data statistics when the ending time is reached, and determining the bandwidth efficiency statistical time of an AXI bus interface according to the starting time and the ending time.

Or the data statistics can be started by clicking a data statistics starting button, and the starting moment is the starting moment of the data statistics. Step 302, determining an effective bit width corresponding to the transmitted data according to the current transmission bit width indication signal when determining that each data is transmitted on a data transmission channel according to the current transmission indication signal;

when the SoC module accesses the DDR, data interaction is completed through the AXI bus interface, each data transmitted in the data channel is monitored in real time through a transmission indicating signal on the AXI bus interface, and whether the data is transmitted effectively is judged; the AXI interface signal has a data bit width indication signal indicating the effective bit width of the transmitted data, and the actual effective bit width of the data is determined by the data bit width indication signal.

The data transmission indication signal in the embodiment of the application comprises: the data transmission method includes the steps that a first indication signal used for indicating whether data transmission is effective or not and a second indication signal used for indicating whether data transmission is available or not are used, specifically, whether the data transmission is available or not can be indicated by the first indication signal, and whether the data transmission is successful or not can be indicated by the second indication signal.

The first indication signal and the second indication signal are used for judging that data is transmitted on the data channel, and the corresponding counter can be enabled to count through the third indication signal.

As an optional implementation manner, the determining that each data is transmitted on the data transmission channel includes:

In implementation, whether the signal is valid may be determined according to the level state of the first indication signal/the second indication signal, and specifically, but not limited to, the following manner may be adopted:

if the first indicating signal is in a high level state, the data transmission is represented currently, and if not, the data transmission is not represented currently;

if the second indicating signal is in a high level state, it indicates that data can be transmitted, for example, for a write data channel, it indicates that the address can receive the data, otherwise, it indicates that data cannot be transmitted, for example, for the write data channel, it indicates that the address cannot receive the data;

when the first indication signal and the second indication signal are at high level at the same time, determining that data needs to be counted when a piece of data is transmitted on the data channel;

as an optional implementation, the data transfer channels include a read data transfer channel and a write data transfer channel.

In the embodiment of the present application, for a read data channel, the first indication signal is RVALID in table 1 above, and the second indication signal is RREADY in table 1 above;

for the write data channel, the first indication signal is WVALID in table 1, and the second indication signal is WRWADY in table 1.

As an optional implementation manner, determining, according to the transmission bit width indication signal, an effective bit width corresponding to the transmitted data includes:

For a read data channel, the transmission bit width indication signal is ARSIZE in table 1 above;

for the write data channel, the transmission bit width indication signal is AWSIZE in Table 1 above.

The method comprises the steps that ARSIZE can adopt different coding values to indicate different effective bit widths of data transmitted by a data reading channel, AWSIZE can adopt different coding values to indicate different effective bit widths of the data transmitted by a data writing channel, the data writing channel and the data reading channel can be respectively coded according to different effective bit widths, namely two coding value tables are respectively adopted, the data writing channel and the data reading channel can be coded according to the same coding mode, namely a coding value table is shared, and the coding value table comprises the coding values and the effective bit widths corresponding to the coding values.

Step 303, counting the data of the effective bit width according to the counter corresponding to the effective bit width determined by the trigger;

in the embodiment of the present application, each data bit width indication signal coded value corresponds to a counter, and the counter is used for recording the number of different valid bit width data.

As an optional implementation manner, the triggering a counter corresponding to the determined valid bit width includes:

And judging that data is transmitted on the data channel through the first indication signal and the second indication signal, determining the effective bit width of the data through the current transmission bit width indication signal, enabling a corresponding counter to count through the third indication signal, and realizing the classified counting of the data with different data bit widths.

In this embodiment, for a read data channel, the third indication signal is RCOUNT _ EN in table 1 above, and for a write data channel, the third indication signal is WCOUNT _ EN in table 1 above;

and when the first indication signal and the second indication signal are high level at the same time, determining that data is transmitted on the data channel, and data statistics needs to be carried out, triggering a third indication signal at the moment, and enabling a corresponding counter by the third indication signal according to the effective bit width of the data.

As an optional implementation manner, the counters include a first counter for counting data transmitted in the data reading channel and corresponding to different effective bit widths, and a second counter for counting data transmitted in the data writing channel and corresponding to different effective bit widths;

In the embodiment of the present application, the first counter is denoted as R _ COUNT in table 1, and the second counter is denoted as W _ COUNT in table 1;

when data statistics is needed when it is determined that one piece of read data is transmitted on the read data channel, determining the effective bit width of the read data according to the transmission bit width indication signal coding value corresponding to the read data, enabling the corresponding first counter by the third indication signal, and updating the value of the corresponding first counter;

when it is determined that one piece of write data is transmitted on the write data channel and data statistics needs to be performed, determining the effective bit width of the write data according to the transmission bit width indication signal coding value corresponding to the write data, enabling the corresponding second counter by the third indication signal, and updating the numerical value of the corresponding second counter.

As an optional implementation manner, when the data statistics is finished, determining the bus bandwidth efficiency by using the number of data counted by each counter and the corresponding effective bit width and the statistical time includes:

In this embodiment of the present application, for a data channel, the data register is RDATA _ COUNT in table 1, and for a data channel, the data register is WDATA _ COUNT in table 1;

for the data reading channel, after the statistics is finished, the numerical value of each first counter is registered in a corresponding data reading register;

and for the data reading channel, after the statistics is finished, the numerical value of each second counter is registered in the corresponding data writing register.

Step 304, determining the bus bandwidth efficiency according to the data number counted by each counter and the corresponding effective bit width and the counting time when the data counting is finished;

reading the statistical time, wherein the number of data corresponding to each counter, namely the number of data with different effective data bit widths, is multiplied by the corresponding effective data bit widths respectively to obtain the bus bandwidth within the statistical time;

dividing the bus bandwidth in the statistical time by the statistical time to obtain the bus bandwidth efficiency;

the bus bandwidth efficiency calculated by using the actual effective bit width of the data is realized, and compared with the bus bandwidth efficiency calculated by using the fixed bit width of the interface in the prior art, the accuracy of the result is improved.

As an optional implementation manner, the determining the bus bandwidth efficiency by using the data number counted by each counter and the corresponding effective bit width and the counted time includes:

dividing the bus bandwidth by the statistical time to determine the bus bandwidth efficiency;

for a data reading channel, reading the value recorded in each data reading register and multiplying the value by the corresponding effective bit width of the data to obtain the total bit width of the data read in the statistical time;

for the data writing channel, reading the numerical value recorded in each data writing register and multiplying the numerical value by the corresponding effective bit width of the data to obtain the total bit width of the data written in the statistical time;

adding the total bit width of the read data and the total bit width of the write data to obtain a bus bandwidth within the statistical time;

and dividing the bus bandwidth in the statistical time by the statistical time to obtain the bus bandwidth efficiency.

The following provides a detailed method flow for bus bandwidth efficiency statistics in combination with corresponding examples, and mainly includes the following steps:

1) setting statistical time

The AXI bus efficiency statistic start time is COUNT _ start, and the AXI bus efficiency statistic END time is COUNT _ END. COUNT _ START and COUNT _ END are preset to calculate the AXI interface bandwidth efficiency statistics TIME COUNT _ TIME according to the TIMEs of COUNT _ START and COUNT _ END. The AXI _ CLOCK is an AXI bus interface CLOCK and is a counting unit of the number of read-write data on the read-write data channel.

2) Calculating the total number of write data of different AXI SIZEs on an AXI bus interface write data channel;

on the write data channel, a write data transfer is asserted when the AXI bus interface signals WVALID and WREADY are high at the same time, i.e., asserted at the same time. The effective bit width of valid data for AXI is also taken into account at this time.

Wherein, the pre-obtained transmission bit width indication signal code value of the data writing channel is shown in table 2, where table 2 is a transmission bit width indication signal code table in the data writing channel;

TABLE 2

AWSIZE[2:0]	Bit width, unit byte of transmission
		0b000	1byte, write data effective width of 8 bits
0b001	2byte, write data effective width of 16bit
		0b010	4byte, write data effective width of 32bit
0b011	8byte, write data effective width of 64bit
		0b100	16 bytes, write data effective width of 128 bits

As shown in table 2, the encoding values of the bit width indicator table correspond to the effective widths of the data one to one, and each data channel transmits one data, the actual effective bit width of the data is determined according to the current encoding value of the bit width indicator, for example: when awgize is 0b001, the corresponding write data effective bit width is 16 bits.

WCOUNT _ EN is high when WVALID and WREADY are defined to be high at the same time, and 5 counters W _ COUNT _ SIZE0, W _ COUNT _ SIZE1, W _ COUNT _ SIZE2, W _ COUNT _ SIZE3, and W _ COUNT _ SIZE4 are defined. Starting from the time COUNT _ START, at each clock cycle AXI _ CLK, if COUNT _ EN is high and awgize is binary 000, then W _ COUNT _ SIZE0 accumulates 1, i.e., W _ COUNT _ SIZE0 is W _ COUNT _ SIZE0+1, otherwise W _ COUNT _ SIZE0 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and awgize is binary 001, then W _ COUNT _ SIZE1 accumulates 1, i.e., W _ COUNT _ SIZE1 is W _ COUNT _ SIZE1+1, otherwise W _ COUNT _ SIZE1 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and awgize is binary 010, then W _ COUNT _ SIZE2 accumulates 1, i.e., W _ COUNT _ SIZE1 is W _ COUNT _ SIZE2+1, otherwise W _ COUNT _ SIZE2 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and awgize is binary 011, then W _ COUNT _ SIZE3 accumulates 1, i.e., W _ COUNT _ SIZE3 is W _ COUNT _ SIZE3+1, otherwise W _ COUNT _ SIZE3 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and awgize is binary 100, then W _ COUNT _ SIZE4 accumulates 1, i.e., W _ COUNT _ SIZE4 ═ W _ COUNT _ SIZE4+1, otherwise W _ COUNT _ SIZE4 remains the original value.

Until the time of COUNT _ END, the values of W _ COUNT _ SIZE0 to W _ COUNT _ SIZE4 are registered to WDATA _ COUNT _ SIZE0 to WDATA _ COUNT _ SIZE 4.

3) And calculating the total number of the read data of different AXI SIZEs on the AXI bus interface read data channel.

On the read data path, a read data transfer is asserted when both the AXI bus interface signals RVALID and RREADY are high, i.e., asserted at the same time. The effective bit width of valid data for AXI is also taken into account at this time.

The pre-obtained bit width indication signal encoding value of the read data channel is shown in table 3, where table 3 is a transmission bit width indication signal encoding table in the read data channel;

TABLE 3

ARSIZE[2:0]	Bit width, unit byte of transmission
		0b000	1byte, write data effective width of 8 bits
0b001	2byte, write data effective width of 16bit
		0b010	4byte, write data effective width of 32bit
0b011	8byte, write data effective width of 64bit
		0b100	16 bytes, write data effective width of 128 bits

As shown in table 3, the encoding values of the transmission bit width indication signal table are in one-to-one correspondence with the effective widths of the data, and each data channel transmits one data, the actual effective bit width of the data is determined according to the current encoding value of the transmission bit width indication signal, for example: when ARSIZE is 0b000, the corresponding write data effective bit width is 8 bits.

RCOUNT _ EN is high when RVALID and RRADAY are defined to be high at the same time, and 5 counters R _ COUNT _ SIZE0, R _ COUNT _ SIZE1, R _ COUNT _ SIZE2, R _ COUNT _ SIZE3, and R _ COUNT _ SIZE4 are defined.

Starting from the time COUNT _ START, at each clock cycle AXI _ CLK, if COUNT _ EN is high and ARSIZE is binary 000, then R _ COUNT _ SIZE0 accumulates 1, i.e., R _ COUNT _ SIZE0 is R _ COUNT _ SIZE0+1, otherwise R _ COUNT _ SIZE0 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and ARSIZE is binary 001, then R _ COUNT _ SIZE1 accumulates 1, i.e., R _ COUNT _ SIZE1 ═ R _ COUNT _ SIZE1+1, otherwise R _ COUNT _ SIZE1 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and ARSIZE is binary 010, then R _ COUNT _ SIZE2 accumulates 1, i.e., R _ COUNT _ SIZE1 ═ R _ COUNT _ SIZE2+1, otherwise R _ COUNT _ SIZE2 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and ARSIZE is binary 011, then R _ COUNT _ SIZE3 accumulates 1, i.e., R _ COUNT _ SIZE3 ═ R _ COUNT _ SIZE3+1, otherwise R _ COUNT _ SIZE3 remains the original value;

at each clock cycle AXI _ CLK, when COUNT _ EN is high and ARSIZE is binary 100, then R _ COUNT _ SIZE4 accumulates 1, i.e., R _ COUNT _ SIZE4 ═ R _ COUNT _ SIZE4+1, otherwise R _ COUNT _ SIZE4 remains the original value.

The values of R _ COUNT _ SIZE0 to R _ COUNT _ SIZE4 are registered to RDATA _ COUNT _ SIZE0 to RDATA _ COUNT _ SIZE4 until the COUNT _ END timing.

The bus bandwidth efficiency statistical method provided by the embodiment of the invention is implemented, and a detailed calculation method is given below, as follows:

reading registers after COUNT _ END time Point the total amount of data is calculated from the results of registers WDATA _ COUNT _ SIZE 0-WDATA _ COUNT _ SIZE4 and RDATA _ COUNT _ SIZE 0-RDATA _ COUNT _ SIZE4

DATA_BIT_NUM＝WDATA_COUNT_SIZE0*8+WDATA_COUNT_SIZE1*16+WDATA_COUNT_SIZE2*32+WDATA_COUNT_SIZE3*64+WDATA_COUNT_SIZE4*128+RDATA_COUNT_SIZE0*8+RDATA_COUNT_SIZE1*16+RDATA_COUNT_SIZE2*32+RDATA_COUNT_SIZE3*64+WDATA_COUNT_SIZE4*128。

Calculating AXI bus bandwidth efficiency according to a formula

AXI_EFFECT＝DATA_BIT_NUM/COUNT_TIME。

Compared with the old scheme, the method and the device take effective data bit width into consideration when calculating the bandwidth efficiency of the AXI interface, and the calculated bandwidth efficiency of the AXI is closer to the real bandwidth efficiency. The following compares the statistical effect of the scheme provided by the embodiment of the present application with the existing scheme by combining the specific examples:

scene one: the COUNT _ START time is 0s, and the COUNT _ END time is 1 s. The bandwidth statistic time is 1 s. The fixed bit width of the data is 128 bits, i.e., the data bit width of WDATA and RDATA is 128 bits. In the bandwidth counting time 1s, the total number W _ COUNT of read data is 10000, wherein the number of write data with the effective data bit width of 64 bits is 10000; the number of read data R _ COUNT is totally 20000, wherein the number of read data with an effective data bit width of 32 bits is 20000.

The calculation result of the bandwidth efficiency of the existing AXI bus is as follows:

the total data number is 10000+20000 which is 30000; the data bit width is 128 bits per N, and the bandwidth efficiency is 30000 × 128 bits/1 s 3.84 Mbps.

The calculation result of the bus bandwidth efficiency in the embodiment of the application is as follows:

the total number of data bits 10000 × 64+20000 × 32 is 1.920 Mbps.

The accuracy of the bus bandwidth efficiency calculation provided by the embodiment is improved by 50%.

Scene two: the COUNT _ START time is 0s, and the COUNT _ END time is 1 s. The bandwidth statistic time is 1 s. The fixed bit width of the data is 128 bits, i.e., the data bit width of WDATA and RDATA is 128 bits. In the bandwidth counting time 1s, the total number of read data W _ COUNT reaches 10000, wherein the number of write data with an effective data bit width of 64 bits is 8000, and the number of write data with an effective data bit width of 128 bits is 2000; the number of read data R _ COUNT is totally counted to 20000, wherein the number of the read data with the effective data bit width of 32 bits is 5000, the number of the read data with the effective data bit width of 64 bits is 10000, and the number of the data with the effective data bit width of 128 bits is 5000.

the total number of data bits is 8000 × 64+2000 × 128+32 × 5000+64 × 10000+128 × 5000 — 2.208 Mbps.

The accuracy of the calculation efficiency of the bus bandwidth efficiency provided by the embodiment is improved by 42.5%.

Example 2

The embodiment of the present application provides a device for bus bandwidth efficiency statistics, as shown in fig. 4, including:

an indication module 401, configured to trigger data statistics, and read a current data transmission indication signal and a current transmission bit width indication signal on an AXI bus interface in real time;

a determining module 402, configured to determine, according to the current transmission indication signal, when each data is transmitted on a data transmission channel, an effective bit width corresponding to the transmitted data according to the current transmission bit width indication signal;

a counting module 403, configured to trigger a counter corresponding to the determined effective bit width, and count the data of the effective bit width;

and the counting module 404 is configured to determine the bus bandwidth efficiency by using the number of data counted by each counter and the corresponding effective bit width and the counting time when the data counting is finished.

In some possible embodiments, the data transmission channels include a read data transmission channel and a write data transmission channel, and the counters include a first counter for counting data transmitted in the read data channel and corresponding to different effective bit widths, and a second counter for counting data transmitted in the write data channel and corresponding to different effective bit widths;

the determining module triggers a counter corresponding to the determined effective bit width, and the counter comprises:

when the determining module determines that the transmitted data is data on a data reading channel, triggering a first counter corresponding to the determined effective bit width;

and when the determining module determines that the transmitted data is data on the data writing channel, triggering a second counter corresponding to the determined effective bit width.

In some possible embodiments, the determining module determines that each data is transmitted on the data transmission channel, including:

the determining module reads a first indicating signal indicating whether data transmission is effective and a second indicating signal indicating whether data can be transmitted;

the determining module determines that one data is transmitted on the data transmission channel when the data transmission of the data channel is effective and the data can be transmitted;

the counter module triggers a counter corresponding to the determined effective bit width, and the counter comprises:

the determining module acquires the coded values of transmission bit width indicating signals corresponding to different effective bit widths of a data reading channel/a data writing channel in advance;

and determining the effective bit width corresponding to the transmitted data by a determining module according to the coding value of the current transmission bit width indication signal.

In some possible embodiments, the determining, by the counting module, the bus bandwidth efficiency by using the number of data counted by each counter and the corresponding effective bit width and the counted time includes:

the counting module multiplies the data number counted by each counter by the corresponding effective bit width and then sums the data to obtain the bus bandwidth of the data channel;

the counting module divides the bus bandwidth by the statistical time to determine the bus bandwidth efficiency.

In some possible embodiments, when the data statistics is finished, the statistics module determines the bus bandwidth efficiency by using the number of data counted by each counter and the corresponding effective bit width and the statistical time, including:

when the data statistics is finished, the statistical module registers the data number counted by each counter in a data register corresponding to the counter;

and the counting module reads the data number from the data register and determines the bus bandwidth efficiency according to the corresponding effective bit width and the counting time.

In some possible embodiments, the statistics module triggers performing data statistics, including:

the statistical module acquires the set statistical starting time and the statistical ending time;

and when the counting module determines that the counting starting moment is reached, triggering to carry out data counting.

Having described the method and apparatus for performing service element level-to-level calls in accordance with exemplary embodiments of the present application, an apparatus for performing service element level-to-level calls in accordance with another exemplary embodiment of the present application is described.

As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or program product. Accordingly, various aspects of the present application may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

In one possible embodiment, a device for bus bandwidth efficiency statistics according to the present application may include at least one processor, and at least one memory. Wherein the memory stores program code that, when executed by the processor, causes the processor to perform the steps of:

triggering a processor to carry out data statistics, and reading a current data transmission indication signal and a current transmission bit width indication signal on an AXI bus interface in real time;

according to the current transmission indication signal, when the processor determines that one data is transmitted on a data transmission channel, the processor determines the effective bit width corresponding to the transmitted data according to the current transmission bit width indication signal;

the processor triggers a counter corresponding to the determined effective bit width to count the data of the effective bit width;

and when the data statistics is finished, the processor determines the bus bandwidth efficiency by utilizing the data number counted by each counter and the corresponding effective bit width and the counting time.

the processor triggers a counter corresponding to the determined effective bit width, and the counter comprises:

when the processor determines that the transmitted data is data on a data reading channel, triggering a first counter corresponding to the determined effective bit width;

and when the processor determines that the transmitted data is data on the data writing channel, triggering a second counter corresponding to the determined effective bit width.

In some possible embodiments, the processor determines that each data is transmitted on the data transmission channel, including:

the processor reads a first indication signal indicating whether data transmission is effective or not and a second indication signal indicating whether data can be transmitted or not;

when the processor determines that the data transmission of the data channel is effective and can transmit data, determining that one data is transmitted on the data transmission channel;

the processor enables a counter corresponding to the determined valid bit width by a third indication signal.

In some possible embodiments, said transmitting the bit width indication signal and determining the valid bit width corresponding to the transmitted data includes:

the processor acquires the coded values of transmission bit width indication signals corresponding to different effective bit widths of a data reading channel/a data writing channel in advance;

and determining the effective bit width corresponding to the transmitted data by the processor according to the coded value of the current transmission bit width indication signal.

In some possible embodiments, the determining, by the processor, the bus bandwidth efficiency by using the data number counted by each counter and the corresponding valid bit width and the counted time includes:

the processor multiplies the data number counted by each counter by the corresponding effective bit width and then sums the data to obtain the bus bandwidth of the data channel;

when the data statistics is finished, the processor registers the data number counted by each counter in a data register corresponding to the counter;

and the processor reads the data number from the data register and determines the bus bandwidth efficiency according to the corresponding effective bit width and the statistical time.

In some possible embodiments, the processor triggers data statistics, including:

the processor acquires the set counting starting time and the counting ending time;

and when the processor determines that the counting starting time is reached, triggering to carry out data counting.

An apparatus 150 for bus bandwidth efficiency statistics according to this embodiment of the present application is described below with reference to the drawings. The electronic device 150 shown in fig. 5 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown, the electronic device 150 is in the form of a general-purpose electronic device. The components of the electronic device 150 may include, but are not limited to: the at least one processor 151, the at least one memory 152, and a bus 153 connecting the various system components (including the memory 152 and the processor 151).

Bus 153 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.

The electronic device 150 may also communicate with one or more external devices 154 (e.g., keyboard, pointing device, etc.), with one or more devices that enable a user to interact with the electronic device 150, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 150 to communicate with one or more other electronic devices. Such communication may occur via an input/output (I/O) interface 155. Also, the electronic device 150 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 156. As shown, the network adapter 156 communicates with other modules for the electronic device 150 over the bus 153. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 150, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

In one possible embodiment, the various aspects of the method for bus bandwidth efficiency statistics provided by the present application may also be implemented in the form of a program product comprising program code means for causing a computer device to carry out the method steps of a bus bandwidth efficiency statistics according to various exemplary embodiments of the present application described above in this specification, when the program product is run on the computer device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The program product for monitoring of the embodiments of the present application may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on an electronic device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method for bus bandwidth efficiency statistics, comprising:

2. The method of claim 1, wherein the data transmission channels comprise a read data transmission channel and a write data transmission channel, and the counters comprise a first counter corresponding to different effective bit widths for counting data transmitted on the read data channel and a second counter corresponding to different effective bit widths for counting data transmitted on the write data channel;

3. The method of claim 1 or 2, wherein determining each data transmitted on the data transmission channel comprises:

4. The method according to claim 2, wherein determining the valid bit width corresponding to the transmitted data according to the transmission bit width indication signal comprises:

5. The method according to claim 1 or 2, wherein determining the bus bandwidth efficiency by using the data number counted by each counter and the corresponding valid bit width and the counted time comprises:

6. The method according to claim 1 or 2, wherein when the data statistics is finished, determining the bus bandwidth efficiency by using the data number counted by each counter and the corresponding effective bit width and the statistical time comprises:

7. The method of claim 1 or 2, wherein triggering data statistics comprises:

acquiring the set counting starting time and the counting finishing time;

8. An apparatus for bus bandwidth efficiency statistics, comprising:

9. An apparatus for bus bandwidth efficiency statistics, comprising at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A computer storage medium, characterized in that the computer storage medium stores a computer program for causing a computer to perform the method according to any one of claims 1-7.