CN106933760A - A kind of dma controller and data uploading method based on AXI protocol - Google Patents
A kind of dma controller and data uploading method based on AXI protocol Download PDFInfo
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- CN106933760A CN106933760A CN201710146171.9A CN201710146171A CN106933760A CN 106933760 A CN106933760 A CN 106933760A CN 201710146171 A CN201710146171 A CN 201710146171A CN 106933760 A CN106933760 A CN 106933760A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The invention discloses a kind of dma controller and data uploading method based on AXI protocol, including channel module, the passage of information transfer is provided for whole controller；Arbitration modules, the arbitration transmission order that can pass through of selection is carried out to the information in passage and control module is sent to；Control module, for processing the read write command for receiving, is converted into meeting the reading and writing signal of AXI protocol, and spread out of；Data cache module, for receiving the data that will be uploaded from control module and transmission order from channel module；Interrupt module, receives the signal from control module and sends information transfer state to outside；Configuration interface module, is the interface for configuring above-mentioned each inside modules register parameters.A kind of dma controller and data uploading method based on AXI protocol compared with prior art, realize the high speed data delivery between ancillary equipment and memory, improve the operating efficiency of whole system.
Description
Technical field
The present invention relates to Computer Applied Technology field, specifically a kind of practical, based on AXI protocol DMA
Controller and data uploading method.
Background technology
In SOC design, with the continuous lifting of CPU disposal abilities, the bandwidth of bus and the work effect of each equipment are improved
Rate turns into the key for improving systematic function.Due to the extensive use of AXI buses high-performance and ARM microprocessor in itself, make
Obtaining AXI turns into widely used bus standard in SOC design.One high performance bus must have the periphery being compatible with to set
Standby interface, could construct an on-chip system with complete function.ARM companies often release new bus standard, all can be successive
The IP of each Peripheral Interface is provided, but these IP are often expensive.So needed to better meet specific project
Ask, at the same it is cost-effective, the project budget is reduced, independent research is carried out to some ancillary equipment, can equally meet performance requirement.
The read-write of data is without CPU execute instructions under dma operation mode, by peripheral hardware（Dma controller）Directly carry out data
Read-write.Therefore, a kind of dma controller and data uploading method based on AXI protocol are proposed, in the SOC based on AXI protocol
In, design meets the dma controller of AXI protocol, realizes the high speed data delivery between ancillary equipment and memory, improves whole
The operating efficiency of system.Present invention is primarily intended to design the dma controller compatible with AXI protocol, for being assisted based on AXI
The data for being responsible for some subsystems in the SOC systems of view are reported.
The content of the invention
Technical assignment of the invention is directed to above weak point, there is provided a kind of practical, based on AXI protocol DMA controls
Device and data uploading method.
A kind of dma controller based on AXI protocol, including with lower module：
Channel module, the passage of information transfer is provided for whole controller；
Arbitration modules, the arbitration transmission order that can pass through of selection is carried out to the information in passage and control module is sent to；
Control module, for processing the read write command for receiving, is converted into meeting the reading and writing signal of AXI protocol, and passed
Go out；
Data cache module, for receiving the data that will be uploaded from control module and transmission order from channel module；
Interrupt module, receives the signal from control module and sends information transfer state to outside；
Configuration interface module, is the interface for configuring above-mentioned each inside modules register parameters.
If the channel module inside includes dry passage, for receiving and processing data upload request, generation upload information
Order, be then sent to arbitration modules；And receive the upload information for having read and it is processed, produce transmission number
According to order, be then sent to data cache module.
The arbitration modules are arbitrated after receiving the requests for arbitration from passage, and arbitration result is re-send into passage
Module, channel module sends in selected passage according to arbitration result and communicates a command to arbitration modules；Arbitration modules receive biography
After defeated order, then transmission order is transformed into reading and writing order, is sent to control module, the number in bus is completed by control module
According to transmission.
The control module carries out the data transfer on physical channel, by command byte in reading order queue, sends
Corresponding operating, and corresponding data is sent to destination address according to the timing requirements of AXI protocol, so as to play the read-write of AXI buses
Parallel the characteristics of.
The interrupt module is used to receive channel number and transmission response from control module, believes to outside transmission state
Number, i.e., the signal that whether information transfer interrupts notifies outside current transmission state, the interrupt signal include completing interrupting and
Fault interrupt.
Configuration interface module is the interface of the internal register for configuring dma controller, its receive the outside data sent and
Control signal, the register that configuration is specified, or read the content of register.
A kind of data uploading method of the dma controller based on AXI protocol, its implementation process is：
First data upload requests are sent to dma controller；
Channel module inside dma controller is received and processes the upload request, produces the order of upload information；
The order for transmitting data is arbitrated into arbitration modules, to determine whether to be selected；
The transmission life that will be chosen is transmitted to control module through arbitration modules, and the control module is converted the data into and meets AXI protocol
Signal；At this moment channel module receives the upload information that has read and it is processed, and produces the order of transmission data；
According to the order of transmission data, the converted signal for meeting AXI protocol is carried out data transmission.
The data of the control module treatment read from AXI buses, and the data that should be read from AXI buses are divided into two classes, one
Class is to be directly entered the data that the expression of data cache module will be uploaded, and a class is the data upload requests for entering channel module
Order, data transfer command is produced in channel module by treatment, is sent to data cache module, after the combination of two class data again
Carry out data transmission.
After the order for transmitting data enters arbitration modules, arbitration modules are arbitrated first, and arbitration result is sent
To channel module, channel module sends in selected passage according to arbitration result communicate a command to arbitration modules again；Arbitration mould
After block receives transmission order, then transmission order is transformed into reading and writing order, is sent to control module, complete total by control module
Data transfer on line；
The read write command that control module will be received is converted into meeting the reading and writing signal of AXI protocol, so as to complete the number in bus
According to transmission.
Also include the step of transmission state is sent by interrupt module, the interrupt module is received and comes from control module channel number
And transmission response, to interrupt signal is sent outside dma controller, notify that outside current transmission state, the transmission state refer to
Interrupt status, including complete to interrupt and fault interrupt, the outside refers to the processor being connected with dma controller.
A kind of dma controller and data uploading method based on AXI protocol of the invention, with advantages below：
A kind of dma controller and data uploading method based on AXI protocol of the invention, in the SOC systems based on AXI protocol
The data for being responsible for some subsystems in system are reported, and realize the high speed data delivery between ancillary equipment and memory, are improve
The operating efficiency of whole system, while specific project demands have been better met, it is cost-effective, the project budget is reduced, it is practical
Property is strong, it is easy to accomplish, it is easy to promote.
Brief description of the drawings
For the clearer explanation embodiment of the present invention or the technical scheme of prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for technology description is briefly described, it should be apparent that, drawings in the following description are only this hair
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with root
Other accompanying drawings are obtained according to these accompanying drawings.
Accompanying drawing 1 realizes schematic diagram for of the invention.
Specific embodiment
In order that those skilled in the art more fully understand the present invention program, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.Obviously, described embodiment is only a part of embodiment of the invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, belongs to the scope of protection of the invention.
As shown in Figure 1, a kind of dma controller based on AXI protocol, gives the overall structure and mould of DMA controllers
Block is divided, and describes the function and method for designing of each submodule of dma controller.Present invention is primarily intended to design and AXI
The dma controller of protocol-compliant, the data for being responsible for some subsystems in the SOC systems based on AXI protocol are uploaded.
Including following module channels module；Arbitration modules；Configuration interface module；Interrupt module；Data cache module；Control
Module.
Wherein：
Channel module, the passage of information transfer is provided for whole controller；
Arbitration modules, the arbitration transmission order that can pass through of selection is carried out to the information in passage and control module is sent to；
Control module, for processing the read write command for receiving, is converted into meeting the reading and writing signal of AXI protocol, and passed
Go out；
Data cache module, for receiving the data that will be uploaded from control module and transmission order from channel module；
Interrupt module, receives the signal from control module and sends information transfer state to outside；
Configuration interface module, is the interface for configuring above-mentioned each inside modules register parameters.
If the channel module inside includes dry passage, for receiving and processing data upload request, generation upload information
Order, be then sent to arbitration modules；And receive the upload information for having read and it is processed, produce transmission number
According to order, be then sent to data cache module.
The arbitration modules are arbitrated after receiving the requests for arbitration from passage, and arbitration result is re-send into passage
Module, channel module sends in selected passage according to arbitration result and communicates a command to arbitration modules；Arbitration modules receive biography
After defeated order, then transmission order is transformed into reading and writing order, is sent to control module, the number in bus is completed by control module
According to transmission.
The control module carries out the data transfer on physical channel, by command byte in reading order queue, sends
Corresponding operating, and corresponding data is sent to destination address according to the timing requirements of AXI protocol, so as to play the read-write of AXI buses
Parallel the characteristics of.
The interrupt module is used to receive channel number and transmission response from control module, believes to outside transmission state
Number, i.e., the signal that whether information transfer interrupts notifies outside current transmission state, the interrupt signal include completing interrupting and
Fault interrupt.
Configuration interface module is the interface of the internal register for configuring dma controller, its receive the outside data sent and
Control signal, the register that configuration is specified, or read the content of register.For example, the module can receive from interrupt module
Error of transmission order, configures corresponding interrupt register for inquiry.
A kind of data uploading method of the dma controller based on AXI protocol, its implementation process is：
First data upload requests are sent to dma controller；
Channel module inside dma controller is received and processes the upload request, produces the order of upload information；
The order for transmitting data is arbitrated into arbitration modules, to determine whether to be selected；
The transmission life that will be chosen is transmitted to control module through arbitration modules, and the control module is converted the data into and meets AXI protocol
Signal；At this moment channel module receives the upload information that has read and it is processed, and produces the order of transmission data；
According to the order of transmission data, the converted signal for meeting AXI protocol is carried out data transmission.
The data of the control module treatment read from AXI buses, and the data that should be read from AXI buses are divided into two classes, one
Class is to be directly entered the data that the expression of data cache module will be uploaded, and a class is the data upload requests for entering channel module
Order, data transfer command is produced in channel module by treatment, is sent to data cache module, after the combination of two class data again
Carry out data transmission.
After the order for transmitting data enters arbitration modules, arbitration modules are arbitrated first, and arbitration result is sent
To channel module, channel module sends in selected passage according to arbitration result communicate a command to arbitration modules again；Arbitration mould
After block receives transmission order, then transmission order is transformed into reading and writing order, is sent to control module, complete total by control module
Data transfer on line；
The read write command that control module will be received is converted into meeting the reading and writing signal of AXI protocol, so as to complete the number in bus
According to transmission.
Also include the step of transmission state is sent by interrupt module, the interrupt module is received and comes from control module channel number
And transmission response, to interrupt signal is sent outside dma controller, notify that outside current transmission state, the transmission state refer to
Interrupt status, including complete to interrupt and fault interrupt, the outside refers to the processor being connected with dma controller.
The dma controller compatible with AXI protocol for designing herein and its data transmission method based on the controller, more
Frequent substantial amounts of data transfer in project where being adapted to is a kind of dedicated for the DMA controls based on AXI bus on-chip systems
Device processed.Compared to existing technology, internal logic structure is improved, is employed on interface and is met the special main equipment of AXI protocol and connect
Mouth, more conducively SOC internal data transfers.
Each embodiment is described by the way of progressive in this specification, and what each embodiment was stressed is and other
The difference of embodiment, between each embodiment same or similar part mutually referring to.For being filled disclosed in embodiment
For putting, because it is corresponded to the method disclosed in Example, so description is fairly simple, related part is referring to method part
Illustrate.
A kind of dma controller and data uploading method based on AXI protocol provided by the present invention have been carried out in detail above
It is thin to introduce.Specific case used herein is set forth to principle of the invention and implementation method, and above example is said
It is bright to be only intended to help and understand the method for the present invention and its core concept.It should be pointed out that for the ordinary skill of the art
For personnel, under the premise without departing from the principles of the invention, some improvement and modification can also be carried out to the present invention, these improvement
Also fallen into the protection domain of the claims in the present invention with modification.
Claims (10)
1. a kind of dma controller based on AXI protocol, it is characterised in that including with lower module：
Channel module, the passage of information transfer is provided for whole controller；
Arbitration modules, the arbitration transmission order that can pass through of selection is carried out to the information in passage and control module is sent to；
Control module, for processing the read write command for receiving, is converted into meeting the reading and writing signal of AXI protocol, and passed
Go out；
Data cache module, for receiving the data that will be uploaded from control module and transmission order from channel module；
Interrupt module, receives the signal from control module and sends information transfer state to outside；
Configuration interface module, is the interface for configuring above-mentioned each inside modules register parameters.
2. a kind of dma controller based on AXI protocol according to claim 1, it is characterised in that in the channel module
If portion includes dry passage, it is then sent to arbitrate mould with processing data upload request, the order of generation upload information for receiving
Block；And receive the upload information for having read and it is processed, the order of transmission data is produced, it is then sent to data
Cache module.
3. a kind of dma controller based on AXI protocol according to claim 1, it is characterised in that the arbitration modules connect
Arbitrated after receiving the requests for arbitration from passage, and arbitration result is re-send into channel module, channel module is according to arbitration
Result sends in selected passage and communicates a command to arbitration modules；After arbitration modules receive transmission order, then transmission is ordered
It is transformed into reading and writing order, is sent to control module, the data transfer in bus is completed by control module.
4. a kind of dma controller based on AXI protocol according to claim 1, it is characterised in that the control module is entered
Data transfer on row physical channel, by command byte in reading order queue, sends corresponding operating, and according to AXI protocol
Timing requirements corresponding data is sent to destination address so that the characteristics of playing AXI bus read-while writings.
5. a kind of dma controller based on AXI protocol according to claim 1, it is characterised in that the interrupt module is used
In channel number and transmission response from control module is received, send what whether status signal, i.e. information transfer interrupted to outside
Signal, notifies outside current transmission state, and the interrupt signal includes completing to interrupt and fault interrupt.
6. a kind of dma controller based on AXI protocol according to claim 1, it is characterised in that configuration interface module is
The interface of the internal register of dma controller is configured, it receives the outside data and control signal sent, the deposit that configuration is specified
Device, or read the content of register.
7. a kind of data uploading method of the dma controller based on AXI protocol, it is characterised in that its implementation process is：
First data upload requests are sent to dma controller；
Channel module inside dma controller is received and processes the upload request, produces the order of upload information；
The order for transmitting data is arbitrated into arbitration modules, to determine whether to be selected；
The transmission life that will be chosen is transmitted to control module through arbitration modules, and the control module is converted the data into and meets AXI protocol
Signal；At this moment channel module receives the upload information that has read and it is processed, and produces the order of transmission data；
According to the order of transmission data, the converted signal for meeting AXI protocol is carried out data transmission.
8. the data uploading method of a kind of dma controller based on AXI protocol according to claim 7, it is characterised in that
The data of the control module treatment read from AXI buses, and the data that should be read from AXI buses are divided into two classes, and a class is direct
Into the data that the expression of data cache module will be uploaded, a class is to enter the data upload requests order of channel module,
Data transfer command is produced by treatment in channel module, data cache module is sent to, two class data enter line number again after combining
According to transmission.
9. the data uploading method of a kind of dma controller based on AXI protocol according to claim 7, it is characterised in that
After the order for transmitting data enters arbitration modules, arbitration modules are arbitrated first, and arbitration result is sent into passage mould
Block, channel module sends in selected passage according to arbitration result communicate a command to arbitration modules again；Arbitration modules receive biography
After defeated order, then transmission order is transformed into reading and writing order, is sent to control module, the number in bus is completed by control module
According to transmission；
The read write command that control module will be received is converted into meeting the reading and writing signal of AXI protocol, so as to complete the number in bus
According to transmission.
10., according to a kind of data uploading method of any described dma controllers based on AXI protocol of claim 7-9, it is special
Levy and be, also including sending transmission state by interrupt module the step of, the interrupt module receive come from control module channel number
And transmission response, to interrupt signal is sent outside dma controller, notify that outside current transmission state, the transmission state refer to
Interrupt status, including complete to interrupt and fault interrupt, the outside refers to the processor being connected with dma controller.
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Cited By (9)
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| CN108845962A (en) * | 2018-05-23 | 2018-11-20 | 中国电子科技集团公司第三十八研究所 | Streaming dma controller based on high-speed AD converter interface protocol |
| CN109902044A (en) * | 2019-02-28 | 2019-06-18 | 厦门码灵半导体技术有限公司 | A kind of control system, a set control system and its design method, electronic device |
| CN109947677A (en) * | 2019-02-27 | 2019-06-28 | 山东华芯半导体有限公司 | Support the AXI bus bit width conversion device and data transmission method of out-of-order function |
| CN110674075A (en) * | 2019-09-27 | 2020-01-10 | 山东华芯半导体有限公司 | Method and system for realizing AXI bus broadcasting mechanism |
| CN111290715A (en) * | 2020-02-24 | 2020-06-16 | 山东华芯半导体有限公司 | Safe storage device based on partition implementation |
| CN112732501A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Test method and multiprocessor SOC chip |
| CN113468084A (en) * | 2021-05-28 | 2021-10-01 | 北京时代民芯科技有限公司 | Multi-mode DMA data transmission system |
| CN115048323A (en) * | 2022-08-16 | 2022-09-13 | 南京芯驰半导体科技有限公司 | Data transmission system and method based on DMA handshake protocol |
| CN115391247A (en) * | 2022-08-12 | 2022-11-25 | 青岛汉泰智能科技有限公司 | PHY data transmission system |
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| CN109947677A (en) * | 2019-02-27 | 2019-06-28 | 山东华芯半导体有限公司 | Support the AXI bus bit width conversion device and data transmission method of out-of-order function |
| CN109902044A (en) * | 2019-02-28 | 2019-06-18 | 厦门码灵半导体技术有限公司 | A kind of control system, a set control system and its design method, electronic device |
| CN110674075A (en) * | 2019-09-27 | 2020-01-10 | 山东华芯半导体有限公司 | Method and system for realizing AXI bus broadcasting mechanism |
| CN111290715A (en) * | 2020-02-24 | 2020-06-16 | 山东华芯半导体有限公司 | Safe storage device based on partition implementation |
| CN111290715B (en) * | 2020-02-24 | 2023-04-28 | 山东华芯半导体有限公司 | Safe storage device based on partition realization |
| CN112732501A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Test method and multiprocessor SOC chip |
| CN113468084A (en) * | 2021-05-28 | 2021-10-01 | 北京时代民芯科技有限公司 | Multi-mode DMA data transmission system |
| CN113468084B (en) * | 2021-05-28 | 2023-08-29 | 北京时代民芯科技有限公司 | Multimode DMA data transmission system |
| CN115391247A (en) * | 2022-08-12 | 2022-11-25 | 青岛汉泰智能科技有限公司 | PHY data transmission system |
| CN115391247B (en) * | 2022-08-12 | 2023-11-03 | 青岛汉泰智能科技有限公司 | PHY data transmission system |
| CN115048323A (en) * | 2022-08-16 | 2022-09-13 | 南京芯驰半导体科技有限公司 | Data transmission system and method based on DMA handshake protocol |
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