CN109285580B - Data preprocessing device and method and asynchronous double-end random access memory system - Google Patents
Data preprocessing device and method and asynchronous double-end random access memory system Download PDFInfo
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- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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Abstract
The invention provides a data preprocessing device, a data preprocessing method and an asynchronous double-end random access memory system; the device comprises a first read-write control circuit, a first data cache circuit, a second data cache circuit and a second read-write control circuit which are connected in sequence; the first data cache circuit is used for receiving and caching a first write request; the first read-write control circuit is used for storing first write data into the asynchronous double-ended random access memory according to the first data address; the second data cache circuit is used for receiving and caching the first write request; the second read-write control circuit is used for receiving the first read request and outputting data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory. The invention improves the working efficiency of the asynchronous double-end random access memory.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a data preprocessing apparatus and method, and an asynchronous dual-ended random access memory system.
Background
A dual-port RAM (Random Access Memory)) is a Static Random Access Memory (SRAM) having two completely independent sets of data lines, address lines, and read/write control lines, and allowing two independent systems to randomly Access the Memory at the same time, i.e., a shared multi-port Memory.
The problem to be noticed in the use of the dual-port RAM is how to avoid contention of two ends for the same RAM memory cell; this problem is usually solved by an anti-collision mode in a plug-in wait state, a signal lamp anti-collision mode or an interrupt anti-collision mode. However, for asynchronous dual-ended RAM, the above anti-collision methods work less efficiently.
Disclosure of Invention
In view of the above, the present invention provides a data preprocessing apparatus and method and an asynchronous dual-ended random access memory system, so as to improve the working efficiency of the asynchronous dual-ended random access memory.
In a first aspect, an embodiment of the present invention provides a data preprocessing apparatus, where the apparatus is connected to an asynchronous dual-ended random access memory; the device comprises a first read-write control circuit, a first data cache circuit, a second data cache circuit and a second read-write control circuit which are connected in sequence; the first read-write control circuit is connected with a first port of the asynchronous double-end random access memory; the second read-write control circuit is connected with a second port of the asynchronous double-ended random access memory; the first data cache circuit is used for receiving and caching a first write request; the first write request comprises first write data and a first data address; the first read-write control circuit is used for storing first write data into the asynchronous double-ended random access memory according to the first data address; the second data cache circuit is used for receiving and caching the first write request; the second read-write control circuit is used for receiving the first read request and outputting data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory; the first read request includes the second data address.
With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, where the first data cache circuit includes a first logic control unit and a first data cache unit that sets a space size; the first logic control unit is used for receiving a first write request and writing first write data and a first data address into the first data cache unit; the first logic control unit is further configured to send the first write request to the second read-write control circuit.
With reference to the first possible implementation manner of the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where the second data cache circuit includes a second logic control unit and a second data cache unit that sets a space size; the second logic control unit is used for receiving the first write request and writing the first write data and the first data address into the second data cache unit.
With reference to the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, where the first read-write control circuit includes a first selector and a first control unit; the first control unit is used for generating a second write-in request when the read-write request is not received, and sending the second write-in request to the first port through the first selector so that the asynchronous double-end random access memory writes preset write-in data into a preset data address according to the caching sequence of the preset write-in data; the preset write data and the preset data address are buffered in the first data buffer circuit according to the time sequence.
With reference to the third possible implementation manner of the first aspect, an embodiment of the present invention provides a fourth possible implementation manner of the first aspect, where after the asynchronous dual-ended random access memory writes the preset write data into the preset data address according to the caching order of the preset write data, the first read-write control circuit is further configured to send a first clear instruction to the first data caching circuit; the first data cache circuit is also used for clearing the preset write-in data and the preset data address cached by the first data cache unit; the first data cache circuit is also used for sending a second clearing instruction to the second data cache circuit; the second data buffer circuit is also used for clearing the preset write-in data and the preset data address buffered by the second data buffer unit.
With reference to the fourth possible implementation manner of the first aspect, an embodiment of the present invention provides a fifth possible implementation manner of the first aspect, where the second read/write control circuit includes a second selector and a second control unit; the second control unit is used for searching data corresponding to the second data address by the writing requests with preset quantity cached in the second data cache circuit when receiving the first reading request, and outputting the data if the data is searched; and if the data address is not found, sending the first read request to the second port through the second selector so that the asynchronous double-ended random access memory outputs the data corresponding to the second data address.
In a second aspect, an embodiment of the present invention further provides a data preprocessing method, where the method is applied to the data preprocessing apparatus, and the apparatus is connected to an asynchronous dual-ended random access memory; the method comprises the following steps: the first data cache circuit receives and caches the first write request; the first write request comprises first write data and a first data address; the first read-write control circuit stores first write data into the asynchronous double-ended random access memory according to the first data address; the second data cache circuit receives and caches the first write request; the second read-write control circuit receives the first read request and outputs data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory; the first read request includes the second data address.
With reference to the second aspect, an embodiment of the present invention provides a first possible implementation manner of the second aspect, where the first data cache circuit includes a first logic control unit and a first data cache unit that sets a space size; the step of receiving and buffering the first write request by the first data buffer circuit includes: the first logic control unit receives the first write request and writes the first write data and the first data address into the first data cache unit.
With reference to the first possible implementation manner of the second aspect, an embodiment of the present invention provides a second possible implementation manner of the second aspect, where after the first data caching circuit receives and caches the first write request, the method further includes: the first logic control unit sends the first write request to the second read-write control circuit.
In a third aspect, an embodiment of the present invention further provides an asynchronous dual-ended random access memory system, including the data preprocessing apparatus, and further including an asynchronous dual-ended random access memory.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a data preprocessing device, a data preprocessing method and an asynchronous double-end random access memory system; the first data cache circuit receives and caches the first write request; the first read-write control circuit stores first write data into the asynchronous double-ended random access memory according to the first data address; the second data cache circuit receives and caches the first write request; after receiving the first read request, the second read-write control circuit outputs data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory; this approach improves the operating efficiency of the asynchronous double-ended random access memory.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention as set forth above.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a data preprocessing apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of another data preprocessing apparatus working with an asynchronous dual port RAM according to an embodiment of the present invention;
fig. 3 is a schematic block diagram of an Rw _ ctl module according to an embodiment of the present invention;
fig. 4 is a schematic block diagram of a Reg _ buf module according to an embodiment of the present invention;
FIG. 5 is a flowchart of a data preprocessing method according to an embodiment of the present invention;
FIG. 6 is a flow chart of another data preprocessing method according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an asynchronous dual-ended random access memory system according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Dual port RAM provides two completely independent ports, each with its own control, address and data lines. Generally, a dual-port RAM can read from the same address, but read and write or dual-write operations to the same address are not allowed. The problem to be noticed in the use of dual-port RAM is how to avoid contention of the same RAM cell by two ends, and generally, the following three anti-collision methods can be adopted:
(1) inserting an anti-collision mode of a waiting state. When the left and right ports access the RAM memory unit of the same address at the same time, the arbitration unit of the RAM will give a BUSY signal. The normal state of the BUSY signal is high level, when the left port accesses a storage unit, if the right port also operates the storage unit, the arbitration unit in the chip can make the signal BUSY low until the operation of the left port is completed and then restore the BUSY to high level. The operation on the dual-port RAM by the two ends is avoided.
(2) Signal lamp anticollision mode. The dual port RAM can avoid conflicts by operating the memory unit with application and release of the semaphore (also called token) for the port. One signal lamp corresponds to a corresponding number of storage units. And the signal lamp can be accessed at two ends of the double-port RAM. When the left port writes '0' into the signal lamp and then reads back the signal lamp, if the signal lamp is also '0', the left port is indicated to have the control right of the storage unit, and otherwise, the right port is indicated to have the control right of the storage unit.
(3) Interrupting the anti-collision mode. The two memory units with the highest addresses in the dual-port RAM can be used as a mailbox, and the left end and the right end can simultaneously operate the two memory units. The highest address is the right port mailbox, and the next highest address is the left port mailbox. When the right port writes in the left port mailbox, the signal INTL of the left port becomes low, and when the left port reads the own mailbox, the signal INTL becomes high again; similarly, when the left port writes into the right port mailbox, the signal INTR of the right port will become low, and when the right port reads its own mailbox, the signal INTR will be high again. The signals INTL and IN TR can be used as interrupt sources to transmit the status of using the memory cell to the other side through the mailbox to achieve the purpose of preventing collision.
The anti-collision method of the dual-port RAM is a general method, and in some specific applications, the general anti-collision processing method is not necessarily suitable. Taking switches or routers which are used in large quantities in network equipment as an example, in some applications, forwarding table look-up modules of the switches or routers are implemented by using a large quantity of RAM, and the forwarding of data frames needs to be guaranteed preferentially in design, so that the read rate of the RAM needs to be guaranteed preferentially. Secondly, with the popularization and application of the SDN network, the requirement for customizing network services is higher and higher, which also requires that a fast response is required for a write request of a forwarding RAM table. The solution is simpler if it is a synchronous RAM design, but is more difficult if it is an asynchronous RAM design.
Based on this, the embodiment of the invention provides a data preprocessing device, a data preprocessing method and an asynchronous double-ended random access memory system, which can be applied to the fields of asynchronous double-ended random access memories and other data storage and storage.
For the convenience of understanding the present embodiment, a detailed description will be given to a data preprocessing apparatus disclosed in the present embodiment.
The embodiment of the invention provides a data preprocessing device, which is connected with an asynchronous double-end random access memory; the device comprises a first read-write control circuit 100, a first data buffer circuit 110, a second data buffer circuit 120 and a second read-write control circuit 130 which are connected in sequence, and the structural schematic diagram is shown in fig. 1; the first read-write control circuit 100 is connected with a first port of the asynchronous double-ended random access memory; the second read-write control circuit 130 is connected with a second port of the asynchronous double-ended random access memory; the first data cache circuit 110 is configured to receive and cache the first write request; the first write request comprises first write data and a first data address; the first read-write control circuit 100 is configured to store first write data in the asynchronous dual-ended random access memory according to the first data address; the second data cache circuit 120 is configured to receive and cache the first write request; the second read/write control circuit 130 is configured to receive the first read request, and output data corresponding to the first read request according to a preset number of write requests buffered in the second data buffer circuit 120 and internal data of the asynchronous dual-ended random access memory; the first read request includes the second data address.
The first data cache circuit and the second data cache circuit are mainly used for caching write-in data and corresponding data addresses in the write-in request so as to prevent the write-in operation from being incomplete when the first port and the second port both have data write-in requests; when the port is idle, executing a write-in request by the data preprocessing device; the first data buffer circuit and the second data buffer circuit may have the same structure.
Specifically, the first data buffer circuit may be composed of a first logic control unit and a first data buffer unit with a set space size; when a write request (hereinafter referred to as a first write request) is sent to the first port, the first logic control unit is configured to receive the first write request, and write the first write data and the first data address into the first data cache unit; the first logic control unit is further configured to send the first write request to the second read-write control circuit.
Specifically, the second data buffer circuit may be composed of a second logic control unit and a second data buffer unit with a set space size; after the first logic control unit sends the first write request to the second read-write control circuit, the second logic control unit is used for receiving the first write request and writing the first write data and the first data address into the second data cache unit; similarly, when there is a write request to the second port, the first data buffer circuit and the second data buffer circuit perform the other operation.
In a write operation, the first read-write control circuit is mainly used for writing the write data buffered in the first data buffer unit into the asynchronous dual-ended random access memory at a proper time. The first read-write control circuit can be composed of a first selector and a first control unit; specifically, the first control unit is configured to generate a second write request when the read-write request is not received, and send the second write request to the first port through the first selector, so that the asynchronous dual-port random access memory writes the preset write data into the preset data address according to the caching sequence of the preset write data; the preset write data and the preset data address are buffered in the first data buffer circuit according to the time sequence.
The first read-write control circuit may be further configured to send a first clear instruction to the first data cache circuit after the asynchronous double-ended random access memory writes the preset write data into the preset data address according to the caching order of the preset write data; the first data cache circuit is also used for clearing the preset write data and the preset data address cached by the first data cache unit, namely deleting the data written into the asynchronous double-ended random access memory and the corresponding address; the first data cache circuit is also used for sending a second clearing instruction to the second data cache circuit; the second data buffer circuit is also used for clearing the preset write data and the preset data address buffered by the second data buffer unit, namely deleting the data written into the asynchronous double-ended random access memory and the corresponding address.
The second read/write control circuit may have the same structure as the first read/write control circuit; the second read/write control circuit may be configured by a second selector and a second control unit. When a read request (hereinafter referred to as a first read request) is sent to the first port, the second control unit is configured to search for data corresponding to the second data address in a preset number of write requests cached in the second data cache circuit when the first read request is received, and if the data is found, output the data; and if the data address is not found, sending the first read request to the second port through the second selector so that the asynchronous double-ended random access memory outputs the data corresponding to the second data address.
The embodiment of the invention provides a data preprocessing device; the first data cache circuit receives and caches the first write request; the first read-write control circuit stores first write data into the asynchronous double-ended random access memory according to the first data address; the second data cache circuit receives and caches the first write request; after receiving the first read request, the second read-write control circuit outputs data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory; this approach improves the operating efficiency of the asynchronous double-ended random access memory.
The embodiment of the invention also provides another data preprocessing device which is realized on the basis of the device shown in the figure 1; the device comprises two Reg _ buf modules (equivalent to the first data cache circuit and the second data cache circuit) and two Rw _ ctl modules (equivalent to the first read-write control circuit and the second read-write control circuit); the functional block diagram of the device working together with the asynchronous dual-port RAM is shown in FIG. 2; meanwhile, fig. 2 also shows the connection relationship between the apparatus and the asynchronous dual port RAM, and similarly to fig. 1, one Reg _ buf module is connected with one Rw _ ctl module, two Reg _ buf modules are connected, and the two Rw _ ctl modules are respectively connected with ports on both sides a and b of the asynchronous dual port RAM.
The RAM module is a standard asynchronous dual-port RAM core, and the left side and the right side of a dotted line are divided into different clock domains for reading and writing. The ports at the two sides of a and b receive interface signals; wherein En _ a _ in and En _ b _ in are interface enabling signals of two ports respectively; rd _ a _ in and Rd _ b _ in are interface read-write control signals of two ports respectively; addr _ a _ in and addr _ b _ in are address buses of interfaces of the two ports respectively; din _ a _ in and din _ b _ in are write data buses of the two ports respectively, and dout _ a _ in and dout _ b _ in are read data buses of the interfaces.
The Reg _ buf module realizes caching of data to be written, and in this embodiment, the Reg _ buf module can store 4 beats of addresses and data to be written into ram at most. The addr signal indicates addresses to be written into the ram 4, and the data signal indicates data to be written into the ram 4. Set _ ab, clr _ ab, addr _ ab, data _ ab, ack _ ab, and Set _ ba, clr _ ba, addr _ ba, data _ ba, ack _ ba are used for realizing the content synchronization of the two reg _ bufs on the left side and the right side. Wr _ rjct _ a, Wr _ rjct _ b are backpressure indications for write commands.
The Rw _ ctl module is a read-write control module of the RAM, which realizes control of read-write requests at each side of the RAM, and has main functions of realizing scheduling of RAM read-write commands on one hand and realizing selection of RAM read data on the other hand. The detailed design of the module will be described in the following description.
The external interface of the whole block diagram is very similar to the standard interface of the RAM, and two signals of wr _ rjct _ a and wr _ rjct _ b are added; and wr _ rjct _ a and wr _ rjct _ b are back pressure indications of the write commands on two sides a and b respectively, and when the cache of the Reg _ buf module is full, the write-in of the write commands is refused.
Specifically, the schematic diagram of the Rw _ ctl module is shown in fig. 3, and since the left and right sides are symmetrical in principle, only one side of the schematic diagram is shown. The Rw _ ctl module mainly includes two selectors (B1 and B2) and a Wr _ gen module (corresponding to the first control unit or the second control unit), wherein the Wr _ gen module is configured to compare whether addr _ a and addr are equal when a read operation is currently performed, and if so, the Wr _ gen module controls the selector B2 through the Rd _ sel signal to output data of the Reg _ buf module and controls the Wr _ sel signal at the same time, so that the read request is not transmitted to the interface of the RAM. If not, the Rd _ sel signal controls the selector B2 to output dout _ a _ in to dout _ a, and controls the Wr _ sel signal to transmit the read request to the interface of the RAM. In other words, when reading, if data to be read exists in the Reg _ buf module, the data is read from the Reg _ buf module, otherwise, the data is read from the RAM.
When the read-write request is idle, the Wr _ gen module generates a write request, controls the Wr _ sel signal, transmits the write request to an interface of the RAM, and simultaneously generates the Wr _ done and the Wr _ sel signal to inform the Reg _ buf module that data to be written in a certain cache is successfully written into the RAM.
Specifically, a schematic block diagram of the Reg _ buf module is shown in fig. 4, where the logic structures on both sides are consistent with the principle, and the logic structure on only one side is shown in the figure. The Reg _ buf module comprises a Reg _ buf _ ctl module (corresponding to the first logic control unit or the second logic control unit) and a cache unit with the depth of 4; the reg _ buf _ ctl module is used for performing logic control on data to be written, when data on the local side needs to be written into the RAM, firstly writing into a cache with the depth of 4 through En _ a, Rd _ a, addr _ a and data _ a interfaces, as shown in the figure, addr1 ~ 4, data1 ~ 4 bit depth is 4 write data buffer, and writes the address and data into the opposite Reg _ buf module through signals of Set _ ab, addr _ ab, data _ ab, Ack _ ab and the like, then informs the rw _ ctl module of the local side through the addr and data interfaces, inserts the write operation into the operation of the RAM, after the write operation is completed, the Rw _ ctl module informs the reg _ buf _ ctl module through signals Wr _ done and Wr _ sel, and after the corresponding address and data are deleted from the cache group, the reg _ buf _ ctl module deletes the corresponding address and data in the opposite reg _ buf through clr _ ab, data _ ab, addr _ ab and ack _ ab.
When data needs to be written on the opposite side, the writing processing process is similar to the above, the address and the data to be written are stored in the address data cache of the local side through Set _ ba, addr _ ba, data _ ba and Ack _ ba, and after the writing on the opposite side is completed, the address and the data with the writing are deleted from the address data cache of the local side through clr _ ba, addr _ ba, data _ ba and Ack _ ba.
In the embodiment of the invention, the two sides of the asynchronous dual-port RAM are respectively provided with the write cache reg _ buf, so that the write operation on the two sides can not influence the read operation; and a synchronous processing interface between the two write cache reg _ buf sides is arranged, so that the write operation of the RAM can not conflict and the data can not make mistakes even if the write operations of the two sides are performed simultaneously.
The embodiment of the invention also provides a data preprocessing method, which is applied to the data preprocessing device, and the device is connected with the asynchronous double-end random access memory; the flow chart of the method is shown in fig. 5, and comprises the following steps:
step 502, the first read-write control circuit stores the first write data into the asynchronous double-ended random access memory according to the first data address;
step 504, the second data cache circuit receives and caches the first write request;
step 506, the second read-write control circuit receives the first read request, and outputs data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory; the first read request includes the second data address.
Specifically, the first data buffer circuit includes a first logic control unit and a first data buffer unit with a set space size; the step of receiving and buffering the first write request by the first data buffer circuit includes: the first logic control unit receives the first write request and writes the first write data and the first data address into the first data cache unit.
After the first data cache circuit receives and caches the first write request, the first logic control unit sends the first write request to the second read-write control circuit.
The data preprocessing method provided by the embodiment of the invention has the same technical characteristics as the data preprocessing device provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
The embodiment of the invention also provides another data preprocessing method, which is realized on the basis of the steps shown in FIG. 5; the method is applied to the read-write operation process of the device, and the flow chart is shown in fig. 6, and the specific process is as follows:
(1) firstly, the request received by the port is write operation or read operation;
(2) when reading operation is carried out, judging whether the degree address in the reading operation is equal to any one of 4 addresses stored in the reg _ buf module or not;
(3) if yes, returning the corresponding data as read data; if not, sending the read address into the RAM, and returning the read result of the RAM as data;
(4) when the write operation is carried out, judging whether the cache space of the reg _ buf module is full;
(5) if yes, the write operation needs to be rejected, and wr _ rjct _ a/b is set high;
(6) if not, judging whether the local side performs the write operation, if so, storing the write address and the write data into reg _ buf modules on the local side and the opposite side.
(7) And after the write operation of the current side is finished, clearing corresponding entries in the current time and the opposite side reg _ buf.
(8) If the write operation is the opposite side, the side only responds to the write and clear operation of the reg _ buf module on the opposite side.
The data preprocessing device provided by the embodiment of the invention can realize that the write operation of the asynchronous RAM required in the design of some ASICs can not influence the read operation at all; especially in application scenes such as forwarding table lookup and the like, the full-speed implementation of the table lookup rate is effectively guaranteed; in addition, the write operations on the two sides cannot influence each other, and errors of data writing cannot be caused when multiple masters access the same RAM space.
Corresponding to the above embodiments, the embodiment of the present invention further provides an asynchronous dual-ended random access memory system, a schematic structural diagram of which is shown in fig. 7, and the asynchronous dual-ended random access memory system includes the data preprocessing device 70 and an asynchronous dual-ended random access memory 71.
The data preprocessing method and apparatus and the computer program product of the asynchronous dual-ended random access memory system provided in the embodiments of the present invention include a computer-readable storage medium storing a program code, where instructions included in the program code may be used to execute the method described in the foregoing method embodiments, and specific implementation may refer to the method embodiments, and will not be described herein again.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and/or the apparatus described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A data preprocessing apparatus, wherein the apparatus is coupled to an asynchronous dual-ended random access memory; the device comprises a first read-write control circuit, a first data cache circuit, a second data cache circuit and a second read-write control circuit which are connected in sequence; the first read-write control circuit is connected with a first port of the asynchronous double-ended random access memory; the second read-write control circuit is connected with a second port of the asynchronous double-ended random access memory;
the first data cache circuit is used for receiving and caching a first write request; the first write request includes first write data and a first data address;
the first read-write control circuit is used for storing the first write data into the asynchronous double-ended random access memory according to the first data address;
the second data cache circuit is used for receiving and caching the first write request;
the second read-write control circuit is used for receiving a first read request and outputting data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory; the first read request includes a second data address;
the first data cache circuit comprises a first logic control unit and a first data cache unit for setting the size of a space;
the first logic control unit is used for receiving a first write request and writing the first write data and the first data address into a first data cache unit;
the first logic control unit is further configured to send the first write request to the second read-write control circuit.
2. The apparatus of claim 1, wherein the second data buffer circuit comprises a second logic control unit and a second data buffer unit with a set space size;
the second logic control unit is configured to receive the first write request, and write the first write data and the first data address into a second data cache unit.
3. The apparatus of claim 1, wherein the first read/write control circuit comprises a first selector and a first control unit;
the first control unit is used for generating a second write request when the read-write request is not received, and sending the second write request to the first port through the first selector so that the asynchronous double-ended random access memory writes preset write data into preset data addresses according to the caching sequence of the preset write data; and the preset write data and the preset data address are cached in the first data cache circuit according to a time sequence.
4. The apparatus of claim 3, wherein the first read-write control circuit is further configured to send a first clear command to the first data cache circuit after the asynchronous double-ended random access memory writes the predetermined write data into the predetermined data address according to a buffering order of the predetermined write data;
the first data cache circuit is further configured to clear the preset write data and the preset data address cached by the first data cache unit;
the first data cache circuit is further configured to send a second flush instruction to the second data cache circuit;
the second data cache circuit is further configured to clear the preset write data and the preset data address cached by the second data cache unit.
5. The apparatus of claim 4, wherein the second read/write control circuit comprises a second selector and a second control unit;
the second control unit is used for searching the data corresponding to the second data address by the writing requests with preset quantity cached in the second data cache circuit when receiving the first reading request, and outputting the data if the data is searched; and if the first reading request is not found, sending the first reading request to the second port through the second selector so that the asynchronous double-ended random access memory outputs data corresponding to the second data address.
6. A data preprocessing method applied to the data preprocessing device of any one of claims 1 to 5, wherein the device is connected with an asynchronous double-ended random access memory; the method comprises the following steps:
the first data cache circuit receives and caches the first write request; the first write request includes first write data and a first data address;
the first read-write control circuit stores the first write data into the asynchronous double-ended random access memory according to the first data address;
the second data cache circuit receives and caches the first write request;
the second read-write control circuit receives a first read request and outputs data corresponding to the first read request according to a preset number of write requests cached in the second data cache circuit and internal data of the asynchronous double-ended random access memory; the first read request includes a second data address;
the first data cache circuit comprises a first logic control unit and a first data cache unit for setting the size of a space;
the step of the first data cache circuit receiving and caching a first write request comprises:
the first logic control unit receives a first write request and writes the first write data and the first data address into the first data cache unit;
after the first data cache circuit receives and caches the first write request, the method further comprises:
the first logic control unit sends the first write request to the second read-write control circuit.
7. An asynchronous double-ended random access memory system comprising the data preprocessing apparatus of any of claims 1-5, and further comprising an asynchronous double-ended random access memory.
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