CN101770437B - Structure and method for realizing concurrent reading and concurrent writing of IP of synchronous dual-port memory - Google Patents
Structure and method for realizing concurrent reading and concurrent writing of IP of synchronous dual-port memory Download PDFInfo
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- CN101770437B CN101770437B CN2008102467427A CN200810246742A CN101770437B CN 101770437 B CN101770437 B CN 101770437B CN 2008102467427 A CN2008102467427 A CN 2008102467427A CN 200810246742 A CN200810246742 A CN 200810246742A CN 101770437 B CN101770437 B CN 101770437B
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Abstract
The invention provides a synchronous dual-port memory IP based method for realizing the concurrent-read and concurrent-write operation. In the IP of the synchronous dual-port memory, when the reading and writing operation is performed on the same address at the same time, a reading and writing conflict at ports appears, so errors occur in the reading and writing operation. The method solves the problem of reading and writing conflict at the ports with a selective reading and writing control strategy and realizes the operation of reading original data in a memory first and then writing new data into the address in the same period. The method has the advantage of effectively solving the problem of reading and writing conflict at the ports of a dual-port memory; besides, a memory system with relatively stable performance can be obtained by designing in the method; and the whole design can be realized by an automated tool, and the design is portable, so the development cycle of a product can be shortened.
Description
Technical field
The present invention relates to a kind of device and method of realizing the concurrent reading and concurrent writing of IP of synchronous dual-port memory.
Background technology
To the system of a plurality of processors is arranged, it needs simultaneously storer to be carried out accessing operation, and this can cause the competition of serious data bus.And this can by adopting the storer of special construction, be avoided such as multiport memory.Current, multiport memory especially dual-ported memory is widely used in the data communications equipment.
For general synchronous dual-port memory intellecture property (Intellectual Property is called for short IP), usually when carrying out read-write operation to same address, can cause synchronization the mistake of read-write operation.Concrete condition is as follows: when a port carries out read operation and another port when simultaneously write operation being carried out in this address, the sense data mistake.The data that read this moment can not guarantee it is original data on this address, can not guarantee it is the data that newly write, but a unascertainable value; When two ports carried out read operation, the read operation of two ports was all correct, all the data on this address of output storage.That is to say that in common IP of synchronous dual-port memory, if another port carried out write operation to same address when a port carried out read operation, the data of then reading might be wrong.In order to guarantee the correctness of two port read and write operations in the above-mentioned situation, IP of synchronous dual-port memory can be made restriction to the clock of two ports usually.As shown in Figure 1, when read and write operation is carried out in same address, can require the clock clockA 101 of two ports and the rising edge certain interval of time t 100 of clockB 102 to avoid read/write conflict, thereby the read-write operation that guarantees two ports is all correct.
In the middle of some design, can require to carve at a time from a port of storer to read original data on a certain address, write new data from the another port to this address simultaneously.Such as: the in-line memory in the commercial fpga chip just needs to realize that the write-after-read in the same period operates.At this moment in order to guarantee the correctness of two port read write operations, traditional way is with these two operating interval regular hours.Such as when the design memory, add detection circuit, carry out again write operation after waiting read operation to finish.If adopt this mechanism, just need the whole storer of customization, bring very large cost and risk to design, and can prolong product development cycle.In order to realize fast this design, multiplexer storage IP adopts new design philosophy to realize as far as possible.
A kind of method is to postpone writing clock, as shown in Figure 2: the rising edge regular hour t that the rising edge of writing clock 202 is lagged behind read clock 201, guarantee to read first the legacy data on this address, then write new data.Can allow system clock 200 obtain writing clock by delay cell, lag behind all the time and read the clock regular hour as long as guarantee to write clock, just can in same period, realize the operation of write-after-read.The shortcoming of this method is that the time-delay of delay cell is subjected to the impact of flow-route and temperature larger, the time-delay of delay cell may have very large difference under different process, the temperature conditions, very difficult assurance in all cases this time-delay all satisfies condition, and when temperature change, the performance of system will be greatly affected, so system's deficient in stability.This method for designing also depends on technique, and the delay of delay cell is different under the different technique.Therefore when changing technique, these delay cells re-start design again, have increased the complicacy of design.
From above analysis, we can find out: clock delay is not a kind of good solution.It has increased the instability of system, and so that design has not portable to different process.For this reason, the present invention proposes the difficulty that a kind of disposal route that is different from these technology is brought to solve above-mentioned technology.
Summary of the invention
The purpose of this invention is to provide a kind of structure and method that realizes the concurrent reading and concurrent writing of IP of synchronous dual-port memory, the structure and the access control policy thereof that have proposed a kind of in-line memory are used for realizing that a port when the dual-port in-line memory carries out write operation, when read operation is carried out to same address simultaneously in the another port, can in same period, read first the legacy data on this address, then write the function of new data in this address.
For achieving the above object, the structure of the concurrent reading and concurrent writing of realization IP of synchronous dual-port memory provided by the invention is an embedded memory structure, and it mainly comprises:
IP of synchronous dual-port memory is used for the basic read-write operation of in-line memory;
Arbitration circuit, according to the control of port input message and level cache device cache information output control signal with the port signal buffer memory to the level cache device or send IP of synchronous dual-port memory to;
The level cache device is according to the control signal buffer memory of arbitration circuit the comprising data, address and write enable signal of port input separately;
The L2 cache device, comprising data, address and writing enable signal when rising edge clock arrives in the buffer memory level cache device;
Selector switch, the control signal that provides according to arbitration circuit determine to IP of synchronous dual-port memory transmit comprise data, address and write the port input signal that enables or the level cache device in comprise data, address and write the signal that enables; And
Read-out control circuit is according to the data in the control of the information in port input message and the L2 cache device output L2 cache device or the output data of output IP of synchronous dual-port memory.
Arbitration circuit of the present invention has the port signal input port, level cache device signal input port; This arbitration circuit according to the signal in port input signal and level cache device output control signal with port input signal buffer memory to the level cache device or directly input dual-ported memory IP, or the signal in the level cache device is sent in the IP of synchronous dual-port memory.
Level cache device of the present invention possesses the input end of receiving port input signal, and its control signal that provides according to arbitration circuit is the buffer memory the port input signal that comprises data, address and write enable signal selectively.
L2 cache device of the present invention possesses the input end that receives level cache device output signal, the output signal that buffer memory comprised data, address and writes the port level cache device of enable signal when its rising edge at clock arrived.
Selector switch of the present invention is controlled according to the control signal of arbitration circuit output port signal is sent to IP of synchronous dual-port memory or sends the signal in the level cache device to IP of synchronous dual-port memory.
Read-out control circuit of the present invention is according to the data in the signal deciding output L2 cache device of buffer memory in port address input signal and the L2 cache device or the output data of output IP of synchronous dual-port memory.
The method of utilizing above-mentioned in-line memory to realize the concurrent reading and concurrent writing of IP of synchronous dual-port memory provided by the invention, determine the source of output data, the data that determine output are data in the L2 cache device or the output data of IP of synchronous dual-port memory, and the method comprises:
Relatively whether the first end port address is identical with the address in the first port L2 cache device, provides foundation for determining the output Data Source;
Relatively whether the first end port address is identical with the address in the second port L2 cache device, provides foundation for determining the output Data Source;
What judge buffer memory in the first port L2 cache device is write operation or read operation, provides foundation for determining the output Data Source;
What judge buffer memory in the second port L2 cache device is write operation or read operation, provides foundation for determining the output Data Source.
Also comprise in the method for the present invention:
Relatively whether the address of first and second port is identical, and whether buffer memory the port input signal provides foundation for the selector switch in the in-line memory selects port signal still to select signal in the level cache device and level cache device;
Relatively whether the first end port address is identical with the address in the first port level cache device, and whether buffer memory the port input signal provides foundation for the selection of the selector switch in in-line memory port signal is still selected signal in the level cache device and level cache device;
Relatively whether the second port address is identical with the address in the first port level cache device, and whether buffer memory the port input signal provides foundation for the selection of the selector switch in in-line memory port signal is still selected signal in the level cache device and level cache device;
Judge that the first port carries out write operation or carries out read operation, whether buffer memory the port input signal provides foundation for the selector switch in the in-line memory selects port signal still to select signal in the level cache device and level cache device;
Judge that the second port carries out write operation or carries out read operation, whether buffer memory the port input signal provides foundation for the selector switch in the in-line memory selects port signal still to select signal in the level cache device and level cache device;
What judge buffer memory in the first port level cache device is write operation or read operation, and whether buffer memory the port input signal provides foundation for the selector switch in the in-line memory selects port signal still to select signal in the level cache device and level cache device.
Effect of the present invention is:
Write operation was carried out to same address in the another port when port of first realization dual-ported memory carried out read operation, and can in same period, read first legacy data on this address, then write this read-write mode of new data, to satisfy system to the demand of storer.
It two is to obtain a stable dual-ported memory, reduces the impact that flow-route and temperature brings as far as possible.Avoid adopting clock delay, and realize that by the way of port signal being taked buffer memory the write-after-read operation can reduce the impact that flow-route and temperature brings, strengthen Systems balanth.
It three is as far as possible to reduce design risk and design cycle.In possible situation, the memory I P that as far as possible uses third party manufacturer to provide designs.The memory I P that adopts the third party to provide can avoid beginning design from basic storage unit, can greatly reduce the risk of reservoir designs, improves design efficiency.
It four is the flow processs that adopt as far as possible robotization, strengthens the portability of design.In case the code of the memory construction that the present invention proposes is achieved, just can with its by a kind of process transplanting to another kind of technique, and code does not need change or change seldom.The portability of this design can improve the efficient of design equally greatly.
Description of drawings
The rising edge clock of read operation and write operation must be separated by a period of time when Fig. 1 carried out read-write operation for existing IP of synchronous dual-port memory requirement to same address.
Fig. 2 is that prior art makes the rising edge clock of write operation lag behind the rising edge clock of read operation by delay cell.
Fig. 3 is dual-ported memory system construction drawing of the present invention
Fig. 4 is the principle flow chart of input signal selection of the present invention and cache policy
Fig. 5 is the principle flow chart that the present invention exports the data selection strategy
Fig. 6 is the decision logic process flow diagram of input signal selection of the present invention and cache policy
Fig. 7 is the decision logic process flow diagram that the present invention exports the data selection strategy
Embodiment
Strategy that the present invention carries has two key points: 1) selection of input signal and buffer memory; 2) selection of output data.These two key points realize by input signal selection and cache policy and output data selection strategy respectively.
Fig. 3 shows the structure of dual-ported memory system among the present invention, it comprises: IP of synchronous dual-port memory 300, arbitration circuit 301, read-out control circuit 302, level cache device 303 and 304, L2 cache device 303 ' and 304 ', and selector switch 305 and 306.
Wherein, arbitration circuit 301, level cache device 303 and 304 and the input signal mainly finished as shown in Figure 4 of selector switch 305 and 306 select and cache policy.Level cache device 303 is corresponding with the A port with selector switch 305, and the input signal of A port is operated; Level cache device 304 is corresponding with the B port with selector switch 306, and the input signal of B port is operated.Need to prove, level cache device 303 and 304 and L2 cache device 303 ' and 304 ' all are techniques well known, be not invention main points of the present invention, therefore its detailed internal structure and principle of work are no longer elaborated, do not recommend accompanying drawing yet.
Arbitration circuit 301 is with input signal: A port address signal 307, A port write enable signal 309, B port address signal 308, B port write enable signal 310, data in the A port level cache device 303, the address and write enable signal 319 and B port level cache device 304 in data, address and write enable signal 320 and judge through data selection and cache policy shown in Figure 4, control signal 311 according to judged result output control A port level cache device 303, the control signal 312 of control B port level cache device 304, the control signal 314 of the control signal 313 of control selector switch 305 and control selector switch 306, in order to control the level cache device, selector switch is finished data selection of the present invention and cache policy, the dual-port that reaches memory I P carries out read and write in the cycle at one time simultaneously, can avoid conflict and guarantee that whole dual-port embedded storage system can read and write the purpose of correct data.
Match with it, read-out control circuit 302 and L2 cache device 303 ', 304 ' and IP of synchronous dual-port memory jointly finish as shown in Figure 5 output data selection strategy.In output data selection strategy, to the address in L2 cache device 303 ' and 304 ' with write enable signal and judge.The input signal of read-out control circuit 302 derives from data, the address in L2 cache device 303 ' and 304 ' and writes enable signal, the output data of IP of synchronous dual-port memory, and the address signal of A, B port input, select according to output data selection strategy shown in Figure 5, finally export required data 322.
The output data selection strategy that the input signal selection that above-mentioned arbitration circuit 301 carries out and cache policy and read-out control circuit 302 carry out carries out simultaneously, only have two strategies to carry out simultaneously, port of guarantee dual-ported memory carries out write operation, when read operation is carried out to same address simultaneously in the another port, can read first legacy data on this address writes new data again to this address function.
Below in conjunction with accompanying drawing, the present invention will be described in more detail.
Fig. 3 is the structure of dual-ported memory of the present invention system.
The input signal of arbitration circuit 301 has: 307,308,309,310,319 and 320,301 concrete conditions according to above-mentioned input signal decide the control signal 311,312,313 and 314 of output.
Level cache device 303 and 304 input signal source are: the input signal 315,316 of A, B port, this input signal mainly comprise data, the address of two ports inputs and write and the signal such as enable; The control signal 311 and 312 of arbitration circuit 301 outputs; The clock signal 323 synchronous with IP of synchronous dual-port memory.The control signal 311 of level cache device 303 by arbitration circuit 301 output determine whether will be corresponding with it A port input signal 315 carry out buffer memory; The control signal 312 of level cache device 304 by arbitration circuit 301 output determine whether will be corresponding with it B port input signal 316 carry out buffer memory.Buffered signal in the level cache device 303 and 304 exports respectively selector switch 305 and 306 and L2 cache device 303 ' and 304 ' to, and they export arbitration circuit 301 simultaneously to.
L2 cache device 303 ' and 304 ' input signal source are: the output signal of A, B port level cache device 303,304, this output signal mainly comprise data, address and write and the signal such as enable.When the rising edge of clock signal 323 arrived, the signal 319 of buffer memory and 320 will be cached to respectively in L2 cache device 303 ' and 304 ' in the level cache device 303 and 304.L2 cache device 303 ' and 304 ' buffered signal comprise data, the address of buffer memory and write the signal such as enabling, and will export read-out control circuit 302 to after the rising edge of clock arrives, to finish the operation of sense data.
Selector switch 305 and 306 input source have: the input signal 315,316 of A, B port, this input signal mainly comprise data, the address of port input and write and the signal such as enable; The control signal 313 and 314 of arbitration circuit 301 outputs; And the buffered signal of output from level cache device 303 and 304, this signal mainly comprises data, address and writes and the signal such as enables.The signal 317 that selector switch 305 determines to send to memory I P by control signal 313 is port input signals 315 or is buffered in buffered signal 319 in the level cache device 303.The signal 318 that selector switch 306 determines to send to memory I P by control signal 314 is port signals 316 or is buffered in buffered signal 320 in the level cache device 304.
The input of read-out control circuit 302 source has: the address of buffer memory in A port address signal 307, B port address signal 308, the L2 cache device 303 ', write enable with data-signal 319 ' and L2 cache device 304 ' in buffer memory the address, write and enable and data-signal 320 ', and from the data of IP of synchronous dual-port memory output.Making it can decide by output data selection strategy shown in Figure 5 final output data 322 is buffered signal 319 ', 320 ' or the output data 321 of memory I P in the L2 cache device on earth.
The input signal of IP of synchronous dual-port memory 300 is the signal by selector switch 305 and 306 outputs; And clock signal 323.Decide the signal source of two ports of IP of synchronous dual-port memory, thereby determine the operation that two ports of IP of synchronous dual-port memory carry out in selector switch 305,306 judged results of carrying out according to as shown in Figure 4 input signal selection strategy.
IP of synchronous dual-port memory 300, level cache device 303 and 304 and L2 cache device 303 ' and 304 ' all be that rising edge at clock 323 triggers.For IP of synchronous dual-port memory, only when arriving, the rising edge of clock 323 just begins to carry out read-write operation.301 of arbitration circuits to the address of A, B port and write enable signal and level cache device 303 and 304 in buffer memory the address and write enable signal and compare and judge and export corresponding control signal 311,312,313 and 314.Selector switch 305 and 306 selects the situation of control end signal 313 and 314 to select the input port signal according to it, it directly with the signal of port input (comprise port data, write enable and whole signals such as address) transfer to IP of synchronous dual-port memory, perhaps with the signal of buffer memory in the level cache device (comprise buffer memory data, write enable and whole signals such as address) transfer to IP of synchronous dual-port memory.When the rising edge of clock 323 arrives, level cache device 303 and 304 according to the situation of its Enable Pin signal 311 and 312 to the data of A, B port, write enable and address etc. all signals carry out buffer memory or do not carry out buffer memory.For L2 cache device 303 ' and 304 ', as long as the rising edge one of clock 323 will carry out buffer memory with the signal of buffer memory in the level cache device (comprise data, write enable and whole signals such as address).Input signal of the present invention select and cache policy in, arbitration circuit 301 compares and the signal judged is the signal of buffer memory in port signal and level cache device 303 and 304.And in output data selection strategy of the present invention, read-out control circuit 302 compares and the signal judged is the signal of buffer memory in port signal and L2 cache device 303 ' and 304 '.
Below in conjunction with Fig. 4, data selection of the present invention and cache policy are elaborated.
The present invention utilizes a kind of optionally cache policy to avoid read/write conflict occurring and the mistake that causes sense data.Figure 4 shows that in the control chart 3 that selector switch 305 and 306 selects still the signal in the level cache device to be sent port signal to IP of synchronous dual-port memory, also control whether buffer memory port signal of level cache device 303 and 304 simultaneously.The below analyzes as an example of the A port example, the situation of B port can the like analyze, do not do repeat specification herein.
400 six contents need to judging for arbitration circuit 301 among the figure: compare 307 and 308, judge whether the A port is identical with the address of B port; Relatively whether the address of buffer memory is identical in 307 (addresses of A port) and its corresponding port level cache device 303; Relatively 308 (addresses of B port) with A port level cache device 303 in the address of buffer memory whether identical; (A port write enable signal) read to enable or writes to enable to judge 309; (B port write enable signal) read to enable or writes to enable to judge 310; And the enable signal of writing of buffer memory is read to enable or writes to enable in the level cache device 303 corresponding with the A port.
Be summed up, mainly need to process following five kinds of situations:
(1) A, the B port address is identical and the A port carries out write operation.This moment is no matter the B port carries out read operation or all can there be read/write conflict in write operation, need to be sent to the data in the level cache device 303 IP of synchronous dual-port memory 300 this moment, when the rising edge of clock 323 arrives, the operation that is sent to IP of synchronous dual-port memory 300 will be carried out by IP of synchronous dual-port memory, the write operation of A port is buffered to the level cache device 303 of A port simultaneously, and the original operation in the A port level cache device also is buffered to L2 cache device 303 ' simultaneously.To have the write operation of conflict to carry out buffer memory for read/write conflict appears in the port of avoiding IP of synchronous dual-port memory, adopt situation shown in Figure 41 to process this moment.
(2) A, B port address are identical, and the A port carries out read operation, but be cached with A port address identical write operation in the A port level cache device 303 this moment.Illustrate that the write operation of A port of last time owing to avoiding read/write conflict or other reason also to be buffered in the level cache device 303, do not give IP of synchronous dual-port memory 300 this moment.The write operation that be buffered in the level cache device 303 this moment is fed to IP of synchronous dual-port memory 300, when the rising edge of clock 323 arrives, this write operation is carried out by IP of synchronous dual-port memory 300, and the write operation of buffer memory is buffered to L2 cache device 303 ' in the level cache device 303 simultaneously.Because the former write operation in the level cache device 303 can be carried out by IP of synchronous dual-port memory 300, the operation of buffer memory also should be updated in its one-level buffer 303, otherwise may be wrong by the data that sense data selection strategy shown in Figure 5 is read.Therefore, when the rising edge of clock 323 arrives, the read operation of A port also simultaneously buffer memory to level cache device 303 and original write operation is override.For this situation, adopt situation 2 shown in Figure 4 to process.
(3) A, B port address difference, the A port carries out write operation, but is cached with the write operation identical with A port write operation address in the A port level cache device 303 at this moment.Although there are not read/write conflict in A, B port at this moment, but owing to be cached with the data that do not write IP of synchronous dual-port memory 300 last time in the A port level cache device, when the rising edge of clock 323 arrives, should allow IP of synchronous dual-port memory 300 carry out the write operation of buffer memory in the level cache devices 303, and the write operation of port also should be buffered simultaneously and original write operation is override to level cache device 303.That is: send the original operation in the level cache device 303 to IP of synchronous dual-port memory 300, when the rising edge of clock 323 arrives, this operation will be carried out by IP of synchronous dual-port memory 300, the simultaneously original operation in the level cache device 303 also can be buffered to L2 cache device 303 ', and the write operation of A port also can be buffered to level cache device 303 and original write operation is override.For this situation, adopt situation 3 shown in Figure 4 to process.
(4) A, B port address difference, the A port carries out read operation, and the B port carries out write operation, is cached with the write operation identical with the B port address in the A port level cache device 303.This moment, the read operation of A port should send IP of synchronous dual-port memory 300 to so that it exports the data on appropriate address, and the write operation of B port also can directly send IP of synchronous dual-port memory 300 to.At this moment, because up-to-date data have been written into IP of synchronous dual-port memory 300, the write operation that is buffered in the A port level cache device 303 should be covered by the read operation of A port.That is: the read operation with the A port directly sends IP of synchronous dual-port memory 300 to, when the rising edge of clock 323 arrives, this operation will be carried out by IP of synchronous dual-port memory 300 and read data on the appropriate address, simultaneously the original write operation in the level cache device 303 can be buffered to L2 cache device 303 ', and the read operation of A port also can be buffered simultaneously to level cache device 303 and original write operation is override.For this situation, adopt situation 4 shown in Figure 4 to process.
(5) for the situation outside above-mentioned four kinds of situations.The A port signal can directly send IP of synchronous dual-port memory 300 to, and the A port operation does not need to be cached in the level cache device 303 corresponding with its port.That is: when the rising edge of clock 323 arrived, IP of synchronous dual-port memory 300 was directly carried out the operation of A port, and the operation of buffer memory remains unchanged in the while level cache device 303, and the at this moment operation of L2 cache device 303 ' in still can buffer memory level cache device 303.For this situation, adopt other situation shown in Figure 5 to process.
Basic thought of the present invention is to avoid two ports of IP of synchronous dual-port memory to occur simultaneously same address being carried out the situation of read-write operation by the write operation that is cached with read/write conflict, thereby avoids from the data of IP of synchronous dual-port memory readout error.Because write operation might be buffered in the buffer, its data do not have write store IP, therefore need to judge that the data that need to read are in IP of synchronous dual-port memory or in buffer by certain method when sense data.The method of judging is exactly output selection strategy proposed by the invention.
Fig. 5 shows the selection strategy of output data among the present invention.As mentioned above, the output data selection strategy of Fig. 5 is mainly finished by read-out control circuit 302.Read-out control circuit 302 by output data selection strategy to input: in A port address signal 307, B port address signal 308, the L2 cache device 303 ' buffer memory write enable with address signal 319 ' and L2 cache device 304 ' in writing of buffer memory enable to judge with address signal 320 ', determine the output data of IP of synchronous dual-port memory 300 are still exported the data in the L2 cache device 303,304 according to judged result.The Output rusults of read-out control circuit 302 is followed the change of its input signal and is changed, after the rising edge of clock 323 arrives, the signal of buffer memory can change in the output data of IP of synchronous dual-port memory, the L2 cache device 303 ' and 304 ', and the output of read-out control circuit also corresponding change can occur thereupon.
Output data selection strategy is exported corresponding data according to the input signal 307 (A port address) of read-out control circuit 302,308 (B port addresss), 319 ' (in the A port L2 cache device 303 ' data, the address of buffer memory and write enable), 320 ' (in the B port L2 cache device 304 ' data, the address of buffer memory and write enable) according to output data selection strategy shown in Figure 5.The selection strategy of B port output data 322 and A port the same can the rest may be inferred obtains.The selection strategy of A port output data 322 mainly comprises seven parts 500,511,512,513,521,522 and 523.Wherein:
500 gives a readout control circuit 302 need to compare and judge the content: A comparison with the two port address buffer 303 'in the cached addresses are the same? 304 A comparison cached address port address and secondary cache 'is the same? Determine the secondary cache 303 'in the cache is a write operation or read operation (through the secondary cache 303' so that the cache write enable signal to judge)? Determine the secondary cache 304 'in the cache is a write operation or read operation (through the secondary cache 304' so that the cache write enable signal to judge)? These signals need to compare and judge the read control circuit 302 from the input 307,308,319 'and 320' provided.Compare and judge and to provide foundation for the source selection of output data 322 by these.
511,512 and 513 have been divided into three classes with 500 comparison judged result.
511 correspondences to be the A port address identical with the address of buffer memory in the B port L2 cache device 304 ' and L2 cache device 304 ' in buffer memory be the situation of write operation.Illustrate this moment to be cached with the data that need output in the L2 cache device 304, should be according to the data of buffer memory in the 521 output L2 cache devices 304 '.
512 correspondences be different from the address of buffer memory in the B port L2 cache device 304 ' at the A port address or L2 cache device 304 ' in buffer memory be in the situation of read operation, A port address and L2 cache device 303 ' middle buffer memory identical with the address of buffer memory in the A port L2 cache device 303 ' be the situation of write operation.Illustrate the data that do not have buffer memory to export in the B port L2 cache device 304 ' this moment, and be cached with the data that need output in the A port L2 cache device 303 ', and this moment should be according to the data of buffer memory in the 522 output A port L2 cache devices 303 '.
513 correspondences be situation outside 511 and 512, the data that all do not have buffer memory to export in L2 cache device 303 ' and 304 ' are described this moment, this moment should be according to the 523 output data 321 of exporting IP of synchronous dual-port memory 300.
521,522 and 523 provided respectively the source of exporting data 322 in 511,512 and 513 these three kinds of situations.
521 explanations are in 511 data that should export in this case buffer memory in the L2 cache device 304 '.
522 explanations are in 512 data that should export in this case buffer memory in the L2 cache device 303 '.
523 explanations are in the 513 output data 321 that should export in this case IP of synchronous dual-port memory 300.
Below in conjunction with Fig. 6 the flow process of selection of the present invention and cache policy is described.
Step 600: arbitration circuit 301 is judged extraneous address 307 to in-line memory A, B port and 308 whether identical according to signal 307 and 308.If the same enter step 601, if difference then enter step 611.
Step 601: arbitration circuit 301 judges that according to the enable signal 309 of writing of A port the A port carries out read operation or write operation.If read operation then enters step 602, if write operation then enters step 604.
Step 602: the output signal 319 of arbitration circuit 301 by level cache device 303 compares with A port address 307, judges whether the address of buffer memory in A port address 307 and the A port level cache device 303 is identical.If the same enter step 603, otherwise enter step 606.
Step 603: arbitration circuit 301 by in the output signal 319 of level cache device 303 what write that enable signal judges buffer memory in the A port level cache device 303 is read operation or write operation.If read operation then enters step 606, if write operation then enters step 604.
Step 604: arbitration circuit 301 output control signals 311 make the input signal (data, address and write enable etc.) 315 of A port enter level cache device 303.Arbitration circuit 301 output control signals 313 make selector switch 305 select to send the original signal in the A port level cache device 303 to IP of synchronous dual-port memory 300 simultaneously; After the rising edge of clock 323 arrives, IP of synchronous dual-port memory is carried out the original signal in the A port level cache device 303, and the original signal in the while A port level cache device 303 is buffered to L2 cache device 303 ', and the A port signal also is cached in the level cache device 303 to cover the original signal in 303.
Step 605: arbitration circuit 301 output control signals 311 make the input signal (data, address and write enable etc.) 315 of A port enter level cache device 303.Arbitration circuit 301 output control signals 313 make selector switch 305 select to send A port signal 315 to IP of synchronous dual-port memory 300 simultaneously.After the rising edge of clock 323 arrives, IP of synchronous dual-port memory is carried out the input signal of A port, and the original signal in the while A port level cache device 303 is buffered to L2 cache device 303 ', and the A port signal also is cached in the level cache device 303 to cover the original signal in 303.
Step 606: arbitration circuit 301 output control signals 311 make the input signal (data, address and write enable etc.) 315 of A port not enter level cache device 303.Arbitration circuit output control signal 313 makes selector switch 305 select to send A port signal 315 to IP of synchronous dual-port memory 300 simultaneously.After the rising edge of clock 323 arrived, IP of synchronous dual-port memory was carried out the input signal of A port, and the original signal in the A port level cache device 303 is buffered to L2 cache device 303 ', and the signal of buffer memory remains unchanged in the A port level cache device 303.
Step 611: arbitration circuit 301 judges that according to A port write enable signal 309 the A port carries out read operation or write operation.If read operation then enters step 612, if write operation then enters step 602.
Step 612: arbitration circuit 301 judges that according to B port write enable signal 310 the B port carries out read operation or write operation.If read operation then enters step 606, if write operation then enters step 613.
Step 613: whether the signal 319 of arbitration circuit 301 by buffer memory in B port address signal 308 and the A port level cache device 303 comes the address of buffer memory in comparison B port address 308 and the A port level cache device 303 identical.If identical, then enter step 614, otherwise enter step 606.
Step 614: arbitration circuit 301 by in the signal 319 of buffer memory in the A port level cache device 303 what write that enable signal judges buffer memory in the A port level cache device 303 is read operation or write operation.If read operation then enters step 606, if write operation then enters step 605.
Fig. 7 shows the selection strategy of A port output data 322 among the present invention, and it has provided A port output data is the data in output L2 cache device 303 ' and 304 ' or the rule of exporting the output data 321 of IP of synchronous dual-port memory 300.The selection strategy of B port output data is the same with the A port, can the rest may be inferred obtains.It is as follows that the output data selection strategy of A port comprises step:
Step 700: read-out control circuit 302 judges by the address signal in the signal 320 ' of A port address signal 307 and B port L2 cache device 304 ' middle buffer memory whether A port address 307 is identical with the address of B port L2 cache device 304 ' middle buffer memory.If the same enter step 701, otherwise enter step 702.
Step 701: read-out control circuit 302 by in the signal 320 ' of buffer memory in the B port L2 cache device 304 ' what write that enable signal judges buffer memory in the B port L2 cache device 304 ' is read operation or write operation.If read operation then enters step 702, if write operation then enters step 704.
Step 702: relatively whether A port address 307 is identical with the address of its port L2 cache device 303 ' middle buffer memory by the address signal in the signal 319 ' of A port address signal 307 and A port L2 cache device 303 ' middle buffer memory for read-out control circuit 302.If the same enter step 703, otherwise enter step 706.
Step 703: read-out control circuit 302 by in the signal 319 ' of buffer memory in the A port L2 cache device 303 ' what write that enable signal judges buffer memory in the A port L2 cache device 303 ' is read operation or write operation.If read operation then enters step 706, if write operation then enters step 705.
Step 704: the data of buffer memory in the read-out control circuit 302 output B port L2 cache devices 304 '.
Step 705: the data of buffer memory in the read-out control circuit 302 output A port L2 cache devices 303 '.
Step 706: the output data 321 of read-out control circuit 302 output storage IP300.
Emphasis of the present invention is to solve port of dual-ported memory to carry out write operation, the read/write conflict problem that the another port produces when simultaneously read operation being carried out in same address.When this conflict occurring, can realize reading first legacy data on this address writes new data again to this address function according to the strategy of the present invention's proposition.Because when powering on, the signal in all buffers can be cleared.As long as the situation of write operation does not appear simultaneously same address being carried out in the storer two-port, after the strategy that proposes according to the present invention is so controlled inputoutput data, will read all the time correct data.
In sum; although the present invention only discloses as above with an example; but it is not to limit the present invention; those skilled in the art are in the situation that does not break away from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention should be as the criterion with the content that the claim scope is defined.
Claims (8)
1. a device of realizing the concurrent reading and concurrent writing of IP of synchronous dual-port memory is an in-line memory, it is characterized in that, mainly comprises:
IP of synchronous dual-port memory is used for the basic read-write operation of in-line memory;
Arbitration circuit, according to the information output control signal in port input message and the level cache device, control with the port signal buffer memory to the level cache device or send IP of synchronous dual-port memory to;
The level cache device is according to the control signal buffer memory of arbitration circuit the comprising data, address and write enable signal of port input separately;
The L2 cache device, comprising data, address and writing enable signal in the buffer memory level cache device;
Selector switch, the control signal that provides according to arbitration circuit determine to IP of synchronous dual-port memory transmit comprise data, address and write the port input signal that enables or the level cache device in comprise data, address and write the signal that enables; And
Read-out control circuit is according to the data in the control of the information in in-line memory port Input Address information and the L2 cache device output L2 cache device or the output data of output IP of synchronous dual-port memory.
2. the device of the concurrent reading and concurrent writing of realization IP of synchronous dual-port memory as claimed in claim 1 is characterized in that, described arbitration circuit has the in-line memory of connection port signal input port, and connects level cache device signal input port; This arbitration circuit is according to the signal output control signal that connects in in-line memory port input signal and the level cache device, to connect in-line memory port input signal buffer memory to the level cache device, or directly input IP of synchronous dual-port memory, or the signal in the level cache device is sent in the IP of synchronous dual-port memory.
3. the device of the concurrent reading and concurrent writing of realization IP of synchronous dual-port memory as claimed in claim 1, it is characterized in that, described buffer possesses the input end that receives in-line memory port input signal, and its control signal that provides according to arbitration circuit is the buffer memory in-line memory port input signal that comprises data, address and write enable signal selectively.
4. the device of the concurrent reading and concurrent writing of realization IP of synchronous dual-port memory as claimed in claim 1, it is characterized in that, there are level cache device and L2 cache device, wherein: the selectable buffer memory port signal of control signal that the level cache device provides according to arbitration circuit, L2 cache device be used for when each rising edge clock arrives will buffer memory level cache device buffer memory comprise data, address and write enable signal.
5. the device of the concurrent reading and concurrent writing of realization IP of synchronous dual-port memory as claimed in claim 1, it is characterized in that described selector switch is controlled according to the control signal of arbitration circuit output the in-line memory port signal is sent to IP of synchronous dual-port memory or sends the signal in the level cache device to IP of synchronous dual-port memory.
6. the device of the concurrent reading and concurrent writing of realization IP of synchronous dual-port memory as claimed in claim 1, it is characterized in that described read-out control circuit is according to the data in the signal deciding output L2 cache device of buffer memory in in-line memory port Input Address signal and the L2 cache device or the output data of output IP of synchronous dual-port memory.
7. utilize in-line memory claimed in claim 1 to realize the method for the concurrent reading and concurrent writing of IP of synchronous dual-port memory, determine the source of output data, the data that determine output are data in the L2 cache device or the output data of IP of synchronous dual-port memory, and the method comprises:
Relatively whether the first end port address is identical with the address in the first port L2 cache device, provides foundation for determining the output Data Source;
Relatively whether the first end port address is identical with the address in the second port L2 cache device, provides foundation for determining the output Data Source;
What judge buffer memory in the first port L2 cache device is write operation or read operation, provides foundation for determining the output Data Source;
What judge buffer memory in the second port L2 cache device is write operation or read operation, provides foundation for determining the output Data Source;
When the first end port address is identical with the address of buffer memory in the second port L2 cache device, and buffer memory is write operation in the second port L2 cache device, then exports the data of buffer memory in the second port L2 cache device;
When the first end port address different from the address of buffer memory in the second port L2 cache device, perhaps
Buffer memory is read operation in the second port L2 cache device, and
The first end port address is identical with the address of buffer memory in the first port L2 cache device, and
Buffer memory is write operation in the second port L2 cache device, then exports the data of buffer memory in the first port L2 cache device;
Situation outside above-mentioned two kinds is then exported the output data of synchronous dual-port memory.
8. utilize in-line memory claimed in claim 1 to realize the method for the concurrent reading and concurrent writing of IP of synchronous dual-port memory, decision with port input signal buffer memory to the level cache device or directly input dual-ported memory IP, or send the signal in the level cache device to IP of synchronous dual-port memory, the method comprises:
Relatively whether the address of first and second port is identical, and whether buffer memory the port input signal provides foundation for selector switch selects port signal still to select signal in the level cache device and level cache device;
Relatively whether the first end port address is identical with the address in the first port level cache device, and whether buffer memory the port input signal provides foundation for selector switch selection port signal is still selected signal in the level cache device and level cache device;
Relatively whether the second port address is identical with the address in the first port level cache device, and whether buffer memory the port input signal provides foundation for selector switch selection port signal is still selected signal in the level cache device and level cache device;
Judge that the first port carries out write operation or carries out read operation, whether buffer memory the port input signal provides foundation for selector switch selects port signal still to select signal in the level cache device and level cache device;
Judge that the second port carries out write operation or carries out read operation, whether buffer memory the port input signal provides foundation for selector switch selects port signal still to select signal in the level cache device and level cache device;
What judge buffer memory in the first port level cache device is write operation or read operation, and whether buffer memory the port input signal provides foundation for selector switch selects port signal still to select signal in the level cache device and level cache device;
The judged result of above-mentioned six actions can be divided into following five kinds of situations:
Situation one: the first end port address is identical with the second port address, and the first port carries out is write operation;
Situation two: the first end port address is identical with the second port address, and the first port carries out is read operation, and the first end port address is identical with the address in the first port level cache device, and in the first port level cache device buffer memory be write operation;
Situation three: the first end port address is different from the second port address, and the first port carries out is write operation, and the first end port address is identical with the address in the first port level cache device, and in the first port level cache device buffer memory be write operation;
Situation four: the first end port address is different from the second port address, and what the first port carried out is read operation, and what the second port carried out is write operation, and the second port address is identical with the address in the first port level cache device, and in the first port level cache device buffer memory be write operation;
Situation five: situation one, two, three, other situation all round.
For above-mentioned five kinds of different situations, adopt three kinds of different input data processing methods, comprise:
Disposal route one: as situation one, two, three appears, then sending the signal in the first port level cache device to IP of synchronous dual-port memory, the first port signal enters the first port level cache device simultaneously;
Disposal route two: as situation four appears, then sending the first port signal to IP of synchronous dual-port memory, the first port signal enters the first port buffer simultaneously;
Disposal route three: as situation five appears, then sending the first port signal to IP of synchronous dual-port memory, the first port signal does not enter the first port level cache device.
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| CN102567248A (en) * | 2010-12-31 | 2012-07-11 | 中国航空工业集团公司第六三一研究所 | Control circuit and method for avoiding access conflict of dual-port memory |
| CN102081591A (en) * | 2011-01-27 | 2011-06-01 | 中国第一汽车集团公司 | Application of dual-port memory in dual-CPU (Central Processing Unit) structure design |
| US8793442B2 (en) * | 2012-02-08 | 2014-07-29 | International Business Machines Corporation | Forward progress mechanism for stores in the presence of load contention in a system favoring loads |
| CN103730149B (en) * | 2014-01-20 | 2016-05-25 | 中国科学院电子学研究所 | A kind of read-write control circuit of dual-ported memory |
| CN103886916B (en) * | 2014-03-27 | 2017-01-25 | 中国科学院电子学研究所 | Encoding/decoding storage system with scalable input bit width |
| CN105448317B (en) * | 2014-06-20 | 2018-03-23 | 中芯国际集成电路制造(上海)有限公司 | The processing units of data, method and the enabled of control signal, process circuit |
| CN106250331B (en) * | 2016-08-04 | 2019-08-13 | 深圳市泽云科技有限公司 | A method of for sata port multiplex optimization |
| CN106656391B (en) * | 2016-12-12 | 2018-10-12 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of exchanger chip multipath clock synchronization primitives clash handle circuit |
| CN109285580B (en) * | 2018-09-06 | 2021-04-13 | 天津市滨海新区信息技术创新中心 | Data preprocessing device and method and asynchronous double-end random access memory system |
| CN110097902B (en) * | 2019-04-15 | 2021-01-29 | 中科亿海微电子科技（苏州）有限公司 | Read-write control module and method for same port and dual-port memory |
| CN111290715B (en) * | 2020-02-24 | 2023-04-28 | 山东华芯半导体有限公司 | Safe storage device based on partition realization |
| CN112052206B (en) * | 2020-08-31 | 2023-03-28 | 浙江双成电气有限公司 | Multi-port data storage system based on arbitration |
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