CN101710270B - High-speed mass memory based on flash memory and chip data management method - Google Patents
High-speed mass memory based on flash memory and chip data management method Download PDFInfo
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Abstract
The invention relates to a high-speed mass memory based on flash memory, comprising a master control board, a first storage board and a second storage board, wherein the first storage board and the second storage board are arranged on two sides of the master control board; the first storage board and the master control board are connected by a first board electrode connector, the master control board and the second storage board are connected by a second board electrode connector, and the first storage board, the master control board and the second storage board are mutually connected in a lamination mode. The invention has high interface transmission speed, greatly improves data real-time interactivity when users use, and has strong error correcting capability, long flash memory service life and data encryption function. The invention encrypts written-in data, increases the safety of data and has the advantage of quick data destroying function.
Description
Technical field
The present invention relates to a kind of high-speed large capacity memory, especially a kind of high-speed large capacity memory based on flash memory.
Background technology
Along with development of semiconductor, the manufacturing technology of flash chip is more and more ripe, and the capacity of single-chip is also increasing.Because advantages such as good anti-vibration that flash memory itself had, low in energy consumption, light weight, high-low temperature resistant rugged surroundings, increasing product selects for use flash memory as storage medium.Such as USB flash disk, digital product, hard disk etc.At industrial measurement and control and military project and space industry, because the various advantages that flash memory possessed have determined it to be more suitable for as storage medium.At present, having based on flash memory is the electronic hard disc of storage medium.Standard-sized electronic hard disc is limited by structure and interface, and speed and capacity are not high.On speed, the fastest present reading speed that can accomplish 100MByte/S, the writing speed of 80MByte/S; Aspect capacity, receive the restriction of the capacity and the volume size of single chips, maximum can be accomplished 128G at present.
In satellite and airborne storage are used, often need the storer of high-capacity and high-speed.The handling characteristics of this type storer is the journal file, need not realize the file system of standard, and interface generally adopts the perhaps standard interface of customization, and agreement is self-defined.And because the environment of these workbenches is very abominable, very big such as vibration, temperature environment is very abominable, requires very high to storage system.Traditional storage medium adopts magnetic storage, such as tape.But this type magnetic storage product has storage speed slow, the shortcoming that capacity is low.Especially modern development along with microelectric technique; The semiconductor devices operating rate is more and more faster; Need data quantity stored increasing, traditional magnetic store can't satisfy demands of applications, even present electronic hard disc; Also can't meet the demands, and be that the high-speed large capacity memory of medium will well address this problem based on flash memory.
At home, also having some at present is the mass storage of storage medium based on flash memory, still; There are low, the slow-footed characteristics of capacity at present in this series products, and interface rate generally is no more than 100MB/S, for the expansion capacity; Often bulky, power consumption is very high.And this series products does not perhaps have very simple ECC verifying function, can not guarantee the reliability of data.The more important thing is that this series products does not have data encryption and function of quick self-destruction, this just makes safety of user data to be protected.
Summary of the invention
The object of the invention is the high capacity that solves demand in existing military project and the industrial rugged surroundings, the problem of high speed reads data-carrier store; Take brand-new method for designing; Improved reading and writing data speed greatly; The more important thing is to have possessed the encryption and the function of quick self-destruction of data, had better confidentiality.
Technical solution of the present invention is: a kind of high-speed large capacity memory based on flash memory; It is characterized in that; This storer comprises master control borad and first memory board and second memory board that are arranged on these master control borad both sides; Be connected with the second polate connector through the first plate connector respectively between first memory board and master control borad, master control borad and second memory board, interconnected with the mode of lamination;
Said master control borad comprises:
PCIe communication interface administration module is used for being responsible for the correspondence with foreign country management; This module has realized the agreement of Physical layer, data link layer and the application layer of PCIe interface;
With the reading and writing interface cache module of FIFO mode work, the read-write operation passage of difference respective user;
Data Management Unit, data write fashionable the data allocations in the write cache in each passage buffer memory; When data are read, be responsible for sending reading of data order, and from each passage buffer memory, read data and be written to and read in the high-speed cache to each passage; Be responsible for conversion and the balance abrasion adjustment algorithm of logical address to physical address;
The inner high speed bus comprises a pair of independently data bus and a pair of independent address bus; Data bus comprises data write bus and data read bus; Address bus comprises read operation address bus and write operation address bus; The address and the data bus that adopt this read-write to separate, the system that can guarantee can carry out data transmission with the mode of full duplex, has improved message transmission rate greatly;
Plate level communication interface administrative unit mainly is responsible for the data communication management between master control borad and the memory board, comprises command interaction and exchanges data; Physical interface adopts Low Voltage Differential Signal LVDS to carry out data transmission, guarantees that data are in interchannel high-speed transfer; Plate level communication interface administrative unit is divided into HOST end and DEVICE end again, and what on master control borad, realized is the HOST end;
Said PCIe communication interface administration module inserts Data Management Unit FPGA through the reading and writing cache module; Said Data Management Unit FPGA is connected with a plurality of parallel passage cache modules through the inner high speed bus; Said passage cache module is connected with plate level communication interface administrative unit;
Said first memory board or second memory board comprise:
Interface communication administrative unit LVDS is responsible for the telecommunication management to master control borad;
Memory manage unit is responsible for bad block management, and the address of defect block addresses remaps;
Command resolution unit is responsible for the parsing of order, and the downward new control command of primary unit transmission, and monitoring subordinate module command executing state;
The encoding and decoding of data stream are responsible in ECC error correction and detection unit;
The data manipulation administrative unit is responsible for the data write operation, and communicates with ECC error correction and detection unit;
The flash reading and writing control module is responsible for the management of the flash array of concrete each passage, and produces the control timing of the various operations of flash memory;
Said interface communication administrative unit LVDS inserts the data manipulation administrative unit through memory manage unit, command resolution unit and data cache module respectively; The data manipulation administrative unit inserts ECC error correction and detection unit respectively and inserts the flash reading and writing control module through a plurality of parallel array channel data cache module.
A kind of chip data management method; Its special character is, cycle running time of branch chips such as this method, and with the time that reads or writes as chip time of each five equilibrium; After the read or write of accomplishing this chip; Immediately next chip is carried out read or write, carry out successively, when accomplishing cycle running time of chip; The read or write of each chip of completion in this cycle running time, and be to accomplish in turn successively in the cycle each chip is carried out read or write with this cycle running time.
A kind of fast data is destroyed management method, and its special character is, the crossing parallel erase command that this method adopts chip to support cooperates the multi-channel parallel management method, makes all chips in all passages almost carry out erase operation simultaneously.
The present invention has following advantage:
1, the interface transmission speed is fast.Adopt PCIe interface at a high speed, cooperate inside flash reading and writing management method efficiently, guarantee that reading and writing data speed can reach more than the 300MB/S.
2, the reading and writing data full duplex is carried out.Unique method for managing system guarantees that the user reads carrying out carrying out high speed when data high-speed writes, and has improved the data in real time interactivity the when user uses greatly.
3, error correcting capability is strong, the flash memory long service life.Separate on the wrong ability entangling, the present invention adopts unique decoding method, can correct 4 random error to the random error of 8 of 512 byte datas inspections.Cooperate efficient unique balance abrasion adjustment algorithm, the serviceable life of having improved flash memory greatly.
4, has data encryption feature.Encrypt writing data, increase safety of data.
5, have rapid data and destroy function.Much capacity no matter, the data erase time is no more than 5S.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 is a master control borad design frame chart of the present invention.
Fig. 3 is a memory board design frame chart of the present invention.
Fig. 4 is the institutional framework synoptic diagram of flash array.
Embodiment
Can be found out that by Fig. 1 the present invention is made up of a master control borad 1 and two memory boards 2, three circuit boards adopt plate connector 3 to connect, and adopt the mode of lamination interconnected.In the middle of wherein master control borad 1 was in, two memory boards 2 were in the both sides of master control borad 1 respectively.
Referring to Fig. 2, master control borad 1 is made up of following unit: PCIe communication interface administration module, read-write high-speed cache, Data Management Unit, inner high speed data bus, passage buffer memory and plate level communication interface administrative unit.
PCIe communication interface administration module is responsible for the correspondence with foreign country management, and the read-write high-speed cache is the read-write operation passage of respective user respectively.Data Management Unit be responsible for write fashionable, the data allocations of write cache in each passage buffer memory; When data read, be responsible for sending reading of data order, and from each passage buffer memory, read data and be written to and read in the high-speed cache to each passage.In addition, Data Management Unit also is responsible for conversion and the balance abrasion adjustment algorithm of logical address to physical address.
Referring to Fig. 3, memory board 2 is made up of following unit: interface communication administrative unit, memory manage unit, command resolution unit, data manipulation administrative unit, ECC error correction and detection unit and flash reading and writing control module.
The interface communication administrative unit is responsible for the telecommunication management of data to master control borad 1.Memory manage unit is responsible for bad block management, and the address of defect block addresses remaps.Command resolution unit is responsible for the parsing of order, and the downward new control command of primary unit transmission, and monitoring subordinate module command executing state.The data manipulation administrative unit is responsible for the data write operation, and communicates with ECC error correction and detection unit.The encoding and decoding of data stream are responsible in ECC error correction and detection unit.The flash reading and writing control module is responsible for the management of the flash array of concrete each passage, and produces the control timing of the various operations of flash memory.
When carrying out read operation, master control borad 1 calculates the actual physical address according to logical address, and this physical address comprises the plate channel information of memory board 2 and the channel number information of memory board 2 interior physical channels.Master control borad 1 order and address information pass to corresponding memory board 2, after memory board 2 receives information, carry out the parsing of address and order.When parse addresses, might find that destination address is bad piece district, this remaps physical address with regard to needs again.The command resolution unit of memory board 2 just is responsible for carrying out the parsing of order, and transmits the sequential operation order after resolving downwards.After the flash reading and writing control module of respective channel executes read operation, writes data in the passage buffer memory, to data manipulation administrative unit feedback feedback signal.After receiving return signal, the data manipulation administrative unit begins in the interface high-speed cache, to move the data in the passage buffer memory, in this process, carries out the decoding work of ECC simultaneously.The read-write interface high-speed cache is worked with the FIFO mode, in case there are data the inside, interface management unit begins reading of data to the master control borad Data transmission.Master control borad starts the outside Data transmission of external interface administrative unit simultaneously.
When carrying out read operation, same, master control borad 1 passes to order biography, address and data in the corresponding memory board 2 together; After memory board 2 receives orders; Resolve to the flash read operation order, and be delivered to the corresponding flash memory read-write control unit to order and address, the ECC of administrative unit startup simultaneously entangles and separates wrong unit; Carry out the coding of data, the data behind the coding are written in the passage buffer memory.Be responsible for writing data in the flash chip by the flash reading and writing control module and go.
Need to prove, read-write operation no matter, the entire stream journey all is to operate with the mode of operation of streamline, improves the data throughput speed of total system like this.
When reading and writing with erase operation, also be the thinking that adopts stream line operation to the chip in the flash array.Writing and wiping of single flash memory all needs a very long stand-by period, and writing maximum latency is 700us, and the maximum latency of wiping is 2ms.If wait for during this period of time always, be a kind of great waste to bus, writing speed can't satisfy interface requirement.Therefore, the present invention has also used the flash memory streamline administrative skill of an innovation.
Referring to Fig. 4, after a chip operation is accomplished, change the operation of next flash chip immediately over to, when the intact circle of polling operation was got back to the flash chip of operation for the first time by the time, the stand-by period of this chip operation last time satisfied.Like this and the like, both guaranteed that the operation awaits time of each flash chip all satisfied, guaranteed that again bus is in busy state always, has improved data throughput speed greatly.The detailed process of this method is: cycle running time of five equilibrium chip; And with time of each five equilibrium as the reading or writing the time of chip, after the read or write of accomplishing this chip, immediately next chip is carried out read or write; Carry out successively; When accomplishing cycle running time of chip, accomplish the read or write of each chip in this cycle running time, and be to accomplish in turn successively in the cycle each chip is carried out read or write with this cycle running time.
When carrying out data destroying, the thinking that in each passage, also is based on above pipeline processes is carried out erase operation, but owing to the write time of erase command is very short, so chip almost can think to carry out simultaneously erase operation in each passage.And to each passage, then parallel erase operation fully.Like this from total system, all chips can be thought and carry out erase operation simultaneously.Like this, no matter what chips are arranged, the performed erasing time is all the same with the erasing time of a chip.And the erasing time of a flash chip is fixing computable, is no more than 5s.Therefore, the physical storage capacity has much, and the erasing time all is no more than 5s totally.
Of the present invention is the high-speed large capacity memory of storage medium based on flash memory, and according to the 3U size, capacity can be accomplished 512G ~ 4T, and interface adopts PCIe, and reading and writing data speed can reach 300MByte/S.Total system adopts FPGA as the hard core control device, has realized dynamic wearing and tearing adjustment algorithm, ECC/EDC error correction algorithm and the bad block management algorithm of flash memory.Support the full duplex of reading and writing data to carry out, really realized reliable, at a high speed and high-performance.The more important thing is to have function of quick self-destruction, much capacity no matter, the data destroying time is no more than 5s totally, has fabulous confidentiality.
Claims (1)
1. high-speed large capacity memory based on flash memory; It is characterized in that: this storer comprises master control borad and first memory board and second memory board that are arranged on these master control borad both sides; Be connected with the second polate connector through the first plate connector respectively between first memory board and master control borad, master control borad and second memory board, interconnected with the mode of lamination;
Said master control borad comprises:
PCIe communication interface administration module is used for being responsible for the correspondence with foreign country management; This module has realized the agreement of Physical layer, data link layer and the application layer of PCIe interface;
With the reading and writing interface high-speed cache of FIFO mode work, the read-write operation passage of difference respective user;
Data Management Unit, data write fashionable the data allocations in the write cache in each passage buffer memory; When data are read, be responsible for sending reading of data order, and from each passage buffer memory, read data and be written to and read in the high-speed cache to each passage; Be responsible for conversion and the balance abrasion adjustment algorithm of logical address to physical address;
The inner high speed bus comprises a pair of independently data bus and a pair of independent address bus; Data bus comprises data write bus and data read bus; Address bus comprises read operation address bus and write operation address bus; The address and the data bus that adopt this read-write to separate, the system that can guarantee can carry out data transmission with the mode of full duplex, has improved message transmission rate greatly;
Plate level communication interface administrative unit mainly is responsible for the data communication management between master control borad and the memory board, comprises command interaction and exchanges data; Adopt Low Voltage Differential Signal LVDS to carry out data transmission, guarantee that data are in interchannel high-speed transfer; Plate level communication interface administrative unit is divided into HOST end and DEVICE end again, and what on master control borad, realized is the HOST end;
Said PCIe communication interface administration module inserts Data Management Unit through the reading and writing cache module; Said Data Management Unit is connected with a plurality of parallel passage cache modules through the inner high speed bus; Said passage cache module is connected with plate level communication interface administrative unit;
Said first memory board or second memory board include:
The interface communication administrative unit is responsible for the telecommunication management of master control borad;
Memory manage unit is responsible for bad block management, and the address of defect block addresses remaps;
Command resolution unit is responsible for the parsing of order, and the downward new control command of primary unit transmission, and monitoring next stage cell command executing state;
The encoding and decoding of data stream are responsible in ECC error correction and detection unit;
The data manipulation administrative unit is responsible for the data write operation, and communicates with ECC error correction and detection unit;
The flash reading and writing control module is responsible for the management of the flash array of concrete each passage, and produces the control timing of the various operations of flash memory;
Said interface communication administrative unit inserts the data manipulation administrative unit through memory manage unit, command resolution unit and data cache module respectively; The data manipulation administrative unit inserts ECC error correction and detection unit respectively and inserts the flash reading and writing control module through a plurality of parallel array channel data cache module.
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| CN102053929A (en) * | 2010-12-17 | 2011-05-11 | 天津曙光计算机产业有限公司 | IO cache operation method and system based on DM layer of Linux system |
| CN102541778A (en) * | 2010-12-17 | 2012-07-04 | 西安奇维测控科技有限公司 | Ultra-high speed and ultra-large capacity storage device and implementation method thereof |
| CN102184151B (en) * | 2011-04-29 | 2013-06-26 | 杭州华三通信技术有限公司 | PCI-E (peripheral component interconnect express) to PCI bridge device and method for actively prefetching data thereof |
| CN102541678B (en) * | 2011-12-30 | 2013-09-18 | 中国人民解放军国防科学技术大学 | Multichannel NAND flash parallel memory controller |
| CN103020551B (en) * | 2012-12-21 | 2015-12-02 | 清华大学 | A kind of memory architecture |
| CN106502577A (en) * | 2015-09-07 | 2017-03-15 | 龙芯中科技术有限公司 | The write accelerated method of memory space, device and system |
| CN106502934A (en) * | 2016-11-09 | 2017-03-15 | 上海微小卫星工程中心 | The spaceborne data management system of high-speed integratedization |
| CN106528443B (en) * | 2016-11-09 | 2019-08-06 | 上海微小卫星工程中心 | FLASH management system and method suitable for spaceborne data management |
| CN107480541B (en) * | 2017-07-28 | 2020-04-28 | 中国航空无线电电子研究所 | Microminiature machine carries record system |
| CN112612418B (en) * | 2020-12-25 | 2024-03-08 | 航天信息股份有限公司 | Method and system for managing large-capacity NandFlash bad blocks |
| CN112882964A (en) * | 2021-03-04 | 2021-06-01 | 中国航空工业集团公司西安航空计算技术研究所 | High-capacity and high-safety storage system supporting multiple interfaces |
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| CN101540191A (en) * | 2009-04-21 | 2009-09-23 | 苏州国芯科技有限公司 | Real-time encrypted U disk and high speed encryption-decryption method |
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| CN101540191A (en) * | 2009-04-21 | 2009-09-23 | 苏州国芯科技有限公司 | Real-time encrypted U disk and high speed encryption-decryption method |
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