CN204347812U

CN204347812U - A kind of server stores circuit based on FPGA

Info

Publication number: CN204347812U
Application number: CN201420873110.4U
Authority: CN
Inventors: 杨敏
Original assignee: Shanghai Normal University
Current assignee: Shanghai Normal University; University of Shanghai for Science and Technology
Priority date: 2014-12-30
Filing date: 2014-12-30
Publication date: 2015-05-20
Anticipated expiration: 2024-12-30

Abstract

The utility model discloses a kind of server stores circuit based on FPGA, comprise processor-server and connect DDR3 memory chip, described processor-server connects PCIE interface and connects fpga chip by described PCIE interface, described fpga chip connects DDR3 cache chip, described fpga chip comprises at least i.e. the first serial RapidIO interface, second serial RapidIO interface, 3rd serial RapidIO interface and the 4th serial RapidIO interface, the first described serial RapidIO interface connects a SATA/SAS memory storage, the second described serial RapidIO interface connects the 2nd SATA/SAS memory storage, the 3rd described serial RapidIO interface connects Three S's ATA/SAS memory storage, the 4th described serial RapidIO interface connects the 4th SATA/SAS memory storage.

Description

A kind of server stores circuit based on FPGA

Technical field

The utility model belongs to server chips technical field, particularly a kind of server stores circuit based on FPGA.

Background technology

In prior art, server stores framework be all be connected to server with special PCH bridge sheet CPU on be used for expanding peripheral memory interface, such as SATA, SAS etc.Such as publication number is that the patent document of CN202795333U discloses redundant arrays of inexpensive disks high-speed read-write control circuit structure in a kind of server, described circuit structure comprises power module, server master board, central processing unit, Redundant Array of Independent Disks (RAID) card, disk array and magnetic disk array buffer storage module, described power module, central processing unit is all connected by described server master board alternately with Redundant Array of Independent Disks (RAID) card, described disk array is all connected with described power module with magnetic disk array buffer storage module, and described disk array and magnetic disk array buffer storage module are all connected with described server master board by described Redundant Array of Independent Disks (RAID) card, described magnetic disk array buffer storage module is solid state hard disc.

At present along with systems technology is in development at full speed, more and more higher to the memory capacity of data, access speed and data integrity safety requirements, particularly some research institutes, military project unit etc.The technical scheme that above-mentioned patent document is mentioned can not meet the demand for development of generic server completely, also there is the problem that system complex, power consumption are comparatively large and cost is higher simultaneously.

Utility model content

The purpose of this utility model is to provide a kind of server stores circuit based on FPGA.

The technical solution of the utility model is, a kind of server stores circuit based on FPGA, described server stores circuit comprises processor-server, described processor-server connects DDR3 memory chip, described processor-server connects PCIE interface and connects fpga chip by described PCIE interface, described fpga chip connects DDR3 cache chip

Described fpga chip comprises at least 4 serial RapidIO interfaces, i.e. the first serial RapidIO interface, the second serial RapidIO interface, the 3rd serial RapidIO interface and the 4th serial RapidIO interface, the first described serial RapidIO interface connects a SATA/SAS memory storage, the second described serial RapidIO interface connects the 2nd SATA/SAS memory storage, the 3rd described serial RapidIO interface connects Three S's ATA/SAS memory storage, and the 4th described serial RapidIO interface connects the 4th SATA/SAS memory storage.

Described processor-server is the E5-2600 processor-server of X86-based, described fpga chip is the stratix5 of altera, described server stores circuit also comprises the FPGA power supply module be connected with described fpga chip, FPGA program parallelization flash, 10/100/1000M network interface and the BMC baseboard management controller chip AST2400 be connected with described fpga chip by local bus, peripheral circuit around BMC baseboard management controller chip AST2400 also comprises connected power module, program flash and DDR3 internal memory, the peripheral circuit of described BMC baseboard management controller chip AST2400 also comprises connected network interface, USB interface, serial line interface and USB interface.

RapidIO is a kind of high-performance, low pin count, the interconnection architecture based on packet-switching that are taken the lead in advocating by companies such as Motorola and Mercury, is for meeting and following high performance embedded system demand and a kind of open system interconnection technical standard of designing.RapidIO is mainly used in embedded system intraconnection, and supporting chip is to the communication between chip, plate to plate, and the backboard (Backplane) that can be used as embedded device connects.

RapidIO agreement is made up of logical layer, transport layer and Physical layer.Logical layer defines institute's protocols having and packet format.This is the necessary information that terminal is carried out to initialization and completed transmission.Transport layer is that packet is from a terminal to the necessary information of another terminal passageway.Physical layer describes interface protocol between equipment, and such as bag passes device, flow control, electrical characteristics and lower level error management etc.Rapid IO is divided into parallel Rapid IO standard and serial Rapid IO standard, and serial RapidIO refers to that Physical layer adopts the RapidIO standard of serial differential analog signal transmission.

PCI-Express is bus and interface standard, and its original name is called " 3GIO ", is proposed in calendar year 2001 by Intel, being clearly meant to it and represent I/O interface standard of future generation of Intel.PCIe belongs to the point-to-point binary channels high bandwidth transmission of high speed serialization, and the equipment connected distribution exclusively enjoys channel bandwidth, not shared bus bandwidth, main support active power management, error reporting, end-to-end reliability transmission, the functions such as hot plug and service quality (QOS).PCIe is just renamed as " PCI-Express " after transferring to PCI-SIG (PCI particular interest tissue) certification to issue, and is called for short PCI-E or PCIE.

SATA is the abbreviation of Serial ATA, i.e. serial ATA.This is a kind of Novel hard disk interface type being different from Parallel ATA completely, gains the name owing to adopting serial mode transmission data.SATA bus uses embedded clock signal, possesses stronger error correcting capability, its maximum difference compared with the past is to check transfer instruction (being not only data), if find mistake meeting automatic straightening, something which increases the reliability of data transmission.Serial line interface also has the advantage that structure is simple, support hot plug.

SAS (Serial Attached SCSI) i.e. Serial Attached SCSI (SAS), it is the SCSI technology of a new generation, identical with Serial ATA (SATA) hard disk of current trend, be all adopt serial technology to obtain higher transmission speed, and improve inner space etc. by shortening tie line.The new interfaces that SAS develops after being parallel scsi interface.The design of this interface is usefulness, availability and extendibility in order to improve storage system, and provides the compatibility with SATA hard disc.

About BMC baseboard management controller chip, in BMC, realize IPMI function completely needs powerful 16 bits or 32 bit microcontrollers and with the RAM of what data storing, the fast flash memory bank stored with what non-volatile data and firmware.One provides the typical BMC of IPMI v1.5 approximately to need 32kRAM and 128k fast flash memory bank.A kind of novelty solution adopting IPMI agreement is the mini baseboard management controller utilizing high performance-price ratio, and it is restarted at safety long-distance, safety re-powers, LAN warns and can provide the basic long-range manageability of IPMI v1.5 in system health supervision.High by what cost performance, this controller can also be used for managerial grid pipeline equipment, as public desktop computer, printer, hub, digital television video signal boxcar etc.

The utility model adopts server processor chip by Memory Extension interface PCIE interface, the high-speed interface RAPIDIO being connected to FPGA, to expand the memory interfaces such as SATA or SAS, solves the technical bottleneck of embedded server expanding storage depth and access speed.

Accompanying drawing explanation

By reference to accompanying drawing reading detailed description hereafter, above-mentioned and other objects of the utility model illustrative embodiments, feature and advantage will become easy to understand.In the accompanying drawings, show some embodiments of the present utility model by way of example, and not by way of limitation, wherein:

Fig. 1 is the server stores circuit composition schematic diagram of the utility model one embodiment.

Fig. 2 is the server stores circuit composition schematic diagram of the another embodiment of the utility model.

Embodiment

As shown in Figure 1, server stores circuit based on FPGA of the present utility model, described server stores circuit comprises processor-server, described processor-server connects DDR3 memory chip, described processor-server connects PCIE interface and connects fpga chip by described PCIE interface, described fpga chip connects DDR3 cache chip, described fpga chip comprises at least 4 serial RapidIO interfaces, i.e. the first serial RapidIO interface, second serial RapidIO interface, 3rd serial RapidIO interface and the 4th serial RapidIO interface, the first described serial RapidIO interface connects a SATA/SAS memory storage, the second described serial RapidIO interface connects the 2nd SATA/SAS memory storage, the 3rd described serial RapidIO interface connects Three S's ATA/SAS memory storage, the 4th described serial RapidIO interface connects the 4th SATA/SAS memory storage.

As shown in Figure 2, described processor-server is the E5-2600 processor-server of X86-based, described fpga chip is the stratix5 of altera, described server stores circuit also comprises the FPGA power supply module be connected with described fpga chip, FPGA program parallelization flash, 10/100/1000M network interface and the BMC baseboard management controller chip AST2400 be connected with described fpga chip by local bus, peripheral circuit around BMC baseboard management controller chip AST2400 also comprises connected power module, program flash and DDR3 internal memory, the peripheral circuit of described BMC baseboard management controller chip AST2400 also comprises connected network interface, USB interface, serial line interface and USB interface.

What deserves to be explained is, although foregoing teachings has described spirit and the principle of the utility model creation with reference to some embodiments, but should be appreciated that, the utility model is created and is not limited to disclosed embodiment, can not combine the feature that the division of each side does not mean that in these aspects yet, this division is only the convenience in order to state.The utility model creates the interior included various amendment of the spirit and scope being intended to contain claims and equivalent arrangements.

Claims

1. the server stores circuit based on FPGA, it is characterized in that, described server stores circuit comprises processor-server, described processor-server connects DDR3 memory chip, described processor-server connects PCIE interface and connects fpga chip by described PCIE interface, described fpga chip connects DDR3 cache chip

2. as claimed in claim 1 based on the server stores circuit of FPGA, it is characterized in that, described processor-server is the E5-2600 processor-server of X86-based, described fpga chip is the stratix5 of altera, described server stores circuit also comprises the FPGA power supply module, FPGA program parallelization flash, 10/100/1000M network interface and the BMC baseboard management controller chip AST2400 that is connected with described fpga chip by local bus that are connected with described fpga chip

Peripheral circuit around BMC baseboard management controller chip AST2400 also comprises connected power module, program flash and DDR3 internal memory,

The peripheral circuit of described BMC baseboard management controller chip AST2400 also comprises connected network interface, USB interface, serial line interface and USB interface.