CN100394384C - Method and system for on-line updating of network - Google Patents
Method and system for on-line updating of network Download PDFInfo
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- CN100394384C CN100394384C CNB2005100513535A CN200510051353A CN100394384C CN 100394384 C CN100394384 C CN 100394384C CN B2005100513535 A CNB2005100513535 A CN B2005100513535A CN 200510051353 A CN200510051353 A CN 200510051353A CN 100394384 C CN100394384 C CN 100394384C
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Abstract
The present invention discloses a network on-line upgrading method which has steps: (a). a universal MCU is electrically connected with at least two external data memories, and is connected with a network; (b). the universal MCU is started, one of the external data memories is determined to be an active state according to a control program, and the other external data memory is a standby state; (c). a business program in the external data memory which lies in the active state is executed, the business program responds a network on-line upgrading request, and a data packet sent by a network is written into the external data memory which lies to the standby state; (d). the active and the standby states of the external data memories are changed to cause the external data memory which originally lies in the active state to be changed into the standby state, and the external data memory which originally lies in the standby state of the data packet written in and sent by the network on-line upgrade. The method can utilize the universal MCU with lost cost to conveniently and fast realize the network on-line upgrading service.
Description
Technical field
The present invention relates to the network communications technology, specifically, relate to a kind of on-line updating of network system.
Background technology
Prior art is to adopt advanced CPU to realize the on-line updating of network function mostly, and itself has Ethernet interface CPU, as the ARM9 processor.But also do not use general MCU (microcontroller) to realize the on-line updating of network function at present.
Summary of the invention
The purpose of this invention is to provide a kind of system that uses the CPU realization on-line updating of network function that cheap, lower-cost general MCU replacement costs an arm and a leg, cost is higher, use this system can be when program run, non-interrupting service, need not be in the action, the application program updating of current operation is replaced.
For achieving the above object, on-line updating of network method provided by the invention comprises the following steps:
16 general MCU are electrically connected with at least two external data memories, and be connected with network;
Start general MCU, and determine that according to control program one in the said external data-carrier store is that the master uses state, other is a stand-by state;
Execution is in main with the business procedure in the external data memory of state, the request of described business procedure response to network online upgrading, and the packet that network is transmitted writes the external data memory that is in stand-by state;
(d) change active and standby state with external data memory, make originally to be in main external data memory and to become stand-by state, the external data memory that before is in stand-by state that writes the packet that on-line updating of network transmits is become main duty with state.
Wherein, in step (a), general MCU also is electrically connected with logic decoder and trappings bit memory, and wherein logic decoder is determined the active and standby status duty of respective memory, and the trappings bit memory is used for storing the active and standby status data of using of external data memory.
Wherein, in step (b), control program at first reads the data in the trappings bit memory, and determines the working method of described logic decoder according to the data of trappings bit memory; Described control program can be thought general MCU internally stored program, also can be program stored in the external data memory.
In addition, in step (a), described general MCU outside also connects a static RAM, is used as the variable of cache software program.
Wherein, described network is an Ethernet, and the online request of described network is the online request of telecommunication network.
Wherein, described general MCU is C51, and described external data memory is the FLASH data-carrier store, and described logic decoder is CPLD, and described trappings bit memory is EEPROM.
On-line updating of network of the present invention system comprises
16 general microcontroller;
Logic decoder, respectively by least-significant byte address bus and 8 bit data multiplex bus AD[0..7], most-significant byte address bus A[8..15], external program space read signal nPSEN, address latch signal ALE, external data space read signal POE, general purpose I/O line PA[0..3], general purpose I/O line NCS1, general purpose I/O line NCS2 link to each other with described general microcontroller, is used for exporting control signal;
At least 2 external data memories, first external data memory is by external program and data space write signal PWR and described general microcontroller electric connection, by chip selection signal F_CS1, least-significant byte address signal A[0..7], most-significant byte address signal A[8..15], read signal F_RD1, high address A[16..19] electrically connect with described logic decoder, second external data memory is by external program and data space write signal PWR and described general microcontroller electric connection, by chip selection signal F_CS2, least-significant byte address signal A[0..7], most-significant byte address signal A[8..15], read signal F_RD2, high address B[16..19] electrically connect with described logic decoder, be used for storage service program and data;
The trappings bit memory is connected with described general microcontroller, is used for storing the Status Flag of described external data memory, and the working method of steering logic code translator.
In addition, described general microcontroller can also connect a static RAM, is used as the buffer memory of software program variable.
Wherein, described general microcontroller is C51, and described logic decoder is CPLD, and described external data memory is the FLASH storer, and described trappings bit memory is EEPROM.
Compared with prior art, according to the method described in the present invention, after at least 2 external data memories of configuration outside general MCU such as C51, and adopt the data in the external data memory are carried out active and standby method of switching, just can realize not going scene, uninterrupted professional on-line updating of network function very easily.
In addition, to have remedied the structure of general MCU too simple by method that external memory storage and activestandby state switch is set, and is difficult to the competent complex task defective of on-line updating of network task as described in the present invention, has simple and practical, with low cost beneficial effect.
Description of drawings
Fig. 1 is a hardware configuration synoptic diagram of implementing technical solution of the present invention.
Fig. 2 is the process flow diagram that technical solution of the present invention provides method.
Embodiment
In order to understand the present invention better, the present invention is further illustrated below in conjunction with accompanying drawing.
Fig. 1 is the system hardware structure synoptic diagram of a kind of embodiment of technical solution of the present invention, also is a kind of particular hardware structural drawing of system provided by the present invention.As shown in Figure 1, in the present embodiment, general microcontroller adopts C51, and logic decoder adopts CPLD, and external memory storage adopts two FLASH storeies, i.e. flashA, flashB, and the trappings bit memory adopts an eeprom memory.Certainly, concrete device described in this embodiment such as C51, FLASH storer etc., spirit for a better understanding of the present invention and usefulness can not constitute the restriction of the system hardware platform that method operation provided by the present invention is relied on just.Under different embodiments, described C51, FLASH etc. can be substituted by other devices with similar functions.In addition, concrete herein hardware configuration combination also can be done various forms of conversion, such as: the quantity of external memory storage can be more than two, as long as the concrete pin of C51 is done corresponding change, these conversion and combination essential spirit all according to the invention and purpose.Therefore; it goes without saying that; all systems that has with the functionally similar general microcontroller+external data memory of concrete system hardware structure of the present invention; the system that particularly has the frame mode of general microcontroller+logic decoder+external memory storage all is included within the claim of the present invention scope required for protection.
The concrete connected mode of system shown in Figure 1 is that C51 passes through data bus, address bus, control bus and CPLD, flashA, flashB, SRAM links to each other.Sheet choosing, read-write and the high address of flashA, flashB, SRAM produce by CPLD decoding simultaneously.The SRAM of Lian Jieing is used for doing the high-speed cache of C51 herein, and can be used for the variable of storing software program.If adopt the inner MCU that has SRAM, also can connect external SRAM, specifically be described in detail as follows:
C51 pin explanation: AD[0..7] be least-significant byte address wire and the 8 bit data multiplex buss of C51, A[8..15] be the most-significant byte address bus.C51 provides 16 bit address buses altogether, 8 bit data bus, so addressing capability is 64kbytes.AD[0..7 wherein] link to each other with any 8 the I/O lines of CPLD, link to each other with 8 position datawires of SRAM, link to each other with 8 position datawires of flashA, flashB.AD[0..7 in addition] behind the input CPLD, output A[0..7], link to each other with the least-significant byte address wire of SRAM, flashA, flashB respectively.The A[8..15 of C51] behind the input CPLD, output A[8..15] respectively with the A[8..15 of SRAM, flashA, flashB] pin links to each other, as the most-significant byte address wire.The ALE of C51 (Address Latch Enable) signal is an address latch signal, directly links to each other with CPLD, is used for distinguishing AD[0..7] address and data message.When ALE is high, this moment AD[0..7] the transport address signal.
The nPSEN pin of C51 is an external program space read signal, and POE is an external data space read signal, and PWR is external program and data space write signal.Wherein PWR directly links to each other with the write signal pin of SRAM, flashA, flashB, links to each other with CPLD and nPSEN, POE are direct.
PA[0..3], NCS1, NCS2 be general purpose I/O line of C51, directly link to each other with CPLD.Produce the high address A[16..19 of flashA by CPLD decoding] with the high address B[16..19 of flashB] link to each other with the high address line of flashA, flashB respectively, be example with 1Mflash here, so have only 20 address wires.Expansion surpasses the 1Mbytes space if desired, then need use more I/O line to produce the high address.But program and the data block of more 64kbytes have then been increased for C51.Chip selection signal F_CS1, F_CS2 that decoding by CPLD produces flashA, flashB directly link to each other with the sheet signal pin of flashA, flashB, and the read signal F_RD1 of flashA, flashB, F_RD2 signal directly link to each other with the output enable pin of flashA, flashB.
According to the active and standby state of using of flashA, flashB, CPLD exports the reading of corresponding main flash, chip selection signal.As main flash, it moves present procedure, and standby flash is accessed as data space then.
Two FLASH are as the external program space (being different from the internal processes space of inner 64Kbytes) of C51, and the flashA among Fig. 2, the capacity of flashB all are 1Mbytes, and every FLASH has two states, main with or standby.For example: when flashA is the program space of current operation, flashB is exactly the standby program space so.
Which sheet adopts current active and standby of a slice EEPROM record is respectively with FLASH.That is the activestandby state of flashA, flashB, thereby the decoded mode of decision CPLD.As when FlashA is main flash, system start-up this moment executive routine, logic chip CPLD will enable F_CS1, F_RD1, and then B is standby.When should flashB being main flash, logic chip will enable F_CS2, F_RD2.
Fig. 2 is the process flow diagram of on-line updating of network method provided by the invention.With reference to Fig. 2, system starts when promptly powering on for the first time for the first time, and generally speaking, the NEA pin is set to height automatically by the pull-up resistor of outside.It is program program space execution internally.Certainly, program also can directly be carried out from the external program space when starting for the first time, when needs are carried out from the external program space, C51 writes an order to CPLD, CPLD is changed to corresponding N EA pin low, and make system reset but not power down, it is low to read the NEA signal after C51 starts so, then start executive routine from the outside, that is to say, after the system start-up internally program space executive routine still directly to carry out from the external program space be selectable, the key of its realization is the level state of NEA pin, after the specific implementation method is each system start-up, and the level state of C51 identification NEA pin, if the NEA pin is a high level, then system will carry out the program in internal processes space.If the NEA pin is a low level, then C51 will not carry out the program in internal processes space, but directly carry out the program in the external memory storage.In the present embodiment during system start-up, be that the program space is carried out internally as shown in Figure 2, after carrying out the inner space program, C51 reads the Status Flag of the FLASH that stores in advance among the plug-in EEPROM, in the present embodiment, EEPROM stored A, two variablees of B, if A=1, B=0 shows that then flashA is main flash, flashB is standby flash, if instead A=0, B=1 shows that flashB is main flash, flashA is the state notifying CPLD of standby flash. C51 this moment according to zone bit, and CPLD will establish the active and standby status of corresponding falshA or flashB, produce corresponding sheet choosing simultaneously, read signal, high-order address signal etc.In case established the status of active and standby flash, the program space changes the outside main flash program space internally over to so, carries out corresponding business work.The program that herein need to prove switches to outside flash space in the space internally, also is to be that low level realizes by the NEA pin that CPLD puts C51, when the NEA pin is low level, after the system reset, will guide again from the external program space.
This moment, system was in normal operating condition, and running software TFTP agreement promptly can begin response to network remote online upgrade request, and network herein is generally Ethernet, also can be token ring, FDDI net etc., and this conversion all within the scope of the present invention.With the Ethernet is example, and when the online request of response Ethernet, the TFTP protocol data bag of CPU receiving remote writes packet (application program of upgrading) among the standby flash then, and the sheet of choosing of the sheet of standby flash and main flash selects mutual exclusion to produce.The response upgrade request promptly upgrade finish after, the value of revising zone bit data among the EEPROM and be A, B changes the active and standby status of two flash.After starting next time, system will move the application program after the upgrading.
The present invention is described with reference to specific most preferred embodiment, those skilled in the art can understand, under not breaking away from as situation by spirit of the present invention and scope, the present invention can carry out the various variations on form and the details, as C51 of the present invention can be any general MCU that has similar functions with C51, and its inside can not have the internal processes space of 64Kbytes; Program can directly start from main FLASH; External program and internal processes can be read EEPROM, read the main and backup status of current flash.Just the not equal suchlike variation of physical location of the program space can both be finished network remote online upgrading function as described in the present invention, and protection scope of the present invention reaches certainly in these variations and conversion.
In sum, adopt method and system of the present invention, realized not going the scene very easily, the uninterrupted professional online upgrading that carries out network.Method that external memory storage and activestandby state switch is set, and to have remedied the structure of general MCU too simple, is difficult to the competent complex task defective of on-line updating of network task as described in the present invention, has simple and practical, with low cost beneficial effect.
Claims (3)
1. an on-line updating of network system includes
16 general microcontroller;
Logic decoder, respectively by least-significant byte address bus and 8 bit data multiplex bus AD[0..7], most-significant byte address bus A[8..15], external program space read signal nPSEN, address latch signal ALE, external data space read signal POE, general purpose I/O line PA[0..3], general purpose I/O line NCS1, general purpose I/O line NCS2 link to each other with described general microcontroller, is used for exporting control signal;
At least 2 external data memories, one of them external data memory is by external program and data space write signal PWR and described general microcontroller electric connection, by chip selection signal F_CS1, least-significant byte address signal A[0..7], most-significant byte address signal A[8..15], read signal F_RD1, high address A[16..19] electrically connect with described logic decoder, wherein another external data memory is by external program and data space write signal PWR and described general microcontroller electric connection, by chip selection signal F_CS2, least-significant byte address signal A[0..7], most-significant byte address signal A[8..15], read signal F_RD2, high address B[16..19] electrically connect with described logic decoder, be used for storage service program and data;
The trappings bit memory is connected with described general microcontroller, is used for storing the Status Flag of described external data memory, and the working method of steering logic code translator.
2. on-line updating of network as claimed in claim 1 system is characterized in that described general microcontroller also connects a static RAM, is used as the buffer memory of software program variable.
3. on-line updating of network as claimed in claim 1 or 2 system is characterized in that described general microcontroller is C51, and described logic decoder is CPLD, and described external data memory is the FLASH storer, and described trappings bit memory is EEPROM.
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| CNB2005100513535A CN100394384C (en) | 2005-03-08 | 2005-03-08 | Method and system for on-line updating of network |
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| CN100394384C true CN100394384C (en) | 2008-06-11 |
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| CN106406925A (en) * | 2015-08-03 | 2017-02-15 | 阿里巴巴集团控股有限公司 | An apparatus and a method used for supporting online upgrade |
| CN108037942B (en) * | 2017-12-06 | 2021-04-09 | 中电科蓉威电子技术有限公司 | Adaptive data recovery and update method and device for embedded equipment |
| CN117193831A (en) * | 2023-11-07 | 2023-12-08 | 上海灵动微电子股份有限公司 | Circuit supporting online upgrade |
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| JPH10124322A (en) * | 1996-10-23 | 1998-05-15 | Dainippon Screen Mfg Co Ltd | Substrate treating device |
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Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: Huasan Communication Technology Co., Ltd. |